EEC 116 Lecture #3:CMOS Inverters
MOS Scaling
Rajeevan AmirtharajahUniversity of California, Davis
Jeff ParkhurstIntel Corporation
Amirtharajah, EEC 116 Fall 2011 3
Outline
• Review: Inverter Transfer Characteristics
• Lecture 3: Noise Margins, Rise & Fall Times, Inverter Delay
• CMOS Inverters: Rabaey 1.3.2, 5 (Kang & Leblebici, 5.1-5.3 and 6.1-6.2)
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InverterVin Vout
Vdd
VddVin
Vout
ideal
actual
Ideal digital inverter:
Review: Inverter Voltage Transfer Curve
–When Vin=0, Vout=Vdd
–When Vin=Vdd, Vout=0
–Sharp transition region
Voltage transfer curve (VTC): plot of output voltage Vout vs. input voltage Vin
0 V
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Review: Actual Inverter Output Levels
• VOH and VOL represent the “high” and “low” output voltages of the inverter
• VOH = output voltage when Vin = ‘0’ (V Output High)
• VOL = output voltage when Vin = ‘1’ (V Output Low)
• Ideally,
– VOH = Vdd
– VOL = 0 V
VddVin
Vout
VOH
VOL0 V
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Review: VOL and VOH
• In transfer function terms:– VOL = f(VOH)
– VOH = f(VOL)
– f = inverter transfer function
• Difference (VOH-VOL) is the voltage swing of the gate
– Full-swing logic swings from ground to Vdd
– Other families with smaller swings
VddVin
Vout
VOH
VOLVOL VOH
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Review: Inverter Switching Threshold
Inverter switching threshold:
– Point where voltage transfer curve intersects line Vout=Vin
– Represents the point at which the inverter switches state
– Normally, VM ≈ Vdd/2
– Sometimes other thresholds desirable
VddVin
Vout
VOH
VOL
Vout=Vin
VM
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VTC Mathematical Definitions
• VOH is the output high level of an inverterVOH = VTC(VOL)
• VOL is the output low level of an inverterVOL = VTC(VOH)
• VM is the switching thresholdVM = VIN = VOUT
• VIH is the lowest input voltage for which the output will be ≥ the input (worst case ‘1’)
dVTC(VIH)/dVIH = -1• VIL is the highest input voltage for which the output will be ≤ the input (worst case ‘0’)
dVTC(VIL)/dVIL = -1
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Noise Margin and Delay Definitions• NML is the difference between the highest acceptable ‘0’ and the lowest possible ‘0’
NML = VIL – VOL• NMH is the difference between the lowest acceptable ‘1’ and the highest possible ‘1’
NMH = VOH – VIH• tPHL is the propagation delay from the 50% point of the input to the output when the output goes from high to low
• tPLH is the propagation delay from the 50% point of the input to the output when the output goes from low to high
• tP is the average propagation delay• tR is the rise time (usually 10% to 90%)• tF is the fall time (usually 90% to 10%)
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CMOS Inverter
• Complementary NMOS and PMOS devices
• In steady-state, only one device is on (no static power consumption)
• Vin=1: NMOS on, PMOS off– Vout = VOL = 0
• Vin=0: PMOS on, NMOS off– Vout = VOH = Vdd
• Ideal VOL and VOH!• Ratioless logic: output is independent of transistor sizes in steady-state
Vin Vout
Vdd
Gnd
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CMOS Inverter: VTC
Vout = VDS
Dra
in c
urre
nt I D
S
Vin=2V
Vdd
Vin=1V
Vin=3V
Vin=4V
Vou
tVin1 2 3 40
Vdd
PMOS NMOS
• Output goes completely to Vdd and Gnd• Sharp transition region
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• NMOS transistor:
– Cutoff if Vin < VTN
– Linear if Vout < Vin – VTN
– Saturated if Vout > Vin – VTN
• PMOS transistor
– Cutoff if (Vin-VDD) > VTP → Vin > VDD+VTP
– Linear if (Vout-VDD)>Vin-VDD-VTP → Vout>Vin - VTP
– Sat. if (Vout-VDD)<Vin-VDD-VTP → Vout < Vin-VTP
CMOS Inverter Operation
Vin Vout
VDD
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CMOS Inverter VTC: Device Operation
P linearN cutoff
P linearN sat P sat
N sat
P satN linear
P cutoffN linear
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CMOS Inverter VTC: Device Sizing
VDD
VDD
Vin
Vout
kp=kn
kp=5kn
kp=0.2kn
• Increase W of PMOSkp increasesVTC moves to right
• Increase W of NMOSkn increasesVTC moves to left
• For VM = VDD/2kn = kp2Wn ≈ Wp
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Effects of VM adjustment
• Result from changing kp/kn ratio:– Inverter threshold VM ≠ VDD/2
– Rise and fall delays unequal
– Noise margins not equal
• Reasons for changing inverter threshold– Want a faster delay for one type of transition
(rise/fall)
– Remove noise from input signal: increase one noise margin at expense of the other
– Interfacing other types of logic (with different swings)
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• KCL (NMOS saturation, PMOS linear):
• Differentiate and set dVout/dVin to –1
• Solve simultaneously with KCL to find VIL
CMOS Inverter: VIL Calculation
( ) ( )[ ]2,,,0,
2,0, 2
22 pDSpDSpTpGSp
nTnGSn VVVV
kVVk
−−=−
( ) ( )( ) ( )[ ]2,0
2,0 2
22 DDoutDDoutpTDDinp
nTinn VVVVVVV
kVVk
−−−−−=−
( ) ( ) ( ) ( ) ⎥⎦
⎤
in
out⎢⎣
⎡−−−+−−=− DDoutDDout
in
outpTDDinpnTinn dV
dVVVVVdVdVVVVkVVk ,0,0
( ) ( )DDpTILoutpnTILn VVVVkVVk −+−=− ,0,0 2
R
nTRDDpToutIL k
VkVVVV
+
+−+=
12 ,0,0
p
nR k
kk =
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CMOS Inverter: VIH Calculation
• KCL:
• Differentiate and set dVout/dVin to –1
• Solve simultaneously with KCL to find VIH
( )[ ] ( )2,0,2
,,,0, 22
2 pTpGSp
nDSnDSnTnGSn VV
kVVVVk
−=−−
( )[ ] ( )2,02
,0 22
2 pTDDinp
outoutnTinn VVV
kVVVVk
−−=−−
( ) ( )pTDDinpin
outoutout
in
outnTinn VVVk
dVdVVV
dVdVVVk ,0,0 −−=⎥
⎦
⎤⎢⎣
⎡−+−
( ) ( )pTDDIHppTIHoutn VVVkVVVk ,0,02 −−=+−
( )R
nToutRpTDDIH k
VVkVVV
+
+++=
12 ,0,0
p
nR k
kk =
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CMOS Inverter: VM Calculation
• KCL (NMOS & PMOS saturated):
• Solve for VM = Vin = Vout
( ) ( )2,0,2
,0, 22 pTpGSp
nTnGSn VV
kVVk
−=−
( ) ( )2,02
,0 22 pTDDinp
nTinn VVV
kVVk
−−=−
( )
R
pTDDR
nT
M
k
VVk
VV
11
1,0,0
+
++=
p
nR k
kk =
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CMOS Inverter: Achieving Ideal VM
• Ideally, VM = VDD/2
• Assuming VT0,n = VT0,p,
( )
R
pTDDR
nT
TH
k
VVk
VV
11
1,0,0
+
++=
p
nR k
kk =
2
,0
,0, 2
2⎟⎟⎠
⎞⎜⎜⎝
⎛
+
+=
nTDD
pTDDidealR VV
VVk
1, =idealRk
5.2≈=⎟⎠⎞
⎜⎝⎛
⎟⎠⎞
⎜⎝⎛
p
n
n
p
LWLW
μμ
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CMOS Inverter: VIL and VIH for Ideal VM
• Assuming VT0,n=-VT0,p, and kR = 1,
( )02381
TDDIL VVV +=
( )02581
TDDIH VVV −=
DDIHIL VVV =+
ILOLILL VVVNM =−=
ILIHDDIHOHH VVVVVNM =−=−=
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MOSFET Scaling Effects
• Rabaey Section 3.5 (Kang & Leblebici Section 3.5)• Scaling provides enormous advantages
– Scale linear dimension (channel length) by factor S > 1– Better area density, yield, performance
• Two types of scaling– Constant field scaling (full scaling)
• A’ = A/S2; L’ = L/S; W’ = W/S; ID’ = ID/S; P’ = P/S2 ; Vdd’ = Vdd/S
• Power Density P’/A’ = stays the same– Constant voltage scaling
• A’ = A/S2; L’ = L/S; W’ = W/S; ID’ = ID*S; P’ = P*S; Vdd’ = Vdd
• Power Density P’/A’ = S3*P (Reliability issue)
Change these two
This changed as well
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Short Channel Effects
• As geometries are scaled down– VT (effective) goes lower– Effective channel length decreases– Sub-threshold Ids occurs
• Current goes from drain to source while Vgs < Vt– Tox is scaled which can cause reliability problems
• Can’t handle large Vg without hot electron effects– Changes the Vt when carriers imbed themselves
in the oxide– Interconnects scale
• Electromigration and ESD become issues
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MOSFET Capacitances
• Rabaey Section 3.3 (Kang & Leblebici Section 3.6)
• Oxide Capacitance
– Gate to Source overlap
– Gate to Drain overlap
– Gate to Channel
• Junction Capacitance
– Source to Bulk junction
– Drain to Bulk junction
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Oxide Capacitances: Overlap
• Overlap capacitances
– Gate electrode overlaps source and drain regions
– xd is overlap length on each side of channel
– Leff = Ldrawn – 2xd (effective channel length)
– Overlap capacitance:
source drain
xd
Ldrawn
doxGDOGSO WxCCC == Assume xd equal on both sides
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Total Oxide Capacitance
• Total capacitance consists of 2 components
– Overlap capacitance
– Channel capacitance
• Cutoff:
– No channel connecting to source or drain
– CGS = CGD = CoxWxd
– CGB = CoxWLeff
– Total Gate Capacitance = CG = CoxWL
source drainCgb
CgdCgs
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Oxide Capacitances: Channel• Linear mode
– Channel spans from source to drain– Channel Capacitance split equally between S and D
effoxGS WLCC21
= effoxGD WLCC21
=
– Total Gate capacitance CG = CoxWL
• Saturation regime– Channel is pinched off: Channel Capacitance --
dOXeffoxGS WxCWLCC +=32
oxdGD CWxC =
– Total Gate capacitance: CG = 2/3 CoxWLeff + 2xdWCOX
0=GBC
0=GBC
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Junction Capacitance
Reverse-biased P-N junctions!Capacitance depends on reverse-bias voltage.
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Junction Capacitance
ad
adj NN
NNVV
qAC+−
=0
22
εFor a P-N junction:
ad
adSij NN
NNV
qC+
=0
0 2ε
If V=0, cap/area =
mj
j
VV
ACC
⎟⎟⎠
⎞⎜⎜⎝
⎛−
=
0
0
1General form:
m = grading coefficient (0.5 for abrupt junctions)(0.3 for graded junctions)
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Junction Capacitance• Junction with substrate
– Bottom area = W * LS (length of drain/source)
– Total cap = Cj
• Junction with sidewalls– “Channel-stop implant”
– Perimeter = 2LS + W
– Area = P * Xj
– Total cap = Cjsw
• Total junction cap C = Cj + Cjsw
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Junction Capacitance
• Voltage Equivalence Factor
– Creates an average capacitance value for a voltage transition, defined as ΔQ/ΔV
00 jsweqswjjeqdb CKPXCAKC +=
( )( ) 0
1
0
1
1
0
2
12
00 111 jeq
mmj
eq CAKVV
VV
mVVVAC
C =⎟⎟
⎠
⎞
⎜⎜
⎝
⎛⎟⎟⎠
⎞⎜⎜⎝
⎛−−⎟⎟
⎠
⎞⎜⎜⎝
⎛−
−−
−=
−−
( ) ( )102012
02VVVV
VVV
Keq −−−−
−= (abrupt junction only)
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Example: Junction Cap
• Consider the following NMOS device– Substrate doping: NA = 1015 cm-3
– Source/drain doping: ND = 2 x 1020 cm-3
– Channel-stop doping: 10X substrate doping
– Drain length LD = 1um
– Transistor W = 10um
– Junction depth Xj = 0.5um, abrupt junction
• Find capacitance of drain-bulk junction when drain voltage = 3V