1
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Electrical Issues in Process Integration of SDE/Halo CMOS Junctions
Michael CurrentFrontier Semiconductor, 199 River Oaks Parkway, San Jose, CA 95134
www.frontiersemi.com
* Transistor effects of SDE/halo process choices* Junction effects for SDE/halo implants* Metrology options for SDE/halo* Process integration example for ms-anneals
Key co-workers: V. Faifer, J. Halim (FSM), P. Timans (Mattson), T. Clarysse (IMEC)
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CMOS Transistor: SDE/Halo/Well Dopants
Source Drain
Gate
Oxide
STI STI
SDE SDE
Well
Halo Halo
Metal Metal
Metal
Source Drain
Gate
Oxide
STI STI
SDE SDE
Well
Halo Halo
Metal Metal
Metal
p-MOS
SDE: B, BF2,B10H14, B18H22, B-clusters
PAI: Ge, Si, FCocktails: C, F, N,
C7H7, C16H10
n-MOS
SDE: As, P, SbAs4, P4,As-clusters
PAI: Ge, Si, FCocktails: C, F, N,
C7H7, C16H10
Halo: As, P, Sb,As-clusters
Halo: B, BF2, InB10H14, B18H22, B-clusters
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SDE/Halo Transistor Issues
Source Drain
Gate
Oxide
STI STI
SDE SDE
Well
Halo Halo
Metal Metal
Metal
Source Drain
Gate
Oxide
STI STI
SDE SDE
Well
Halo Halo
Metal Metal
Metal
Xj
SDE/gate overlap
Source Drain
Gate
Oxide
STI STI
SDE SDE
Well
Halo Halo
Metal Metal
Metal
Source Drain
Gate
Oxide
STI STI
SDE SDE
Well
Halo Halo
Metal Metal
Metal
Xj
SDE/gate overlap
Threshold voltage: VthSDE dose, Xj, abruptness, Tox, Halo profile, gate doping, etc.
Drive Current: IonSDE dose, Xj, abruptness,Gate overlap
Off-state Current, IoffVth, SCE, gate oxide leakage,junction leakage (Halo dose)
R. Duffy et al., Philips/IMEC, ECS 06
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CMOS Scaling: S. Thompson, P. Packen, M. Bohr (1998)
ftp://download.intel.com/technology/itj/q31998/pdf/trans.pdf
Off-statePotentials
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Leakage Current Control for Low Power 65 nm
C.H Jan et al. (Intel) IEDM05But for 45 and 32 nm, “no” junction diffusion is allowed !!
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Metrology Challenges for SDE/Halo (1)Lightly-doped substratesB-doped epi on n-Si (4x1014 d/cm3)(~20 Ohm-cm)
T. Clarysse (IMEC) et al. E-MRS05
For p-USJ on lightly-doped Si:Principal effect is a decrease in Rs value with increasing loading for contact probes (4PP, VPS).
RsL
Pene
tratio
n (n
m)
IRSE
VPS
4 D
imen
s.
SSM
240
0 05
30~15
non-contact 4 probes
> 100
Con
v.4P
P
RsL
Pene
tratio
n (n
m)
IRSE
VPS
4 D
imen
s.
SSM
240
0 05
30~15
non-contact 4 probes
> 100
Con
v.4P
P
RsL
Pene
tratio
n (n
m)
IRSE
VPS
4 D
imen
s.
SSM
240
0 05
30~15
non-contact 4 probes
> 100
Con
v.4P
P
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Metrology Challenges for SDE/Halo (2)Medium-doped substrates
T. Clarysse (IMEC) et al. MRS06
B
As
For p-USJ on medium-doped Si:Huge low Rs error for 4PP and VPS (SRP).RsL and micro-4PP OK to 10 nm epi.Active layer ~2 nm for 10 nm epi.
B-doped epi on medium doped n-Si (7x1017 d/cm3, ~20 um, ~14 Ohm/sq)
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RsL – Non-Contact Sheet Resistance and Leakage CurrentHow it works
Junction
Depletion
Substrate
Spreading
Modulated LED Beam
Vin Vout
Recombination
Junction
Depletion
Substrate
Spreading
Modulated LED Beam
Vin Vout
Recombination
1. Free carrier creation (by the light) and measurement of the junction photo-voltage signal.
2. Carrier spreading (proportional to Rs).
3. Carrier recombination (leakage current).
IMEC Round Robin for 10 to 100 nm Epi
4PP (WC and EM),Variable spacing 2-probeMicro-4PPRsLOnly RsL (and micro-4PP) are free of junction shorting effects.
4PPRsL
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SDE/Halo Integration: Sheet Resistance (1)
0100
200300
400500
600700
800
spike fRTPB
fRTPA
fRTPD
fRTPD+D
fRTPC
Rs,
Ohm
/sq
c-Sihalo+anneal
0100
200300
400500
600700
800
spike fRTPB
fRTPA
fRTPD
fRTPD+D
fRTPC
Rs,
Ohm
/sq
c-Sihalo+anneal
Tanneal: B<A<D<D+D<C
Ti=750°C+∆T =550°C(Tp=1300°C)fRTP D 1.5ms
Ti=750°C+∆T =600°C(Tp=1350°C)fRTP C 1.5ms
Ti=700°C+∆T=550°C(Tp=1250°C)fRTP B 1.5ms
Ti=700°C+∆T=600°C(Tp=1300°C)fRTP A 1.5ms
1050°C, 100 ppm O2 in N2Spike anneal
Ti=750°C+∆T =550°C(Tp=1300°C)fRTP D 1.5ms
Ti=750°C+∆T =600°C(Tp=1350°C)fRTP C 1.5ms
Ti=700°C+∆T=550°C(Tp=1250°C)fRTP B 1.5ms
Ti=700°C+∆T=600°C(Tp=1300°C)fRTP A 1.5ms
1050°C, 100 ppm O2 in N2Spike anneal
•B-USJ (0.5keV, 1015 cm-2 );•Ge - PAI (30keV, 1015cm-2);•As- HALO (40keV, 4*1013cm-2); ;•Halo implant annealing: 10 s at 1050C before the PAI or B implants
V. Faifer et al. Insight (USJ07)
Addition of halo profile to SDE increases Rs by ~35% (decreased Xj).
1E+14
1E+15
1E+16
1E+17
1E+18
1E+19
1E+20
1E+21
1E+22
0 100 200 300 400
Depth from Surface , A
Dop
antC
once
ntra
tion
(Ato
ms/
cm3 )
0.5 keV B
40 keV As
10 Ohm-cm p-Si
Xj for 10 Ohm-cm
Xj for halo
SRIM03
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Metrology Challenges for SDE/Halo (3)
200
300
400
500
600
700
0 20 40 60 80 100 120
Probe loading (g)
Shee
t Res
ista
nce
(Ohm
/squ
are)
20 Ohm-cm wafer
RsL
4PP40 keV As haloHalo anneal
0.5 keV B1050 C / 1 s anneal
4PP, no Halo
Lightly-doped (10 ohm-cm)substrates (wide depletion,low leakage) have close agreement between RsL and 4PP measurements.
Heavy-doped (Halo, ~5e18) substrates (narrow depletion,higher leakage) shows strongloading pressure shifts with4PP and higher RsL values.
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SDE/Halo Integration: Sheet Resistance (2)
P. Timans et al.
~1300 to 1375 C
~500 to 800 C
~1 ms
Time
Tem
pera
ture
~1300 to 1375 C
~500 to 800 C
~1 ms
Time
Tem
pera
ture
0
100
200
300
400
500
600
700
800
900
1000
1000 1100 1200 1300 1400
Peak Temperature (C)
Shee
t Res
ista
nce
(Ohm
/sq)
Spike (~1 s)
Flash (~1 ms)
Substrates:2 Ohm-cm Si: diamondsHalo profiles: squares
Flash conditions:Tbase = 700 C: open sysmbolsTbase = 750 C: filled symbols
0.5 keV B, 1015 B/cm2
halo
c-Si
RTP and ms-anneals show systematic effects of base and peak temperature and halo doping with RsL.
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Leakage Current: Effect of Halo Doping and PAI Energy
Wdepletion
Xjunction
halo/wellCarrier
recombinationTrap-assisted
tunneling
Surface dopingLeakage current mechanisms under forward bias (RsL) are:
* carrier recombination* trap-assisted tunneling.
Depletion layer thickness (Wdepletion) decreases with halo doping, increasing leakage current.
EOR damage within depletion layer increases leakage. EOR damage location depends on Ge PAI energy.
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Implants & Leakage
α-Si c-Si
As-implanted
Xj
W
np
EOR Damage
After anneal
EOR Depth for Ge PAI
EOR Depth (A) = 60.013*x0.6531
X-TEM
10
100
1,000
10,000
1 10 100
Ge Energy (keV)
<x> ± <∆x> for Ge in Si(SRIM03)
Dep
th in
Si (
A)
USJ Leakage Process Options
1
10
100
1000
1.E+14 1.E+15 1.E+16 1.E+17 1.E+18 1.E+19 1.E+20
Sub-junction Doping (atoms/cm3)
Depletion Layer Depth
EOR damage withindepletion layer:high leakage
EOR damage belowdepletion layer:low leakage
Dep
letio
n la
yer (
nm)
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0.5 KeV B, 1250-1325 C/ 10 ms
1.E-08
1.E-07
1.E-06
1.E-05
1.E-04
1.E-03
1.E-02
1.E-01
No Halo, No PAI
No Halo, PAI
Halo anneal, No PAI
Halo, PAI
Process ConditionsLe
akag
e C
urre
nt (A
/cm
2 )
1.1015 1.1016 1.10 17 1.10 18 1.10191.10 10
1.10 9
1.10 8
1.10 7
1.10 6
1.10 5
1.10 4
1.10 3
0.01
0.1
1
DOPING CONCENTRATION, dopants/cm3
LEA
KA
GE
CU
RR
EN
T, A
/cm
2
Nmax = 1018 traps/cm3
V= -1 V
V= -26 mV
V= +26 mV
1.1015 1.1016 1.10 17 1.10 18 1.10191.10 10
1.10 9
1.10 8
1.10 7
1.10 6
1.10 5
1.10 4
1.10 3
0.01
0.1
1
DOPING CONCENTRATION, dopants/cm3
LEA
KA
GE
CU
RR
EN
T, A
/cm
2
Nmax = 1018 traps/cm3
V= -1 V
V= -26 mV
V= +26 mV
SDE/Halo Integration: Leakage Current (1)Low leakage for no Halo.
High leakage for single Flash anneal for Halo/PAI/SDE.
Lower leakage for post-Haloanneal followed by flash anneal of SDE (with no PAI).
Upshot: Damage present before ms-scale anneals is not easily removed.
Integration of ms-anneals has large opportunity for leakage reduction.
M. Current et al. IIT06
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SDE/Halo Integration: Leakage Current (2)
1.E-08
1.E-07
1.E-06
1.E-05
1.E-04
1.E-03
1.E-02
1.E-01
1.E+00
1000 1050 1100 1150 1200 1250 1300 1350
Peak Temperature (C)
Leak
age
Cur
rent
(A/c
m2 )
c-SiPAIHalo + annealPAI + Halo + annealPAI + Halo
0.5 keV B, 1015 B/cm2
Spike (~1 s)
Flash (~1 ms)
Halo doping increases leakage .
Higher peak temp.
Reduces leakage.
(Increases Xj)
PAI increases damage.
(An opportunity for molecular & cluster ions)
J. Borland et al. IIT06
0.5 keV B B18H22
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n-SDE/ p-Halo Components; IWJT07
A. Mineji et al. (NEC, Nissin, Mattson) IWJT07
p-Halo with In give high leakage.p-Halo with B10 or BF2 is low leakage.
Combined SDE/Halo process next.
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Leakage Current: Epi layers
RsLVr=-0.05V
Vr=-1V
Vr=-1V
Vr=-0.05V
RsL
1016 1017 1018
10-9
10-6
10-3
Doping concentration, cm-3
Leak
age
curr
ent d
ensi
ty, A
/cm
2
.
IMPLANT
EPI
RsLVr=-0.05V
Vr=-1V
Vr=-1V
Vr=-0.05V
RsL
1016 1017 1018
10-9
10-6
10-3
Doping concentration, cm-3
Leak
age
curr
ent d
ensi
ty, A
/cm
2
.
IMPLANT
EPI
B
As
B
As
T. Clarysse (IMEC) et al. MRS06
10-3
2*10-3
3*10-3
0 500 1000 1500JUNCTION DEPTH, A
1/R
s, O
hm-1
10-6
10-4
10-2
Leak
age
curr
ent d
ensi
ty,
A/c
m2
10-3
2*10-3
3*10-3
0 500 1000 1500JUNCTION DEPTH, A
1/R
s, O
hm-1
10-6
10-4
10-2
Leak
age
curr
ent d
ensi
ty,
A/c
m2
10-3
2*10-3
3*10-3
0 500 1000 1500JUNCTION DEPTH, A
1/R
s, O
hm-1
10-6
10-4
10-2
Leak
age
curr
ent d
ensi
ty,
A/c
m2
1 / Rs = Xj / ρ
~8 nm “dead” layer
Epi-doped layers also have leakage current signatures.
Defects at growth interfaces impact activation & leakage.
Process issues for doped SiGe & Si-C strained epi.
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Leakage Currents in RsL and Transistors
Metal
Ox
S D
Metal Metal
G
******* *******
ThermionicEmission
Gate OxLeakage
Band-bandTunneling
EOR damage
Substrate
Well
SDEHalo
Depletion layer************************
Carrier Recombination
XjSDE
Metal
Ox
S D
Metal Metal
G
******* *******
ThermionicEmission
Gate OxLeakage
Band-bandTunneling
EOR damage
Substrate
Well
SDEHalo
Depletion layer************************
Carrier Recombination
Metal
Ox
S D
Metal Metal
G
******* *******
ThermionicEmission
Gate OxLeakage
Band-bandTunneling
Metal
Ox
S D
Metal Metal
G
******* *******
ThermionicEmission
Gate OxLeakage
Band-bandTunneling
EOR damage
Substrate
Well
SDEHalo
Depletion layer************************
Carrier Recombination
EOR damage
Substrate
Well
SDEHalo
Depletion layer************************
Carrier Recombination
EOR damage
Substrate
Well
SDEHalo
Depletion layer************************
Carrier Recombination
Substrate
Well
SDEHalo
Substrate
Well
SDEHalo
Depletion layer************************
Carrier Recombination
XjSDE
RsL (forward bias ~ +26 mV)RecombinationTrap-assisted tunneling
Transistors (reverse bias ~ -1 V)GenerationTrap-assisted tunneling Band tunnelingContact emissionGate leakage Sub-threshold current
J = Io(A/cm2) * (eqV/kT – 1)
RsL measures the “process dependent” (damage and doping) component of junction leakage, the recombination/ generation current amplitude, Io(A/cm2).
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Forward & Reverse Bias Leakage
1.E-08
1.E-07
1.E-06
1.E-05
1.E+16 1.E+17 1.E+18 1.E+19
Well/Halo concentration level (at/cm3)
Leak
age
curr
ent (
A/c
m2)
Reverse diodeleakageRsL leakage
RsL leakage (at +Vt) is slightly smaller than reverse bias leakage(including band-to-band tunneling), as expected.
1.1015 1.1016 1.10 17 1.10 18 1.10191.10 10
1.10 9
1.10 8
1.10 7
1.10 6
1.10 5
1.10 4
1.10 3
0.01
0.1
1
DOPING CONCENTRATION, dopants/cm3
LEA
KA
GE
CU
RR
EN
T, A
/cm
2
Nmax = 1018 traps/cm3
V= -1 V
V= -26 mV
V= +26 mV
1.1015 1.1016 1.10 17 1.10 18 1.10191.10 10
1.10 9
1.10 8
1.10 7
1.10 6
1.10 5
1.10 4
1.10 3
0.01
0.1
1
DOPING CONCENTRATION, dopants/cm3
LEA
KA
GE
CU
RR
EN
T, A
/cm
2
Nmax = 1018 traps/cm3
V= -1 V
V= -26 mV
V= +26 mV
T. Clarysse et al., Insight07 (USJ07)
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Junction Leakage in Transistors
J-P. Han et al. Infineon, IBM, Samsung Chartered, IEDM06
c-SiGe c-SiGe
c-Stress Liner
SDE SDE
Channel
40 nm p-MOS transistor
Area of SDE junction is ~2x channel area per transistor.
Junction leakage of ~10-2 A/cm2
exceeds entire operating limits for low-power devices (ITRS05).
Generation leakage currents are determined by implant residual damage and halo doping profiles, measured as recombination currents in RsL from 10-7 to >10-2 A/cm2.
10-6
10-4
10-2
1016 1017 1018
Trap concentration, cm-3
Leak
age
curr
ent d
ensi
ty A
/cm
2
RsL (+0.025 V)
Vr= -0.05V
Vr= -0.5V
Vr= -1V
10-6
10-4
10-2
1016 1017 1018
Trap concentration, cm-3
Leak
age
curr
ent d
ensi
ty A
/cm
2
RsL (+0.025 V)
Vr= -0.05V
Vr= -0.5V
Vr= -1V
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SDE/Halo Integration: Process Agenda
Doping: (Dose, energy, ion type, beam current/scan rate, wafer temperature, PAI, incident angle, anneal).
1. SDE & Halo ion type (single or multiple dopant ions).
2. Halo angle & dose (Xj effects).
3. Diffusion-less anneals: RTA & cocktails, SPE, Flash, Laser.
Damage: (Dose, energy, ion type, beam current/scan rate, wafer temperature, PAI, incident angle, anneal).
1. Damage accumulation & annealing (ion type, scan rate).
2. Impact of Halo dose & damage on leakage.
Relevant Metrologies: RsL (Rs, leakage), Transistors (Vt, Ion, Ioff)
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Goals: from T. Clarysse (IMEC)
22
• Improve our theoretical understanding of RsL• Develop an accurate JPV simulator for RsL• Gain better insights in RsL behavior under non
standard conditions through modeling (simulations)
62
218
Leakage (µA/cm2)
62
218
Leakage (µA/cm2)
Experimental
+
Simulations
=
INSIGHT !!
T. Clarysse et al., Insight07 (USJ07)
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IIT08 is a year away (June 2008) !
School: June 5-7, ‘08
Conference:June 8-13, ‘08
www.iit2008.com
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Coming also!
Ion Implantation Process EngineeringInteraction of IC Process,
Machines & Devices
Michael I. Current (and perhaps others)
A practical handbook for ion implantation, annealing and metrology for process controls.
Draft editions: late 2008.