EM Field Solver Modellingof Floating EUT Module Boardsin Automotive EMC Test Setups
S. Miropolsky, S. Jahn, F. KlotzAutomotive Power EMC Center,Infineon Technologies AG
Motivation and GoalsTest Stages / Levels in EMC-Aware Design
› IC / Chip-Level› Component-Level
› Vehicle-Level
22017-06-07 Copyright © Infineon Technologies AG 2015. All rights reserved.
Automotive Direct Power Injection TestEMC Testboard and Procedure
› RF disturbance is injectedinto the IC under test (DUT)
– dedicated EMC testboard withcoupling/decoupling networks
– monitoring of IC functionality
› RF immunity is the RF power level,which can be withstood by the ICw/o any malfunction
32017-06-07 Copyright © Infineon Technologies AG 2015. All rights reserved.
monitoring DUT output functions for possible IC malfunction under
RF disturbance
VRF DIFF : resulting RF disturbance amplitudethat has reached the IC pin (e.g. supply)
Useful DC / LF signals(e.g. the supply voltage)
are mixed withinjected RF disturbance
using CDNs* at EMC board
*: CDN: Coupling / Decoupling Network
DC
RF
DC+RF
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Frequency, Hz
RF
Imm
unity
Leve
l, dB
m
Example DPI RF ImmunityExample DPI Test Limit
RF power increased up to the test limit
w/o EUT malfunction
RF power increased until EUT failure
is monitored
DUT is fully functional
DUT malfunction takes place here
Automotive Bulk Current Injection TestEMC Test Setup and Procedure
› RF disturbance is injected usinga laboratory EMC test setup intoa complete system in operation
› RF immunity is the power level, which can be withstood by the EUT (as a part of the complete system under test) without any malfunction
42017-06-07 Copyright © Infineon Technologies AG 2015. All rights reserved.
LISN: line impedancestabilization network
peripheryequipment
DCcable harness
reference ground
injection clamp(transformer)
"EUT" – Equipment under Test
floating EUT module boardwith IC under test ("DUT“)
low-permittivitydielectric support
RF
useful LF signals (supply, comm., etc.)
+ CM RFNOISE
EUT malfunctionund RF injection?
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Frequency, Hz
RF
Imm
unity
Lev
el,
dBm
RF power limit (100 W amplifier + 3 dB att.)Calibrated RF power (200 mA @ 50R Term.)BCI measurement result
RF power was increased up to the test limit with no EUT malfunction
RF power was increased until EUT malfunction was monitored
EUT malfunction takes placeat certain frequencies
DC supply and ground are provided over cable, the EUT is “floating” for RF signals!!!
Motivation and goalsTransfer of results between different test levels?
› Main assumption, supported by multiple authors and research groups:
EMC failures are not directly caused by RF power injected into the system, but by the part of this RF power delivered to the DUT
› The DUT response is dependent on RF level(voltage, current or similar) at DUT IC pins
› The test setup is just a complex linear transfer function from RF signal source to the DUT IC
52017-06-07 Copyright © Infineon Technologies AG 2015. All rights reserved.
Common Mode(CM) RF injection
CM-DM conversion atimpedance asymmetries
Differential ModeDM RF power
at EUT interface
Direct RF Port Injection
Contents
› Motivation and goals
› Previous research
– White-box modelling method and experimental validation
– Drawbacks and open issues
› Black-box EM FS model for EUT module
› Edge ports definition and calibration technique
› Simulation and test result prediction
› Results and discussions
› Application example
62017-06-07 Copyright © Infineon Technologies AG 2015. All rights reserved.
DC supply
cable harness
reference ground
injectionclamp
RF injection
Test setup modelling(EMC Compo 2013, Nara, Japan)
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Frequency, Hz
S-P
aram
eter
s, d
B
S'41 (VNA, Fixtures)
S'41 (VNA, Sensor)
S'41 (Model)
VNA, Method #1VNA, Method #2Spice model
72017-06-07 Copyright © Infineon Technologies AG 2015. All rights reserved.
› Setup transfer function modeled
– on a modular basis– using only RLC circuits and MTL devices– with passive dummy in place of active IC
› Model validated with two independentS-parameter measurement approaches
› Setup TF including CM-DM conversion was reproduced with high accuracy!
A Generalized Accurate Modelling Methodfor Automotive BCI Setups up to 1 GHzS. Miropolsky, A. Sapadinsky, S. Frei, EMC Compo 2013, Nara, Japan
Experimental validation(EMC Compo 2015, Edinburgh, Scotland)
82017-06-07 Copyright © Infineon Technologies AG 2015. All rights reserved.
› Model extended and validated with an active demonstrator EUT module
Experimental Validation of the Generalized Accurate Modelling Method for Automotive BCI SetupsS. Miropolsky, S. Jahn, F. Klotz, S. Frei, EMC Compo 2015, Edinburgh, Scotland
DC supply
cable harness
reference ground
injectionclamp
DUT IC: mass-market 5V voltage regulator Min. amount of ext. passive componentsDefined output voltage tolerance: ±100 mV
VVS-RF
h = 50 mm
floating EUT ground plane
reference ground(metal plane)
optically-decoupled monitoring of output voltage
CM RF injectionwith BCI setup
› High accuracy of the proposed methods was confirmed!
Bulk Current Injection experimentPrediction of BCI test results
› RF amplitude at VS pin
– simulated for a constant RF power of 47 dBm
– ... and plotted over the IC failure threshold
› Should the RF amplitude exceed the threshold, IC malfunction in a system-level test is expected
› Failure level below test limitcan be roughly estimated as
VVS-RF-Fail – VVS-RF
(in dB scale)
92017-06-07 Copyright © Infineon Technologies AG 2015. All rights reserved.
107 108 109-60
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0
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Frequency, Hz
RF
Vol
tage
Am
plitu
de,
dBV
VVS-RF, white-box EUT model
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Frequency, Hz
RF
Vol
tage
Am
plitu
de,
dBV
VVS-RF-Fail (DUT Failure Threshold)VVS-RF, white-box EUT model
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Frequency, Hz
RF
Vol
tage
Am
plitu
de,
dBV
VVS-RF-Fail (DUT Failure Threshold)VVS-RF, white-box EUT model, pass pts.VVS-RF, white-box EUT model, fail pts.
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Frequency, Hz
RF
Imm
unity
Lev
el,
dBm
Max. RF power level (PFWD = 47 dBm)EUT RF immunity, measurement (reference)
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Frequency, Hz
RF
Imm
unity
Lev
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Max. RF power level (PFWD = 47 dBm)EUT RF immunity, measurement (reference)EUT RF immunity, white-box EUT model
Contents
› Motivation and goals
› Previous research
– White-box modelling method and experimental validation
– Drawbacks and open issues
› Black-box EM FS model for EUT module
› Edge ports definition and calibration technique
› Simulation and test result prediction
› Results and discussions
› Application example
102017-06-07 Copyright © Infineon Technologies AG 2015. All rights reserved.
General Model Concept:Distributed RLC Impedance Network
› The complete system including all sub-components is represented with a distributed RLC impedance network
112017-06-07 Copyright © Infineon Technologies AG 2015. All rights reserved.
Drawbacks of previous research
› Both model and study case too academic:
– RLC- and MTL-based circuit concepts – are effective for modelling of passive setup parts (cables, clamps, etc.)– are hardly applicable to realistic EUT boards with complex layouts
– A more generic approach necessary: EM field solver?
› EM field solvers not really applicable for complete EMC setups
– Neither exact geometry data nor the material EM properties (cable isolation, ferromagnetic clamp core, etc.) are known
– Generic modelling with rough evaluation is possible, but– No accuracy in HF range should be expected
› RLC model for the setup + EM FS model for the EUT board?
– Where to make the cut between RLC- and EM FS models?– How to define this cut?
122017-06-07 Copyright © Infineon Technologies AG 2015. All rights reserved.
Contents
› Motivation and goals
› Previous research
– White-box modelling method and experimental validation
– Drawbacks and open issues
› Black-box EM FS model for EUT module
› Edge ports definition and calibration technique
› Simulation and test result prediction
› Results and discussions
› Application example
132017-06-07 Copyright © Infineon Technologies AG 2015. All rights reserved.
EM Model of the demonstrator EUT module3D Structure and RF Ports Definitions
142017-06-07 Copyright © Infineon Technologies AG 2015. All rights reserved.
Dielectric layer 3, Airε =1.0, lossless
h = infinite
Top-Btm VIA (Cu)
Reference ground, PEC
Top metal, Cuσ = 5.8e7 S/mh = 35 um
Bot. metal, Cuσ = 5.8e7 S/mh = 35 um
Dielectric layer 2, FR4ε =4.8, TanD = 0.02
h = 1.5 mm
Dielectric layer 1, Airε =1.0, losslessh = 50 mm (*)
* technically 3 stacked layers with total height of 50 mm
ex po
h = 50 mm
reference ground plane
DUT ICports
SMDports
SMD port
RC filterSMD ports
monitoringprobe ports (calibrated)
P1 (QT P2 P5P6
P7
P8P9
P3 (QTML)
P4
P10
P11
EUT board layout Vertical stack-up
EUT 3D structure reconstructedby the EM field solver
Local diff. ports defined in place
of all components
Single-ended ground-referenced RF ports are defined at the board edges for connection to the cable
and monitoring probe
floating configuration is modeled with an additional dielectric
layer below the board
EM Simulation Model IssueHow to Define Edge Ports?
› Direct EM simulation returns non-physical S-parameters
– No issues with small-size local differential ports at board level
– Major issue with edge ports for external connections
› RF ports between the floating EUT and reference groundare non-physical due to large pin-to-pin distance (50mm)!
› Special calibration techniques necessary to define such ports
– Well-known technique is TML port calibration
– Similar technique called quasi-TML is used here
152017-06-07 Copyright © Infineon Technologies AG 2015. All rights reserved.
Contents
› Motivation and goals
› Previous research
– White-box modelling method and experimental validation
– Drawbacks and open issues
› Black-box EM FS model for EUT module
› Edge ports definition and calibration technique
› Results and discussions
› Application example
162017-06-07 Copyright © Infineon Technologies AG 2015. All rights reserved.
Conventional TML Port Calibration(e.g. as implemented in Agilent ADS (TM))
› RF port is connected to the analyzed structureusing an RF feed line
– Feed line is calibrated with an independent simulation run
– Feed line properties are removed from the simulated SNP dataset
– After deembedding is performed, the RF port results to be connected directly to the structure
172017-06-07 Copyright © Infineon Technologies AG 2015. All rights reserved.
› Primary purpose:
– Emulate the effects of the structure transition into a TL of specified cross-section
– Remove the local stray field effects at the port location
› How does it help in our case?
Source: Agilent ADS Online Documentationhttp://edadocs.software.keysight.com/display/
/ads2011/Using+Calibrated+Ports
RF Feed Line with Ground FixturesCalibration Structure and Principle
› Same principle can be applied manually with a subtle change:
– Use an explicitly defined perfect electrically conducting (PEC) feed line with ground fixtures
– Port pin distance is now smalland not an issue anymore
› Manual feed line calibration?
– R and G are negligible due to PEC material properties
– Per-unit-length (p.u.l.) L', C'
– Unknown local offsets ΔL and ΔCdue to presence of the fixtures
– All properties can be extracted from SNP simulation data for several structure lengths
182017-06-07 Copyright © Infineon Technologies AG 2015. All rights reserved.
reference ground plane
PEC feed line to be cali
h = 50 mmgrounded
fixtures(PEC)
P1
+Δ L+Δ С
RLCG: L'×l, C'×l,
l = 100, 150, 200 mm
P2
R=0, G=0 +Δ L+Δ С
groufixtu
(PEC)
(
l [mm]
X: L [nH] or C [pF]
X1
X2
X3
2ΔX
X'
l1 l2 l3
Feed line LC properties calibration principle:
– Simulate S2P data for three structure lengths– Extract total loop RLCC properties – Plot extracted values vs. structure length– Fit linearly and extrapolate to zero length
EM Simulation of Floating EUT Boardwith a Feed Line and the deembedding of the latter
› Final structure is simulated together with the feed line› Feed line effect is removed with two-step de-embedding› Resulting S-parameters describe the sought floating EUT board
192017-06-07 Copyright © Infineon Technologies AG 2015. All rights reserved.
reference ground plane
h = 50 mmgrounded
fixture(PEC)
L'×l, C'×l ΔLΔС
l = 50 mm
pre-calibrated feed line (PEC)
EUT board2.5/3D model
diff. port(s) for local node(s) at the tips of signal lines at floating EUT board edge referencing to the feed line
feed line
floating ground plane
P1
P2
(a)
EUT board2.5/3D model
return current of cal. RF port
reference ground plane
floating ground plane
quasi-TM gr
P2
P1(QTML)
(b)
soughtfloating EUT
network
(SP dataset)P1
P2
P1
RF feed by cas
LC valu
RF feed line effects are assumed tobe present in the simulated networkin form of two lossless TL networks
A-A B-B
complete simulated network (S-parameter dataset)
–L' ∙l, –C' ∙llossless
–ΔL, – ΔСlossless
ΔL, ΔСlossless
L' ∙l, C' ∙llossless
TLTLTLTL
feed line effect remova
P1(QTML)
P2 P2
P1
deemb.
soughtfloating EUT
network
(SP dataset)
(b)
Contents
› Motivation and goals
› Previous research
– White-box modelling method and experimental validation
– Drawbacks and open issues
› Black-box EM FS model for EUT module
› Edge ports definition and calibration technique
› Simulation and test result prediction
› Results and discussions
› Application example
202017-06-07 Copyright © Infineon Technologies AG 2015. All rights reserved.
Final system-level simulationusing EM FS macromodel for floating EUT
212015-11-05 Copyright © Infineon Technologies AG 2015. All rights reserved.
› EUT SNP data is processed in a standard way (e.g. Vector Fitting)
› EUT macromodel is connected to the system-level (RLC) setup model
› IC model is connected to the local differential ports of EUT macromodel
› Local RF signal levels in a system-level test can now be estimated with AC simulation and the test result prediction can be made
DUT ICsmallsignalmodel
effect of the stray field at the 'open'floating ground edge (missing dueto quasi-TML edge ports calibration)
monitoring probeimpedance modelZProbeIn(C ≈ 3.5 pF)
ZProbeGnd(C ≈ 2.5 pF)Сstray
(≈ 0.5pF)
RF power injectiointo the RF portof coupling clam
"local" RF disturbanceat DUT IC supply pins
PFWD
setu
p
EUT
Open-LooBCI setup
circuit m
P1 REF
P4
P5
REF
P2+
P2–P1
REF
P4+
P4–P3
REF
Floating EUT board macromodel
P5–
P5+
P6–
P6+
incl. passive RC SMD componentimpedances and local parasitics
reference ground
VVS-RF
Bulk Current Injection experimentPrediction of BCI test results
› Same prediction procedureas performed before withthe white-box RLC model
... is now performed withthe proposed black-box model
› Black-box EM FS EUT modelreturns the same results up to insignificant deviations
› Modelling method is applicable to more complicated realistic EUT layouts!
222017-06-07 Copyright © Infineon Technologies AG 2015. All rights reserved.
107 108 109-60
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Frequency, Hz
RF
Vol
tage
Am
plitu
de,
dBV
VVS-RF-Fail (DUT Failure Threshold)VVS-RF, white-box EUT model, pass pts.VVS-RF, white-box EUT model, fail pts.
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Frequency, Hz
RF
Imm
unity
Lev
el,
dBm
Max. RF power level (PFWD = 47 dBm)EUT RF immunity, measurement (reference)EUT RF immunity, white-box EUT model
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Frequency, Hz
RF
Vol
tage
Am
plitu
de,
dBV
VVS-RF-Fail (DUT Failure Threshold)VVS-RF, white-box EUT model, pass pts.VVS-RF, white-box EUT model, fail pts.VVS-RF, black-box EUT model, pass pts.VVS-RF, black-box EUT model, fail pts.
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Frequency, Hz
RF
Imm
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Lev
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Max. RF power level (PFWD = 47 dBm)EUT RF immunity, measurement (reference)EUT RF immunity, white-box EUT modelEUT RF immunity, black-box EUT model
Summary
› Previously-developed white-box setup model (up to EUT interface)
– Physically-reasonable models, parameter variations possible
– Modular structure, easy changes in setup configuration
… is now extended with a Black-Box EM FS EUT model
– Black-box EUT model shows the same or similar accuracy as the reference white-box RLC+MTL EUT model used before
– Handling arbitrary (also realistic) EUT board layouts possible
– Possible issues with external RF port definitions are solved with the proposed quasi-TML port calibration technique
232017-06-07 Copyright © Infineon Technologies AG 2015. All rights reserved.
Artificial Network
PeripheryEquipment
DC Supply
DC Ground
Cable harness
Reference Ground
InjectionClamp
RF InjectionFloating ungrounded Demonstrator EUT
Application Example
› Apply the model to make the given demonstrator EUT module robust?
242017-06-07 Copyright © Infineon Technologies AG 2015. All rights reserved.
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Frequency, Hz
RF V
olta
ge A
mpl
itude
, dBV
VVS-RF-FailVVS-RF CVS=100nFVVS-RF CVS=100+10nFVVS-RF CVS=100+10+1nFVVS-RF > VVS-RF-Fail
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Frequency, Hz
RF V
olta
ge A
mpl
itude
, dBV
VVS-RF-FailVVS-RF CVS=100nFVVS-RF C1[AC]=100nF,10nFVVS-RF C1[ABC]=100,10,1nFVVS-RF > VVS-RF-Fail
Typical solution: add more blocking capacitors of smaller valuese.g. 100 nF + 10 nF + 1 nF => Still insufficient!
Alternative solution:Exploit the trace inductance to build a pi-filter=> Local RF disturbance decreases
below IC failure threshold!
Measurement instrumentationfor floating ungrounded nodes
› VNA S-parameter measurements at floating nodes– Measurement performed using
pre-characterized test fixtures
– Fixtures are deembeddedup to the device edge
– Single-ended ports converted to floating differential port
– Resulting floating diff. porthas no ground reference
› Methodic successfully verified on several test cases
262015-11-05 Copyright © Infineon Technologies AG 2015. All rights reserved.
Demonstrator EUT module
› Active 5V voltage regulator DUT IC
› Minimal external circuitrysufficient for IC operation
– EMC protection capacitors
(with an alternative cap. location with different total ESL value)
– Resistive load of 470R (10 mA)
– RC filter for output DC level monitoring
› Traces routed up to PCB edge
– Cable harness soldered directlyto the trace pads at board level
EMC Protection Capacitors
DUT: Voltage Regulator IC Resistive
load
<C1>100 nFlow-ESL
<C2>100 nF
high-ESL
C310 nF
RL470Ω
Traces with Z0 ≈ 50 Ω in top layer Continuous ground plane in bottom layer
Low-pass filterfor DC output
monitoring
RF10 kΩ
CF1 nF
LPCB ≈ 50 mm
WPC
B≈
40
mm
ExternalDC supply
with RF CW disturbance
Monitored DC outputlevel
272015-11-05 Copyright © Infineon Technologies AG 2015. All rights reserved.
DUT IC small-signal modelVNA S-parameters characterization
› S-parameters characterization › DC supply and resistive
load attached using ext.Bias Tee’s
› Two-port S-parameters measured with VNA
› SMA ports and traces aredeembedded up to IC pins
› VectFit-Macromodelingprocedure is applied to S-parameters data
› Macromodel shows the samelinear electrical behaviour as the original S-dataset
PCB is thoroughly grounded
Final ICdataset
Calibrationplane for P1
Calibrationplane for P2
Deembedding planes(P1, P2)
Supply voltageapplied usinga Bias Tee
Load attached using a Bias Tee
PCB tracesdeembedded
up to IC pins
P1 P2P1 P2
282015-11-05 Copyright © Infineon Technologies AG 2015. All rights reserved.
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Frequency, Hz
S-P
aram
eter
s, d
B()
S11 (deemb. VNA data)S22 --- // ---S21 --- // ---S12 --- // ---
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0
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Frequency, Hz
S-P
aram
eter
s, d
B()
Smn (deemb. VNA data)
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0
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Frequency, Hz
S-P
aram
eter
s, d
B()
S11 (VectFit macromodel)S22 --- // ---S21 --- // ---S12 --- // ---Smn (deemb. VNA data)
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0
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Frequency, Hz
S-P
aram
eter
s, d
B()
Smn (deemb. VNA data)
DUT IC small-signal modelVectFit macromodel generation
› Vector Fitting (VectFit) approximation applied to S-parameter dataset
› Data are approximated with a set of rational functions in state-space form
› Approximated functions are implemented as a eq. circuit
– RC-networks as coefficients
– VCVS / VCCS as operators
› VectFit macromodels …
… show the same linear electrical behaviour as the original S, Y or Z-dataset
… also for non-50Ω systems with any ext. impedances and sources
a1=v1+ z0⋅i1
2√z0x⃗ '= A⋅⃗x+ B⋅⃗a
b= C⋅⃗x+ D⋅⃗ab1=
v1− z0⋅i1
2√z0
a 2=v2+z0⋅i2
2√z0
b2=v2−z0⋅i2
2√z0
Macromodel CorePort 1 Equation Port 2 Equations
v1
i1
v2
i2
Z0
a1
b1
a2
b2
iS1 iS1 = 2b1/√z0 iS2 =2b2/√z0
VectFit-Approximated .sNp Transfer Function
in State-Space Form
Z0
iS2
292015-11-05 Copyright © Infineon Technologies AG 2015. All rights reserved.
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Frequency, Hz
S-P
aram
eter
s, d
B()
S11 (VectFit macromodel)S22 --- // ---S21 --- // ---S12 --- // ---Smn (deemb. VNA data)
DUT IC small-signal modelVectFit macromodel verification
› Fitting of S-parameters doesn’t yet imply the model accuracy
› Several verification steps are performed with macromodels
– Z-parameter decomposition(open-circuit signal transfer)
– Y-parameter decomposition(short-circuit signal transfer)
– Pi- or T-circuit decomposition
Model impedances to groundand pin-to-pin are extractedand compared vs. orig. data
› Pass in all representations
› Macromodel may be used for further simulations
S2P Dataset Lumped-Pi-Circuit
S21,12
S11 S22 ZIN
1
ZIN
2
ZTR21,12
P1 P2 P1 P2
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Frequency, Hz
Impe
danc
e, d
BO
hm
ZIn1 (VectFit Model) ZIn2 --- // --- ZTr21 (VectFit Model) ZTr12 --- // --- Z[all] (Deemb. VNA data)
ZIN1
ZIN2
ZTR21
ZTR12
302015-11-05 Copyright © Infineon Technologies AG 2015. All rights reserved.
DUT IC failure thresholdIC-level DPI measurement
› Customized DPI setup
– RF wave is mixed with DC supply using a Bias Tee
– Output DC level monitored through the RC filter
Pass: ∆VOUT < 100 mV
– Measurement repeated for two EMC capacitor locations(“good” C1 and “bad” C2)
– RF level at IC pin captured with a HF active probe
PCB is thoroughly grounded
RF voltage amplitudeat IC pin measuredusing an active probe
to monitoring oscilloscope
C1C2 C3
RL CF
RF
312015-11-05 Copyright © Infineon Technologies AG 2015. All rights reserved.
Measurement repeated for two alternative capacitor locations:
(a) C1, 100 nF, low-ESL(b) C2, 10 nF, high-ESL
Direct injection of theRF wave + DC levelmixed with Bias Tee
DC outputmonitored
through an RC low-pass
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Frequency, Hz
RF
Imm
unity
Lev
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dBm
RF Immunity, DPI, with SMD Cap С1RF Immunity, DPI, with SMD Cap С2Smoothed interpolated data
RF voltage amplitudeat IC pin measuredusing an active probe
DUT IC failure thresholdIC failure threshold extraction
› RF signal amplitude at VS supply pin is capturedat all failure points
VVS-Fail(F) = 0.4 … 1.2 VPk
› IC failure occurs at the same RF voltage amplitude for both EMC cap. locations
For a different cap. locationa different RF power level is necessary to achieve the same RF voltage level at IC pin, but the IC failure occurs first, whenthis RF voltage at pin is reached
› This RF amplitude is storedas the IC failure threshold
322015-11-05 Copyright © Infineon Technologies AG 2015. All rights reserved.
PCB is thoroughly grounded
C1C2 C3
RL CF
RF
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Frequency, Hz
RF
Vol
tage
Am
plitu
de,
Vpk
VVS-RF, DPI, with C1, HF probe measurementData points where IC failure not reached
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Frequency, Hz
RF
Vol
tage
Am
plitu
de,
Vpk
VVS-RF, DPI, with C1, HF probe measurementVVS-RF, DPI, with C2, HF probe measurementData points where IC failure not reached
107 108 1090.0
0.2
0.4
0.6
0.8
1.0
1.2
Frequency, Hz
RF
Vol
tage
Am
plitu
de,
Vpk
VVS-RF, DPI, with C1, HF probe measurementVVS-RF, DPI, with C2, HF probe measurementData points where IC failure not reachedVVS-RF-Fail - expected IC failure threshold