Download - Emitter Coupled Logic (ECL)
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A Presentation On Emitter Coupled Logic
Course Title: Digital Electronics and Pulse Techniques
Course No: ECE 2203
Presented To:Shakila NazninLecturerElectronics & Communication Engineering DisciplineKhulna university,Khulna.
Presented By:Group 2Student ID:120902,120928,1209332nd Year 2nd TermElectronics & Communication Engineering DisciplineKhulna university,Khulna
Date of Presentation: 08 Sep, 2014
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Emitter
Coupled
Logic
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ECL Vs Others Logic Gate
Differential amplifier configuration
Taking cut-off & active modeLower time delayTaking negative voltage
supply
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Why ECL?More speedySmall voltage swingFastest switchingConstant current supplyNoise immunity
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Disadvantages Low fan-out Input-Output voltage
variation not matching
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Basic circuit diagram of ECL
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Basic operation of ECL:
All voltage are negativeMore negative= Logic lowLess negative=Logic high
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VR>VA,VB
VA,VB>VR
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A B Y1
0 0 1
0 1 0
1 0 0
1 1 0
Y1
A B Y2
0 0 0
0 1 1
1 0 1
1 1 1
Y2
NOR
OR
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Why it is more speedy?
When, IE1 is 95% of Io
VA=VR+75mV
And IE1 is 5% of Io VA=VR-75mV
VA=VR±75mV
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If this circuit drives N similar gates then output current will be N*I0/β
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HOW TO SOLVE THE PROBLEM
?
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Previous circuit diagram:
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Emitter follower is used
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Solving the problem of fan-out
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Why negative voltage supply used
?
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330 ohm
1.5k
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V01
V02
Noise margin circuit
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V01 ≈ 0
V02 ≈ Vn
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Thank you
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Any question please