eSi-CFAR
eSi-CFAR
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1 Contents
1 Contents _____________________________________________________________ 2 2 Overview _____________________________________________________________ 3 3 Hardware Interface _____________________________________________________ 4
3.1 Constraints on Input Parameters ________________________________________ 6 4 Core Internal Lateny ____________________________________________________ 8 5 Architecture __________________________________________________________ 9
5.1 Choosing algorithm parameters ________________________________________ 10 5.2 Theoretical formulas for False Alarm and Detection Probabilities in the CFAR
algorithms assuming Swerling 2 clutter model __________________________________ 11 5.3 Scilab Scripts for computing DP and the π· threshold scaling parameter _________ 11
6 Simulation Models and RTL Verification ____________________________________ 13 7 References __________________________________________________________ 14 8 Revision History ______________________________________________________ 18
eSi-CFAR
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2 Overview
The eSi-CFAR Contant False Alarm Rate core is a high throughput IP core, whose main
application area is target detection in radar systems. It is normally applied post-FFT in order to
scan output bins for targets in noise, with a pre-designed False Alarm (FA) probability. Pre-
screening the FFT output bins in hardware reduces substantially the size of data transfers to
the embedded processing system, and equally reduces computationally intensive embedded
processing load.
eSi-CFAR supports the following features:
Can accept a new data sample per clock cycle, making it suitable for interfacing with
Pipelined FFT cores.
Can processes data blocks with no clock-cycle gaps between them.
Parameterised input linear power samples (max 64 bits).
Generalised Ordered Statistic (GOS) CFAR algorithms [1,2]:
o GOS Cell Averaging (CA) β CFAR;
o GOS Greatest Of (GO) β CFAR;
o GOS Smallest Of (SO) β CFAR;
Cell Averaging (CA) CFAR algorithms [1]:
o Classical CA β CFAR;
o Greatest of (GO) CA - CFAR;
o Smallest of (SO) CA β CFAR;
Cell Averaging Statistic Hofele (CASH) CFAR algorithms [5]
Concurrent operation of CASH/CA-CFAR core and GOS-CFAR core
Conversion of linear input power samples in log2 (16-bit) domain
Real-time configuration of algorithm parameters.
Equivalent processing in logarithmic domain for reduced area and power use.
Macro based configuration between asynchronous/synchronous resets.
eSi-CFAR
Figure 1: eSi-CFAR
Clock
core config. parameters
CFAR Engine
Binary target
detection flag (per bin)
Linear power
samples
Register reprogram
Log2-domain power sample
Log2-domain
detection threshold
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3 Hardware Interface
Module Name cfar_top
HDL Verilog
Technology Generic
Source Files cfar_top.v, log_conversion_pipe64.v, gos_cfar_log.v, sorter.v,
log_combining.v, cash_ca_cfar.v, cell_averaging.v, min.v,
esi_sync_small_fifo.v, esi_include.v, esi_cfg_include.v
Parameter Range Default Description DATA_WIDTH_IN 4-64 64 Input data bit width. DATA_WIDTH_OUT 16 16 Output data bit width. WIND_SIZE 2- 32 Maximum leading/lagging window sizes in
GOS/CA/CASH-CFAR algorithms. Maximum range
parameter value is unspecified but constrained by
ASIC area usage or FPGA resources. WIND_INDEX_WIDTH 1- 5 Parameter is determined as
ceil[log2(SORT_WIND_SIZE)].
Table 1: Parameters
eSi-CFAR
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Port Directi
on
Width Description
clk Input 1 clock reset_n Input 1 active low reset
Common CFAR Inputs cfar_algo_select Input 2 Select CFAR algorithm:
0 = CFAR disabled,
1 = GOS-CFAR enabled,
2 = CASH/CA-CFAR enabled,
3 = Both GOS and CASH/CA-
CFAR enabled. sample_in_valid Input 1 Active high input sample valid sample_in Input DATA_WIDTH_IN Linear power input sample register_reprogram Input 1 Active high signal to be pulsed at
least for 1 clock cycle in order for
the core to capture internally
configuration parameter values. block_length Input 16 Number of samples in a block
(FFT bins).
GOS-CFAR Inputs gos_index_lead Input WIND_INDEX_WIDTH Index of sorted statistic in
leading window in GOS-CFAR. gos_index_lag Input WIND_INDEX_WIDTH Index of sorted statistic in
lagging window in GOS-CFAR. gos_window_cells Input WIND_INDEX_WIDTH+1 Number of active cells in
leading/lagging windows to be
sorted in GOS-CFAR. Should be
less than or equal to WIND_SIZE. gos_beta Input DATA_WIDTH_OUT Additive constant scaling the
GOS-CFAR threshold. Unsigned
number with 7 integer bits and 9
fractional bits. gos_cfar_mode Input 2 type of GOS-CFAR to be applied:
0 = GOSCA-CFAR,
1 = GOSGO-CFAR,
2/3 = GOSSO-CFAR. gos_guard_cells Input WIND_INDEX_WIDTH+1 Number of guard cells in GOS-
CFAR leading and lagging the cell
under test.
CASH/CA-CFAR Inputs cash_window_cells_exp Input 3 Exponent of 2 for defining the
number of active cells in
leading/lagging windows to be
averaged in CASH/CA-CFAR.
2^(ca_window_cells_exp) should
be less than or equal to WIND_SIZE.
cash_beta Input DATA_WIDTH_OUT Additive constant scaling the
CASH/CA-CFAR threshold.
Unsigned number with 7 integer
bits and 9 fractional bits. cash_cfar_mode Input 2 type of CASH/CA-CFAR to be
applied:
0 = CASH-CFAR,
1 = CA-CFAR,
2 = CAGO-CFAR,
3 = CASO-CFAR.
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cash_guard_cells Input WIND_INDEX_WIDTH+1 Number of guard cells in
CASH/CA-CFAR leading and
lagging the cell under test. cash_subwindow_cells_
exp Input 3 Exponent of 2 for defining the
number of active cells in
subwindows to be averaged in
CASH-CFAR. Should be set equal
to βcash_window_cells_expβ for
CA/CAGO/CASO CFAR.
GOS-CFAR Outputs gos_sample_out_valid Output 1 Active high valid signal on coreβs
GOS-CFAR outputs. gos_sample_out Output DATA_WIDTH_OUT Log2-domain power sample of
input to the GOS-CFAR core,
delayed by the latency of the
core. gos_threshold Output DATA_WIDTH_OUT Log2-domain detection threshold
value in the GOS-CFAR core. gos_thresh_decision Output 1 0 if (gos_sample_out <
gos_threshold),
1 if (gos _sample_out >=
gos_threshold).
CASH/CA-CFAR Outputs cash_sample_out_valid Output 1 Active high valid signal on coreβs
CASH/CA-CFAR outputs. cash_sample_out Output DATA_WIDTH_OUT Log2-domain power sample of
input to the CASH/CA-CFAR core,
delayed by the latency of the
core. cash_threshold Output DATA_WIDTH_OUT Log2-domain detection threshold
value in the CASH/CA-CFAR core. cash_thresh_decision Output 1 0 if (cash _sample_out <
cash_threshold),
1 if (cash_sample_out >=
cash_threshold).
Table 2: Interface I/O Ports
3.1 Constraints on Input Parameters
This section provides some additional information on selecting valid values for the input signal
parameters given in Table 2.
- block_length:
o Min value tested in simuations = 16
o Max value tested in simulation = 32,768
o As a general rule min value must be greater than or equal to the total length of
the CFAR processing window. This includes leading/lagging sub-windows,
leading/lagging guard cells and the cell under test.
- gos_window_cells:
o Min value tested in simuations = 1
o Max value tested in simulation = 32
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o The min possible value is 1
o The max possible value is WIND_SIZE
- gos_index_lead , gos_index_lag:
o Min possible value is 0
o Max possible value is βgos_window_cells-1β
- gos_beta:
o Min possible value is 0
o Max possible value is 32,767
- gos_guard_cells:
o Min possible value is 0
o Max possible value is 31
- cash_window_cells_exp:
o Min value tested in simuations = 1
o Max value tested in simulation = 5
o The min possible value is 1
o The max possible value is log2(WIND_SIZE)
- cash_subwindow_cells_exp:
o Should be set = βcash_window_cells_expβ for CA/CAGO/CASO CFAR
o Min value for CASH CFAR = 0
o Max value for CASH CFAR = βcash_window_cells_expβ
- cash_beta:
o Min possible value is 0
o Max possible value is 32,767
- cash_guard_cells:
o Min possible value is 0
o Max possible value is 31
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4 Core Internal Lateny
eSi-CRAR can accept a new valid input sample per clock cycle. It is also capable of handling a
streaming mode, where there are no clock cycle gaps between concecutive input (FFT) data
blocks.
The coreβs internal latency depends on the selected CFAR algorithm; GOS-CFAR or CASH/CA-
CFAR. For the GOS-CFAR algorithms the latency does not depend on the βgos_cfar_modeβ
input. On the other hand for the CASH/CA-CFAR algorithms, the latency does depend on
βcash_cfar_modeβ input.
The expressions for computing the internal latencies are given as1:
GOS-CFAR algorithms (all modes) :
Latency = (gos_window_cells + gos_guard_cells) * I + 19 cycles
CASH-CFAR algorithms (cash_cfar_mode = 0) :
Latency = [2^(cash_window_cells_exp) + 2^(cash_subwindow_cells_exp) +
cash_guard_cells] * I + 21 cycles
CASH-CFAR algorithms (cash_cfar_mode = 1,2,3) :
Latency = [2^(cash_window_cells_exp) + 2^(cash_subwindow_cells_exp) +
cash_guard_cells] * I + 18 cycles
where I = (clock cycles per input sample)
I = 1 means that there are no clock cycle gaps between valid input samples,
I = 2 means that there is 1 clock cycle gap between valid input samples,
I = 3 means that there is 2 clock cycles gap between valid input samples,
and so on
It is noted that the above expressions assume that the clock cycle gaps between input valid
samples are fixed according to the value of I.
1 For I>1 , i.e. when there are clock cycle gaps between valid input samples, these expressions may not
apply for the very first output sample, but apply for the remaining samples in the output block. These expressions may also vary by a few clock cycles for short block_length frames with gaps.
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5 Architecture
The CFAR algorithms supported within esi-CFAR are based on the generic processing
architecture shown in Figure , which is discussed in [1].
Figure 2: Generic CFAR processing Architecture
Linear power samples input to the core are converted into 16bit-width log2 power samples.
The log2 samples constrain the processed sample bit-width to 16, representing a maximum
linear power bit width of 64. Logarithmic power samples are stored in unsigned fixed point
fractional format with 9 fractional bits.
As shown in Figure 2, input power samples are shifted through the processing window, which
consists of lagging and leading sub-windows, guard cells and the central Cell Under Test
(CUT). The CUT value is compared to a generated threshold value from the CFAR signal
processor in order to make a target detection decision.
In the GOS-CFAR algorithms, the samples within the leading/lagging windows are processed
through a non-linear sorting operation and selected ordered statistics: π1, π2 are extracted
from the two sub-windows, respectively. The GOSCA, GOSGO, and GOSSO algorithms, which
were initially reported in [2], as an improved generalisation of the OS-CFAR [3], differ in the
manner π1, π2 are combined:
GOSCA: π = π1 + π2 (1)
GOSGO: π = max {π1, π2} (2)
GOSSO: π = min {π1, π2} (3)
The resulting statistic π is finally scaled by the πΌ scaling factor in order to determine the
threshold value. The value of the πΌ parameter determines the probabilities of False Alarm (FA)
and Missed Detection (MD), and need to be set accordingly by the user.
For the GOSGO and GOSSO algorithms the log2-domain input power sample implementation is
directly equivalent to the linear one, since both the sorting and max/min operations produce
equivalent (log2-domain) values for π. The only difference is that the threshold value is
produced by scaling π additively with π½ = πππ2 πΌ. On the other hand a direct log2-domain
implementation of the GOSCA algorithm is not normally equivalent to the linear-domain
implementation, since log2(π1 + π2) β log2(π1) + log2(π2). However in esi-CFAR an equivalent
log2-domain result to the linear domain one is obtained by post processing.
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In the CASH and CA-CFAR algorithms the π1, π2 stastics are produced through sample
averaging over the leading and lagging windows respectively. Averaging is performed in the
linear power domain and conversion in log2-domain is performed prior to the application of the
non-linear/linear operation as shown in Fig.2. In CASH-CFAR, the log2-converted averaged
power samples are processed through MAX and MIN operations, as described in [5] and
associated patents. On the other hand, in CA/CAGO/CASO-CFAR the log2-domain processing is
similar to the GOS-CFAR as per (1)-(3)2. As with the GOS-CFAR, threshold scaling in
CASH/CA-CFAR is performed additively using π½ = πππ2 πΌ.
As discussed in Section 2, the eSi-CFAR allows real-time reconfiguration of the algorithm
parameters through the APB interface:
CFAR algorithm; GOS-CFAR or CASH/CA-CFAR, or both
Processed block size
Leading/Lagging window sizes3
Number of guard cells
Ordered statistic indices in the GOS-CFAR algorithms
Averaging sub-window sizes in CASH-CFAR algorithm
Leading/Lagging statistics combining approach in GOS-CFAR and CA/CAGO/CASO-
CFAR, as given in (1)-(3)
Threshold scaling parameter in log2 domain
Reconfiguration of algorithm parameters takes effect when the βregister_reprogramβ input
signal is pulsed for the duration of at least 1 clock cycle. While this signal is held high the core
remains in a reset state, and therefore needs to be de-asserted in order for the core to begin
data processing under the new parameter configuration. Note that register_reprogram should
not be asserted when the core is busy processing a frame of data.
5.1 Choosing algorithm parameters
Choosing the most suitable CFAR algorithm and related algorithmic configuration parameters
is dependent on the characteristics of the radar operating environment, and therefore subject
to system performance analysis, which needs to be performed by the coreβs user
Some general guidelines on selecting the most suitable CFAR algorithm can be found in [1-5].
In dynamic environments, where there can be step transitions in clutter power, and also
multiple closely spaced targets can occur, the GOS-CFAR and CASH-CFAR algorithms are
known to perform more robustly and consistently, relative to CA-CFAR algorithms.
Furthermore, the βGOβ type of CFAR algorithms are known to provide improved robustness
relative to the βCAβ and βSOβ types, in environments with step transitions in clutter power. On
the other hand the βSOβ type of CFAR algorithms are known to provide improved robustness
relative to the βCAβ and βGOβ types, in environments where multiple closely spaced targets can
occur.
The window size selection for the leading/lagging windows also depends on general system
assumptions. In principle increasing the window sizes improves the detection performance, but
also increases susceptibility to interferers (e.g. nearby targets) and clutter transition regions.
Since the window sizes have a direct relationship with physical distances, informed selections
for this parameter can be made for the given type of operating environment.
2 In CA-CFAR the right side of (1) is actually scaled by Β½. 3 In the CASH/CA-CFAR algorithms, the leading/lagging window sizes are selected as a power of 2.
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Guard-cells prevent detection performance deterioration due to self-interference, which is
caused by the spread of a target in multiple FFT output bins. This spread is dependent on the
type of windowing function which is applied prior to FFT. Using 2 guard cells on each side of
the CUT is sufficient for most windowing functions, however the core will operate as expected
without guard cells.
The additive threshold scaling parameter π½ determines the False Alarm (FA) probability for a
given assumption regarding the statistical behaviour of the clutter, and also the corresponding
Detection Probability (DP) for a given (per bin) SNR value. Selections based on theoretical
formulas for the Sweling 2 clutter model for the GOS and CA CFAR algorithms are available in
[2,4].
In the GOS, GOSGO, GOSSO algorithms, the index for the extracted sorted statistic in each
window is commonly around Β½ of the window size, although more optimised selections can be
made by the user depending on detailed analysis of the operating environment.
5.2 Theoretical formulas for False Alarm and Detection Probabilities in the CFAR algorithms assuming Swerling 2 clutter model
Theoretical formulas for the FA and DP of the GOS and CA CFAR algorithms supported in esi-
CFAR for a Swerling 2 statistical clutter model, are provided in Appendix A. No such formulas
are available for the CASH-CFAR algorithm.
5.3 Scilab Scripts for computing DP and the π· threshold scaling
parameter
Scilab4 scripts are provided for aiding the user in computing the DP, given in Appendix A, for
any given selection of the GOS and CA CFAR algorithm parameters and targeted FA rate.
The provided Scilab files are located in:
\esi_7569_cfar\sw\Scilab\cfar_scale_param_scilab\
The main Scilab script file to be edited is: cfar_scale_compute.sci
The script allows selection for the following algorithm parameters:
CFAR algorithm (βcfar_algoβ)
Target FA probability (βPfa_targetβ)
Leading window size (βMβ)
Lagging window size (βNβ)
Leading window sort index (βkβ) ; relevant for GOSCA/GOSGO/GOSSO-CFAR
Lagging window sort index (βlβ) ; relevant for GOSCA/GOSGO/GOSSO-CFAR
Assumed SNR in dB per bin for computing DP
4 Scilab is similar to Matlab. It is freely available at : http://www.scilab.org/
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The script also runs a bisection bracketing algorithm in order to compute the value for the π½
threshold scaling parameter for any set of selected parameters.
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6 Simulation Models and RTL Verification
Initial development of eSi-CFAR was based on Matlab models, which allowed verifying the
system-level functionality of supported CFAR algorithms. These Matlab models can be found
in:
\esi_7569_cfar\sw\Matlab\multi_cfar_log
Simulation models for the GOS-CFAR algorithms are included in: gos_cfar_log.m
Simulation models for the CASH/CA-CFAR algorithms are included in: cash_ca_cfar.m
The above Matlab models are consistent with the RTL implementation of the CFAR algorithms,
but are nearly bit-exact.
A C++ based bit-exact model for the implemented CFAR cores is available in:
\esi_7569_cfar\sw\cfar.cpp
This C++ model is used within the RTL testbench for a randomised co-simulation of the CFAR
core. In particular the RTL testbench uses the βcfar.soβ file, which is generated by running the
βbuild.cshβ script from \esi_7569_cfar\sw\. It is noted that compilation of the βcfar.cppβ
makes use of systemc libraries (see within βbuild.cshβ).
Running βbuild.cshβ also copies the βcfar.soβ file in \esi_7569_cfar\hw\sim, which is the
required destination. RTL simulation is based on randomised tests generated by the testbench
files within: \esi_7569_cfar\hw\tbench.
The main testbench file is: multi_cfar_tb.v. In order to concentrate simulation in setups of
interest, there are a few core parameters which are specified at the very top within
multi_cfar_tb.v. These parameters are:
Input i/q sample bit-width (βdata_width_inβ)
Maximum CFAR leading/lagging window size and log2 equivalent (βwind_sizeβ and
βwind_index_widthβ)
FFT block size (βsamples_per_blockβ)
Number of randomised test per simulation run (βnumber_of_testsβ)
The remaining of the algorithm configuration parameters as well as randomised i/q data
samples are produced randomly by making use of esi_cfar_tb_include.sv
Simulation is run from \esi_7569_cfar\sw\, by first running the compilation script:
\scripts\rand_stim\compile.sh and subsequently the simulation script:
\scripts\rand_stim\sim.sh
It is noted that running the simulation requires a license for SV randomize feature.
The simulation will run for the number of specified randomised tests. Each test will first run
three consecutive data blocks in sequence with no gaps between the blocks. A second group of
three blocks will then be run with small gaps between them. Finally a third group of three
blocks will be run with small gaps between the blocks and also small gaps between i/q
samples within blocks.
Simulation will end in failure if a mismatch is detected between the outputs of the RTL and the
C++ model. A wave file for the simulation is available in \esi_7569_cfar\sw\
wave_gos_cash_cfar.do.
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7 References
[1] R. Perez-Andrade, R. Cumpildo, C. Feregrino-Uribe, F. Martin Del Campo, βA versatile
hardware architecture for constant false alrm rate processor based on a linear insertion
sorterβ, Elsevier Digital Signal Processing, No. 20, 2010.
[2] Y. He, βPerformance of some generalized modified order statistics CFAR detectors with
automatic censoring technique in multiple target situations,β IEE Proc. Radar Sonar
Navig., Issue 141, No. 4, pp. 205-212, 1994.
[3] H. Rohling, βRadar CFAR thresholding in clutter and multiple target situations,β IEEE
Trans. Aerospace Electron. Syst., Issue 19, No. 4, pp. 608-621, 1983.
[4] M. A. Richards, Fundamentals of Radar Signal Processing, McGraw Hill, 2005.
[5] F. X. Hofele, An Innovative CFAR Algorithm, CIE Intern. Conf. on Radar, 2001.
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Appendix A : Theoretical formulas for False Alarm and Detection
Probabilities in the CFAR algorithms assuming Swerling 2 clutter model
CA β CFAR
ππΉπ΄ = (1 +πΌ
π)
βπ
ππ· = (1 +πΌ
π(1 + πππ ))
βπ
π : is the total window size (sum of leading and lagging window sizes)
SNR : is the assumed per FFT-bin SNR in linear scale πΌ : is the multiplicative threshold scaling factor
CASO β CFAR
ππΉπ΄ = 2 (2 +πΌ
π)
βπ
{β (π β 1 + π
π) (2 +
πΌ
π)
βππβ1
π=0
}
ππ· = 2 (2 +πΌ
π(1 + πππ ))
βπ
{β (π β 1 + π
π) (2 +
πΌ
π(1 +)
βππβ1
π=0
}
π : is the window size of the leading (or lagging) window
SNR : is the assumed per FFT-bin SNR in linear scale πΌ : is the multiplicative threshold scaling factor
(π
π) : is the enumeration of combinations of π elements over π elements.
CAGO β CFAR
ππΉπ΄ = 2 [(1 +πΌ
π)
βπ
β (2 +πΌ
π)
βπ
{β (π β 1 + π
π) (2 +
πΌ
π)
βππβ1
π=0
}]
ππ· = 2 [(1 +πΌ
π(1 + πππ ))
βπ
β (2 +πΌ
π(1 + πππ ))
βπ
{β (π β 1 + π
π) (2 +
πΌ
π(1 + πππ ))
βππβ1
π=0
}]
π : is the window size of the leading (or lagging) window
SNR : is the assumed per FFT-bin SNR in linear scale πΌ : is the multiplicative threshold scaling factor
(π
π) : is the enumeration of combinations of π elements over π elements.
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GOSCA β CFAR
ππΉπ΄ = π (π
π)
Ξ(π β π + 1 + πΌ)Ξ(π)
Ξ(π + 1 + πΌ) π (
π
π)
Ξ(π β π + 1 + πΌ)Ξ(π)
Ξ(π + 1 + πΌ)
ππ· = π (π
π)
Ξ (π β π + 1 +πΌ
(1 + πππ )) Ξ(π)
Ξ (π + 1 +πΌ
(1 + πππ ))
π (π
π)
Ξ (π β π + 1 +πΌ
(1 + πππ )) Ξ(π)
Ξ (π + 1 +πΌ
(1 + πππ ))
π : is the window size of the leading window
π : is the window size of the laging window
π : is the selected index of the sorted leading window (possible values; 1:N)
π : is the selected index of the sorted lagging window (possible values; 1:M)
Ξ( ) : is the βGammaβ function
πΌ : is the multiplicative threshold scaling factor
SNR : is the assumed per FFT-bin SNR in linear scale
(π
π) : is the enumeration of combinations of π elements over π elements.
GOSGO β CFAR
ππΉπ΄ = π (π
π) β (
π
π)
π
π=π
Ξ(π β π + 1 + π β π + πΌ)Ξ(π + π)
Ξ(π + π + 1 + πΌ)+ π (
π
π) β (
π
π)
π
π=π
Ξ(π β π + 1 + π β π + πΌ)Ξ(π + π)
Ξ(π + π + 1 + πΌ)
ππ· = π (π
π) β (
π
π)
π
π=π
Ξ (π β π + 1 + π β π +πΌ
(1 + πππ )) Ξ(π + π)
Ξ (π + π + 1 +πΌ
(1 + πππ ))
+ π (π
π) β (
π
π)
π
π=π
Ξ (π β π + 1 + π β π + πΌπΌ
(1 + πππ )) Ξ(π + π)
Ξ (π + π + 1 +πΌ
(1 + πππ ))
π : is the window size of the leading window
π : is the window size of the laging window
π : is the selected index of the sorted leading window (possible values; 1:N)
π : is the selected index of the sorted lagging window (possible values; 1:M)
Ξ( ) : is the βGammaβ function
πΌ : is the multiplicative threshold scaling factor
SNR : is the assumed per FFT-bin SNR in linear scale
(π
π) : is the enumeration of combinations of π elements over π elements.
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GOSSO β CFAR
ππΉπ΄ = π (π
π) [
Ξ(π β π + 1 + πΌ)Ξ(π)
Ξ(π + 1 + πΌ)β β (
π
π)
π
π=π
Ξ(π β π + 1 + π β π + πΌ)Ξ(π + π)
Ξ(π + π + 1 + πΌ)]
+ π (π
π) [
Ξ(π β π + 1 + πΌ)Ξ(π)
Ξ(π + 1 + πΌ)β β (
π
π)
π
π=π
Ξ(π β π + 1 + π β π + πΌ)Ξ(π + π)
Ξ(π + π + 1 + πΌ)]
ππ· = π (π
π) [
Ξ (π β π + 1 +πΌ
(1 + πππ )) Ξ(π)
Ξ (π + 1 +πΌ
(1 + πππ ))
β β (π
π)
π
π=π
Ξ (π β π + 1 + π β π +πΌ
(1 + πππ )) Ξ(π + π)
Ξ (π + π + 1 +πΌ
(1 + πππ ))
]
+ π (π
π) [
Ξ (π β π + 1 +πΌ
(1 + πππ )) Ξ(π)
Ξ (π + 1 +πΌ
(1 + πππ ))
β β (π
π)
π
π=π
Ξ (π β π + 1 + π β π +πΌ
(1 + πππ )) Ξ(π + π)
Ξ (π + π + 1 +πΌ
(1 + πππ ))
]
π : is the window size of the leading window
π : is the window size of the laging window
π : is the selected index of the sorted leading window (possible values; 1:N)
π : is the selected index of the sorted lagging window (possible values; 1:M)
Ξ( ) : is the βGammaβ function
πΌ : is the multiplicative threshold scaling factor
SNR : is the assumed per FFT-bin SNR in linear scale
(π
π) : is the enumeration of combinations of π elements over π elements.
eSi-CFAR
Version 1.4.0 - Confidential 18 of 18 Β© 2015 EnSilica Ltd, All Rights Reserved
8 Revision History
Hardware
Revision
Date Description
1.0 03/09/2013 Initial release 1.2 29/09/2014 CASH-CFAR supported as an option in the CA-CFAR core Control
register updated accordingly. Input is now linear power instead
of i/q samples. 1.3 7/10/2014 Updated-corrected Overview Section with up-to-date core
features 1.4 20/4/2015 Added Section 3.1. Updated Section 4. Updated description of
βregister_reprogramβ signal in Table 2.
Table 3: Revision History