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EUV: From Development to HVM
Sam Sivakumar
Intel Corporation
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The Litho Landscape
Sivakumar 2013 International Workshop on EUV Lithography
1.35NA ArF
0.93NA ArF
k1 = 0.3
1.35NA ArF Pitch Halving
(PH)
EUV
45nm node
80nm HP
’07 HVM
Dry
22nm node
~40nm HP
’11 HVM
Immersion
1.35NA ArF Pitch Quartering
(PQ)
14nm node
26-30nm HP
’13 HVM
Immersion
10nm node
15-22nm HP
’15 HVM
ArF PQ EUV
7nm node
’17 HVM
EUV
ArF PD
32nm node
56nm HP
’09 HVM
Immersion
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The Real Scaling Challenge
Sivakumar
Ideal Layout
Real Layout
1D Structures Scale Well…. 2D Structures Don’t
2013 International Workshop on EUV Lithography
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Grating and Cut
Sivakumar
1.Print Grating 2.Cut Grating
Two fundamentally different patterning challenges
2013 International Workshop on EUV Lithography
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Gridded Unidirectional Layouts
Sivakumar
65 nm Layout Style 45 nm Layout Style
• Bi-directional features
• Varied gate dimensions
• Varied pitches
• Uni-directional features
• Uniform gate dimension
• Gridded layout
Standard now, density neutral or better
2013 International Workshop on EUV Lithography
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Likely EUV Use Scenario
Sivakumar
b c a
60nm
1 2
3
4
5 3
2
ArF MP
60nm
1
2
2
2
2 2
2
EUV
Grating
ArF PD
Cuts and Vias
EUV SP ArF MP
EUV offers the best value as a replacement of ArF multi-pass cut/via layers
2013 International Workshop on EUV Lithography
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The Challenges of EUV
Sivakumar
Resists Patterning requirements...
Resolution LWR/Dose
Outgassing IDM TPT requirements Scanner outgassing requirements
Tool Source
Availability Power
Scanner
Hardware
Reticle Defectivity
Killer defect impact >> wafer process defect impact Mitigation strategies
Reticle inspection Patterned wafer inspection Alternative strategies
EUV HVM implementation depends on satisfactory progress on all these fronts!
2013 International Workshop on EUV Lithography
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Scanner/Track Performance
Sivakumar 2013 International Workshop on EUV Lithography
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NXE Overlay Residuals
Sivakumar
NXT aligned to NXE overlay and NXE focus and tilt performance are well within ArF baseline distribution
NXT:NXE MMO NXT:NXT MMO
2013 International Workshop on EUV Lithography
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Focus and Tilt Performance
Sivakumar 2013 International Workshop on EUV Lithography
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Scanner/Track Defectivity
Sivakumar
EUV
ArF
June Oct Feb
Total Defects
2013 International Workshop on EUV Lithography
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Scanner/Track Defectivity
Sivakumar
EUV
ArF
June Oct Feb
Resist “Intrinsic” Defects
2013 International Workshop on EUV Lithography
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Scanner/Track Hardware Summary
Basic tool hardware performance appears to be more or less in line with ArF baseline
– Overlay and focus performance appear to be as expected
Overlay performance of EUV systems appear to be roughly in line with ArF mix-match baseline
– Further improvements likely with better characterization of reticle components and other EUV-specific effects
Significant improvement made in linked defect performance
– Current performance still lags ArF but within striking range
– Residual defects appear to be largely resist related
Sivakumar 2013 International Workshop on EUV Lithography
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Resist Performance
Sivakumar 2013 International Workshop on EUV Lithography
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Resist Resolution
Sivakumar
L18P36
EL = 0.5 nm/mJ
Esize = 42 mJ
EUVJ-1099
Min LWR = 3.8 nm
L16P32 Modulation
L16P32
CA Resist
Non-CA Resist
C32P84
C32P70
2013 International Workshop on EUV Lithography
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LWR Mitigation
Sivakumar
NXE3100, 50 nm FT, 30 HP Litho LWR Mitigation
NXE3100 70P
2013 International Workshop on EUV Lithography
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Resist Performance – Key Takeaways
Resist resolution performance looks reasonable for 18-20 nm HP, will need further improvement beyond this target
LWR performance is a challenge but promising results seen for post-litho treatments
– Non-CA resist LWR looks good but photospeed is key issue
Good results seen for hole patterning, but pattern shrink techniques would be needed to achieve CD targets
Preliminary double pass approaches (LFLE, LELE, etc.) look reasonable for EUV
Sivakumar
Current resists when pushed for pitch on NXE 3300 will require significant improvement
2013 International Workshop on EUV Lithography
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Source Performance
Sivakumar 2013 International Workshop on EUV Lithography
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Max Dose Error Per Field
Sivakumar
Power delivery reasonable, getting better
2013 International Workshop on EUV Lithography
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Laser Power Roadmap
Sivakumar
Lack of power remains the main impediment to EUV HVM
2013 International Workshop on EUV Lithography
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Source Performance – Key Takeaways
Intrinsic source performance showing good improvement over time
– Significantly higher availability seen week to week with better predictability in maintenance/consumable changes
– Good dose error performance seen with scope defined for further improvements
While higher HW reliability is needed, key remaining technical hurdle is source power
– Delays to roadmap threaten to impact EUV insertion
– SPIE Cymer data of >50W power is welcome news!
– Need to build on the momentum and focus attention on power roadmap and any collateral impact to lifetime of other ancillary hardware
Sivakumar
Achieving high, reliable power is key!
2013 International Workshop on EUV Lithography
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Reticles
Sivakumar 2013 International Workshop on EUV Lithography
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Blank Defects
<40defects @50nm being produced (low yield)
– Process capable of generating blanks with <20 defects @ 50nm has been demonstrated
Inspection capability @ 30nm needs to be set up at blank vendor for further improvement
Sivakumar
15 defects @ ≥50 nm
2013 International Workshop on EUV Lithography
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Reticle Integrated Performance
Sivakumar
FS=439nm
BS=493nm
Mask: 22 nm node test chip
Blank: LTEM, Full ML, 84nm Ta based absorber
Pattern Reg: X/Y=-3.59nm/4.89nm
Flatness: FS=439nm, BS=493nm
EUV Reflectivity: Ref.=62.1%, CW()=13.524nm
Absorber EUV leakage: 0.75%
Defectivity: single digit before repair
2013 International Workshop on EUV Lithography
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Daily Cost of a Reticle Fall-on Defect Excursion
Sivakumar
Model assumptions: •Critical area = die area •200 mm2 die •300 die per wafer •Fab capacity = 5000 wafer starts per week
Representative data from the semiconductor industry
Reticle defects are tremendously expensive
Tim Crimmins, Litho Workshop 2012
2013 International Workshop on EUV Lithography
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EUV In-Fab Reticle Flow
Sivakumar
In situ inspection
Stocker Scanner Stocker
Reticle
inspection
Wafer
inspection
Defect free reticle
Print check
AIMS
Reticle, mask and wafer inspection metrology need to be ready to support the EUV launch
Tim Crimmins, Litho Workshop 2012
2013 International Workshop on EUV Lithography
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Inspection for EUV HVM – Key Takeaways
Yield cost of random reticle adders is very high
– Wafer inspection to catch reticle adders is an extremely costly and unworkable strategy
– Higher wafer TPT and greater capital inspection capital investment
– High need for EUV AIMS
Need to ensure that adders are not patterned
– Need to make them too small to resolve
– How to ensure 10-5 adders per reticle pass?
– Need to ensure reticle is in a known clean state at the point of exposure - in-situ reticle inspection?
Keep adders away from absorber surface
– Pellicles are essential to long-term defectivity health of reticles at previous wavelengths, and they are critical for EUV!
– Physical requirements are available for pellicles and frames for NXE platform
– Pellicles will reduce EUV transmission, so source must keep up
Sivakumar
2013 International Workshop on EUV Lithography
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Integrated Performance
Sivakumar 2013 International Workshop on EUV Lithography
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Production Reticle Printed Defectivity
Sivakumar
Reticle Pattern Defects Imaged Reticle Defects
No reticle imaged defects detected
2013 International Workshop on EUV Lithography
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Integrated Defect Performance
Sivakumar
ArF EUV
Integrated post-etch production wafer defectivity roughly comparable, no new EUV-specific defect modes
2013 International Workshop on EUV Lithography
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Contact/Metal Resistances
Sivakumar
ArF Baseline
EUV
ArF Baseline
EUV
EUV Performance within ArF fab distribution
2013 International Workshop on EUV Lithography
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Electrical Performance - Transistor
Sivakumar
P Channel Drive Current P Channel Threshold Voltage
ArF EUV
ArF EUV
EUV On-Wafer Electrical Performance Matched to ArF Baseline
2013 International Workshop on EUV Lithography
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Recent Results –Yield
22nm node SRAM test chip processed through entire line
EUV yield was achieved – no EUV-unique defect modes identified
All yield-loss mechanisms are unrelated EUV patterning process steps
Sivakumar
There appears to be no fundamental roadblock to EUV achieving yield parity
with ArF
2013 International Workshop on EUV Lithography
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Summary
The Good:
EUV hardware performance roughly in line with ArF
Resist performance looks reasonable for 18-20nm HP, needs improvement for tighter pitches
Integrated data shows EUV performance matched to ArF baseline for defectivity and CD control. Reasonable yield achieved on 22nm
Steady progress on mask blanks, need long term improvement
Reticle pellicle program gaining momentum
The Not-So-Good:
Source power is a significant concern, well behind schedule
Reticle defectivity is a significant concern
– Need good strategy for maintaining reticle cleanliness
– Send-aheads are prohibitive for EUV HVM
– Reticle inspection capability is needed in time
Sivakumar
Demonstrable progress on these key items over next 1-1.5 years is essential!
2013 International Workshop on EUV Lithography
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Thank You!
Sivakumar