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Famílias Lógicas• TTL (Bipolar): Transistor-Transistor-Logic
– 74,74L,74H,74S,74LS,74AS,74ALS,74F(Low-Power; High-Speed; Schottky; Advanced; Fast)
VCC: +5 V ± 5%—————————————————
• CMOS: Complementary Metal-Oxide Semiconductor
– 4000; 74C (VDD :+3 a +15 V)– 74HC; 74AC; (VDD :+2 a +6 V)– 74HCT; 74ACT (VDD :+5 V)(CMOS; TTL-compatible)
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Ciclo de Vida das Famílias Lógicas
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Gates Básicos
• INVERTER
• NAND
• NOR
Por que?
Importante: Ler págs. 53-56, do livro “Sistemas Digitais” de R. Tocci
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ÂNODO CATÔDO
P N
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ÂNODO CATÔDO
+ –VB
+ –VB
+ –VB
(a) Se VB < +0.6 V
(b) Se VB > +0.6 V
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(NPN)
VC >VE e VBE > 0.6 V
P NN
(B)(E)(C)
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Níveis de Voltagem e Estados Lógicos p/ TTL
INPUT OUTPUT
VHN
VLN
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1.6mA
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10µA
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I. TOTEM-POLEII. OPEN-COLLECTORIII.TRI-STATE
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I. TOTEM-POLE
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II. OPEN-COLLECTOR
SIMBOLOGIA PARA UM INVERSORCOM COLETOR ABERTO
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OPEN-COLLECTORCOM RESISTOR DE “PULL-UP”
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OPEN-COLLECTORAPLICAÇÃO COMO “WIRED-AND”
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SAÍDAS TOTEM-POLE
E CONEXÃO WIRED-AND?
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OPEN-COLLECTORAPLICAÇÃO COMO “BUFFER/DRIVER”
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III.TRI-STATE
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TRISTATE APLICAÇÃO EMBARRAMENTO DE DADOS
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Simbologia p/ dispositivos c/ saída TRISTATE
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MOS Field Effect Transistors
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Níveis de Voltagem e Estados Lógicos p/ CMOS
INPUT OUTPUTVHN
VLN
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I. PUSH-PULLII. OPEN-DRAINIII. TRI-STATE
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Transmission Gate
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Níveis de Voltagem e Estados Lógicos p/ CMOS e TTL
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tPHL: propagation delay time from HIGH to LOW
tPLH: propagation delay time from LOW to HIGH
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Gate Power versus Frequency
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CMOS versus TTL
ICs CMOS: consomem uma potência menor do que os TTL permitem uma maior densidade de integração possuem uma maior imunidade a ruídos elétricos e alta impedância de entrada podem operar numa faixa maior de alimentação têm maiores fan-ins e fan-outs são mais sujeitos a danos por descarga eletrostática suas entradas não podem ser deixadas em aberto não são tão rápidos quanto aos TTLs
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small outline integrated circuit
plastic leadedchip carrier
leadless ceramicchip carrier
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