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S. Boyd EE102
Lecture 15Applications of feedback
Oscillators
Phase-locked loop
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Oscillators
feedback is widely used inoscillators , which generate sinusoidal signals
to generate sinusoidal signal at frequency 0 ,
closed-loop system should have poles at j0 other poles should have negative real part(i.e. , other terms decay)closed-loop pole at j 0 L( j0 ) = 1, i.e. ,
L( j0 ) = 180 + q360 ,
|L( j0 )
|= 1
intuition: gain around whole loop, including sign, is q360 ; thefeedback regenerates the signal (at frequency 0 )
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Example. voltage amplier has gain a, a > 0v in ( t ) v out ( t )
C C C
R R R
a
design variables: R, C , a
transfer function of RC feedback network is
F (s) = V in (s)V out (s)
= 1(sRC )3 + 5( sRC )2 + 6( sRC ) + 1
loop transfer function is L = aF Applications of feedback 153
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Bode plot of F :
102
101
100
101
80
60
40
20
0
102
101
100
101
180
360
0
RC
RC
F ( j
R C )
| F ( j R C )
|
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want loop transfer function L = aF = 1 at 0
L( j0 ) = aF ( j0 ) = F ( j0 ) = 180
from Bode phase plot we see 0
2.5/ (RC )
from Bode magniture plot we see F (0 ) 30dB, so we need a +30 dB
analytically: L( j0 ) = 180 is same as
1/L ( j0 ) =1a
( j0 RC )3 + 6( j0 RC ) = 0
so 0 = 6/ (RC )hence L( j0 ) =
a
5( j
6)2
+ 1
= a29
, so we need a = 29
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summary: with gain a = 29 , system oscillates at freq. 0 = 6/ (RC )(can check third pole is real & negative)
in practice, gain needs to be a little larger; nonlinearities limit amplitude of oscillation (careful analysis is hard)
intuitive analysis of RC oscillator:
at 0 = 6/ (RC ), RC network gives180 loop phase shift amplifer gain a = 29 makes up for amplitude loss of RC network at 0
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Phase-locked loop (PLL)
PLL is widely used to synchronize one signal to another
applications:
synchronize clocks, frequency multiplication/division
video signal sync FM demodulation
synchronize data communications transmitter, receiver track varying frequency source (e.g. , Doppler from space vehicle oraircraft)
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basic PLL block diagram:
in
osc
v out
v phase
VCO
Phase detector Loop lter
signals on left (marked in , osc ) are frequency-varying sinusoids, of form cos((t)t); instantaneous frequency (t) varies only a smallamount around some xed value
signals on right (vphase , vout ) are (usually) voltagesidea: feedback from phase detector adjusts voltage controlled oscillator(VCO) frequency to match input frequency
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Phase detector
phase detector generates voltage proportional to phase difference of freqeuncy-varying sinusoids
vphase (t) = kdet err (t)
err (t) =
t
0
(in ( )
osc ( )) d
provided phase difference err is less than 90 or sokdet is the detector gain (V/ rad)
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Voltage controlled oscillator
VCO generates frequency-varying sinusoid, with frequency depending on itsinput voltage vout (t):
osc (t) = free + kosc vout (t)
free is called the free running frequency
kosc is the VCO gain (in (rad/ sec)/ V)real VCOs have a minimum and maximum frequency
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LTI analysis of PLL
loop lter is often LTI, i.e. , T.F. G(s)
in
osc
free
err1s
k det
k osc
v out
v phaseG ( s )
this LTI model of PLL is goodprovided
|err | 90 (or so)
osc stays within limits
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transfer function from free to osc is
ss + kdet kosc G(s)
which is zero at s = 0 , so free does not affect osc (in steady-state)
transfer function H from in to osc is
H (s) =kdet kosc G(s)/s
1 + kdet kosc G(s)/s =kdet kosc G(s)
s + kdet kosc G(s)
phase detector gives integral action: H (0) = 1
for constant in , osc (t) in as t ,i.e. , VCO frequency locks to input frequency
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First order loop
simplest PLL uses G(s) = 1 , which yields
H (s) = 11 + s/ (kdet kosc )
(hence the name rst order)
kosc kdet is called loop bandwidth
osc (t) tracks in (t), with time constant 1/ (kdet kosc )
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Second order loop
very common PLL uses lowpass loop lter
G(s) =1
1 + s/ loop
which yields
H (s) =1
1 + s/ (kdet kosc ) + s2 / (loop kdet kosc )
(hence the name second order)
common choices for loop :
loop = 4 kdet kosc (sets both poles of H to loop / 2 = 2kdet kosc ) loop = 2 kdet kosc(sets poles of H to (1 j )loop / 2 = (1 j )kdet kosc )
oscis 2nd order lowpass ltered version of
in
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Phase detectors
basic idea of common phase detector:
v 1 ( t )
v 2 ( t )
w 1 ( t )
w 2 ( t )
F ( s )
input signals are converted to squarewaves, then multiplied lowpass ltered (averaged) by F (s)
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w 1 ( t )
w 2 ( t )
w 1 ( t ) w 2 ( t )
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average value of w1 (t)w2 (t) depends on phase difference :
w 1 ( t ) w 2 ( t )
1
1
0 180 360
this phase detector operates between 0 and 180 instead of 90 ;doesnt affect PLL if bandwidth of lowpass lter is input frequencies, its output
w1 (t)w2 (t)
phase detector is linear (plus constant) for 0 180
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Lock range
lock range: range of in over which can the PLL can maintain lockrecall that we must have |err | < / 2 or so for linear phase detectoroperationtransfer function from in free to err :
F (s) =1
s + kdet kosc G(s)
for in constant, we have in steady-state
err = F (0)( in free ) =in free
kdet kosc G(0)
so lock range for slowly varyingin is
|in free | (/ 2)kdet kosc G(0)
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lock range analysis for rapidly varyingin :
assume |in (t) free (t)| for all t
err = f (in free )where f is impulse response of F
by peak-gain analysis, peak of err (t) is no more than
0 |f ( )| d
so lock occurs for
0 |f ( )| d / 2
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rst order loop lter (G(s) = 1 ):
F (s) = 1s + kdet kosc
, f (t) = e k det k osc t
so
0 |f ( )| d = F (0) =1
kdet kosc
therefore lock range, for rapidly varyingin , is
(/ 2)kdet kosc
(same as slowly-varying lock range . . . )
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PLL: nonlinear analysis
our linear analysis holds as long as
phase difference stays in the linear range (say,
90 )
frequency stays within VCO limits (usually not the problem)
when phase difference moves out of linear range, dynamics of PLL arehighly nonlinear, very complex
analysis of losing and acquiring lock is very difficult there is no complete theory or analysis, but lots of practical experience
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