Fractionally Injection-Locked Frequency Synthesizer
Ultra-Low-Power Frequency Synthersizer
Pow
er c
onsu
mpt
ion
[mW
] 16
12
8
4
0
Output frequency [GHz]0 2 4 6 8 10
PE=2.3PE=0.94
JSSC12TCAS11
VLSI07
JSSC09
TCAS10TCAS01
Target
I-phase
Q-phase
Unwanted input pointPhase correction point
Vinj
4×Tin
Tin
t
Con
vent
iona
lPr
opos
ed
2000 2005 2010 2015 2020 2025
Sup
ply
volta
ge [V
]
0
1.2
0.8
0.4
Year
-70dB-65dB34.6MHz
ChargePump
LoopFilterPhase
FrequencyDetector
Ref
Divider
Prescaler
ILFD÷4÷40
LC-VCO
PNnorm [dBc/Hz]
PE
[mW
/GH
z]
PLL (LC QVCO)PLL (LC VCO)
PLL (Ring VCO)This work
-150 -160 -170 -180 -190
6.0
5.0
4.0
3.0
2.0
1.0
0This work
LC-VCOLF
PFD,CP Divider
800μm
800μ
m
Vinj
+- +
-+- +
-
Vinj
VDD
Vbn
Vbp
Delay cellInverter
-80
-120
-100
-140
Offset frequency [Hz]
Pha
se n
oise
[dB
c/H
z]
103 104 105 106 107
-60
-40
-105 dBc/Hz
W/o FBB
W/ FBB
Out
put f
requ
ency
[GH
z]
5.546
5.542
5.538
5.534
5.530
5.526
ILFD control voltage [mV]300 320 340 360 380 400
W/ FBB (nMOS×2) (proposed)
Injection signal amplitude [V]0.1 0.2 0.3 0.4
0.2
0
0.4
0.6
0.8
1.0
Lock
rang
e [G
Hz]
W/o FBB (nMOS×2)W/ FBB (nMOS×1)
W/o FBB (nMOS×1)
LC VCO core
Bias control circuitVDD
VDD
Vtune
Vctrl
Vctrl
Vout Voutb
Tech.[nm] [GHz] [V]
PN[dBc /Hz]
Power[mW]
This work 65 5.54 0.5 -105 1.6[1] 180 1.9 0.5 -120 4.5[2] 180 2.56 0.5 -105 14.4[3] 90 2.59 0.5/0.65 -113 6.0[4] 130 9.12 0.5/0.8 -105 12[5] 90 2.24 0.5 -87 2.1
[1] H. -H. Hsieh, et al., VLSI 2007 [4] C. -Y. Yang, et al., TCAS 2001[2] C. -T. Lu, et al., TCAS 2010 [5] K. -H. Cheng, et al., TCAS 2011[3] S. -A. Yu, et al., JSSC 2009
VDDfout
CT<2:0>CT<2:0>CT<2:0>
Vbs2
CT<2:0>
Vb Vbs1
Vinj1 Vinj2
+-
-+
+-
-+
+-
-+
+-
-+
Vout180
Vout0
Vout45
Vout225
Vout135
Vout315
3-bit coarse tuning
Fine tuning
Vout270
Vout90
Vbs2
Vb Vbs1
Vinj3 Vinj4
Vbs2
Vb Vbs1
Vbs2
Vb Vbs1
PFD(DZ)
CPRef.
4
fref
÷N
÷2
∆T PG PS
4
finj
LF
f0
8-phaseringVCO
Injection locking
fPFD
PLL/FLL
Vb
C1 C2
R
Vinj
Phase corrections by injection signalsTpw
T0VoutVoutb
(a) Tinj01 = 2.5 × T0
Vinj01Tinj01
T0VoutVoutb
(b) Tinj02 = 1.25 × T0
Vinj02Tinj02
Unwated pulses are injected
Tpw
T0
VoutVoutb
Vinj0Tinj0
ΔФ
T0Vout,IVoutb,I
Vinj03Tinj03
Vinj0,I
Vinj0,Q
Vout,QVoutb,Q
VCODiv.
LFLF
Dum.
250
μm
330 μm
CP, PFDPG, etc
Vout225
Vout45
Vout135
Vout315
Vout225
Vout135
Vout45
Vout315 Vinj
Vinj1
Vinj2
Vinj3
Vinj4
Vout315
Vout225
Va1
Va1
Vinj
Vinj1
Vout0
Vout180
NAND operation
Phase selecting
NOR operationVCO Jitter
Conv. PLL
ILPLL w/ DZ
ILPLL
CP noise reduction
-80
-40
-60
-20
0
-100
-120
-140
-160
Pha
se n
oise
[dB
c/H
z]
103 104 105 106 107 4×107
Offset frequency [Hz]
1.8 2.051.55Frequency [GHz]
0
-20
-40
-60
-80
-100Mea
sure
d sp
ectru
m [d
Bm
]
-35 dBc
Ref.Pulse
generator VCOfref finj
M×finj
Vb
Vinj1
Vinj2
Vinj3
Vinj4
Vinj
Vout0
Vout180
Vout0
Vout180
Vout90
Vout270
Vout90
Vout270
Ref. VCOfinj
M×finjVb
Ref. VCOfinj
(M+1/4)×finjVb
?
Process 90 nm CMOSSupply voltage 1.0 V
Input frequency (fref) 80 MHzInjection frequency (finj) 160 MHz
Output frequency (f0) 1.8 GHz 2.0 GHzf0/finj 11.25 12.5
Phase noise@ 1 MHz -106 dBc/Hz -103 dBc/Hz
Power consumption
22 mW (w/ I/O buffers)
VCO: 50%Injection path: 36%
PLL blocks: 14%{19 mW (sim.), w/o I/O buffers}
Motivation:Low phase-noise without LC
Proposed Frequency Synthesizer
Fractional Subharmonic Locking
Conventional Subharmonic Locking
Proposed Pulse-Selection Technique
Measurement Results
Motivation:Low voltage operation
Proposed Frequency Synthesizer
Proposed ILFD
Measurement Results
Subharmonic locking Fractional subharmonic locking
PLL with injection locking8-phase ring VCO
Pulse for injection locking
Output signal spectram Phase noise
・Devided-by-4 ILFD・Class-C VCO・Forward body bias (FBB)
Output signal spectram
ITRS01~09
ITRS11
[1][3]
[4][5]
[2]