-
FTF2416C4M Full-Frame CCD Image Sensor
IMAGE SENSORS
Preliminary specification 2003 February 6
DALSAProfessional Imaging
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2003 February 6 2
DALSA Professional Imaging Preliminary specification
4M Full-Frame CCD Image Sensor FTF2416C
• APS compatible optical image format
• 4M active pixels (2460H x 1640V)
• RGB Bayer pattern
• Progressive scan
• Excellent anti-blooming
• Variable electronic shuttering
• Vertical subsampling
• Square pixel structure
• H and V binning
• 90% optical fill factor
• High linear dynamic range (>72dB)
• High sensitivity
• Low dark current and fixed-pattern noise
• Low read-out noise
• Data rate up to 27 MHz
• Mirrored and split read-out
• Perfectly matched to visual spectrum
DescriptionThe FTF2416C is a full frame CCD colour image sensor designedfor professional digital photography applications, with very low darkcurrent and a linear dynamic range of over 12 true bits at roomtemperature. The two low-noise output amplifiers, one at each cornerof the output register, make the FTF2416C suitable for a wide rangeof high-end visual light applications. With one output amplifier, aprogressively scanned image can be read out at 5 frames per second.By using multiple outputs the frame rate increases accordingly. Thedevice structure is shown in figure 1.
Device structure
Optical size: 22.140 mm (H) x 14.760 mm (V)Chip size: 23.900 mm (H) x 16.000 mm (V)Pixel size: 9 µm x 9 µmActive pixels: 2460 (H) x 1640 (V)Total no. of pixels: 2508 (H) x 1652 (V)Optical black pixels: Left: 20 Right: 20Timing pixels: Left: 4 Right: 4Dummy register cells: Left: 7 Right: 7Optical black lines: Bottom: 6 Top: 6
Figure 1 - Device structure
Image Area
2460 active pixels
1640
active
lines
20 20
6 black lines
6 black lines
1652
lines
44
7 72508 cellsOutput amplifier Output register
2522 cells
G B G B
G B G BR G R G
G B G B
G B G BR G R G
G B G BR G R G
G B G BR G R G
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2003 February 6 3
DALSA Professional Imaging Preliminary specification
4M Full-Frame CCD Image Sensor FTF2416C
Architecture of the FTF2416C
The optical centers of all pixels in the image section are aligned ona square grid. The charge is generated and integrated in this section.An output register is located below the image section for read-out.After the integration time, the image charge is shifted one line at thetime to the register. A separate transfer gate (TG) between the image
section and output register will enable sub-sampling features. Theleft and the right half of the register can be controlled independently.This enables either single or multiple read-out. The register can beused for vertical binning. A summing gate at both ends of the registercan be used for horizontal binning (see figure 2).
IMAGE SECTION
Image diagonal (active video only)Aspect ratioActive image width x heightPixel width x heightGeometric fill factorImage clock pinsCapacity of each clock phaseNumber of active linesNumber of black reference linesNumber of dummy black linesTotal number of linesNumber of active pixels per lineNumber of overscan (timing) pixels per lineNumber of black reference pixels per lineTotal number of pixels per line
27.97 mm3:222.140 x 14.760 mm2
9 x 9 µm2
90%8 pins (A1..A4), left and right connected in sensor2.0 nF per pin16404 (=2x2)8 (=2x4)165224608 (2x4)40 (2x20)2508
OUTPUT REGISTER
Output buffersNumber of dummy cells per registerNumber of register cells per registerOutput register horizontal transport clock pinsCapacity of each C-clock phaseOverlap capacity between neighbouring C-clocksOutput register Summing GatesCapacity of each SGReset Gate clock phasesCapacity of each RG
2 x Three-stage source followers14 (2x7)2522 (2508+14)6 pins per register (C1..C3), left and right100 pF per pin25 pF2 pins (SG)15 pF2 pins (RG)15 pF
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2003 February 6 4
DALSA Professional Imaging Preliminary specification
4M Full-Frame CCD Image Sensor FTF2416C
Figure 2 - Detailed internal structure
A1, A2, A3, A4: clocks of image section C1, C2, C3: clocks of horizontal registers
SG:summing gateOG:output gateRG:reset gateRD:reset drainTG:transfer gate
OG
One Pixel
A3
A4
A2
A3
A4
A2
A1
A2
A3
A4
A2
A3
A4
A1
A2
A3
A4
A1
A2
A3
A4
A2
A3
A4
A1
A2
A3
A1
A3
A4
A1A1
A3A3
A4
A4
A3
A4
A2
A2
A4
A3
A2
A2
6 blacklines
2460 image pixels
1640 activeimageslines
6 blacklines
IMAGE
SG
RG
RD
OUT_R
RG
RD
OGSG
7 dummy pixels 20 black & 4 timing columns
20 black & 4 timing columns
7 dummy pixels
OUT_L
2460 x 1640FF CCD
A1 A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
TGTG
C1 C3C2C1 C3C2 C1 C3C2 C1C2C1 C3C2C1 C3C2C1 C3C2C1 C3C2C1 C3C2C1 C3C2C1 C3C2C1 C3C2
RightLeft
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2003 February 6 5
DALSA Professional Imaging Preliminary specification
4M Full-Frame CCD Image Sensor FTF2416C
1 During Charge Reset it is allowed to exceed maximum rating levels (see note 7).2 All voltages in relation to SFS.3 Power-on sequence: VNS, SFD, RD, VPS, all others.4 To set the VNS voltage for optimal Vertical Anti-Blooming (VAB), it should be adjustable between minimum and maximum values.5 Transfer gate should be clocked as A1 during normal transport or held low during a line shift to sub-sample image.6 Three-level clock is preferred for maximum charge; the swing during vertical transport should be 3V higher than the voltage during integration. A two level clock (typically 10V) can be used if a lower maximum charge handling capacity is allowed.7 Charge Reset can be achieved in two ways:• The typical A-clock low level is applied to all image clocks; for proper CR, an additional Charge Reset pulse on VNS is required (preferred).• The minimum CR level is applied to all image clocks simultaneously.
Specifications
ABSOLUTE MAXIMUM RATINGS1 MIN. MAX. UNIT
GENERAL:storage temperatureambient temperature during operationvoltage between any two gatesDC current through any clock phase (absolute value)OUT current (no short circuit protection)
-40-20-20-0.20
+80+60+20+0.210
°C°CVµAmA
VOLTAGES IN RELATION TO VPS:VNS, SFD, RDVCS, SFSall other pins
-0.5-8-5
+30+5+25
VVV
VOLTAGES IN RELATION TO VNS:SFD, RDVCS, SFS, VPSall other pins
-15-30-30
+0.5+0.5+0.5
VVV
DC CONDITIONS 2, 3 MIN. [V] TYPICAL [V] MAX. [V] MAX. [mA]
VNS 4 VPS SFD SFS VCS OG RD
N substrate P substrate Source Follower Drain Source Follower Source Current Source Output Gate Reset Drain
20 1 19 0 -5 2.0 19
25.5 6 20 0 0 2.5 20
28 7 24 0 3 4.5 21
15 15 4.5 1 - - -
AC CLOCK LEVEL CONDITIONS2 MIN. TYPICAL MAX. UNIT
IMAGE CLOCKS / TRANSFER GATES 5: A-clock amplitude during integration and hold A-clock amplitude during vertical transport (duty cycle=5/8) 6 A-clock low level Charge Reset (CR) level on A-clock 7
8 11 - -5
8 11 0 0
8.5 11.5 - -
V V V V
OUTPUT REGISTER CLOCKS: C-clock amplitude (duty cycle during hor. transport = 3/6) C-clock low level Summing Gate (SG) amplitude Summing Gate (SG) low level
4.75 2
5 4 10 tbd
5.25 10
V V V V
OTHER CLOCKS: Reset Gate (RG) amplitude Reset Gate (RG) low level Charge Reset (CR) pulse on Nsub 7
4.5 17 0
5 18 10
5.5 19 10
V V V
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2003 February 6 6
DALSA Professional Imaging Preliminary specification
4M Full-Frame CCD Image Sensor FTF2416C
Timing diagrams (for default operation)
1 Tp = 1 clock period2 Duty cycle = 50%
Figure 3 - Frame timing diagram
Frame timing
AC CHARACTERISTICS MIN. TYPICAL MAX. UNIT Horizontal frequency (1/Tp) 1 Vertical frequency Charge Reset (CR) time Rise and fall times: image clocks (A) register clocks (C) 2 summing gate (SG) reset gate (RG)
10 10 3 3 -
25 75 Line time 20 5 5 3
27 150 1/8 Tp 1/8 Tp 1/8 Tp
MHz kHz µs ns ns ns ns
LH
A2HL
1 31 1 11 1 2 98 1650
1646
1651
1647
1648
1654
1649
1
L
HL
HSSC
NS pulse/CRCR
HL
1652 image lines
6 black 1640 active lines 6 black
4 5 6 7 1652
1653
CR
VA high
REMARKS* CR is applied during the first line after the transition from L to H of Trig_in * CCD is integrating during high period of Trig_in* After read-out sequence the timing goes into idle mode.
1
integrationintegration
A3 LH
A4HL
TG/A1
11 11
Trig_in LH
idle
11
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2003 February 6 7
DALSA Professional Imaging Preliminary specification
4M Full-Frame CCD Image Sensor FTF2416C
Figure 4 - Vertical read-out, single and dual output modes
Line timing - single output
Line timing - dual output
SSC18.4us
Sensor Output2460
Active PixelsB2460
Active Pixels
LH
B
VA highHL
5us
5us
8.3us
A4
A3
A2
TG/A1
L
L
H
H
HL
HL
10us
6.7us
3.3us
5us
5us
Pixel numbers represent the beginning of the pixel concerned
126
210
336
Rising edge of pixel 0Falling edge of pixel 2975
460
42020
4
2955
2951
84
168
252
REMARKS* Thorizontal = 2975 * 1/25E6 = 119us* Vertical transport frequency = 75kHz
378
18.4us
timingblack
timingdummyblack
294
460
460
467
487
491
SSC18.4us
Sensor Output1230
Active PixelsB1230
Active Pixels
LH
VA highHL
5us
5us
8.3us
A4
A3
A2
TG/A1
L
L
H
H
HL
HL
10us
6.7us
3.3us
5us
5us
Pixel numbers represent the beginning of the pixel concerned
126
210
336
Rising edge of pixel 0Falling edge of pixel 1721
460
420
84
168
252
REMARKS* Thorizontal = 1721 * 1/25E6 = 68.84us* Vertical transport frequency = 75kHz
378
18.4us
timingdummyblack
294
460
460
467
487
491
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2003 February 6 8
DALSA Professional Imaging Preliminary specification
4M Full-Frame CCD Image Sensor FTF2416C
Figure 5 - Start horizontal read-out, single and dual output modes
L
H
L
H
L
H
L
H
L
H
Sensor output
40ns
13.33ns
20ns
26.67ns
6.67ns
black
signal
RG
SG
C2
RG
C3
C1
GR R
GGB
GB B
GRG G
R GB
RG B
GGR R
GGB B
GBG
GR
7 dummy 20 black 4 overscan 2460 active 4 overscan 20 black
SSC
SG
C2
RG
C3
C1
SSC clocked with rising edge of C2
7 dummy 20 black 4 overscan 1230 active
SINGLE OUTPUT
GR R
GGB
GB B
GRG G
R GB
RG B
GGR R
GGB B
GBG
GR
DUAL OUTPUT
DUAL OUTPUT
SINGLE OUTPUT Right
SINGLE OUTPUT Left
SENSOR PIN C1L C2L C3L C1R C2R C3R
C1 C2 C3 C1 C2 C3
C2 C1 C3 C2 C1 C3
C1 C2 C3 C2 C1 C3
PHIC'S @ 25MHz
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2003 February 6 9
DALSA Professional Imaging Preliminary specification
4M Full-Frame CCD Image Sensor FTF2416C
0
1024
2048
3072
4096
5120
6144
7168
8192
9216
0 5 10 15 20 25
Horizontal Read-out Frequency (MHz)
Line
air D
ynam
ic R
ange
Performance
The test conditions for the performance characteristics are as follows:• All values are measured using typical operating conditions.• VNS is adjusted as low as possible while maintaining proper
Vertical Anti-Blooming.• Sensor temperature = 60°C (333K).• Horizontal transport frequency = 25MHz.• Vertical transport frequency = 75kHz.
1 Charge Transfer Efficiency values are tested by evaluation and expressed as the value per gate transfer.2 Low Pass Shading is defined as the ratio of the one-σ value of an 8x8 pixels blurred image (low-pass) to the mean signal value.3 RNU is defined as the ratio of the one-σ value of the high-pass image to the mean signal value at nominal light.
• Integration time = 10ms.• The light source is a lamp of 3200K in conjunction with neutral
density filters and a 1.7mm thick BG40 infrared cut-off filter. ForLinear Operation measurements, a temperature conversion filter(Melles Griot type no. 03FCG261, -120 mired, thickness: 2.5mm)is applied.
Figure 6 - Typical Linear dynamic range vs. horizontal read-out frequency and sensor temperature
35°C
45°C
55°C
LINEAR OPERATION MIN. TYPICAL MAX. UNIT
Charge Transfer Efficiency 1 vertical
Charge Transfer Efficiency 1 horizontal
Image lag
Resolution (MTF) @ 56 lp/mm
Light sensitivity Green pixels @ 530nm
Red/Green ratio
Blue/Green ratio
Low Pass Shading 2
Random Non-Uniformity (RNU) 3
65
tbd
65
40
0.999995
0.999999
1000
80
55
2
1
0
tbd
95
70
5
5
%
%
mV/lux·s
%
%
%
%
Linear dynamic range is defined as the ratio of Qlin
to read-out noise with the read-out noise reduced by CDS.
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2003 February 6 10
DALSA Professional Imaging Preliminary specification
4M Full-Frame CCD Image Sensor FTF2416C
Figure 8 - Quantum efficiency versus wavelength
Figure 7 - Maximum number of images/second versus integration time
0
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
400 500 600 700 800 900 1000
Qua
ntum
Effi
cien
cy (
%)
Wavelength (nm)
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
11.0
12.0
0 10 20 30 40 50 60 70 80 90 100
Integration Time (ms)
Imag
es/s
ec.
1 output
2 outputs
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2003 February 6 11
DALSA Professional Imaging Preliminary specification
4M Full-Frame CCD Image Sensor FTF2416C
1 Qmax is determined from the low-pass filtered image.2 Qmax, shading is the maximum difference of the full-well charges of all pixels, relative to Qmax.3 The linear full-well capacity Qlin is calculated from linearity test (see dynamic range). The evaluation test guarantees 97% linearity.4 Charge handling capacity is the largest charge packet that can be transported through the register and read-out through the output buffer.5 Overexposure over entire area while maintaining good Vertical Anti-Blooming (VAB). It is tested by measuring the dark line.
Figure 9 - Charge handling
LINEAR/SATURATION MIN. TYPICAL MAX. UNIT
Full-well capacity saturation level (Qmax ) 1
Full-well capacity linear operation (Qlin ) 3
Charge handling capacity 4
Overexposure 5 handling
tbd
tbd
tbd
tbd
tbd
200
tbd
mV
mV
mV
x Qmax level
0
3500
2800
2100
1400
700
0 1 2 3 54
Out
put S
igna
l (m
V)
Exposure (arbitrary units)
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2003 February 6 12
DALSA Professional Imaging Preliminary specification
4M Full-Frame CCD Image Sensor FTF2416C
1
10
100
1000
0 10 20 30 40 50 60
1 FPN is the one-σ value of the highpass image.
1 Matching of the two outputs is specified as ∆ACF with respect to reference measured at the operating point (Qlin/2).
Figure 10 - Dark current versus temperature
Dar
k C
urre
nt (
pA/c
m2)
Temp. (oC)
OUTPUT BUFFERS MIN. TYPICAL MAX. UNIT
Conversion factor
Mutual conversion factor matching (∆ACF)1
Supply current
Bandwidth (Rload = 3.3kΩ)
Output impedance buffer (Rload = 2.2kΩ, Cload = 2pF)
32
70
35
0
4.5
85
400
38
2
µV/el.
µV/el.
mA
MHz
Ω
DARK CONDITION MIN. TYPICAL MAX. UNIT
Dark current level @ 20° C
Dark current level @ 60° C
Fixed Pattern Noise 1 (FPN) @ 60° C
RMS system readout noise over full bandwidth after CDS
-
-
10
0.3
15
tbd
30
0.6
20
tbd
pA/cm2
nA/cm2
mV
mV
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2003 February 6 13
DALSA Professional Imaging Preliminary specification
4M Full-Frame CCD Image Sensor FTF2416C
Application information
Current handlingOne of the purposes of VPS is to drain the holes that are generatedduring exposure of the sensor to light. Free electrons are eithertransported to the VRD connection and, if excessive (from over-exposure), free electrons are drained to VNS. No current shouldflow into any VPS connection of the sensor. During high overexposurea total current 5 to 10mA through all VPS connections together maybe expected. The PNP emitter follower in the circuit diagram (figure11) serves these current requirements.
VNS drains superfluous electrons as a result of overexposure. Inother words, it only sinks current. During high overexposure a totalcurrent of 5 to 10mA through all VNS connections together may beexpected. The clamp circuit, consisting of the diode and electrolyticcapacitor, enables the addition of a Charge Reset (CR) pulse on topof an otherwise stable VNS voltage. To protect the CCD, the currentresulting from this pulse should be limited. This can be accomplishedby designing a pulse generator with a rather high output impedance.
Uncoupling of DC voltagesAll DC voltages (not VNS, which has additional CR pulses asdescribed above) should be uncoupled with a 22nF uncouplingcapacitor. This capacitor must be mounted as close as possible tothe sensor pin. Further noise reduction (by bandwidth limiting) isachieved by the resistors in the connections between the sensorand its voltage supplies. The electrons that build up the chargepackets that will reach the floating diffusions only add up to a smallcurrent, which will flow through VRD. Therefore a large series resistorin the VRD connection may be used.
OutputsTo limit the on-chip power dissipation, the output buffers are designedwith open source outputs. Outputs to be used should therefore beloaded with a current source or more simply with a resistance toGND. In order to prevent the output (which typically has an outputimpedance of about 400Ω) from bandwidth limitation as a result ofcapacitive loading, load the output with an emitter follower built from
a high-frequency transistor. Mount the base of this transistor as closeas possible to the sensor and keep the connection between theemitter and the next stage short. The CCD output buffer can easilybe destroyed by ESD. By using this emitter follower, this danger issuppressed; do NOT reintroduce this danger by measuring directlyon the output pin of the sensor with an oscilloscope probe. Instead,measure on the output of the emitter follower. Slew rate limitation isavoided by avoiding a too-small quiescent current in the emitterfollower; about 10mA should do the job. The collector of the emitterfollower should be uncoupled properly to suppress the Miller effectfrom the base-collector capacitance.A CCD output load resistor of 3k3 typically results in a bandwidth of85MHz.
Device protectionThe output buffers of the FTF2416C are likely to be damaged if VPSrises above SFD or RD at any time. This danger is most realisticduring power-on or power-off of the camera. The RD voltage shouldalways be lower than the SFD voltage.
Never exceed the maximum output current. This may damage thedevice permanently. The maximum output current should be limitedto 10mA.Be especially aware that the output buffers of these image sensorsare very sensitive to ESD damage.
Because of the fact that our CCDs are built on an n-type substrate,we are dealing with some parasitic npn transistors. To avoid activationof these transistors during switch-on and switch-off of the camera,we recommend the application diagram of figure 11.
Unused sectionsTo reduce power consumption the following steps can be taken.Connect unused output register pins (C1...C4, SG) and unused SFSpins to zero Volts.
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2003 February 6 14
DALSA Professional Imaging Preliminary specification
4M Full-Frame CCD Image Sensor FTF2416C
Figure 11 - Application diagram for single output operation
Device Handling
An image sensor is a MOS device which can be destroyed by electro-static discharge (ESD). Therefore, the device should be handledwith care.
Always store the device with short-circuiting clamps or on conductivefoam. Always switch off all electric signals when inserting or removingthe sensor into or from a camera (the ESD protection in the CCDimage sensor process is less effective than the ESD protection ofstandard CMOS circuits).
Being a high quality optical device, it is important that the coverglass remain undamaged. When handling the sensor, use fingercots.
When cleaning the glass we recommend using ethanol (or possiblywater). Use of other liquids is strongly discouraged:
• if the cleaning liquid evaporates too quickly, rubbing is likely tocause ESD damage.
• the cover glass and its coating can be damaged by other liquids.
Rub the window carefully and slowly.
Dry rubbing of the window may cause electro-static charges orscratches which can destroy the device.
47K
36K
3K3
BC
860C
22K
BF
R92
2K2
100K
BAS28
BAS28
100K
BAS28
BA
T74
BA
T74
CCD OUT
VS
FD
TG
A4 A3
A2
A1
CR
SG
RG
C1
C2
C3
From V-Driver
From PPG
100K
100E
22n
22n
NS
BAT74
3K4K
53K
12K
56K
74ACT04
H DRIVER
1
22n
22n
37K5
100K
BAS28
22n
BAS28
100K
120K
BA
T74
VPS
VRD
VOG
BA
S28
22n
22n
VRD VRD
22n
22n
22n
NS
VOG
22n
NS_CR
22n
VPS
NS_CR
NS_CR
22n
NS
BAS28
NS
22n
22n
22n
74ACT04
H DRIVER
1
OU
TL
SF
DL
VC
SL
RD
L
RG
L
SG
L
C1L
C2L
C3L
VN
S
VN
S
C3R
C2R
C1R
SG
R
RG
R
RD
R
VC
SR
SF
DR
OU
TR
VP
SL
A2L
A3L
A4L
A1L
TG
L
VN
S
OG
L
VN
S
SF
SL
SF
SR
VN
S
OG
R
VN
S
TG
R
A1R
A3R
A4R
A2R
VP
SR
1u
35V
VPS
22n
22n
VSFD
VSFD
22n
22n
22n
BAS28
BAS28
100K
100K
BAS28
100K
CCD image sensor
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2003 February 6 15
DALSA Professional Imaging Preliminary specification
4M Full-Frame CCD Image Sensor FTF2416C
Pin configuration
The FTF 2416C is mounted in an LCC package with 40 pins (20 each side).
Figure 12 - Pin configuration (top view)
Notes: - Pin 1 has a small dot next to the lead. - "open" bond pads must be left unconnected. They are currently tied to VNS in the silicon, but this may change in the future.
Symbol Name Pin # (Out_L) Pin # (Out_R)
OUT Output 1 20
SFD Source Follower Drain 2 19
VCS Voltage Current Source 3 18
RD Reset Drain 4 17
RG Reset Gate 5 16
SG Summing Gate 6 15
C1 Register Clock (1) 7 14
C2 Register Clock (2) 8 13
C3 Register Clock (3) 9 12
A1 Image Clock (1 36 25
A2 Image Clock (2) 39 22
A3 Image Clock (3) 37 24
A4 Image Clock (4) 38 23
TG Transfer Gate 35 26
OG Output Gate 33 28
SFS Source Follower Source 31 30
VPS P Substrate 40 21
VNS N Substrate 10, 32, 34 11, 27, 28
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2003 February 6 16
DALSA Professional Imaging Preliminary specification
4M Full-Frame CCD Image Sensor FTF2416C
Package information
Figure 13 - Mechanical drawing of the PGA package
Sensor flatness: < 30 µm (P-V)
Cover glass: Hoya CG1Thickness of cover glass: 1 ± 0.05Refractive index: nd = 1.53Double sided AR coating < 1% (430-660 nm) reflectionHermetically sealed package
All drawing units are in mm
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2003 February 6 17
DALSA Professional Imaging Preliminary specification
4M Full-Frame CCD Image Sensor FTF2416C
Order codesThe sensor can be ordered using the following code:
You can contact DALSA Professional Imaging at the followingaddress:
DALSAProfessional ImagingProf. Holstlaan 4 (WZ08)5656 AA EindhovenThe Netherlands
phone +31 - 40 - 27 45 600fax +31 - 40 - 27 44 090
www.dalsa.com
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© D
ALS
A B
.V. 2
002FTF2416C sensor
Description Quality Grade Order Code
FTF2416c Test grade xxxx xxx xxxx