1 • PowerSOC—Cork Ireland • Sept-08 Confidential Proprietary
High Performance Integrated Power MOSFETs
P. Moens and M. Tack
ON Semiconductor, Belgium
2 • PowerSOC—Cork Ireland • Sept-08 Confidential Proprietary
High Performance Integrated MOSFETs• Integrate
– High Voltage (<100V) - Power (< 10A) functions
– with Intelligence (μC, DSP, memory, logic)
• High performance– Sub-micron CMOS (feature size well below 0.5 µm)
– Competitive Ron-Vbd-(Qgd)
• Driven by high growth markets: Automotive, Communications and Industrial Applications
• Often operating in Harsh Environments:– High temperature : >150ºC up to 200 ºC
– ESD (8kV HBM, SystemESD, ...), EMC, LU, …
• Some requiring highest quality levels (“0 ppm”)
3 • PowerSOC—Cork Ireland • Sept-08 Confidential Proprietary
Typical Integrated Power SoC
What ? Innovation by ?
HV/power device
Digital Scaling
LV IOs Scaling
HV analog Isolation
LV analog Scaling
4 • PowerSOC—Cork Ireland • Sept-08 Confidential Proprietary
Outline
• Integrated Power Technology Scaling
• Technology Options
• Power Drivers
– Ron–Vbd trade-off
• Isolation Density
– Lateral (component-to-component)
– Vertical (component-to-substrate)
• Safe Operating Area
– Electrical and Thermal Effects
• Conclusions
5 • PowerSOC—Cork Ireland • Sept-08 Confidential Proprietary
Integrated Power Node Scaling
0,1
1
1990 1995 2000 2005 2010
Te
ch
no
log
y N
od
e (
µm
)
~2 years
6-8 years
Year of Market Introduction
CMO
S Logic
Smart Pow
er 50V-100V
Automotive Grade
Smart Power 50V-100V
6 • PowerSOC—Cork Ireland • Sept-08 Confidential Proprietary
Technology Options
• HV CMOS (CMOS+)– (Deep) submicron CMOS process
– Few extra process layers to cope with HV requirements
– No buried layers, no power metal
– Standard Junction Isolation
• Smart Power BCD– Submicron CMOS process
– Substantial extra process cost
– Buried layers for robustness against LU, ESD, ….
– Power Metal to cope with high current capability (several Amps)
– Trench Isolation (for higher voltage ranges)
• SOI – (Sub) micron CMOS process
– Complete dielectric isolation, allowing HV (>150V)
7 • PowerSOC—Cork Ireland • Sept-08 Confidential Proprietary
Techno Options ���� Application Features
CMOS+
DTI/p++
VDM
OS
RESU
RF
Power M
Buried
Layer
SOI
Isol dens
Ron
Power
Latchup
Floating
High Temp
SOA/ESD
Cost
Application Features
Techno Features
+++
++ +
++
++ ++
++
----
-
-
-
-
-
-
---
+
Integrated Power
+
+
-
-
+
+ +
8 • PowerSOC—Cork Ireland • Sept-08 Confidential Proprietary
Power Drivers – LDMOS
Floating RESURF LDMOS in n-epi
Source
GateDrain
ndrift layer
N+
P+
pbody
N+
p-substrate
n-epi
buried N+
N+
buried P+
pwell
9 • PowerSOC—Cork Ireland • Sept-08 Confidential Proprietary
Power Drivers – Q-VDMOS
• VDMOS: Vbd not scalable, depends on technology
• JFET principle protects the gate ⇒ ROBUST
Source
pbody
p-substrate
buried N+
N+
Drain Bulk Source
P+
N+
Bulk
pbody
N+
P+
N sinker+
Gate
n-epi
10 • PowerSOC—Cork Ireland • Sept-08 Confidential Proprietary
Power Drivers – Trench-Based MOS (1)
• A TB-MOS is a LDMOS integrated vertically in Silicon, benefit from the depth of the Si wafer !!
Top silicon
Top silicon
Top silicon
11 • PowerSOC—Cork Ireland • Sept-08 Confidential Proprietary
Power Drivers – Trench-Based MOS (2)
• Spacing between trenches (w) is a crucial device parameter
• Vbd depends on w (silicon fin thickness parameter)
– w<wcrit : full depletion of drift region
– w>wcrit : p-body/n-epi junction breaks first
n-e
pi
ga
te
ga
te
ga
te
ga
te
BLN = drain
p-body p-body p-body
Source terminal
Tre
nch
oxid
e
Thin gate oxide
VK
w 20
30
40
50
60
70
80
90
100
1 1.2 1.4 1.6 1.8 2 2.2
w (µm)
Vb
d (
V)
Vbd of p-body/nepijunction
12 • PowerSOC—Cork Ireland • Sept-08 Confidential Proprietary
Power Drivers – Taskmaster (50-100V)
• Ron (Area) scaling driven by device innovation– VDMOS�rLDMOS�TBMOS
10
100
1000
1994 1996 1998 2000 2002 2004 2006 2008 2010
Year of publication
Ro
n_
10
0V
(m
Oh
m*m
m2
)
TB-MOS
VDMOS
rLDMOS
10
100
1000
10 100 1000
Vbd (V)
Ro
n (
mO
hm
*mm
2)
rLDMOSVDMOSTB-MOSSeries1
Silicon Limit
13 • PowerSOC—Cork Ireland • Sept-08 Confidential Proprietary
Electrical isolation
• Junction isolation
– Simple and straightforward
– Area increases with blocking voltage requirement
(e.g. ~30 µm for 100V isolation)
• Deep trench isolation
– Requires deep trench etching equipment
– Area consumption independent of voltage requirement (e.g. ~6 µm for 100V isolation)
– Allows for innovative solutions
14 • PowerSOC—Cork Ireland • Sept-08 Confidential Proprietary
Deep Trench Isolation (1)
• Increase trench isolation breakdown through voltage
divider concept
80
90
100
110
120
130
140
150
0 0.2 0.4 0.6 0.8 1
ratio
Vb
d (
V)
outer trench
inner trench
Breakdown of isolation structure can be significantly increased
6 µm
30 µm
15 • PowerSOC—Cork Ireland • Sept-08 Confidential Proprietary
Deep Trench Isolation (2)
• Latch-up monitor : collected current/emitted current
• “SOI-alike” isolation
0.000001
0.00001
0.0001
0.001
0.01
0.1
1
10
20 22 24 26 28 30 32 34 36 38 40
1/kT (eV-1
)
I c/I
e (
%)
2
2
3
3
4
4
# trenches
10-20 mOhm.cm
2-5 mOhm.cm
Substrate resistivityis prime parameter for latch-up improvement
� reduces minority carrier lifetime
16 • PowerSOC—Cork Ireland • Sept-08 Confidential Proprietary
Safe Operating Area
• Total Safe Operating Area (SOA)
– Electrical SOA : triggering of the parasitic npn transistor due to electrical effects. Short pulses (ns-µs). E.g. ESD, CDM. Destruction of the device.
– Thermal SOA : triggering of the parasitic npn transistor due to thermal effects. Medium time pulses (µs-ms). E.g. Inductive switching. Destruction of the device.
– Hot Carrier SOA : slowly shifting of the device parameter upon electrical gate/drain stress. Long term : seconds to year.
– Interface/dielectric wear-out : TDDB, NBTI, ….
17 • PowerSOC—Cork Ireland • Sept-08 Confidential Proprietary
Safe Operating Area—Electrical Effects (1)
• Destruction of the power device by triggering of the parasitic NPN transistor by electrical effects
• Measured by 100 ns TLP pulses
200
300
400
500
600
700
800
30 40 50 60 70 80 90 100Vds (V)
I sb (
µA
/µm
)
□ VDMOS
∆ LDMOS
○ TBMOS
(a)
02000400060008000
100001200014000160001800020000
30 40 50 60 70 80 90 100Vds (V)
Pd
en
s,s
b (
W/m
m2)
(b) □ VDMOS
∆ LDMOS
○ TBMOS
• TB-MOS has 4X larger power density !
18 • PowerSOC—Cork Ireland • Sept-08 Confidential Proprietary
Safe Operating Area—Electrical Effects (2)
• What is the limit for Pdens,sb ?
• Device will snapback when silicon becomes intrinsic.
• Tsnap-back is dependent on doping level, ∆Tsb~500 K
• Silicon parameters (k, D) are temperature dependent �need for self-consistency check.
02000400060008000
100001200014000160001800020000
30 40 50 60 70 80 90 100Vds (V)
Pd
en
s,s
b (W
/mm
2)
(b) □ VDMOS
∆ LDMOS
○ TBMOStD
TkcmWP
sb
sb
..4
..)/( 2 ∆
=π
TB-MOS approaches the limits of silicon
19 • PowerSOC—Cork Ireland • Sept-08 Confidential Proprietary
Safe Operating Area—Thermal Effects (1)
• Thermal Safe Operating Area yields information on time-to-fail under power pulsing (µs-ms)
• Determined by the properties of Silicon
• No difference between LDMOS and VDMOS
• TB-MOS slightly worse (trench oxide blocks heat)
• Mainly dependent on area of the driver i.e. cooling efficiency
0
0.05
0.1
0.15
0.2
0.25
Ids (
A/m
m)
10µs
100
30
300
1ms
3
area 0.37mm2
(a)
0
0.05
0.1
0.15
0.2
0.25
0 5 10 15 20 25 30 35 40
Ids (
A/m
m)
Vds (V)
10µs
100300
1ms
3
30
area 0.043mm2
(b)
20 • PowerSOC—Cork Ireland • Sept-08 Confidential Proprietary
Thermal SOA (Energy Capability)
• Upon thermal failure : device is melted
in center (hottest spot). Vds=12V
Tcrit ~ 800K (thermal runaway)
-800
-600
-400
-200
0
200
400
600
800
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
pulse time (ms)
�� ��T
(K
), V
dro
p (
mV
).
0
1
2
3
4
5
6
Ids (A
)
∆ T
V drop
Ι
∆ T~550K
loss o f gate
contro le
∆∆ ∆∆T
(K)
21 • PowerSOC—Cork Ireland • Sept-08 Confidential Proprietary
Thermal SOA (Energy Capability)
• Power Metal (Cu) effectively reduces Tmax for single pulse, hence also improves Energy Capability
0
1
2
3
4
5
6
7
8
0
5
10
15
20
0 0.2 0.4 0.6 0.8 1
Ids (
A)
Vds (V
)time (s)
reference DUTcopper DUT
full lines : Idsdotted lines : Vds
failure
0
50
100
150
200
250
300
ref opening only full extended full-comb
center passivation opening25um copper
EC
@1m
s (
mJ/m
m2)
0
50
100
150
200
250
300
ref opening only full extended full-comb
center passivation opening25um copper
EC
@1m
s (
mJ/m
m2)
22 • PowerSOC—Cork Ireland • Sept-08 Confidential Proprietary
Critical Temperature
• Tcrit is dependent on Vds (electro-thermal effects)
• Extraction needs to take into account temperature dependency of silicon properties (thermal conductivity)
• No difference between VDMOS and LDMOS (within exp. error). TB-MOS has slightly lower Tcrit
100
1000
0.01 0.1 1 10
0.0110.043
0.160.37P
ow
er
to f
ailu
re (
W/m
m2)
time (ms)
Teff = 355K
Tcrit = 594K
area (mm2)
Vds=38V
Tcrit=721K
0
100
200
300
400
500
600
700
800
200 300 400 500 600 700 800
area 0.011mm2
Po
we
r a
t 1
ms (
W/m
m2)
Ambient temperature (K)
dotted line: before calibrationfull line: after calibration
Vds = 38V
Vds = 25V
23 • PowerSOC—Cork Ireland • Sept-08 Confidential Proprietary
Conclusions
• Trends and Challenges for innovation in integrated power technologies– Scaling of the technology node
– Device Innovation
– Electrical Isolation
– Safe Operating Area
• Correct choice of devices depends on– Performance
– SOA – robustness
– Cost