Design Examples
1
Outlines
• Power Integrity Overview
• PI-induced EMI effect
• PI for LPDDR4 in InFO
2
Power Integrity
Overview
High-f Caps
Mid-f Caps
Motherboard
VRM
Power Delivery Network
. VRM
. Interconnects
. DeCap’s on PCB & package
4
Hierarchical Power Delivery Network
Multiple power/
ground planes as
PDN
5
Challenges in Power Delivery System
• With clock speeds increasing, supply voltages decreasing
and the number of device on a chip increasing, the SSN is
getting seriously.
• SSN is one of the major concerns for designing high speed
circuit.
PQ
NQ
dd VSystem
GroundSystem
effL
effL
Vin Vout Vin Vout
Noise voltage↑
Number of device↑
Effective
inductance of PDN
Change of current↑
Rise/Fall time↓
diV N L
dt
6
Target Impedance
• Target impedance states that
voltage to current ratio has to
equal the impedance in the
network.
• If exceeds it at any freq.,
resultant power supply noise
will exceeds 5% of Vdd
7
0.1 1 10 100 1000Frequency(MHz)
0.001
0.01
0.1
1
Z r
es
po
nse
(Oh
ms)) (
Ripple
MAX
ddTarget
I
VZ
Power Noise Signature
8
PI-Induced EMI
Overview – Ground Bounce Induced EMI
• Induced from ground bounce or other mechanisms.
• Fringing field and radiation.
• Interfere other devices.
• Signal-noise fluctuation, system crash.
10
Digital
IC Die
RF IC
Die
Ground
PowerParallel plates
stripline
Microstrip line
Bonding Wire
Bend
Through-hole
Vias
Solder Ball
Decoupling capacitor
GBN coupling to P/G
via of Digital IC Die
GBN coupling
to Signal Trace
Signal Trace
Edge Radiation
Bend structure
Radiation
Digital
IC Die
Radiation Radiation
Bonding wire
20-H Rule vs. Edge Radiation
• 20-H rule – Back the edge of the power plane away from the edge of
the board by a distance equal to 20 times the separation distance
between the planes.
• Ground plane acts as a reflector.
• Maximum 6dB incremental in field strength ideally.
11
Cross View and Radiation 20-H rule
De-Caps vs. Edge Radiation
• On the whole board
• Shift the resonances
• Work at lower frequency (depends on
the resonance of de-cap)
12
With capacitors
10nF/1nH/1mOhm
Without 20-H rule
With 20-H rule
20-H Rule vs. Edge Radiation
13
Resonance Mode Frequency (MHz) Radiated E-Field (0H) Radiated E-Field (20H)
TM01 940 102.7dB 108.1dB
TM10 1490 110.9dB 115.9dB
TM02 1640 101.2dB 103.6dB
TM11 1840 107.6dB 113.1dB
Without capacitors (only 20-H rule)
Ref.: S. Ikami, and A. Sakurai, ―Practical analysis on 20H rule for PCB‖ Asia-Pacific
Symp. EMC, pp. 180-183, 2008
Key Parameters of Edge Radiation
• Cavity Model
• Radiation field
14
0
01 1
1( ', ')
'4
rad
jk R
ij
C
E F
n Z I x y eh h
dsR
h
2 f
j h
h
f
Board height
Frequency
Radiation Model of Three-Layer GPG
Structure
• Mode decomposition – even- and odd-mode.
• Array factor.
15
Ground
Power
Ground
: Equivalent magnetic current (outward the sheet)
: Equivalent magnetic current (inward the sheet)
h
h
Io
Ground
Power
Ground
Ground
Power
Ground
h
h
h
h
1
2oI
1
2oI
1
2oI
1
2oI
0 ,cos for even mode
2, for odd mode
jk hAF
Magnetic current pair of Even Mode
Even Mode
Odd Mode
Even- and Odd-Mode Radiation and
Attenuation Factor • With sufficient shorting vias, odd-
mode excitation can be greatly
reduced.
• Ratio of even-mode and odd-mode
radiation is given by an attenuation
factor:
• For example, EMI suppression of
20dB from dc to 3GHz layer
height h < 3.1mm so that A < 0.1 for
all .
16
h = 1mm
εr = 4.4
(0,0) (140,0)
(140,140)(0,140)
(70,70)
l = 1
40m
m
w = 140mm
0 1 2 3
Frequency (GHz)
-160
-140
-120
-100
-80
-60
To
tal R
ad
iate
d P
ow
er
(dB
W)
Three-Layer Radiation, Iinc = 1mA
Even-Mode Excitation, h = 1mm
Odd-Mode Excitation, h = 1mm
Even-Mode Excitation, h = 0.5mm
Odd-Mode Excitation, h = 0.5mm
Io = 1mA
Io
1
ideal ideal 02
rad, even
rad, odd
cos ; A A A k hE
E
Simplification of GPG Structure
with Shorting Vias
• Via stitched three-layer structure with odd-mode excitation can be
simplified to a two-layer structure with shorting vias.
17
h
h
h
1
2oI
1
2oI
Io
: Source: Shorting vias
Einc
P
D
r
PMC
PMC
PM
C
x
y
-DD
hr
P
Einc
x
y
z
Canonical problem
Top View Side View
Even Mode Excitation
Scattering Field Analysis in Canonical
Problem
• Incident wave is from the left side of canonical problem
• Boundary condition: total E-field should be zero at the via
• The odd-mode suppression factor Aodd:
18
(2)0
1
4( )z via
jE j I H k
Einc
P
D
x
y
-D D
Ivia
I'via I'via
I'via
I'viaI'via
: Real via with current Ivia : Image via with image current I'via
Einc
P
D
r
PMC
PMC
PM
C
x
y
-D
( , ) ( , )
2 cos , ,
tot jkx jkx s
z inc inc z
inc via
E x y E e E e E x y
E kx j I g x D y g x D y
,max
odd
2 2
(0, ) (0, 0)
2 ( , 0) 2 2 cos( )
( , ) (2 , )
total total
z z
inc inc
P P
E y EA
E E
g DkD kr
g r g D r
Ref.: K.-B. Wu, et. al., “Modeling and optimal design of shorting vias to
suppress radiated emission in high-speed alternating PCB planes,” IEEE T-
CPMT, vol. 1, no. 4, pp. 566-573, Apr. 2011.
Design Procedure for Shorting Vias
• Weighting : (kD<π/2)
• Design from low importance to high importance
• Choose 1mm for example
• Step1: Determine the distance D from edge to shorting via
• Maximum E-field suppression when kD = 0.15 ~ 0.6
• Choose kD=0.15, D1.138mm @3GHz
• Step3: Determine radius ―r‖
• kr given by PCB factory
• Suppose kr=0.02, r151.7um@3GHz
• Step4: Choose the via pitch P by Aodd
• Use the design chart
• Find corresponding kP=0.287
• For 3GHz, P2.178mm
19
kP kD kr
kD = 0.15 (rad)
kP
(ra
d)
kr (rad)
Measurement Environment
• GTEM cell (GHz Transverse Electromagnetic Cell)
• Function generator—SG-hp83650B (10MHz-50GHz)
• Spectrum analyzer—R&S FSP (9kHz-40GHz)
20
GTEM Cell
Spectrum AnalyzerFunction Generator
DUT
Cable BCable A
GTEM 500
Function Generator
Spectrum Analyzer
Measurement Results with Shorting Vias
21
0 1 2 3
Frequency (GHz)
-160
-140
-120
-100
-80
-60
To
tal R
ad
iate
d P
ow
er
(dB
W)
Three-Layer Radiation with Vias Comparison
Simulation Data (HFSS)
Measurement Data(P = 2.178mm, D = 1.138mm, r = 6mil)
Simulation Data (without vias))
2 2
0 11
08inc
inc
I meas
in
Z Z IP P
Z P
h = 1mm
εr = 4.4
(0,0) (140,0)
(140,140)(0,140)
(70,70)l =
14
0m
m
w = 140mm
h
h
Iinc
Ground
Power
GroundShorting vias
Cross View
Top View
Applications to Next
Generation DRAM @ 3DIC
Chip and Package Stacking
23
Next Generation DRAM
• Wide IO II / LPDDR4
• High-bandwidth and low-power DRAM
• Thin and compact: 3D integration
• Wafer level packaging (WLP) 3D-IC
– Integrated Fan-Out in TSMC.
– LPDDR3 / LPDDR4.
– Cost-effective technique for 3D-IC.
– Vertical interconnect of through
InFO via between stacked chips.
– Thinner
– Lower loss on molding
compound and routing area
but longer interconnect.
– Better thermal.
InterfaceVDD/VDDQ
Speed
Density
PKG
2010 2011 2012 2013 2014 2015
LPDDR2 1.2V/1.2V LPDDR3 1.2V/1.2V LPDDR4
Wide-IO and Wide-IO 2
6.4GB/s 8.5GB/s 12.8GB/s Up to 68GB/s
2Gb 4Gb 8Gb
Up to 4 die stacks : 1.0mm -> 0.9mm and below
24
Bandwidth of Mobile DRAM
25
Next Generation Mobile DRAM Using
3DIC Type Wide IO II LPDDR4
Chip photo
Pin amounts ~430 per die (4ch die) 66 per die
Signaling speed Max. 1066 Mpbs Max. 4266 Mpbs
Bandwidth Up to 68 GBps Up to 34 GBps
Package
TSV-based 3DIC Various, WLP or PoP
Cost Higher Lower
Energy per Byte ~40mW ~60mW
Wide IO DRAM
AP Die
Substrate
TSV
Micro bump
BumpLower Die
Upper Die
Bond wire Bond wire
Micro bump Micro bumpTI
V
TIV
TIV
TIV
TIV
TIV
RDL
Solder ballPCB
Molding compoundMolding compound
26
Who Uses LPDDR4?
27
Signal/Power Integrity in 3D
Packaging • Signal integrity: providing the solution space and guideline for RDL
routing design on InFO to meet LPDDR4 specification.
• Power integrity: developing and designing the decoupling capacitor for
InFO power integrity.
0.50.55
0.55
0.6
0.6
0.6
0.65
0.65
0.65
0.65
0.7
0.7
0.7
0.7
0.75
0.75
0.75
0.75
0.75
0.8
0.8
0.8
0.8
0.8
0.85
0.85
0.850.85
0.85
0.9
0.9
InFO RDL Length (mm)
Da
ta R
ate
(M
bps)
3 4 5 6 7 8 9 10
2000
2500
3000
3500
4000
Unit: UI
0.01 0.1 1 10Frequency (GHz)
0.01
0.1
1
10
100
1000
Inp
ut
Imp
ed
an
ce
(O
hm
)
Only with 1pF on-chip capacitance
5 de-caps (Cap 4+5+6+7+9)
1 de-cap (10pF)
1 de-cap (100pF)
Signal Integrity Power Integrity
Good eye-diagram
28
– Set the upper and lower bound from
the requirement of Spec.
– Acquire the maximum eye height
Electrical Definition of Eye for
LPDDR4 – Set the right and left bound from
the requirement of Spec.
– Acquire the maximum eye width
Ref: LPDDR4 specification,JESD209-4 , JEDEC Standard (2014, Aug.).Available: http://www.jedec.org
Eye width
Eye height
requirement
from Spec.
psec
Vo
lta
ge Eye height
requirement
from Spec.
Eye width requirement
from Spec.
Eye width requirement
from Spec.
Eye height
psec
Vo
lta
ge
▪ Clear eye mask in JEDEC definition.
▪ Rectangular eye mask.
29
Bottleneck of Signal Integrity in InFO
LPDDR4
Substrate
RDL
Wire-bonding
100 μm50 μm
300 μm200 μm
Mounding Compound
Substrate
RDL
TIV and micro bump
G
G
G
PCB (Printed circuit board)
Micro bump
10000 μm
3000 μm ~ 8000 μm
TIV
RDL (Re-distribution layer)
Upper Stacked-die (LPDDR4)
Molding compound
RDLLower die (AP)
Solder ball
Wire-Bonding
DK = 4, Df = 0.01
Ground
Signal5 μm
Silicon Chip
Power
@ 2400Mbps @ 3200Mbps @ 4266Mbps
0.22UI
140mV
0.25UI
140mV
0.25UI
120mV
DK = 3.1, Df = 0.017Ground
Signal5 μm
5 μm
Silicon Chip
Power
30
Model Construction for Lower
RDL and TIV
PCB (Printed circuit board)
RDL
Upper Stacked-die (LPDDR4)
Lower die (AP)
Wire-Bonding
On-chip de-capIO
VRMOn package
de-cap
On board de-cap
On board de-cap
IO
Through InFO Via (TIV) Model
VSSQ(Ground)
DQ8_A
DQ9_A
DQ10_A
DQ11_A
DQ8_A
DQ9_A
DQ10_A
DQ11_A
Lower RDL
VSSQ(Ground)
VDDQ(Power)
VDDQ(Power)TIVTIVTIV
TIVTIVTIV
Lower RDL (AP) Model
VSSQ(Ground)
DQ8_A
DQ9_A
DQ10_A
DQ11_A
DQ8_A
DQ9_A
DQ10_A
DQ11_A
t
Vagg
PRBS1
Vvic
PRBS2
Con-chip
= 1pf
Vvic
Vagg
IO
IO
IO
IO
AP DieTIV
Vagg
Vagg
De-cap1
De-cap2
VSSQ(Ground)
VDDQ(Power)
VDDQ(Power)
On-package de-cap
31
Model Construction for Upper
RDL and PCB
Upper RDL (DRAM) Model
VSSQ(Gnd)
DQ8_A
DQ9_A
DQ10_A
DQ11_A
DQ8_A
DQ9_A
DQ10_A
DQ11_A
Con-chip
= 1pf
DRAM DieTIV
VSSQ(Ground)
VDDQ(Power)
VDDQ(Power)
Cterm=1pf
PCB (Printed circuit board)
RDL
Upper Stacked-die (LPDDR4)
Lower die (AP)
Wire-Bonding
On-chip de-capIO
VRMOn package
de-cap
On board de-cap
On board de-cap
IO
PCB Power plane
InFOVRM
Ground plane
50mm
50m
m
VDDQ(Power)
VSSQ(Ground)
PCB Power/Ground Model
4 mil
TIV
32
PCB (Printed circuit board)
RDL
Upper Stacked-die (LPDDR4)
Lower die (AP)
Wire-Bonding
On-chip de-capIO
VRMOn package
de-cap
On board de-cap
On board de-cap
IO
Model Connection
• Vvic (victom) and Vagg
(aggressor) are
different patterns to
excite maximum
crosstalk condition.
• Voltage probes are at
victim (DQ10_A) and
btw power/ground
nets on IOs.
• Only on-chip and on-
package decaps are
in simulation
Lower RDL
(AP) Model
VSSQ(Ground)
DQ8_A
DQ9_A
DQ10_A
DQ11_A
t
Vagg
PRBS1
Vvic
PRBS2
Con-chip
= 1pf
Vvic
Vagg
IO
IO
IO
IO
Vagg
Vagg
De-cap1
De-cap2
VDDQ(Power)
On-package de-cap
Through InFO
Via (TIV)DQ8_A
DQ9_A
DQ10_A
DQ11_A
VSSQ(Ground)
VDDQ(Power)
VDDQ(Power)
VSSQ(Global Ground)
PCB Power/Ground
Model
VSSQ(Gnd)
DQ8_A
DQ9_A
DQ10_A
DQ11_A
Con-chip
= 1pf
VSSQ(Ground)
VDDQ(Power)
VDDQ(Power)
Cterm=1pf
Upper RDL
(DRAM) Model
V
DQ8_A
DQ9_A
DQ10_A
DQ11_A
Voltage probe
at Victim
V+
V-
Voltage probe
between power and
ground (V+-V-)
33
Signal Integrity by Lower RTL
Design
GSPSGSPSG @ 2400Mbps GSPSGSPSG @ 3200Mbps GSPSGSPSG @ 4266Mbps
GS SPS SG @ 2400Mbps GS SPS SG @ 3200Mbps GS SPS SG @ 4266Mbps
GSSPSSG @ 2400Mbps GSSPSSG @ 3200Mbps GSSPSSG @ 4266Mbps
5 μm5 μm
Silicon Chip
Ground Power DK = 3.1, Df = 0.017
DK = 3.1, Df = 0.017Ground
5 μm 5 μm
Silicon Chip
Power
DK = 3.1, Df = 0.017Ground
Signal5 μm
5 μm
Silicon Chip
Power
34
Solution Space for DQ
(GSPSGSPSG) • Dominant factor: InFO RDL length
• Bi-directional transmission.
• Under requirement of Spec.
0.50.55
0.55
0.6
0.6
0.6
0.65
0.65
0.65
0.65
0.7
0.7
0.7
0.7
0.75
0.75
0.75
0.75
0.75
0.8
0.8
0.8
0.8
0.8
0.85
0.85
0.850.85
0.85
0.9
0.9
InFO RDL Length (mm)
Da
ta R
ate
(M
bps)
3 4 5 6 7 8 9 10
2000
2500
3000
3500
4000
Unit: UI
PCB (Printed circuit board)10000 μm
RDL (Re-distribution layer)
Upper Stacked-die (LPDDR4)
Lower die (AP)
Wire-Bonding
De-cap De-capOn-chip decap
IO
De-cap
DK = 3.1, Df = 0.017Ground
5 μm 5 μm
Silicon Chip
Power
Eye width (normalized) Eye height
200220
220
240
240
260
260
260
280
280
280
300
300
300
300
320
320
320
320
320
340
340
340
340
340
340
360
360
360
360
380
380
380
InFO RDL Length (mm)
Da
ta R
ate
(M
bp
s)
3 4 5 6 7 8 9 10
2000
2500
3000
3500
4000
Unit: mV
35
Power Distribution System for
InFO
PCB (Printed circuit board)10000 μm
RDL
Upper Stacked-die (LPDDR4)
Lower die (AP)
Wire-Bonding
On-chip de-capIO
On board de-cap
VRMOn package
de-cap
On board de-cap
On board de-cap
IO
• Power Distribution System – LPDDR4 to AP
– AP to LPDDR4
• Improve power integrity – Change layout of power bus
– Add decoupling capacitors
• Decoupling capacitors – On-chip capacitance: without parasitic effect but small capacitance (~1pF)
– Off-chip capacitance
• On package de-cap: close to IO but small area and choice for de-cap
• On board de-cap: the most flexible but far away from IO
TIV Region
TIV Region
AP Die
AP Die
GSSPSSGSSPSSG
36
Single Node Analysis for De-caps
Design
1 1 1
2 2 ( )( )
i j
antii j i j j i
i j
i j
C Cf
C C C C L LL L
C C
( ) ( )1
1 1 ( )
i i j j
in
i j i j
i j
R jX R jXZ
R R j X X
Z Z
▪
Z
Li
CjCi
Ri
Lj
Rj
1
1
i i i i i
i
j j j j j
j
X L Z R jXC
X L Z R jXC
37
De-cap Design Example
▪ Current drawing per IO: ~10mA
▪ 10% tolerance of power noise(0.44V):0.44x10%
▪ Number of switching IO: 4
▪ Target impedance: 1 Ohm
5 various de-caps: type 3 4 6 7 10
2 identical de-caps: 47p + 47p
2 identical de-caps: 100p + 100p
1 de-cap: 100p
1 de-cap: 4.7n
Z
Li
CjCi
Ri
Lj
Rj
0.01 0.1 1 10Frequency (GHz)
0.01
0.1
1
10
100
1000
10000
Inp
ut
Imp
ed
an
ce
(O
hm
)
Only 1pF on-chip capacitance
1pF on-chip capacitance and 5 decaps
1pF on-chip capacitance and 47p+47p decaps
1pF on-chip capacitance and 100p+100p decaps
1pF on-chip capacitance and 100p decap
1pF on-chip capacitance and 4.7n decap
38
Comparison of Power Noise Signature
• As design for target impedance, the 5 de-caps case satisfies the 10% noise
requirement.
Only 1pF on-chip capacitance 100p decap 4.7n decap
47p + 47p decaps
210mV
53mV
31mV
100p + 100p decaps
33mV
48mV
5 μm5 μm
Silicon Chip
Ground Power DK = 3.1, Df = 0.016
39
DQ Eye-Diagram Comparison @
4266MHz
EW EH
Only on-chip cap Out of Spec.
4.7n 0.34UI 192mV
100p 0.34UI 193mV
47p + 47p 0.35UI 208mV
100p + 100p 0.35UI 208mV
4.7n de-cap 100p de-cap
47p + 47p de-caps 100p + 100p de-caps
w/o decap
40
DQ Eye-Diagram Comparison @ 4266MHz Using 100pF Decap and Different ESL
EW EH
Only on-chip cap Out of Spec.
Ideal power 0.54UI 289mV
100pF+1nF ESL 0.40UI 238mV
100pF+0.4nF ESL 0.45UI 261mV
0.4nH ESL (0.333nH total)
Only on-chip capacitance
5 μm5 μm
Silicon Chip
Ground Power DK = 3.1, Df = 0.016
1nH ESL (0.667nH total)
Ideal power
41
PI Design by Meshed Ground/Power
85μm
135μ
m
Via
Silicon Chip
Ground Power1 2 3 4
Silicon Chip
Ground Power1 2 3 4
5 μm5 μm
Silicon Chip
Ground Power DK = 3.1, Df = 0.016
Only on-chip capacitance
EW: 0.49UI
EH: 276mV
42
Conclusions
• Solution space is proposed and the pin assignment can meet the
specification up to 4266 Mbps.
• One 100p de-cap can meet the PI requirement at 4266 Mbps.
However, the large power noise will be induced when the
resonant frequency is excited at IO.
• For 8mm GSPSGSPSG routing, one 100p decap with smaller
than 2.1nH ESL can meet design requirement.
• Using meshed ground/power, InFO without on-package decap
but with improved performance deserves further study.
43