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How Computers Work Lecture 5 Page 1
How Computers Work
Lecture 5
Memory Implementation
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WD Memory
WDRegister File
RA2Memory
RD2
WA RC
WERF WEMEM
WA
WEWE
A B
A op B
Register FileRA1
RD1
RA2
RD2
RA RB RC
BSELASEL
ALUFN
WDSEL0
0 1
010 1 2
1
ALU
Register FileSEXT
C
4:0 9:5 20:5 25:2131:26
OPCODE
RA1Memory
RD1
PCQ
+1
DPC
Z
0 1
JMP(R31,XADDR,XP)
XADDR
0 1
2
ISEL
PCSEL
OPCODE
A Top-Down View of the Beta ArchitectureWith st(ra,C,rc) : Mem[C+<rc>] <- <ra>
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Today’s Lecture:How do we build these?
WD Memory
WDRegister File
RA2Memory
RD2
WA WA
WEWE
Register FileRA1
RD1
RA2
RD2Register File
RA1Memory
RD1
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Recall the Enable-Controlled Register
D
E
Q
CLK
3232
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How do we select 1 of 31 registers to read?D
E
Q
D
E
Q
D
E
Q
.
.
.
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A: Add an output selector.D
E
Q
D
E
Q
D
E
Q
.
.
.
0
RA1
RD1 = <RA1>
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Q: How do we add a second port?D
E
Q
D
E
Q
D
E
Q
.
.
.
0
RA1
RD1 = <RA1>
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A: Add a second multiplexorD
E
Q
D
E
Q
D
E
Q
.
.
.
0
RA1
RD1 = <RA1>
RA2
RD2 = <RA2>
0
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Q: How do we write selectively?D
E
Q
D
E
Q
D
E
Q
.
.
.
0
RA1
RD1 = <RA1>
RA2
RD2 = <RA2>
0
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A: Use a decoder on the EnablesD
E
Q
D
E
Q
D
E
Q
.
.
.
0
RA1
RD1 = <RA1>
RA2
RD2 = <RA2>
0
WERF
WA
WD
0
1
30
31
0
1
30
31
0
1
30
31
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The Decoder / Demultiplexor
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To minimize wires:D
E
Q
D
E
Q
D
E
Q
.
.
.
0
RA1
RD1
RA2
0
WERF
WA
WD
0
1
30
31
0
1
30
31
0
1
30
31
D
E
Q
D
E
Q
D
E
Q
.
.
.
RD2
WD
0
1
30
31
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Q: What about the clocks?D
E
Q
D
E
Q
D
E
Q
.
.
.
0
RA1
RD1 = <RA1>
RA2
RD2 = <RA2>
0
WERF
WA
WD
0
1
30
31
0
1
30
31
0
1
30
31
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A: Connect them all together.D
E
Q
D
E
Q
D
E
Q
.
.
.
0
RA1
RD1 = <RA1>
RA2
RD2 = <RA2>
0
WERF
WA
WD
0
1
30
31
0
1
30
31
0
1
30
31
Clock
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Q: Is it practical to do the big Memory this way?
A: NO
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Minimize per-bit circuitry
.
.
.
. . .
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1 Bit Cell
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Minimizing per-bit circuitry
.
.
.
. . .
Sense Amplifiers
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How about ROMs?
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Q: What can we use for a switch?
A: The Field-Effect Transistor
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The N-Channel FET (NFET)
L
H
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The P-Channel FET (PFET)
L
H
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How do we implement multiple ports?
• 2 Read and 1 Write Ports– For now, LD and ST instructions are mutually
exclusive.• 1 RD + 1 RD/WR port needed
• LD and ST are don’t happen that often– Most of the time only 1RD port necessary
• Easy answer : Do them sequentially– Need a way to “stall” machine waiting for Mem
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Q: How do we stall this machine?
WD Memory
WDRegister File
RA2Memory
RD2
WA RC
WERF WEMEM
WA
WEWE
A B
A op B
Register FileRA1
RD1
RA2
RD2
RA RB RC
BSELASEL
ALUFN
WDSEL0
0 1
010 1 2
1
ALU
Register FileSEXT
C
4:0 9:5 20:5 25:2131:26
OPCODE
RA1Memory
RD1
PCQ
+1
DPC
Z
0 1
JMP(R31,XADDR,XP)
XADDR
0 1
2
ISEL
PCSEL
OPCODE
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A: Stalls are done by:
• Disabling WERF
• Disabling Memory Write
• Disabling PC write
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Another Approach - Increasing Memory Bandwidth
• Make memory twice as wide– 64 Bits Instead of 32
• Should work out in the long run, as 2 words are read per machine cycle, but– Words read are next to each other in address space
– Need a place to stash the extra word
– Sometimes, the stashed word isn’t used.
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Summary
• What Did we learn today?– How to Implement Registers + Big Memory– Multi-Port Big Memories aren’t easy
• Sequential Access (stalls + extra logic)
• Wide Access + Some sort of cache + extra logic
• Recitation– Review of today’s lecture