State-of-the-Art Pipeline A/D Converter Survey and

Analysis Tanvir Hussain

1, MD. Ghulam Zakir

2, Md. Rafiqul Islam Sheikh

3

1,2,3Dept. of Electrical and Electronic Engineering, Rajshahi University of Engineering & Technology (RUET)

Rajshahi 6204, Bangladesh 1bappi.ruet.eee@gmail.com, 2paban81@gmail.com, 3ris_ruet@yahoo.com

Abstract- This paper surveys and analyzes state-of-the-art

pipeline A/D Converter reported in IEEE from 1987 to June

2011, including performance comparison of these converters on

the ground of Resolution, Sampling Rate, Power, Spurious Free

Dynamic Range (SFDR), and Signal to Noise plus Distortion

Ratio (SNDR)/ Signal to Noise and Distortion Ratio (SINAD).

Technological and architectural progress brings low power, low

voltage high sampling rate pipeline A/D converter though the

resolution being constant over the period. We found that power

consumption of pipeline A/D converter decreased

1.62mW/month, sampling frequency increased 360

KHz/month, improvement of SFDR is approximately stagnant,

and SNDR decreased 0.127dB/month over the time.

Keywords- Analog to digital converter, resolution, SNDR, SINAD,

SFDR, Sampling rate.

I. INTRODUCTION

The analog world meets digital processing at the Analog

to Digital Converter (A/D Converter); where continuous time

and continuous amplitude analog signals are being converted

to discrete time (sampled) and discrete amplitude (quantized)

signal i.e. the ADC acts as a bridge between the analog and

the digital world. In today’s integrated mixed signal circuit

design, it is one of the most prominent and widely used mixed

signal circuits.

Since the commencement of digital circuit, various

methods for converting the analog signal to digital signal has

been devised, and still today those are the basic foundation for

A/D conversion technique. There are so many different types

of architecture for A/D conversion to mention but a few of

them has superseded all; namely Flash ADC (in early 1960s

time it was mostly known as parallel ADC), SAR ADC,

Folding ADC, Sigma Delta ADC, Pipeline ADC, and Sub-

ranging ADC.

The pipeline ADC has its own origin in the sub-ranging

architecture first used in the 1950s. All pipeline ADC can be

considered as sub-ranging ADC but the reverse is not true.

Pipeline ADC is one of the most popular architecture for A/D

converter finds its application in the medium resolution (10-14

bit) high speed (typically several hundred MS/s), medium

power application. Recently by using time-interleaved

Pipeline architecture 12-16 bit Several GS/s A/D converter

has been reported [1]-[3].

Though the pipelining can be used for various types of

A/D converter architectures, the term “pipeline A/D

converter” is hereafter defined to be an A/D converter

consisting of multiple identical stages operated in pipeline

fashion. There is no single criterion to compare between

different pipeline converters, though Figure of Merit (FOM)

takes into account of power, ENOB, and sampling frequency;

but SFDR, CMOS die area, INL, and DNL is left out of this

equation. In this paper state-of-the-art pipeline A/D converter

performance has been analyzed considering about 205 IEEE

paper on pipeline A/D converter reported in IEEE xplore

digital library from 1987 to June 2011.

II. A/D CONVERTER CHARACTERIZAION

For a long time the main performance analysis criterion

for Pipeline A/D converter is its Resolution, Sampling rate,

and FOM. The international Technology Roadmap for

Semiconductor (ITRS) published the following requirement

for A/D converter in 2011 [4] shown in Fig. 1.

Fig. 1 Recent ADC Performance Needs for Important Product Classes

IEEE/OSA/IAPR International Conference on Informatics, Electronics & Vision

978-1-4673-1154-0/12/$31.00 ©2012 IEEE ICIEV 2012

For a long time, pipeline A/D converter has been used for

mid resolution (8 – 16 bit) and high speed (10MHz –

400MHz) application. From Fig. 1 it can be seen that pipeline

A/D converter is the main candidate for video, cell phones,

mobile base station, wireless LAN, inter-connectivity, UWB

etc. IEEE standard 1241-2000 [5] tabulated some critical A/D

converter parameter. According to the need of pipeline A/D

converter application range, some parameter are reproduced

below in Table I.

TABLE I

CRITICAL A/D CONVERTER PARAMETER

Critical

Applications

Critical A/D

converter

Parameter

Performance Issues

Video DNL, SFDR,

SINAD, DG, DP

Differential gain and

phase errors,

Frequency response.

Telecommunication

personal

communications

SINAD, NPR,

SFDR, IMD

Bit error rate

Word error rate

Wide input bandwidth

channel bank. Inter-

channel crosstalk.

Compression. Power

consumption.

Wideband digital

receivers SIGINT,

ELINT, COMINT

SFDR, IMD

SINAD

Linear dynamic range

for detection of low-

level signals in a

strong interference

environment.

Sampling frequency.

A. Resolution and Sampling Frequency

Resolution and sampling frequency is the main

performance criterion for any A/D converter. Various

application requires specific resolution and sampling

frequency requirement to be fulfilled. Analog circuit designer

is developing newer and newer circuit design method to

increase its sampling frequency and resolution.

B. Effective Number of Bit (ENOB)

Aside from the Resolution of an A/D converter, ENOB is

also an important parameter for performance evaluation of the

converter which shows the effect of SNDR over resolution of

the A/D converter. ENOB is always being calculated using the

following formulae (1),

���� = ���� − 1.766.02 (1)

C. Spurious Free Dynamic Range (SFDR)

In all but especially in communication application SFDR

is the most significant specification for an A/D converter.

SFDR is used to show the A/D Converter usable dynamic

range beyond which special detection and threshold problems

occur during spectral analysis. IEEE standard 1241-2000 [5]

defines SFDR as (2),

������ = 20����� � |��� (!")|#$%!&' ∩ !)*+��� *!&',+ ∪ +��� *!&',+,.

(2)

Here, ��� (!") is the averaged magnitude spectral component

at discrete frequency !" after a DFT. In General SFDR is a

function of Amplitude of input signal ��� (!/), input signal

frequency !/, sampling frequency !&, and input noise.

D. Signal to Noise plus Distortion Ratio (SNDR)

The signal to noise plus distortion ratio (SNDR) (also

Signal to Noise and Distortion Ratio) is the ratio of the signal

to the total noise. All the paper we have analyzed use the term

SINAD or Signal to noise plus Distortion Ratio (SNDR)

interchangeably. This SNDR includes quantization error,

harmonic and inter-modulation distortion, spurious distortion,

thermal noise, random noise, aperture uncertainty and

comparator ambiguity. If 01 is the sample data set and 01′ is

the data set of the best-fit sine wave then noise for an given

A/D converter is defined by the following equation (3) [5],

�2� ��345 = 67 12 8(01 − 01′ )9:1;� < (3)

Then SNDR can be defined as (4),

���� = �2� �3�>$��2� ��345 (4)

It is always true that a lower SNDR value means worse

performance of the A/D converter.

E. Figure of Merit (FOM)

The International Technology Roadmap for

Semiconductor (ITRS) and IEEE uses completely reverse

notation for Figure of Merit retaining the individual term same

in calculating FOM. The analog Program committee of the

IEEE International Solid-State Circuit Conference suggested a

Figure of Merit for A/D converter [6] which is given by the

following equation (5),

��2@AAA = B2C × �& (5)

ITRS gives the definition of FOM by the following

mathematical expression (6),

��2@FGH = 2ACI� × #3>(J!&K, J2 × ���MK)B (6)

IEEE/OSA/IAPR International Conference on Informatics, Electronics & Vision

477 ICIEV 2012

Fig. 2 Comparison of speed trends: ADCs versus digital

Fig. 3 Comparison of energy efficiency trends: ADCs versus digital

In this work to calculate the FOM, IEEE mathematical

expression has been used (5).

III. PERFORMANCE ANALYSIS

Since the commencement of pipeline A/D converter,

various design for this converter has been proposed such as

full flash A/D converter, SAR assisted converter, the Time

Interleaved (TI) converter etc. Authors are proposing and

implementing newer and newer circuit design concept

methods in order to reduce power consumption,

sampling rate, to improve the dynamic and static performance

of this mixed signal component. Boser et al. in their book [

compared the advancements in digital circuits to the

improvement of ADCs performance shown in Fig.

Microprocessors benefited from the raw improvement

technology speed, aggressively increasing parallelism

device scaling keeping forward the moore’s law [

semiconductor technology improvement roadmap. The

resulting steep progress rate of performance doubling every

1.5 years has created a performance gap of 150x

digital computing power and A/D Converter speed. The

situation for energy efficiency is also similar [

Fig. 3. At the time of writing of this paper, we were unable to

Comparison of speed trends: ADCs versus digital

Comparison of energy efficiency trends: ADCs versus digital

Fig. 4 Pipeline A/D converter Resolution Distribution

5b

2%

6b

2%

11b

2%

12b

19%

13b

3%

14b

11%

15b

4%

16b

5%

Others

5%

he FOM, IEEE mathematical

NALYSIS

Since the commencement of pipeline A/D converter,

various design for this converter has been proposed such as,

full flash A/D converter, SAR assisted converter, the Time

nterleaved (TI) converter etc. Authors are proposing and

implementing newer and newer circuit design concept, newer

methods in order to reduce power consumption, to increase

rove the dynamic and static performance

of this mixed signal component. Boser et al. in their book [7]

compared the advancements in digital circuits to the

improvement of ADCs performance shown in Fig. 2.

from the raw improvement in

increasing parallelism, and

device scaling keeping forward the moore’s law [8] as the

semiconductor technology improvement roadmap. The

resulting steep progress rate of performance doubling every

rformance gap of 150x between

and A/D Converter speed. The

situation for energy efficiency is also similar [7] as shown in

At the time of writing of this paper, we were unable to

collect sufficient authorative data to extend

and Fig.3 upto year 2011. However, it is obvious from the

curve that at present the speed difference between

converter and digital circuit is far more greater than year 2003

which can be justified by moor's law [8

this paper’s analysis is based on has been tabulated in Table

II.

A. Resolution

The first factor comes forward in performance

comparison of any A/D converter is its Resolution. Analyzing

the data for pipeline A/D converter it has been seen that 33%

converter is 10bit, 19% is 12 bit converter, 11% is 14bit

converter, 11% is 8bit converter of the total Pipeline A/D

converter designed from 1987 to June,

chart Fig. 4.

In Fig. 5 Bit vs. Month of the pipeline converter has been

plotted. It is evident from the plot that over the last 23 years

the resolution improvement of the converter is quite stagnant

Fig. 5 Plot of Bit vs. Month from 1987 to June 2011

4 Pipeline A/D converter Resolution Distribution

6b

2%

8b

11% 9b

3%

10b

33%

nt authorative data to extend the curve of Fig.2

to year 2011. However, it is obvious from the

the speed difference between A/D

is far more greater than year 2003

8]. The data upon which

has been tabulated in Table

The first factor comes forward in performance

comparison of any A/D converter is its Resolution. Analyzing

the data for pipeline A/D converter it has been seen that 33%

converter is 10bit, 19% is 12 bit converter, 11% is 14bit

converter, 11% is 8bit converter of the total Pipeline A/D

converter designed from 1987 to June, 2011 as shown in pie

5 Bit vs. Month of the pipeline converter has been

plotted. It is evident from the plot that over the last 23 years

the resolution improvement of the converter is quite stagnant

Plot of Bit vs. Month from 1987 to June 2011

IEEE/OSA/IAPR International Conference on Informatics, Electronics & Vision

478 ICIEV 2012

Fig. 6 Plot of Power vs. Month from 1987 to June 2011

Fig. 7 Plot of SFDR vs. Month from 1987 to June 2011

20

40

60

80

100

120

SFDR

Analysis of fit "SFDR VS MONTH"

0 12 24 36 48 60 72 84 96 108 120 132 144 156 168 180 192 204 216-1

-0.5

0

0.5

1

1.5

1st deriv

which can be seen from the first derivate of the B

Curve. From Fig. 4 it can be deduced that pipeline converter is

best candidate for those application where 10 bit to 14bit

resolution is required.

B. Power

In Fig. 6 Power vs. Month for pipeline A/D converter

has been plotted. From the tangent of this decreasing trend

curve it has been found that the power of this converter

decreased 1.62mW/month.

C. Spurious Free Dynamic Range (SFDR)

In Fig. 7 SFDR vs. month for pipeline A/D converter has

been plotted. From the tangent of this curve it has been found

that the improvement of the SFDR over time is approximately

constant.

D. Signal to Noise plus Distortion Ratio (SNDR)

In Fig. 8 SNDR vs. month for pipeline A/D converter has

been plotted. From the tangent of this decreasing

it has been found that the SNDR decreased 0.127dB/month

Plot of Power vs. Month from 1987 to June 2011

Plot of SFDR vs. Month from 1987 to June 2011

SFDR VS MONTH

SFDR vs. Month

228 240 252 264 276 288 300

Fig. 8 Plot of SNDR vs. Month from 1987 to June 2011

Fig. 9 Plot of Sampling rate for 10 bit vs. Month from 1987 to June 2011

which can be seen from the first derivate of the Bit vs. Month

pipeline converter is

best candidate for those application where 10 bit to 14bit

6 Power vs. Month for pipeline A/D converter

has been plotted. From the tangent of this decreasing trend

curve it has been found that the power of this converter

SFDR vs. month for pipeline A/D converter has

been plotted. From the tangent of this curve it has been found

that the improvement of the SFDR over time is approximately

Distortion Ratio (SNDR)

SNDR vs. month for pipeline A/D converter has

decreasing trend curve

0.127dB/month.

E. Sampling Frequency

In Fig. 9 Sampling frequency for 10bit vs. Month of

pipeline A/D converter has been plotted. From the tangent of

this increasing trend curve it has been found that the sampling

frequency for 10 bit pipeline converter increase

KHz/month.

IV. CONCLUSION

Survey and Analysis of pipeline A/D converter has been

carried out on the basis of resolution, sampli

power, SFDR, SNDR. In last 23 years 33% pipeline converter

has been designed in 10 bit resolution, 19% in 12bit, 11% for

both in 8 bit and 14 bit resolution. It has been found that

power consumption of pipeline A/D converter decrease

1.62mW/month, and sampling frequency i

KHz/month. Improvement of SFDR is approximately stagnant

and SINAD decreased 0.127dB/month.

Plot of SNDR vs. Month from 1987 to June 2011

Sampling rate for 10 bit vs. Month from 1987 to June 2011

Sampling frequency for 10bit vs. Month of

pipeline A/D converter has been plotted. From the tangent of

this increasing trend curve it has been found that the sampling

pipeline converter increased 360

ONCLUSION

Survey and Analysis of pipeline A/D converter has been

carried out on the basis of resolution, sampling frequency,

. In last 23 years 33% pipeline converter

has been designed in 10 bit resolution, 19% in 12bit, 11% for

8 bit and 14 bit resolution. It has been found that

power consumption of pipeline A/D converter decreased

quency increased 360

mprovement of SFDR is approximately stagnant

0.127dB/month. This point is also to be

IEEE/OSA/IAPR International Conference on Informatics, Electronics & Vision

479 ICIEV 2012

noted that, we found considering more than 200 papers and

books written on Pipeline A/D converter by approximately

580 authors that, among all these authers there is only one

Female author named Susanne A. Paul [9].

REFERENCES

[1] Payne, R.; Sestok, C.; Bright, W.; El-Chammas, M.; Corsi, M.; Smith,

D.; Tal, N.; , "A 12b 1GS/s SiGe BiCMOS two-way time-interleaved

pipeline ADC," Solid-State Circuits Conference Digest of Technical

Papers (ISSCC), 2011 IEEE International , vol., no., pp.182-184, 20-24

Feb. 2011

[2] Mulder, J.; van der Goes, F.M.L.; Vecchi, D.; Westra, J.R.; Ayranci, E.;

Ward, C.M.; Jiansong Wan; Bult, K.; , "An 800MS/s dual-residue

pipeline ADC in 40nm CMOS," Solid-State Circuits Conference Digest

of Technical Papers (ISSCC), 2011 IEEE International , vol., no.,

pp.184-186, 20-24 Feb. 2011

[3] Sundstrom, T.; Svensson, C.; Alvandpour, A.; , "A 2.4 GS/s, Single-

Channel, 31.3 dB SNDR at Nyquist, Pipeline ADC in 65 nm CMOS,"

TABLE II

DATA of PIPELINE A/D CONVERTER Here, data of papers published from 2007 to 2011 are included only due to

page constraint. Data was collected from IEEE xplore digital Library* 2007

Date R SF P SFDR SNDR Ref/DOI

7 400 108 40 [17]

6-9 Feb 10 50 18 82 56.9 10.1109/ISSCC.2006.1696119

20 Feb 10 100 30 70 54 [18]

20 Feb 8 100 30 52.6 45 [19]

20 Feb 12 75 273 65.6 [20]

Mar. 13 40 268 80 10.84 [33]

Apr. 10 100 33 71.5 55 [34]

27-30 May 10 30 36.8 66.1 58.5 [35]

May 11 0.1 0.385 [36]

27-30 May 8 300 40 58 45.5 10.1109/ISCAS.2007.378583

27-30 May 8 150 20 59 47 10.1109/ISCAS.2007.378361

14-16 June 8 22 2.5 80 49 10.1109/VLSIC.2007.4342711

14-16 June 14 30 102 82.8 70.7 10.1109/VLSIC.2007.4342712

5-8 Aug. 14 50 10.1109/MWSCAS.2007.4488556

16 Sep. 10 100 19.2 69 56 10.1109/CICC.2007.4405709

26 Oct. – 3

Nov.

12 25 35 10.1109/NSSMIC.2007.443666

0

30 Oct. – 2

Nov.

5 1000 63 31 10.1109/TENCON.2007.44288

97

Dec. 10 205 40 55 10.1109/JSSC.2007.908760

Dec. 8 200 8.5 10.1109/JSSC.2007.908770

2008

10 210 52 74 55 10.1109/SOCC.2007.4545415

3-7 Feb. 10 100 4.5 59 10.1109/ISSCC.2008.4523151

Feb. 10 30 22 65 57 10.1109/JSSC.2007.914253

Feb. 15 20 285 98 73 10.1109/JSSC.2007.914260

Apr. 8 10 2.4 57.2 48.1 10.1109/JSSC.2008.917470

Apr. 240 89 10.1109/JSSC.2011.2143811

18-21 May 6 1000 20 47 34 10.1109/ISCAS.2008.4541903

22-24 May 8 12.8 10.1109/ISMVL.2008.25

18-20 June 14 100 250 91 73 10.1109/VLSIC.2008.4585957

18-20 June 13 250 140 65.9 10.1109/VLSIC.2008.4586015

July 10 50 27 60.5 52.2 10.1109/JSSC.2008.923727

11-13 Sep. 11 45 81 70 48.9 10.1109/ESSCIRC.2007.4430267

21-24 Sep. 11 16 50 66 56 10.1109/CICC.2009.5280858

21-24 Sep. 15 30 123 86.5 75 10.1109/CICC.2008.4672034

2009

23-Jan. 8 250 108 57.5

4

[21]

8-12 Feb. 16 125 385 96 78.6 [22]

Mar 10 50 12 72.8 56.2

Apr. 9.4 50 1.44 100 49.2 [23]

Date R

SF

P

SFDR SNDR Ref/DOI

24-27 May 10 140 65 55

24-27 May 10 50 23 70.8 38.3

16-18 June 10 80 11.2 70 53.8 [24]

2-5 Aug. 12 0.05 0.06 [25]

Sep. 11 80 36 10.1109/JSSC.2009.2025408

13-16 Sep. 80 10 10.1109/4.62176

Oct. 12 20 231 80.3 70.2 10.1109/JSSC.2009.2028756

Oct. 8 22 2.5 36 10.1109/JSSC.2009.2028052

Nov. 6 1000 49 40.7 33.7 10.1109/JSSC.2009.2032258

16-18 Nov. 10 100 6 75 58 10.1109/JSSC.2010.2063590

Dec. 12 50 4.5 73 66 10.1109/JSSC.2009.2032639

Dec. 100 130 88 69 10.1109/JSSC.2009.2032637

13-16 Dec. 16 0.00

1

0.15 87 10.1109/ICECS.2009.5410796

14-16 Dec. 9 50 12 58 53 INSPEC Accession No.: 11105405

2010

Feb. 10 40 1.21 71.5 55.1 [26]

Feb. 10 42 11.1 67.5 55.6 [27]

13-14 Mar. 12 50 55 75.3 69.3 [28]

Apr. 80 94 75.4 [39]

May 10 50 9.9 66 58.2 [30]

May 30 - Jun

2

10 300 77 65.7 55.1 [31]

May 30 – Jun

2

10 1600 430 57.67 54.3 [32]

16-18 June 12 50 3.5 78 66 10.1109/VLSIC.2010.5560243

5-7 July 8 50 22 40 10.1109/ISVLSI.2010.27

Aug. 9 90 13.5 63.4 51.8 10.1109/TCSII.2010.2050937

24-26 Aug. 10 50 36 54 10.1109/CMCE.2010.5609932

19-22 Sep. 10 204 9.15 63 55 10.1109/CICC.2010.5617457

22-24 Sep. 12 40 65 56 10.1109/PRIMEASIA.2010.5604945

Oct. 6 2200 2.6 31.6 10.1109/JSSC.2010.2061611

1-4 Nov. 12 5 30.4 53 10.1109/ICSICT.2010.5667703

1-4 Nov. 3 4000 44.7 27.74 10.1109/ICSICT.2010.5667682

12-15 Dec. 9 1 .012

6

53 10.1109/ICECS.2010.5724652

Dec. 18 12.5 105 104

Dec. 16 160 1600 90 10.1109/JSSC.2010.2074650

Dec. 16 250 850 100 76.5 10.1109/JSSC.2010.2073194

2011

20-24 Feb. 12 1000 575 76 62 [10]

20-24 Feb. 16 80 100 81 69 [11]

20-24 Feb. 12 800 105 59 [12]

Apr. 12 50 3.5 78 66 [13]

June 10 40 1.21 71.5 55.1 [14]

June 10 100 4.5 62.3 55 [15]

July 2400 218 50.5 30.1 [16]

*R – Resolution(bit), SF – Sampling Frequency (MS/s), P – Power

(mW), Ref – Reference, SFDR – Spurious Free Dynamic Range,

SNDR – Signal to Noise plus Distortion Ratio. DOI – Digital

Object Identifier.

IEEE/OSA/IAPR International Conference on Informatics, Electronics & Vision

480 ICIEV 2012

Solid-State Circuits, IEEE Journal of , vol.46, no.7, pp.1575-1584, July

2011

[4] (2011) The international Technology Roadmap for Semiconductors

website, [Available Online], website: http://www.itrs.net/

[5] "IEEE Standard for Terminology and Test Methods for Analog-to-

Digital Converters," IEEE Std 1241-2010 (Revision of IEEE Std 1241-

2000) ,pp.1-139, Jan. 14 2011

[6] Frank Goodenough, “Analog Technology of All Varieties Dominate

ISSCC”, Electronic Design, 44(4): 96-111, February 19, 1996.

[7] Boris Murmann, Bernhard E. Boser; “Digitally Pipeline ADCs, theory

design and implementation”, Kluwer Academic Publications; NY, USA;

2004

[8] Intel, (2011) "Moore's Law," [Online]. Available:

http://www.intel.com/technology/mooreslaw/

[9] Paul, S.A.; Lee, H.-S.; Goodrich, J.; Alailima, T.F.; Santiago, D.D.; , "A

Nyquist-rate pipelined oversampling A/D converter," Solid-State

Circuits, IEEE Journal of , vol.34, no.12, pp.1777-1787, Dec 1999

[10] Payne, R.; Sestok, C.; Bright, W.; El-Chammas, M.; Corsi, M.; Smith, D.;

Tal, N.; , "A 12b 1GS/s SiGe BiCMOS two-way time-interleaved pipeline

ADC," Solid-State Circuits Conference Digest of Technical Papers (ISSCC),

2011 IEEE International , vol., no., pp.182-184, 20-24 Feb. 2011

[11] Brunsilius, J.; Siragusa, E.; Kosic, S.; Murden, F.; Yetis, E.; Luu, B.; Bray,

J.; Brown, P.; Barlow, A.; , "A 16b 80MS/s 100mW 77.6dB SNR CMOS

pipeline ADC," Solid-State Circuits Conference Digest of Technical

Papers (ISSCC), 2011 IEEE International , vol., no., pp.186-188, 20-24

Feb. 2011

[12] Mulder, J.; van der Goes, F.M.L.; Vecchi, D.; Westra, J.R.; Ayranci, E.;

Ward, C.M.; Jiansong Wan; Bult, K.; , "An 800MS/s dual-residue

pipeline ADC in 40nm CMOS," Solid-State Circuits Conference Digest of

Technical Papers (ISSCC), 2011 IEEE International , vol., no., pp.184-186,

20-24 Feb. 2011

[13] Lee, C.C.; Flynn, M.P.; , "A SAR-Assisted Two-Stage Pipeline ADC," Solid-

State Circuits, IEEE Journal of , vol.46, no.4, pp.859-869, April 2011

[14] Razavi, B.; Wooley, B.A.; , "A 12-b 5-Msample/s two-step CMOS A/D

converter," Solid-State Circuits, IEEE Journal of , vol.27, no.12, pp.1667-

1678, Dec 1992

[15] Yen-Chuan Huang; Tai-Cheng Lee; , "A 10-bit 100-MS/s 4.5-mW

Pipelined ADC With a Time-Sharing Technique," Circuits and Systems I:

Regular Papers, IEEE Transactions on , vol.58, no.6, pp.1157-1166, June

2011

[16] Sundstrom, T.; Svensson, C.; Alvandpour, A.; , "A 2.4 GS/s, Single-

Channel, 31.3 dB SNDR at Nyquist, Pipeline ADC in 65 nm CMOS," Solid-

State Circuits, IEEE Journal of , vol.46, no.7, pp.1575-1584, July 2011

[17] Hwei-Yu Lee,; I-Hsin Wang,; Shen-Iuan Liu,; , "A 7-BIT 400MS/s sub-

ranging flash ADC in 0.18um CMOS," SOC Conference, 2007 IEEE

International , vol., no., pp.11-14, 26-29 Sept. 2007

[18] Honda, K.; Masanori, F.; Kawahito, S.; , "A 1V 30mW 10b

100MSample/s Pipeline A/D Converter Using Capacitance Coupling

Techniques," VLSI Circuits, 2006. Digest of Technical Papers. 2006

Symposium on , vol., no., pp.224-225, 20 February 2007

[19] Ying Wu; Cheung, V.S.L.; Luong, H.; , "A 1-V 100MS/s 8-bit CMOS

Switched-Opamp Pipelined ADC Using Loading-Free Architecture," VLSI

Circuits, 2006. Digest of Technical Papers. 2006 Symposium on , vol.,

no., pp.136-137, 20 February 2007

[20] Iroaga, E.; Murmann, B.; , "A 12b, 75MS/s Pipelined ADC Using

Incomplete Settling," VLSI Circuits, 2006. Digest of Technical Papers.

2006 Symposium on , vol., no., pp.222-223, 20 February 2007

[21] Roy, S.; Dey, S.K.; Banerjee, S.; , "A parallel pipeline ADC with a Sub-

ADC employing an improvized dynamic comparator," TENCON 2009 -

2009 IEEE Region 10 Conference , vol., no., pp.1-6, 23-26 Jan. 2009

[22] Devarajan, S.; Singer, L.; Kelly, D.; Decker, S.; Kamath, A.; Wilkins, P.; ,

"A 16b 125MS/s 385mW 78.7dB SNR CMOS pipeline ADC," Solid-State

Circuits Conference - Digest of Technical Papers, 2009. ISSCC 2009. IEEE

International , vol., no., pp.86-87,87a, 8-12 Feb. 2009

[23] Hu, J.; Dolev, N.; Murmann, B.; , "A 9.4-bit, 50-MS/s, 1.44-mW

Pipelined ADC Using Dynamic Source Follower Residue Amplification,"

Solid-State Circuits, IEEE Journal of , vol.44, no.4, pp.1057-1066, April

2009

[24] Yu, Xinyu; Lin, Fang; Li, Kevin; Ranganathan, Sumant; Kwan, Tom; , "A

dual-channel 10b 80MS/s pipeline ADC with 0.16mm2 area in 65nm

CMOS," VLSI Circuits, 2009 Symposium on , vol., no., pp.272-273, 16-18

June 2009

[25] Xiang Fang; Srinivasan, V.; Wills, J.; Granacki, J.; LaCoss, J.; Choma, J.; ,

"CMOS 12 bits 50kS/s micropower SAR and dual-slope hybrid ADC,"

Circuits and Systems, 2009. MWSCAS '09. 52nd IEEE International

Midwest Symposium on , vol., no., pp.180-183, 2-5 Aug. 2009

[26] Furuta, M.; Nozawa, M.; Itakura, T.; , "A 0.06mm2 8.9b ENOB 40MS/s

pipelined SAR ADC in 65nm CMOS," Solid-State Circuits Conference

Digest of Technical Papers (ISSCC), 2010 IEEE International , vol., no.,

pp.382-383, 7-11 Feb. 2010

[27] Peach, C.T.; Un-Ku Moon; Allstot, D.J.; , "An 11.1 mW 42 MS/s 10 b ADC

With Two-Step Settling in 0.18 $mu$m CMOS," Solid-State Circuits, IEEE

Journal of , vol.45, no.2, pp.391-400, Feb. 2010

[28] Heijim Wu; Zhengping Li; Huabin Zhang; Yongping Wang; , "A 12-bit

50MS/s Low-Power Pipeline ADC for WiMAX," Measuring Technology

and Mechatronics Automation (ICMTMA), 2010 International

Conference on , vol.1, no., pp.11-13, 13-14 March 2010

[29] Rajaee, O.; Musah, T.; Maghari, N.; Takeuchi, S.; Aniya, M.; Hamashita,

K.; Moon, U.-K.; , "Design of a 79 dB 80 MHz 8X-OSR Hybrid Delta-

Sigma/Pipelined ADC," Solid-State Circuits, IEEE Journal of , vol.45, no.4,

pp.719-730, April 2010

[30] Ahmed, I.; Mulder, J.; Johns, D.A.; , "A Low-Power Capacitive Charge

Pump Based Pipelined ADC," Solid-State Circuits, IEEE Journal of ,

vol.45, no.5, pp.1016-1027, May 2010

[31] Young-Hwa Kim; Jaewon Lee; SeongHwan Cho; , "A 10-bit

300MSample/s pipelined ADC using time-interleaved SAR ADC for

front-end stages," Circuits and Systems (ISCAS), Proceedings of 2010

IEEE International Symposium on , vol., no., pp.4041-4044, May 30

2010-June 2 2010

[32] Picolli, L.; Crespi, L.; Chaahoub, F.; Malcovati, P.; Baschirotto, A.; , "A

1.6-GHz, 54-dB signal-to-noise and distortion ratio pipeline A/D

converter," Circuits and Systems (ISCAS), Proceedings of 2010 IEEE

International Symposium on , vol., no., pp.1735-1738, May 30 2010-

June 2 2010

[33] Sourja Ray; Bang-Sup Song; , "A 13-b Linear, 40-MS/s Pipelined ADC

With Self-Configured Capacitor Matching," Solid-State Circuits, IEEE

Journal of , vol.42, no.3, pp.463-474, March 2007

[34] Honda, K.; Furuta, M.; Kawahito, S.; , "A Low-Power Low-Voltage 10-bit

100-MSample/s Pipeline A/D Converter Using Capacitance Coupling

Techniques," Solid-State Circuits, IEEE Journal of , vol.42, no.4, pp.757-

765, April 2007

[35] Chi-Chang Lu; Jyun-Yi Wu; Tsung-Sum Lee; , "A 1.5V 10-b 30-MS/s

CMOS Pipelined Analog-to-Digital Converter," Circuits and Systems,

2007. ISCAS 2007. IEEE International Symposium on , vol., no., pp.1955-

1958, 27-30 May 2007

[36] Aksin, D.; Al-Shyoukh, M.A.; Maloberti, F.; , "An 11 Bit Sub-Ranging SAR

ADC with Input Signal Range of Twice Supply Voltage," Circuits and

Systems, 2007. ISCAS 2007. IEEE International Symposium on , vol.,

no., pp.1717-1720, 27-30 May 2007

IEEE/OSA/IAPR International Conference on Informatics, Electronics & Vision

481 ICIEV 2012