International Journal of Trend in Research and Development, Volume 3(6), ISSN: 2394-9333
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IJTRD | Nov-Dec 2016 Available [email protected] 56
Improvement of Power Quality in Three-Phase Four-
Wire Distribution System by IUPQC Using Dual
Control Strategy 1V.Chitra and
2S.Rajan Babu,
1PG Scholar,
2Assistant Professor,
1,2Department of Electrical and Electronics Engineering, Valliammai Engineering College, Chennai, Tamilnadu, India
Abstract—This paper presents the study and analysis of
Interline unified power quality conditioner (IUPQC)which can
be connected in both three-phase three-wire or three-phase
four-wire distribution system. Interline UPQC is one of the
custom power device to compensate supply voltage power
quality problems such as sags, swells, unbalance, flicker, and
harmonics and for load current power quality problems such as
harmonics, unbalance, reactive current etc. Different from the
control strategies used in IUPQC applications, in which the
controlled quantities are non sinusoidal, this paper employs
dual control strategy in which the controlled quantities are
always sinusoidal. Therefore it is possible to reduce the
complexity of algorithms which is used to calculate
compensation references. By using PI controllers, the steady
state errors are reduced. Thereby, series Active Power Filter
acts as sinusoidal voltage source whereas the shunt Active
Power Filter acts as sinusoidal current source. The results are
analyzed and presented using MATLAB software.
Keywords-- Dual control strategy, Interline Unified Power
Quality Conditioner (IUPQC), Active power filter (APF),
Phase Locked Loop (PLL), Power Quality (PQ), Synchronous
Reference Frame (SRF),Proportional and Integral
controller(PI).
I. INTRODUCTION
The term “power quality” (PQ) has gained significant attention
in the past few years. The advancement in the semiconductor device technology has made it possible to realize most of the power electronics based devices at commercial platform. The usage of power quality
conditioners in the distribution system network has increased
during the few years due to the steady increase of nonlinear
loads. The current drawn by nonlinear loads has a high harmonic content, distorting the voltage at the utility grid and therefore affecting the operation of critical loads. Furthermore, additional procedures should be taken into account in order to overcome PQ problems associated with harmonic currents generated by nonlinear loads, load unbalances, and reactive power demanded by the load. To
improve the quality of power for non-linear and voltage
sensitive load, UPQC is one of the best solutions. The
following power quality improvements are obtained:
(i)suppression of load harmonic currents; (ii) compensation of
load reactive power;(iii) Compensation of voltage sag. The
scheme of the IUPQC is very similar to the conventional
UPQC, using an association of the SAF and PAF, deviate only
from the way the series and shunt filters are controlled. Thus,
different from the conventional conditioning strategy, which
uses non sinusoidal control references, the dual compensating
strategy uses only sinusoidal references to control the PWM
converters. As a result, the generation of the control references
is easier to obtain, allowing the use of simpler algorithms to
accomplish this aim.
II. DUAL CONTROL STRATEGY
In order to make the input currents sinusoidal, balanced and in
phase with the utility voltages, in the dual control strategy, the
series PWM converter is controlled to operate as a sinusoidal
current source. In this case, its impedance must be high enough
to isolate the harmonic currents generated by the nonlinear
loads. On the other hand, the shunt PWM converter also makes
the output voltages sinusoidal, balanced, regulated and in
phase with the utility voltages. In other words, it is controlled
to operate as a sinusoidal voltage source, such that its
impedance must be sufficiently low to absorb the load
harmonic currents.
III. CONTROL METHODS
Synchronous Reference Frame(SRF) based controller(dqo
axes) is used to control the input currents and output voltages
of the UPQC for speed control and vary the system operation
using PI controller. The PI controller leads to reduction in the
steady state errors when continuous control references(V and
I) into the SRF based controller is allowed[1]. Here, abc to dq
transformation is called as Park’s transformation. 3phase PLL
suffers with utility voltage disturbances such as harmonics or
unbalances, STF is used in conjunction with the 3phase PLL
scheme. The system is very stable since the controller deals
mainly with the d-q quantities. The computation is
instantaneous but incurs time delays in filtering the d-q
quantities. STF is located in between the utility voltages and
3phase PLL. Where, ω is the angular frequency of 3phase PLL
is used to adjust STF cut-off frequency. With proper delay, the
unit vector templates are generated.
Ua=sinωt
Ub=sin(ωt-1200)
Uc=sin(ωt+1200)
Multiplying the peak amplitude of fundamental input voltage
with unit vector templates gives the reference load voltage
signals.
V∗=Vm∙Uabc
The shunt APF is used to compensate for current harmonics as
well as to maintain the dc link voltage at constant level[2]. To
achieve this, dc link voltage is sensed and compared with
reference dc link voltage. The error is then processed by PI
controller.
IV.UPQC DESCRIPTION
The UPQC consists of two voltage source inverters connected
back to back with each other sharing a common dc link. One
inverter is controlled as a variable voltage source in the series
APF, and the other as a variable current source in the shunt
APF.
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Figure 1: Block Diagram Of Upqc
The shunt active filter of the UPQC can compensate all
undesirable current components, including harmonics,
imbalances due to negative- and zero sequence components at
fundamental frequency, and the load reactive power as well.
The same kind of compensation can be performed by the series
active filter for the supply voltage, hence, the simultaneous
compensation performed by the UPQC guarantees that both
the compensated voltage VL at load terminal and compensated
current is that is drawn from the power system become
balanced. However, the UPQC has some disadvantages.
V. IUPQC DESCRIPTION
The scheme of the IUPQC is very similar to the conventional
UPQC, using an association of the SAF and PAF,
diverging only from the way the shunt and series filters
are controlled.
Fig 2(a): Complete structure of an IUPQC
The VSC-1 is connected in shunt to feeder-1 while the VSC-2
is connected in series with feeder-2. Each of the two VSCs is
realized by three H-bridge inverters. In its structure, each
switch represents a power semiconductor device (IGBT-
Insulated Gate Bipolar Transistor) and an anti-parallel diode.
All the inverters are supplied from a common single dc
capacitor Cdc and each inverter has a transformer connected at
its output[3]. The six inverters of the IUPQC are controlled
individually.
Fig 2(B): Block Diagram Of Iupqc
The purpose of the IUPQC is to hold the voltages constant
against voltage sag/swell, temporary interruption and
momentary interruption etc. in either of the two feeders. Series
inverter controls the Sag/ swell detection, voltage reference
generation, voltage injection strategies and methods for
generating of gating signals. Whereas the Shunt inverter
controls the Current reference generation, methods for
generating of gating signals and capacitor voltage control.
Table 1: Design Specifications of The Iupqc
Input line-to-line RMS
voltage
Vin=220V
Output nominal power Po=2500VA
DC link voltage Vb=400V
Utility grid frequency fgrid=60Hz
Switching frequency of
series and parallel active
filters
fs=20kHz
Transformer ratio n=1
VI. SERIES AND PARALLEL CONVERTER
MODELING
A. Series Converter Modeling
The modeling is accomplished considering that all involved
inductances and resistances are identical. By means of Fig 2,
the equations that represent the system are given by (1) and (2)
usab_PWM=vLfsa+vRfsa+vCab-vRfsb-vLfsb (1)
usbc_PWM=vLfsb+vRfsb+vCbc-vRfsc-vLfsc (2)
Where usab_PWM and usbc_PWM are the respective PWM
voltages at the 3-Leg series converter terminals. Considering
the voltages of the PWM series converter in the dq axes, the
state-space equation is given by
•x sdq(t)=Asdqxsdq(t)+Bsdqusdq(t)+Fsdqwsdq(t) (3)
disddt
x sdq tdisqdt
,
isdxsdq t
isq
, _
_
usd PWMusdq
usq PWM
,
(t)vcd
wsdqvcq
,
RfsLfs
AsdqRfs
Lfs
,
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1 013 0 1
BsdqLfs
,1 01
3 0 1Fsdq
Lfs
Thereby, based on (3), the series converter average model
represented as a signal flow graph is shown in the dotted area
of Fig. 2.
( , )( ) 1( ( , ) ( , ))2is*(d,q)(s) ( 1 ( , )) 1 ( , )
is d q s X Kps d q s Kis d q
Lfss Rfs X Kps d q s X Kis d q
(4)
B. Parallel Converter Modeling
The modeling is accomplished considering that all involved
inductances, resistances and capacitances are identical. The
equations that represent the system are given by (5), (6), and
(7) as follows:
dia dicnupan_PWM = Rfpa.iia + Lfpa + vLa + Lfpn + Rfpn.icn
dt dt
dib dicnupbn_PWM=Rfpb.iib+Lfpb +vLb+Lfpn +Rfpn.icndt dt
dic dicnupcn_PWM = Rfpc.iic + Lfpc + vLc + Lfpn + Rfpn.icn
dt dt
Where upan_PWM , upbn_PWM and upcn_PWM are the
respective PWM voltages at the terminals a, b, and c of the 4-
Leg parallel converter. The capacitor currents of the output
filters (iCfpa ,iCfpb and iCfpc ) are given by
dvLaicfpa = cfpa = iia - ica (5)
dt
dvLbicfpb = cfpb = iib - icb (6)
dt
dvLcicfpc = cfpc = iic - icc (7)
dt
Where iia, iib and iic are the currents of the inductors, and ica, icb
and icc are the output currents of the parallel converter.
VII. STABILITY ANALYSIS OF SYSTEM
The aim of this was to verify the ability of the system to
remain stable even under load disturbances.
A. Series APF
The closed-loop transfer function in the dq coordinates can be
represented by (4). Thereby, the stability analysis of the series
converter involves only the second-order denominator (λi) of
(4). By applying the Routh–Hurwitz stability criterion, the
necessary and sufficient condition for ensuring the series
converter stability is that all the coefficients of λi must have
the same sign[5]. Since the reference currents are always
sinusoidal, it is possible to assume that the series converter
remains acting as a sinusoidal current source even when load
transients occur.
B. Parallel APF
Considering that the PI controller gains KpPI = KpPI(d,q ) =
KpPI(0)/4, Kpp = Kpp(d,q ) = Kpp(0), and Kip = Kip(d,q ) =
Kip(0), the same transfer function is obtained for each control
loop implemented in the d, q, and 0 coordinates as given by
(8), allowing the study of the voltage control loops by means
of a unique transfer function Gv(s).
( , , )( )( )
*(d,q,o)(s)vL d q o s
Gv svL
(8)
However, it is not possible to analyze how the load current
transients will interfere in the controls of the UPQC output
voltages only by using the transfer function Gv(s). Thus, the
load current (iL ) is considered as an input of the system,
whereas the voltage (vL ) is the output. By applying the
Routh–Hurwitz stability criterion, two conditions must be met:
1) all the polynomial coefficients of the denominator must
have the same sign and 2) the inequality Y2Y3 > Y1Y4 must
be respected[6]. Thus, taking into account the aforementioned
conditions, the system will always be stable, even when load
transients occur.
Fig 3: Signal flow graphs of the reference current generation
and control scheme of both series and parallel PWM
converters: (a) reference current generation and the input
current controllers; (b) output voltage controllers.
2( , , )( ) 1 2 3
( )3 2iL(d,q,o)(s) 1 2 3 4
vL d q o s X S X S XGvi s
Y S Y S Y S Y
(9)
VIII. SIMULATION RESULTS AND DISCUSSION
The simulation results are presented to show the performance
of UPQC for harmonic elimination and sag mitigation.
Fig 4: Simulation model of UPQC
Fig 4(a): Compensation of voltage sag VLabc
International Journal of Trend in Research and Development, Volume 3(6), ISSN: 2394-9333
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Fig 4(b): Suppression of load harmonic current ILabc
Fig 4(c): Real and Reactive power waveform
The simulation results are presented to show the performance
of IUPQC for harmonic elimination and sag mitigation.
Fig 5: Simulation model of IUPQC with distortions in feeder1
A. Compensation of Voltage Sag and Harmonic Currents in
Feeder 1
In the figures below, fig 5(a) denotes the supply voltage
voltage(Vsa,b,c) waveform of effective nominal voltage of
utility(line to neutral) which is of 127V ie.,
127*1.732=219.968V, where as fig(b) shows the waveform of
compensation of source current harmonics(Isa,b,c). Sag is the
decrease in rms voltage waveform for the duration of about
0.15 to 0.2p.u. The current drawn by the load is 25A. There
occurs a suppression of current for about 15A. With the help of
IUPQC the compensation of harmonic current is done by
injecting the required harmonic current to the load. Figures
(a),(b),(c),(d) and (e) shows the distortions that occurred in
feeder 1.
Fig 5(a) Voltage source for feeder 1:Vsabc
Fig 5(b) Suppression of source current:Isabc
Figures(c) and (d) shows the waveform of load side
compensation of voltage sag(Vla,b,c) and harmonics current
suppression(Ila,b,c).
Fig 5(c) Compensation of voltage sag:VLabc
The input supply voltage and current values of 219.968V and
25A is obtained at the output with no distortions since there
occurs a fault at feeder 1.
Fig 5(d) Suppression of load harmonic currents:ILabc
Fig 5(e) Output voltage for feeder 2:VLabc
Fig 5(f) Output current for feeder 2: ILabc
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Fig 5(g) Real and Reactive power for feeder 1
Figure (g) denotes the waveform representing the real and
reactive power. The real and reactive power is compensated by
IUPQC. The required reactive power is injected through shunt
active power filter (at fundamental frequency) to control the
power factor.
B. Compensation of Voltage Sag and Harmonic Currents In
Feeder 2
In this section, fault occurred in feeder 2 instead of feeder 1.
Figures (h) and (i) shows the utility side voltage and current
waveforms Vsa,b,c and Isa,b,c after compensation for feeder 2.
Fig 6: Simulation model of IUPQC with distortions in feeder2
Fig 6(a) Source voltage for feeder 2: Vsabc
Fig 6(b) Suppression of source current :Isabc
Fig 6(c) Compensation of load voltage sag for feeder 2:VLabc
Figure 6(c) denotes the waveforms for voltage sag that occurs
at feeder 2 in the load side ie.,VLa,b,c and compensation of
harmonic currents with the use of shunt active filter using
IUPQC.
Fig 6(d) Suppression of load harmonic currents for feeder
2:ILabc
Fig 6(e) Real and Reactive power for feeder 2
Figure 6(e) shows the waveform for real and reactive power
compensation of feeder 2. The reactive power is injected into
the load by using the compensator of shunt APF.
A 3-phase supply voltage (219.168 V, 50Hz) with momentary
sag of 0.07 pu to 0.1 pu magnitude with the duration about 20
to 30 cycles is taken. With the system operating in the steady
state, a 20-30 cycle momentary sag of 0.1 pu magnitude for
which the peak of the supply reduces from its nominal value of
219.168V to 170V. The Total Harmonic Distortion (THD) of
UPQC is 4.73%.
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Fig 7(a) : THD waveform using UPQC.
With the momentary sag of 0.15 pu to 0.2 pu magnitude with
the duration about 20 to 30 cycles is taken. A momentary sag
of 0.185 pu for which the peak of the supply voltage reduces
from its nominal value of 219.168V to 170V. The Total
Harmonic Distortion by using IUPQC is 3.95%.
Fig 7(b): THD waveform using IUPQC
CONCLUSION
An IUPQC is able to protect the distribution system from
various disturbances occurring either in Feeder-1 or in Feeder-
2. Even for a voltage sag or a fault in Feeder-2, VSC-1 passes
real power through the dc capacitor onto VSC-2 to regulate the
voltage. Finally when a fault occurs in Feeder-2 or Feeder-2 is
lost, the power required by the Load L-2 is supplied through
both the VSCs. This implies that the power semiconductor
switches of the VSCs must be rated such that the total power
transfer through them must be possible. By using a dual
control compensating strategy, the controlled voltage and
current quantities are always sinusoidal. Since voltage and
current SRF based controllers are employed, the control
references becomes continuous, reducing the steady-state
errors when PI controllers are used.
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