![Page 1: Interrupts)and)System)Calls)porter/courses/cse506/f14/... · CSE506:OperangSystems Logical)Diagram) Memory)) Management CPU) Scheduler) User Kernel) Hardware) Binary) Formats) Consistency)](https://reader033.vdocument.in/reader033/viewer/2022042310/5ed83acd0fa3e705ec0e1437/html5/thumbnails/1.jpg)
CSE 506: Opera.ng Systems
Interrupts and System Calls
Don Porter CSE 506
![Page 2: Interrupts)and)System)Calls)porter/courses/cse506/f14/... · CSE506:OperangSystems Logical)Diagram) Memory)) Management CPU) Scheduler) User Kernel) Hardware) Binary) Formats) Consistency)](https://reader033.vdocument.in/reader033/viewer/2022042310/5ed83acd0fa3e705ec0e1437/html5/thumbnails/2.jpg)
CSE 506: Opera.ng Systems
Housekeeping • Welcome Tas Amogh Akshintala and Yizheng Jiao (1/2 Hme) – Office Hours posted
• Next Thursday’s class has a reading assignment • Lab 1 due Monday 9/8 • All students should have VMs and private repos soon – Email Don if you don’t have one by tonight – Unless you just got in the class since Wed night (sigh)
![Page 3: Interrupts)and)System)Calls)porter/courses/cse506/f14/... · CSE506:OperangSystems Logical)Diagram) Memory)) Management CPU) Scheduler) User Kernel) Hardware) Binary) Formats) Consistency)](https://reader033.vdocument.in/reader033/viewer/2022042310/5ed83acd0fa3e705ec0e1437/html5/thumbnails/3.jpg)
CSE 506: Opera.ng Systems
Logical Diagram
Memory Management
CPU Scheduler
User
Kernel
Hardware
Binary Formats
Consistency
System Calls
Interrupts Disk Net
RCU File System
Device Drivers
Networking Sync
Memory Allocators Threads
Today’s Lecture
![Page 4: Interrupts)and)System)Calls)porter/courses/cse506/f14/... · CSE506:OperangSystems Logical)Diagram) Memory)) Management CPU) Scheduler) User Kernel) Hardware) Binary) Formats) Consistency)](https://reader033.vdocument.in/reader033/viewer/2022042310/5ed83acd0fa3e705ec0e1437/html5/thumbnails/4.jpg)
CSE 506: Opera.ng Systems
Background: Control Flow
// x = 2, y = true if (y) {
2 /= x; printf(x);
} //...
void printf(va_args) {
//...
}
Regular control flow: branches and calls (logically follows source code)
pc
![Page 5: Interrupts)and)System)Calls)porter/courses/cse506/f14/... · CSE506:OperangSystems Logical)Diagram) Memory)) Management CPU) Scheduler) User Kernel) Hardware) Binary) Formats) Consistency)](https://reader033.vdocument.in/reader033/viewer/2022042310/5ed83acd0fa3e705ec0e1437/html5/thumbnails/5.jpg)
CSE 506: Opera.ng Systems
Background: Control Flow
// x = 0, y = true if (y) {
2 /= x; printf(x);
} //...
void handle_divzero(){
x = 2;
}
Irregular control flow: excepHons, system calls, etc.
pc Divide by zero! Program can’t make
progress!
![Page 6: Interrupts)and)System)Calls)porter/courses/cse506/f14/... · CSE506:OperangSystems Logical)Diagram) Memory)) Management CPU) Scheduler) User Kernel) Hardware) Binary) Formats) Consistency)](https://reader033.vdocument.in/reader033/viewer/2022042310/5ed83acd0fa3e705ec0e1437/html5/thumbnails/6.jpg)
CSE 506: Opera.ng Systems
Lecture goal • Understand the hardware tools available for irregular control flow. – I.e., things other than a branch in a running program
• Building blocks for context switching, device management, etc.
![Page 7: Interrupts)and)System)Calls)porter/courses/cse506/f14/... · CSE506:OperangSystems Logical)Diagram) Memory)) Management CPU) Scheduler) User Kernel) Hardware) Binary) Formats) Consistency)](https://reader033.vdocument.in/reader033/viewer/2022042310/5ed83acd0fa3e705ec0e1437/html5/thumbnails/7.jpg)
CSE 506: Opera.ng Systems
Two types of interrupts • Synchronous: will happen every Hme an instrucHon executes (with a given program state) – Divide by zero – System call – Bad pointer dereference
• Asynchronous: caused by an external event – Usually device I/O – Timer Hcks (well, clocks can be considered a device)
![Page 8: Interrupts)and)System)Calls)porter/courses/cse506/f14/... · CSE506:OperangSystems Logical)Diagram) Memory)) Management CPU) Scheduler) User Kernel) Hardware) Binary) Formats) Consistency)](https://reader033.vdocument.in/reader033/viewer/2022042310/5ed83acd0fa3e705ec0e1437/html5/thumbnails/8.jpg)
CSE 506: Opera.ng Systems
Intel nomenclature • Interrupt – only refers to asynchronous interrupts • ExcepHon – synchronous control transfer
• Note: from the programmer’s perspecHve, these are handled with the same abstracHons
![Page 9: Interrupts)and)System)Calls)porter/courses/cse506/f14/... · CSE506:OperangSystems Logical)Diagram) Memory)) Management CPU) Scheduler) User Kernel) Hardware) Binary) Formats) Consistency)](https://reader033.vdocument.in/reader033/viewer/2022042310/5ed83acd0fa3e705ec0e1437/html5/thumbnails/9.jpg)
CSE 506: Opera.ng Systems
Lecture outline • Overview • How interrupts work in hardware • How interrupt handlers work in sodware • How system calls work • New system call hardware on x86
![Page 10: Interrupts)and)System)Calls)porter/courses/cse506/f14/... · CSE506:OperangSystems Logical)Diagram) Memory)) Management CPU) Scheduler) User Kernel) Hardware) Binary) Formats) Consistency)](https://reader033.vdocument.in/reader033/viewer/2022042310/5ed83acd0fa3e705ec0e1437/html5/thumbnails/10.jpg)
CSE 506: Opera.ng Systems
Interrupt overview • Each interrupt or excepHon includes a number indicaHng its type
• E.g., 14 is a page fault, 3 is a debug breakpoint • This number is the index into an interrupt table
![Page 11: Interrupts)and)System)Calls)porter/courses/cse506/f14/... · CSE506:OperangSystems Logical)Diagram) Memory)) Management CPU) Scheduler) User Kernel) Hardware) Binary) Formats) Consistency)](https://reader033.vdocument.in/reader033/viewer/2022042310/5ed83acd0fa3e705ec0e1437/html5/thumbnails/11.jpg)
CSE 506: Opera.ng Systems
x86 interrupt table
0 255
…
31
… …
47
Reserved for the CPU
Sodware Configurable
Device IRQs 48 = JOS System Call
128 = Linux System Call
![Page 12: Interrupts)and)System)Calls)porter/courses/cse506/f14/... · CSE506:OperangSystems Logical)Diagram) Memory)) Management CPU) Scheduler) User Kernel) Hardware) Binary) Formats) Consistency)](https://reader033.vdocument.in/reader033/viewer/2022042310/5ed83acd0fa3e705ec0e1437/html5/thumbnails/12.jpg)
CSE 506: Opera.ng Systems
x86 interrupt overview • Each type of interrupt is assigned an index from 0—255.
• 0—31 are for processor interrupts; generally fixed by Intel – E.g., 14 is always for page faults
• 32—255 are sodware configured – 32—47 are for device interrupts (IRQs) in JOS
• Most device’s IRQ line can be configured • Look up APICs for more info (Ch 4 of Bovet and CesaH)
– 0x80 issues system call in Linux (more on this later)
![Page 13: Interrupts)and)System)Calls)porter/courses/cse506/f14/... · CSE506:OperangSystems Logical)Diagram) Memory)) Management CPU) Scheduler) User Kernel) Hardware) Binary) Formats) Consistency)](https://reader033.vdocument.in/reader033/viewer/2022042310/5ed83acd0fa3e705ec0e1437/html5/thumbnails/13.jpg)
CSE 506: Opera.ng Systems
Sodware interrupts • The int <num> instrucHon allows sodware to raise an interrupt – 0x80 is just a Linux convenHon. JOS uses 0x30.
• There are a lot of spare indices – You could have mulHple system call tables for different purposes or types of processes! • Windows does: one for the kernel and one for win32k
![Page 14: Interrupts)and)System)Calls)porter/courses/cse506/f14/... · CSE506:OperangSystems Logical)Diagram) Memory)) Management CPU) Scheduler) User Kernel) Hardware) Binary) Formats) Consistency)](https://reader033.vdocument.in/reader033/viewer/2022042310/5ed83acd0fa3e705ec0e1437/html5/thumbnails/14.jpg)
CSE 506: Opera.ng Systems
Sodware interrupts, cont • OS sets ring level required to raise an interrupt – Generally, user programs can’t issue an int 14 (page fault) manually
– An unauthorized int instrucHon causes a general protecHon fault • Interrupt 13
![Page 15: Interrupts)and)System)Calls)porter/courses/cse506/f14/... · CSE506:OperangSystems Logical)Diagram) Memory)) Management CPU) Scheduler) User Kernel) Hardware) Binary) Formats) Consistency)](https://reader033.vdocument.in/reader033/viewer/2022042310/5ed83acd0fa3e705ec0e1437/html5/thumbnails/15.jpg)
CSE 506: Opera.ng Systems
What happens (generally): • Control jumps to the kernel – At a prescribed address (the interrupt handler)
• The register state of the program is dumped on the kernel’s stack – SomeHmes, extra info is loaded into CPU registers – E.g., page faults store the address that caused the fault in the cr2 register
• Kernel code runs and handles the interrupt • When handler completes, resume program (see iret instr.)
![Page 16: Interrupts)and)System)Calls)porter/courses/cse506/f14/... · CSE506:OperangSystems Logical)Diagram) Memory)) Management CPU) Scheduler) User Kernel) Hardware) Binary) Formats) Consistency)](https://reader033.vdocument.in/reader033/viewer/2022042310/5ed83acd0fa3e705ec0e1437/html5/thumbnails/16.jpg)
CSE 506: Opera.ng Systems
How it works (HW) • How does HW know what to execute? • Where does the HW dump the registers; what does it use as the interrupt handler’s stack?
![Page 17: Interrupts)and)System)Calls)porter/courses/cse506/f14/... · CSE506:OperangSystems Logical)Diagram) Memory)) Management CPU) Scheduler) User Kernel) Hardware) Binary) Formats) Consistency)](https://reader033.vdocument.in/reader033/viewer/2022042310/5ed83acd0fa3e705ec0e1437/html5/thumbnails/17.jpg)
CSE 506: Opera.ng Systems
How is this configured? • Kernel creates an array of Interrupt descriptors in memory, called Interrupt Descriptor Table, or IDT – Can be anywhere in memory – Pointed to by special register (idtr)
• c.f., segment registers and gdtr and ldtr!
• Entry 0 configures interrupt 0, and so on
![Page 18: Interrupts)and)System)Calls)porter/courses/cse506/f14/... · CSE506:OperangSystems Logical)Diagram) Memory)) Management CPU) Scheduler) User Kernel) Hardware) Binary) Formats) Consistency)](https://reader033.vdocument.in/reader033/viewer/2022042310/5ed83acd0fa3e705ec0e1437/html5/thumbnails/18.jpg)
CSE 506: Opera.ng Systems
x86 interrupt table
0 255
…
31
… …
47
idtr
Linear Address of Interrupt Table
![Page 19: Interrupts)and)System)Calls)porter/courses/cse506/f14/... · CSE506:OperangSystems Logical)Diagram) Memory)) Management CPU) Scheduler) User Kernel) Hardware) Binary) Formats) Consistency)](https://reader033.vdocument.in/reader033/viewer/2022042310/5ed83acd0fa3e705ec0e1437/html5/thumbnails/19.jpg)
CSE 506: Opera.ng Systems
x86 interrupt table
0 255
…
31
… …
47
idtr
Code Segment: Kernel Code Segment Offset: &page_fault_handler //linear addr Ring: 0 // kernel Present: 1 Gate Type: Exception
14
![Page 20: Interrupts)and)System)Calls)porter/courses/cse506/f14/... · CSE506:OperangSystems Logical)Diagram) Memory)) Management CPU) Scheduler) User Kernel) Hardware) Binary) Formats) Consistency)](https://reader033.vdocument.in/reader033/viewer/2022042310/5ed83acd0fa3e705ec0e1437/html5/thumbnails/20.jpg)
CSE 506: Opera.ng Systems
Interrupt Descriptor • Code segment selector – Almost always the same (kernel code segment) – Recall, this was designed before paging on x86!
• Segment offset of the code to run – Kernel segment is “flat”, so this is just the linear address
• Privilege Level (ring) – Ring that can raise this interrupt with an int instrucHon
• Present bit – disable unused interrupts • Gate type (interrupt or trap/excepHon) – more in a bit
![Page 21: Interrupts)and)System)Calls)porter/courses/cse506/f14/... · CSE506:OperangSystems Logical)Diagram) Memory)) Management CPU) Scheduler) User Kernel) Hardware) Binary) Formats) Consistency)](https://reader033.vdocument.in/reader033/viewer/2022042310/5ed83acd0fa3e705ec0e1437/html5/thumbnails/21.jpg)
CSE 506: Opera.ng Systems
x86 interrupt table
0 255
…
31
… …
47
idtr
Code Segment: Kernel Code Segment Offset: &breakpoint_handler //linear addr Ring: 3 // user Present: 1 Gate Type: Exception
3
![Page 22: Interrupts)and)System)Calls)porter/courses/cse506/f14/... · CSE506:OperangSystems Logical)Diagram) Memory)) Management CPU) Scheduler) User Kernel) Hardware) Binary) Formats) Consistency)](https://reader033.vdocument.in/reader033/viewer/2022042310/5ed83acd0fa3e705ec0e1437/html5/thumbnails/22.jpg)
CSE 506: Opera.ng Systems
Interrupt Descriptors, ctd. • In-‐memory layout is a bit confusing – Like a lot of the x86 architecture, many interfaces were later deprecated
• Worth comparing Ch 9.5 of the i386 manual with inc/mmu.h in the JOS source code
![Page 23: Interrupts)and)System)Calls)porter/courses/cse506/f14/... · CSE506:OperangSystems Logical)Diagram) Memory)) Management CPU) Scheduler) User Kernel) Hardware) Binary) Formats) Consistency)](https://reader033.vdocument.in/reader033/viewer/2022042310/5ed83acd0fa3e705ec0e1437/html5/thumbnails/23.jpg)
CSE 506: Opera.ng Systems
How it works (HW) • How does HW know what to execute? – Interrupt descriptor table specifies what code to run
• And at what privilege (via code segment)
– This can be set up once during boot for the whole system
• Where does the HW dump the registers; what does it use as the interrupt handler’s stack? – Specified in the Task State Segment
![Page 24: Interrupts)and)System)Calls)porter/courses/cse506/f14/... · CSE506:OperangSystems Logical)Diagram) Memory)) Management CPU) Scheduler) User Kernel) Hardware) Binary) Formats) Consistency)](https://reader033.vdocument.in/reader033/viewer/2022042310/5ed83acd0fa3e705ec0e1437/html5/thumbnails/24.jpg)
CSE 506: Opera.ng Systems
Task State Segment (TSS) • Another segment, just like the code and data segment – A descriptor created in the GDT (cannot be in LDT) – Selected by special task register (tr) – Unlike others, has a hardware-‐specified layout
• Lots of fields for rarely-‐used features • Two features we care about in a modern OS: – 1) LocaHon of kernel stack (fields ss0/esp0) – 2) I/O Port privileges (more in a later lecture)
![Page 25: Interrupts)and)System)Calls)porter/courses/cse506/f14/... · CSE506:OperangSystems Logical)Diagram) Memory)) Management CPU) Scheduler) User Kernel) Hardware) Binary) Formats) Consistency)](https://reader033.vdocument.in/reader033/viewer/2022042310/5ed83acd0fa3e705ec0e1437/html5/thumbnails/25.jpg)
CSE 506: Opera.ng Systems
TSS, cont. • Simple model: specify a TSS for each process – Note: Only 2^13 entries in the GDT
• OpHmizaHon (JOS): – Our kernel is prevy simple (uniprocessor only) – Why not just share one TSS and kernel stack per-‐process?
• Linux generalizaHon: – One TSS per CPU – Modify TSS fields as part of context switching
![Page 26: Interrupts)and)System)Calls)porter/courses/cse506/f14/... · CSE506:OperangSystems Logical)Diagram) Memory)) Management CPU) Scheduler) User Kernel) Hardware) Binary) Formats) Consistency)](https://reader033.vdocument.in/reader033/viewer/2022042310/5ed83acd0fa3e705ec0e1437/html5/thumbnails/26.jpg)
CSE 506: Opera.ng Systems
Summary • Most interrupt handling hardware state set during boot
• Each interrupt has an IDT entry specifying: – What code to execute, privilege level to raise the interrupt
• Stack to use specified in the TSS
![Page 27: Interrupts)and)System)Calls)porter/courses/cse506/f14/... · CSE506:OperangSystems Logical)Diagram) Memory)) Management CPU) Scheduler) User Kernel) Hardware) Binary) Formats) Consistency)](https://reader033.vdocument.in/reader033/viewer/2022042310/5ed83acd0fa3e705ec0e1437/html5/thumbnails/27.jpg)
CSE 506: Opera.ng Systems
Comment • Again, segmentaHon rears its head • You can’t program OS-‐level code on x86 without gewng your hands dirty with it
• Helps to know which features are important when reading the manuals
![Page 28: Interrupts)and)System)Calls)porter/courses/cse506/f14/... · CSE506:OperangSystems Logical)Diagram) Memory)) Management CPU) Scheduler) User Kernel) Hardware) Binary) Formats) Consistency)](https://reader033.vdocument.in/reader033/viewer/2022042310/5ed83acd0fa3e705ec0e1437/html5/thumbnails/28.jpg)
CSE 506: Opera.ng Systems
Lecture outline • Overview • How interrupts work in hardware • How interrupt handlers work in so>ware • How system calls work • New system call hardware on x86
![Page 29: Interrupts)and)System)Calls)porter/courses/cse506/f14/... · CSE506:OperangSystems Logical)Diagram) Memory)) Management CPU) Scheduler) User Kernel) Hardware) Binary) Formats) Consistency)](https://reader033.vdocument.in/reader033/viewer/2022042310/5ed83acd0fa3e705ec0e1437/html5/thumbnails/29.jpg)
CSE 506: Opera.ng Systems
High-‐level goal • Respond to some event, return control to the appropriate process
• What to do on: – Network packet arrives – Disk read compleHon – Divide by zero – System call
![Page 30: Interrupts)and)System)Calls)porter/courses/cse506/f14/... · CSE506:OperangSystems Logical)Diagram) Memory)) Management CPU) Scheduler) User Kernel) Hardware) Binary) Formats) Consistency)](https://reader033.vdocument.in/reader033/viewer/2022042310/5ed83acd0fa3e705ec0e1437/html5/thumbnails/30.jpg)
CSE 506: Opera.ng Systems
Interrupt Handlers • Just plain old kernel code
![Page 31: Interrupts)and)System)Calls)porter/courses/cse506/f14/... · CSE506:OperangSystems Logical)Diagram) Memory)) Management CPU) Scheduler) User Kernel) Hardware) Binary) Formats) Consistency)](https://reader033.vdocument.in/reader033/viewer/2022042310/5ed83acd0fa3e705ec0e1437/html5/thumbnails/31.jpg)
CSE 506: Opera.ng Systems
Example
User Kernel
Stack Stack
if (x) { printf(“Boo”); ...
printf(va_args…){
...
Disk_handler (){ ...
}
RSP
RIP
RSP
RIP
Disk Interrupt!
![Page 32: Interrupts)and)System)Calls)porter/courses/cse506/f14/... · CSE506:OperangSystems Logical)Diagram) Memory)) Management CPU) Scheduler) User Kernel) Hardware) Binary) Formats) Consistency)](https://reader033.vdocument.in/reader033/viewer/2022042310/5ed83acd0fa3e705ec0e1437/html5/thumbnails/32.jpg)
CSE 506: Opera.ng Systems
ComplicaHon: • What happens if I’m in an interrupt handler, and another interrupt comes in? – Note: kernel stack only changes on privilege level change – Nested interrupts just push the next frame on the stack
• What could go wrong? – Violate code invariants – Deadlock – Exhaust the stack (if too many fire at once)
![Page 33: Interrupts)and)System)Calls)porter/courses/cse506/f14/... · CSE506:OperangSystems Logical)Diagram) Memory)) Management CPU) Scheduler) User Kernel) Hardware) Binary) Formats) Consistency)](https://reader033.vdocument.in/reader033/viewer/2022042310/5ed83acd0fa3e705ec0e1437/html5/thumbnails/33.jpg)
CSE 506: Opera.ng Systems
Example
User Kernel
Stack Stack
if (x) { printf(“Boo”); ...
printf(va_args…){
...
disk_handler (){ lock_kernel(); ... unlock_kernel();
...
RSP
RIP
net_handler (){ lock_kernel(); …
Network Interrupt!
Will Hang Forever! Already Locked!!!
![Page 34: Interrupts)and)System)Calls)porter/courses/cse506/f14/... · CSE506:OperangSystems Logical)Diagram) Memory)) Management CPU) Scheduler) User Kernel) Hardware) Binary) Formats) Consistency)](https://reader033.vdocument.in/reader033/viewer/2022042310/5ed83acd0fa3e705ec0e1437/html5/thumbnails/34.jpg)
CSE 506: Opera.ng Systems
Bovom Line: • Interrupt service rouHnes must be reentrant or synchronize
• Period.
![Page 35: Interrupts)and)System)Calls)porter/courses/cse506/f14/... · CSE506:OperangSystems Logical)Diagram) Memory)) Management CPU) Scheduler) User Kernel) Hardware) Binary) Formats) Consistency)](https://reader033.vdocument.in/reader033/viewer/2022042310/5ed83acd0fa3e705ec0e1437/html5/thumbnails/35.jpg)
CSE 506: Opera.ng Systems
Hardware interrupt sync. • While a CPU is servicing an interrupt on a given IRQ line, the same IRQ won’t raise another interrupt unHl the rouHne completes – Bovom-‐line: device interrupt handler doesn’t have to worry about being interrupted by itself
• A different device can interrupt the handler – ProblemaHc if they share data structures – Like a list of free physical pages… – What if both try to grab a lock for the free list?
![Page 36: Interrupts)and)System)Calls)porter/courses/cse506/f14/... · CSE506:OperangSystems Logical)Diagram) Memory)) Management CPU) Scheduler) User Kernel) Hardware) Binary) Formats) Consistency)](https://reader033.vdocument.in/reader033/viewer/2022042310/5ed83acd0fa3e705ec0e1437/html5/thumbnails/36.jpg)
CSE 506: Opera.ng Systems
Disabling interrupts • An x86 CPU can disable I/O interrupts – Clear bit 9 of the EFLAGS register (IF Flag) – cli and sti instrucHons clear and set this flag
• Before touching a shared data structure (or grabbing a lock), an interrupt handler should disable I/O interrupts
![Page 37: Interrupts)and)System)Calls)porter/courses/cse506/f14/... · CSE506:OperangSystems Logical)Diagram) Memory)) Management CPU) Scheduler) User Kernel) Hardware) Binary) Formats) Consistency)](https://reader033.vdocument.in/reader033/viewer/2022042310/5ed83acd0fa3e705ec0e1437/html5/thumbnails/37.jpg)
CSE 506: Opera.ng Systems
Gate types • Recall: an IDT entry can be an interrupt or an excepHon gate
• Difference? – An interrupt gate automaHcally disables all other interrupts (i.e., clears and sets IF on enter/exit)
– An excepHon gate doesn’t • This is just a programmer convenience: you could do the same thing in sodware
![Page 38: Interrupts)and)System)Calls)porter/courses/cse506/f14/... · CSE506:OperangSystems Logical)Diagram) Memory)) Management CPU) Scheduler) User Kernel) Hardware) Binary) Formats) Consistency)](https://reader033.vdocument.in/reader033/viewer/2022042310/5ed83acd0fa3e705ec0e1437/html5/thumbnails/38.jpg)
CSE 506: Opera.ng Systems
ExcepHons • You can’t mask excepHons – Why not?
• Can’t make progress ader a divide-‐by-‐zero
– Double and Triple faults detect faults in the kernel • Do excepHon handlers need to be reentrant? – Not if your kernel has no bugs (or system calls in itself) – In certain cases, Linux allows nested page faults
• E.g., to detect errors copying user-‐provided buffers
![Page 39: Interrupts)and)System)Calls)porter/courses/cse506/f14/... · CSE506:OperangSystems Logical)Diagram) Memory)) Management CPU) Scheduler) User Kernel) Hardware) Binary) Formats) Consistency)](https://reader033.vdocument.in/reader033/viewer/2022042310/5ed83acd0fa3e705ec0e1437/html5/thumbnails/39.jpg)
CSE 506: Opera.ng Systems
Summary • Interrupt handlers need to synchronize, both with locks (mulH-‐processor) and by disabling interrupts (same CPU)
• ExcepHon handlers can’t be masked – Nested excepHons generally avoided
![Page 40: Interrupts)and)System)Calls)porter/courses/cse506/f14/... · CSE506:OperangSystems Logical)Diagram) Memory)) Management CPU) Scheduler) User Kernel) Hardware) Binary) Formats) Consistency)](https://reader033.vdocument.in/reader033/viewer/2022042310/5ed83acd0fa3e705ec0e1437/html5/thumbnails/40.jpg)
CSE 506: Opera.ng Systems
Lecture outline • Overview • How interrupts work in hardware • How interrupt handlers work in sodware • How system calls work • New system call hardware on x86
![Page 41: Interrupts)and)System)Calls)porter/courses/cse506/f14/... · CSE506:OperangSystems Logical)Diagram) Memory)) Management CPU) Scheduler) User Kernel) Hardware) Binary) Formats) Consistency)](https://reader033.vdocument.in/reader033/viewer/2022042310/5ed83acd0fa3e705ec0e1437/html5/thumbnails/41.jpg)
CSE 506: Opera.ng Systems
System call “interrupt” • Originally, system calls issued using int instrucHon • Dispatch rouHne was just an interrupt handler • Like interrupts, system calls are arranged in a table – See arch/x86/kernel/syscall_table*.S in Linux source
• Program selects the one it wants by placing index in eax register – Arguments go in the other registers by calling convenHon – Return value goes in eax!
![Page 42: Interrupts)and)System)Calls)porter/courses/cse506/f14/... · CSE506:OperangSystems Logical)Diagram) Memory)) Management CPU) Scheduler) User Kernel) Hardware) Binary) Formats) Consistency)](https://reader033.vdocument.in/reader033/viewer/2022042310/5ed83acd0fa3e705ec0e1437/html5/thumbnails/42.jpg)
CSE 506: Opera.ng Systems
Lecture outline • Overview • How interrupts work in hardware • How interrupt handlers work in sodware • How system calls work • New system call hardware on x86
![Page 43: Interrupts)and)System)Calls)porter/courses/cse506/f14/... · CSE506:OperangSystems Logical)Diagram) Memory)) Management CPU) Scheduler) User Kernel) Hardware) Binary) Formats) Consistency)](https://reader033.vdocument.in/reader033/viewer/2022042310/5ed83acd0fa3e705ec0e1437/html5/thumbnails/43.jpg)
CSE 506: Opera.ng Systems
Around P4 era… • Processors got very deeply pipelined – Pipeline stalls/flushes became very expensive – Cache misses can cause pipeline stalls
• System calls took twice as long from P3 to P4 – Why? – IDT entry may not be in the cache – Different permissions constrain instrucHon reordering
![Page 44: Interrupts)and)System)Calls)porter/courses/cse506/f14/... · CSE506:OperangSystems Logical)Diagram) Memory)) Management CPU) Scheduler) User Kernel) Hardware) Binary) Formats) Consistency)](https://reader033.vdocument.in/reader033/viewer/2022042310/5ed83acd0fa3e705ec0e1437/html5/thumbnails/44.jpg)
CSE 506: Opera.ng Systems
Idea • What if we cache the IDT entry for a system call in a special CPU register? – No more cache misses for the IDT! – Maybe we can also do more opHmizaHons
• AssumpHon: system calls are frequent enough to be worth the transistor budget to implement this – What else could you do with extra transistors that helps performance?
![Page 45: Interrupts)and)System)Calls)porter/courses/cse506/f14/... · CSE506:OperangSystems Logical)Diagram) Memory)) Management CPU) Scheduler) User Kernel) Hardware) Binary) Formats) Consistency)](https://reader033.vdocument.in/reader033/viewer/2022042310/5ed83acd0fa3e705ec0e1437/html5/thumbnails/45.jpg)
CSE 506: Opera.ng Systems
AMD: syscall/sysret • These instrucHons use MSRs (machine specific registers) to store: – Syscall entry point and code segment – Kernel stack
• A drop-‐in replacement for int 0x80!• Everyone loved it and adopted it wholesale – Even Intel!
![Page 46: Interrupts)and)System)Calls)porter/courses/cse506/f14/... · CSE506:OperangSystems Logical)Diagram) Memory)) Management CPU) Scheduler) User Kernel) Hardware) Binary) Formats) Consistency)](https://reader033.vdocument.in/reader033/viewer/2022042310/5ed83acd0fa3e705ec0e1437/html5/thumbnails/46.jpg)
CSE 506: Opera.ng Systems
Adermath • Getpid() on my desktop machine (recent AMD 6-‐core): – Int 80: 371 cycles – Syscall: 231 cycles
• So system calls are definitely faster as a result!
![Page 47: Interrupts)and)System)Calls)porter/courses/cse506/f14/... · CSE506:OperangSystems Logical)Diagram) Memory)) Management CPU) Scheduler) User Kernel) Hardware) Binary) Formats) Consistency)](https://reader033.vdocument.in/reader033/viewer/2022042310/5ed83acd0fa3e705ec0e1437/html5/thumbnails/47.jpg)
CSE 506: Opera.ng Systems
In JOS • You will use the int instrucHon to implement system calls
• There is a challenge problem in lab 3 (i.e., extra credit) to use systenter/sysexit – Note that there are some more details about register saving to deal with
– Syscall/sysret is a bit too trivial for extra credit • But sHll cool if you get it working!
![Page 48: Interrupts)and)System)Calls)porter/courses/cse506/f14/... · CSE506:OperangSystems Logical)Diagram) Memory)) Management CPU) Scheduler) User Kernel) Hardware) Binary) Formats) Consistency)](https://reader033.vdocument.in/reader033/viewer/2022042310/5ed83acd0fa3e705ec0e1437/html5/thumbnails/48.jpg)
CSE 506: Opera.ng Systems
Summary • Interrupt handlers are specified in the IDT • Understand when nested interrupts can happen – And how to prevent them when unsafe
• Understand opHmized system call instrucHons – Be able to explain vdso, syscall vs. int 80