ME262
Introduction to Microprocessor & Digital Logic
(Sequential Logic)(Sequential Logic)Summer 2010
Introduction to Microprocessor and Digital Logic, ME262, University of Waterloo, S'10 1
Sequential Logic
h ( ) f l d d h
DefinitionThe output(s) of a sequential circuit depends on the current and past states of the inputs,
ororA combinational circuit with memory elements is called a sequential circuit.
C bi ti l O t t
Combinational Memory
Combinational Outputs
SequentialCircuits
CombinationalCircuit
MemoryElements
Introduction to Microprocessor and Digital Logic, ME262, University of Waterloo, S'10 2Inputs
A synchronous sequential circuit employs signals that affectthe storage only at discrete instants of time.g y
C bi i lInputs OutputsCombinationalCircuit
Flip-flops
Inputs Outputs
Clock pulses
Introduction to Microprocessor and Digital Logic, ME262, University of Waterloo, S'10 3
Digital Logic with Feedbackif we alter gate circuits so as to give signal feedback from the output to one of theinputs, strange things begin to happen!!. Let’s take an OR gate as an example.
X ZX Z
Z
When X is 0, the output could be either 0 or 1, depending on the circuit's prior state. The proper way to complete the above truth table would be to insert the word latch in place ofproper way to complete the above truth table would be to insert the word latch in place of the question mark, showing that the output maintains its last state when X is 0.
X Z
Introduction to Microprocessor and Digital Logic, ME262, University of Waterloo, S'10 4
0 LATCH11
Any digital circuit employing feedback is also called a multi-vibrator. The previous example (OR gate) is a bistable multi-vibrator which has two stable status. There are circuits which d h bl hi h i ll d b bldo not have any stable status which is called abstable.
For example, consider the following example (an inverter with the output fed directly back to the input):p )
Y Y
The result is a high frequency (several megahertz) oscillator, if implemented with a solid-state (semiconductor) inverter gate. If implemented with relay logic, the resulting oscillator will be considerably slower, cycling at a frequency well within the audio
h b ib i i h f d d i l i l dirange. The buzzer or vibrator circuit thus formed was used extensively in early radio circuitry, as a way to convert steady, low-voltage DC power into pulsating DC power which could then be stepped up in voltage through a transformer to produce the high voltage necessary for operating the vacuum tube amplifiers.
Introduction to Microprocessor and Digital Logic, ME262, University of Waterloo, S'10 5
vo tage ecessa y o ope at g t e vacuu tube a p e s.
Memory ElementMemory elements like other logic circuits can be realized with basic gates.The most important memory element is the flip-flop. To understand the structure of a flip-flop we start with designing Latches. Before that, we need to understated the meaning of propagation delay
Propagation DelayIn any logic gate or circuit, there is a delay between the time you change the inputs and the time you see the effects of the inputs on the outputs. This delay is called the propagation delay.
XNOT
Y
X
Y=X
Y
Introduction to Microprocessor and Digital Logic, ME262, University of Waterloo, S'10 6
Propagation Delay (e.g., 10-8 Sec.)
GatesNANDLatch withRS It operates with both inputs normally at 1 unless the state of the latch has to bechanged.
0 0 1
After S=0 & R=1
0 1 1 0 Set StateS RS Q1
1
After S=0 & R=1
After S=1 & R=0
1 1 1 0 Store1 0 0 1 Reset1 1 0 1 Store
Q10
Instable
0
Stable
0 0 1 1 DisallowedR Q1
Introduction to Microprocessor and Digital Logic, ME262, University of Waterloo, S'10 7
Input Control Latch withRS S
Q
CLK
RQ
S R CLK
0
1
X X
0 0
No change; Store state
Next State of Q
h1
1
1
0 0
0 1
01
No change, Store state
Q=0; Reset state
Q=1, set state
Introduction to Microprocessor and Digital Logic, ME262, University of Waterloo, S'10 8
1 1 1 Disallowed
Latch DHaving a disallowed state in SR latch can be resolved using D latch.
DQ
CLK
Q
DCLK
0 X h
Next State of Q
0
1
1
X
0
1
No change; Store state
Q=0; Reset State
Q=1; Set state
Introduction to Microprocessor and Digital Logic, ME262, University of Waterloo, S'10 9
Flip-Flops (Edge-triggered latches)(Edge-triggered latches)
The latch responds to the data inputs (S-R or D) only when the input is enabled. Inmany digital applications, however, it is required to limit the responsiveness of ay g pp q platch circuit to an input activated in a very short period of time. One method ofenabling a latch circuit is called edge triggering, where the circuit's data inputs havecontrol only during the time that the enable input is transitioning from one state toanotheranother.
Response to positive levelResponse to positive level
Response to positive-edge (rising edge)
Introduction to Microprocessor and Digital Logic, ME262, University of Waterloo, S'10 10
Response to negative-edge (falling edge)
D Flip-Flops In order to generate a very narrow clock pulse consider the following circuit
X X Z
1X
0
1X
01
XXXX0
1Z R l t t ft d l
Output before delay
Introduction to Microprocessor and Digital Logic, ME262, University of Waterloo, S'10 11
Z0 Real output after delay
Now, we can integrate the previous circuit into a D latch circuit. The integrated circuit is called D Flip-Flop.
DQ
CLK
Q
CLK D Next state of Q
0 X N h ( t )0 X No change (store)D Q
CLK QQ = 0; Reset StateQ=1; Set State
01
Introduction to Microprocessor and Digital Logic, ME262, University of Waterloo, S'10 12
J-K Flip-Flops
QJ SQ
CLK
QKR
CLKJ QK Q
0 1 0 1Q
J
x x
1 0 1 00 0 Q 01 1 Toggle
Q0
Q0Q00
Q
QK
Clk
Introduction to Microprocessor and Digital Logic, ME262, University of Waterloo, S'10 13
x x Q0Q00
Output toggles at eachrising edge if j=k=1
No change ifj=k=0
K
J
CLK
Q
O t t t lTransition to J
value if j=k
Output togglebecause j=k=1
Switch will be high, but it isalready high, so no transition
Introduction to Microprocessor and Digital Logic, ME262, University of Waterloo, S'10 14
Sequential Logic Design Method You need to answer these questions:
Is the problem a sequential system?If h d d b d? If yes, what does need to be stored?
Determine the number of flip-flops. Find the state table Derive the flip-flop inputs and outputs from state stable Simplify logic equations
Combinational Outputs N S (FF’ I )
Combinational Flip-Flops
Combinational Outputs
SequentialCircuits
Next States (FF’s Inputs)
CircuitFlip Flops
Introduction to Microprocessor and Digital Logic, ME262, University of Waterloo, S'10 15
CLKInputs
Present States (FF’s Outputs)
ExamplePurpose: Design a Divide-by-2 counter
Present State = Q Next state = DPresent State Q Next state D
0D Q
CLK1
1
0Q
D Q
CLK
Q0Q0.D
CLK Q0Q0Q
Q
Introduction to Microprocessor and Digital Logic, ME262, University of Waterloo, S'10 16
The frequency of output is half of the input clock frequency.Q0
ExamplePurpose D i Di id b 8 tPurpose: Design a Divide-by-8 counter. In fact, we would like to count the number of pulses, however, we use three bits display to present the counter. The main use of this counter is in SHIFT REGISTERS. A register capable of shifting its binary information in one or both g p g ydirections is called a shift register. The logical configuration of a shift register consists of a chain of flip-flops, with the output of one flip-flop connected to the inputs of the other flip-flop. All flip-flops receive common clock pulses, which acti ate the shift from one stage to the ne tactivate the shift from one stage to the next.
Present States Next StatesQQ2 Q1 Q0 Q2.D
0 0 0 0 0 10 0 1 0 1 00 1 0 0 1 1
Q0D QQ 1.D Q0.DQ0.D
CLK Q
0 1 0 0 1 10 1 1 1 0 01 0 0 1 0 11 0 1 1 1 01 1 0 1 1 1
Q1Q D Q1.DCLK Q
Introduction to Microprocessor and Digital Logic, ME262, University of Waterloo, S'10 17
1 1 0 1 1 11 1 1 0 0 0
Q2Q D Q2.DCLK Q
CLK
Q1
Q0
Q2
Q Q Q QQ
Having truth table, the Boolean expressions can be obtained.
Q1Q0 Q0
Q2 00 01 11 10
0 1 2
Q0Q0
QQQQQQQQQ
Q2 1 1 1 1
1 Q1Q
0212012.2 QQQQQQQQ D
Introduction to Microprocessor and Digital Logic, ME262, University of Waterloo, S'10 18
1 Q1Q
Q1Q0 Q0
Q2 00 01 11 10Q0Q0
Q2 00 01 11 10
0 1 2
Q2 1
1
1 1
Q
0101.1 QQQQQ D
1 Q1Q
Q1Q0 Q0
Q 00 01 11 10Q0 Q0
Q2 00 01 11 10
0 1 2
1
1
1 1
Q
0.0 QQ D Q2 1 1 1
1 Q1Q
Introduction to Microprocessor and Digital Logic, ME262, University of Waterloo, S'10 19
D QQ0
D QQ0 D
Q1Q
D Q
D QQ
D Q
D Q1.D
Q0.D
CLK Q
CLK Q
PulseGenerator
QQ D Q
2Q D Q2.DCLK Q
Introduction to Microprocessor and Digital Logic, ME262, University of Waterloo, S'10 20
ExamplePurpose D i Di id b 4 t i J K Fli FlPurpose: Design a Divide-by-4 counter using J-K Flip-Flops
JA
ClkA
KA
JBB
KB
ClkB
Clk
BJ A JA
KA
ClkA
BK A 1BJ JB
ClkB
Introduction to Microprocessor and Digital Logic, ME262, University of Waterloo, S'10 21
1BK KB
Clk +5v
ExamplePurpose D i M d l 5 C t It t f 0 t 4 t dlPurpose: Design a Modulo-5 Counter. It can count from 0 to 4 repeatedly.
QPresent state Next State Q0Q2 Q1 Q0 Q 2.D Q1.D
0 0 0 0 0 10 0 1 0 1 00 1 0 0 1 1
D QQ0.DQ0.D
CLK Q
Q1Q0 1 0 0 1 10 1 1 1 0 01 0 0 0 0 01 0 1 X X X1 1 0 X X X
D Q1.DCLK Q
Q2Q D Q1 1 0 X X X1 1 1 X X X 2.D
CLK Q
Using K-map, the following equations are derived.
Introduction to Microprocessor and Digital Logic, ME262, University of Waterloo, S'10 22
Q1Q0 Q0
Q2 00 01 11 10Q0 Q0
0 1 2
Q2 1 x x x
Q
01.2 QQQ D
1 Q1Q
Q1Q0 Q0Q0 Q0
Q2 00 01 11 10
0 1 2
Q2 1 xx
1
x
Q
0101.1 QQQQQ D Q2
1 Q1Q
Q1Q0 Q0Q0 Q0Q1Q0 Q0
Q2 00 01 11 10
0 1 2
Q 1
1
Q0 Q0
Q
020 QQQ D
Introduction to Microprocessor and Digital Logic, ME262, University of Waterloo, S'10 23
Q2 1 xx
1 Q1
x
Q
02.0 QQQ D