[email protected]://csce.uark.edu +1 (479) 575-6043
Introduction to PrimetimeCourtesy of Dr. Gil Rahav@Freescale
DTA (Simulation)
●Traditionally, a dynamic simulator has been used to verify the functionality and timing of an entire design or blocks within the design.
●Dynamic timing simulation requires vectors, a logic simulator and timing information. With this methodology, input vectors are used to exercise functional paths based on dynamic timing behaviors for the chip or block.
●Dynamic simulation is becoming more problematic because of the difficulty in creating comprehensive vectors with high levels of coverage.
●Time-to-market pressure, chip complexity, limitations in the speed and capacity of traditional simulators are all motivating factors for migration towards static timing techniques.
Dynamic Timing Analysis
11/8/2017 CSCE/ELEG 4914: Advnaced Digital Design 2
STA
●STA is an exhaustive method of analyzing, debugging and validating the timing performance of a design.
●First, a design is analyzed, then all possible paths are timed and checked against the requirements.
●Since STA is not based on functional vectors, it is typically very fast and can accommodate very large designs (multimillion gate designs).
●STA is exhaustive in that every path in the design is checked for timing violations.
●STA does not verify the functionality of a design. Also, certain design styles are not well suited for static approach. For instance, dynamic simulation may be required for asynchronous parts of a design and certainly for any mixed-signal portions.
Static Timing Analysis (STA)
11/8/2017 CSCE/ELEG 4914: Advnaced Digital Design 3
STA consists of three major steps:
●Break down the design into timing paths (R-R, PI-R,PI-PO & R-PO).
●Delay of each path is calculated
●All path delays are checked against timing constraints to see if it is met.
STA advantage
●Speed (orders of magnitude faster than dynamic simulation)
●Capacity to handling full chip
●Exhaustive timing coverage
●Vectors are not required
STA disadvantage
● It is pessimistic (too conservative)
●Reports false paths
Static Timing Analysis (STA)
11/8/2017 CSCE/ELEG 4914: Advnaced Digital Design 4
Static Verification Flow
Functional
Simulation
Scan Place
Testbench
Clock
TreeRoute
RTL Domain
Equivalence CheckingGate-level Domain
Synthesis
Equivalence
Checking
Static Timing Analysis
Sign
Off
11/8/2017 CSCE/ELEG 4914: Advnaced Digital Design 5
Static Timing Analysis Flow
Every
Co
rner
an
dM
od
e
Errors/
Warnings?Fix data
Next step in design
flow
Analyze Reports
Read required files
Validate inputs
no
yes
Ready to perform STA
on a gate-level
synchronous design
using SDF
PrimeTime
11/8/2017 CSCE/ELEG 4914: Advnaced Digital Design 6
Parasitic Extraction
●Distributed format enables PrimeTime to annotate each physical segment of the routed netlist (most accurate form of RC back-annotation)
Back-Annotation - Parasitics
C1 C2
R1
C3
R2
C4
R3 . . .
11/8/2017 CSCE/ELEG 4914: Advnaced Digital Design 7
Cell delays are calculated from a Non Linear Delay Model (NLDM) table in the technology library
Tables are indexed by input transition and total output load for each gate
Cell Delay Calculation
Cell Delay = f (Input Transition Time, Output Load)
Cell Delay (ns)
O
.005
utput
.05
Load (
.10
pF)
.15
0.0 .1 .15 .2 .25
0.5 .15 . 23 .3 .38
1.0 .25 .4 .55 .75
Inp
ut
Tra
ns
(ns
)
0.005pF
0.045pF
Cell Delay = .23 ns
From Library
From Wire Load Model
0.5 ns
11/8/2017 CSCE/ELEG 4914: Advnaced Digital Design 8
Net delay is the “time-of-flight” due to the net’s RC
Net’s RC is obtained from wire load model for pre-layout design
Net delay
Net Delay Calculation
Rnet Cnet
Cpin
Net Delay = f (Rnet, Cnet + Cpin)
Post-layout Rs and Cs are extracted as a parasitics file.Post-layout Rs and Cs are extracted as a parasitics file.
11/8/2017 CSCE/ELEG 4914: Advnaced Digital Design 9
There is another NLDM table in the library to calculate output transition
Output transition of a cell becomes the input transition of the next cell down the chain
Output Transition Calculation
Output Transition = f (Input Transition Time, Output Load)
Output Transition (ns)
0.00
O
.005
0.10
utput
. 05
0.20
Load
(p
.10
0.37
F)
.15
0.60
0.50 0.18 0.30 0.49 0.80
1.00 0.25 0.40 0.62 1.00Inp
ut
Tra
ns
(ns
)
Output Trans = 0.30 ns0.5 ns
0.005pF0.045 pF
From Library
From Wire Load Model
11/8/2017 CSCE/ELEG 4914: Advnaced Digital Design 10
PrimeTime
ASIC design from
Design Compiler
Layout Verilog from
IC Compiler
or
PrimeTimeTiming performance
and violation report
Design
Constraints
Rise/Fall Time
Gate delay
11/8/2017 CSCE/ELEG 4914: Advnaced Digital Design 11
PrimeTime Basic Flow
set library path
• set search_path
• set link_path
read the design
• read_verilog
link library and the design
• link
add design constraints
• read_sdc
add constant value to input port (for timing simulation)
• set_case_analysis
report
• report_constraint
• report_timing
11/8/2017 CSCE/ELEG 4914: Advnaced Digital Design 12
Startpoint: FF1 (rising edge-triggered flip-flop clocked by Clk)
Endpoint: FF2 (rising edge-triggered flip-flop clocked by Clk)
Path Group: Clk
Path Type: max
Point Incr Path
-----------------------------------------------------------
0.00
1.10 *
0.00
0.50 *
0.11 *
0.11 *
0.05 *
clock Clk (rise edge)
clock network delay (propagated)
FF1/CLK (fdef1a15)
FF1/Q (fdef1a15)
U2/Y (buf1a27)
U3/Y (buf1a27)
FF2/D (fdef1a15)
data arrival time
0.00
1.10
1.10 r
1.60 r
1.71 r
1.82 r
1.87 r
1.87
4.00
1.00 *
-0.21 *
clock Clk (rise edge)
clock network delay (propagated)
FF2/CLK (fdef1a15)
library setup time
data required time
4.00
5.00
5.00 r
4.79
4.79
------------------------------------------------------------
data required time 4.79
data arrival time -1.87
------------------------------------------------------------
slack (MET) 2.92
report_timing
Four Sections in a Timing Report
Data
arrival
Data
required
Slack
Header
11/8/2017 CSCE/ELEG 4914: Advnaced Digital Design 13
The Header
Startpoint: FF1 (rising edge-triggered flip-flop clocked by Clk)
Endpoint: FF2 (rising edge-triggered flip-flop clocked by Clk)
Path Group: Clk
Path Type: max
F1
FF2
Clk
DF1
FF1
Q
CLK
CLKU3
U2
Header
Report is for setup
Capture clock
11/8/2017 CSCE/ELEG 4914: Advnaced Digital Design 14
Data Arrival Section
Point Incr Path
-----------------------------------------------------------
clock Clk (rise edge)
clock network delay (propagated)
FF1/CLK (fdef1a15)
FF1/Q (fdef1a15)
U2/Y
U3/Y
(buf1a27)
(buf1a27)
0.00
1.10 *
0.00
0.50 *
0.11 *
0.11 *
0.05 *FF2/D (fdef1a15)
data arrival time
0.00
1.10
1.10 r
1.60 r
1.71 r
1.82 r
1.87 r
1.87
F1
FF2
DF1
FF1
Q
CLK
CLKU3
U2
Data
arrival
1.1ns
.05ns.11ns
.11ns
.50ns
0 2 4
Clk
r
r
rr
r
Library reference
names
Calculated
latency
11/8/2017 CSCE/ELEG 4914: Advnaced Digital Design 15
Data Required Section
Point Incr Path
-----------------------------------------------------------
0.00
1.10 *
0.00
0.50 *
0.11 *
0.11 *
0.05 *
clock Clk (rise edge)
clock network delay (propagated)
FF1/CLK (fdef1a15)
FF1/Q (fdef1a15)
U2/Y (buf1a27)
U3/Y (buf1a27)
FF2/D (fdef1a15)
data arrival time
0.00
1.10
1.10 r
1.60 r
1.71 r
1.82 r
1.87 r
1.87
clock Clk (rise edge)
clock network delay (propagated)
4.00
1.00 *
-0.21 *
FF2/CLK (fdef1a15)
library setup time
data required time
4.00
5.00
5.00 r
4.79
4.79
Data
required
F1
FF2
DF1
FF1
Q
CLK
CLKU3
U2
0 2 4
Clk
1.0ns
0.21ns
r
11/8/2017 CSCE/ELEG 4914: Advnaced Digital Design 16
Startpoint: FF1 (rising edge-triggered flip-flop clocked by Clk)
Endpoint: FF2 (rising edge-triggered flip-flop clocked by Clk)
Path Group: Clk
Path Type: max
Point Incr Path
-----------------------------------------------------------0.00
1.10 *
0.00
0.50 *
0.11 *
0.11 *
0.05 *
clock Clk (rise edge)
clock network delay (propagated)
FF1/CLK (fdef1a15)
FF1/Q (fdef1a15)
U2/Y (buf1a27)
U3/Y (buf1a27)
FF2/D (fdef1a15)
data arrival time
0.00
1.10
1.10 r
1.60 r
1.71 r
1.82 r
1.87 r
1.87
4.00
1.00 *
-0.21 *
clock Clk (rise edge)
clock network delay (propagated)
FF2/CLK (fdef1a15)
library setup time
data required time
4.00
5.00
5.00 r
4.79
4.79
------------------------------------------------------------
data required time 4.79
data arrival time -1.87
------------------------------------------------------------
slack (MET) 2.92
Summary - Slack
Slack
11/8/2017 CSCE/ELEG 4914: Advnaced Digital Design 17
Setting Environment
● initrc invs171
● initrc FreePDK45
● initrc cal172
● initrc pts-m
Download primetime.tgz and merge the content of primetime folder with the innovus folder
Example VQS64_4
11/8/2017 CSCE/ELEG 4914: Advnaced Digital Design 18
Adder Filler Cells
Add Filler
11/8/2017 CSCE/ELEG 4914: Advnaced Digital Design 19
Parasitic Extraction
Perform parasitic extraction
11/8/2017 CSCE/ELEG 4914: Advnaced Digital Design 20
GDS is the standard file type for layout
Export GDS
11/8/2017 CSCE/ELEG 4914: Advnaced Digital Design 21
Command line: calibredrv
Calibre DRV
11/8/2017 CSCE/ELEG 4914: Advnaced Digital Design 22
Refer to virtuoso slides (Verification>Start nmDRC)
Calibre DRC
11/8/2017 CSCE/ELEG 4914: Advnaced Digital Design 23
Start DRC
DRC
11/8/2017 CSCE/ELEG 4914: Advnaced Digital Design 24
Start DRC
DRC
11/8/2017 CSCE/ELEG 4914: Advnaced Digital Design 25
Similar to Design Compiler script (pt_shell -f pt.tcl)
Primetime
11/8/2017 CSCE/ELEG 4914: Advnaced Digital Design 26
PrimeTime GUI
11/8/2017 CSCE/ELEG 4914: Advnaced Digital Design 27
GUI - Timing Path
11/8/2017 CSCE/ELEG 4914: Advnaced Digital Design 28
11/8/2017 29CSCE/ELEG 4914: Advnaced Digital Design
Timing Report
11/8/2017 30CSCE/ELEG 4914: Advnaced Digital Design
Power Report