Download - Introduction to Programmable Logic Devices
Introduction toProgrammable Logic Devices
John Coughlan
STFC Technology Department
Detector & Electronics Division
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Programmable Logic is a Key Underlying Technology for PP Experiments.
First-Level and High-Level Triggering
Data Transport (Networks)
Computers interacting with Hardware (Networks)
Silicon Trackers (Millions of Data Channels)
Commercial Devices. Developments driven by Industry.
Telecomms, Gaming, Aerospace, Automotive, Set-top boxes….
PPD Lectures
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
CMS
CERN LHC
Particle Physics Electronics
Custom Electronics ChipsASICs ANALOGUE $$$Rad Hard, Low Power
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
CMS
CERN LHC
Electronics Rooms
Particle Physics Electronics
Trigger Systems. DAQ Systems.DIGITAL
Custom Electronics ChipsASICs ANALOGUE $$$Rad Hard, Low Power
Custom Digital Processing BoardsVME Bus Crates
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Particle Physics Electronics
Special Dedicated Logic Functions (not possible in CPUs) Ultra Fast Trigger Systems (Trigger Algorithms) Clock Accurate
Timing Massively Parallel Data Processing (Silicon Trackers with Millions of
Channels)
Custom DesignedPrinted Circuit Boards PCBs.
CommercialProgrammable LogicDevices, FPGAs
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
CMS DAQ/Trigger Architectures
CMS
“Telecoms Network” ~ 1 Tbps
Fully custom PP ASICs
CPUs Commodity PCs
Programmable LogicDIGITAL
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Lecture Outline
Programmable Logic Devices Basics Evolution
FPGA Field Programmable Gate Array Architecture
Design Flow Hardware Description Languages Design Tools
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Digital Logic
Logic Gates
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Digital Logic
Logic Gates
Transistor Switches
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Digital Logic
Logic Gates
Transistor Switches
< 40 nm ! $$$
MOORE’S LAW
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Digital Logic
Black BoxSUM of PRODUCTS
Truth Table(Look Up Table LUT)
Digital Logic Function
3 Inputs
Product AND (&)Sum OR (|)
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Digital Logic
Black BoxSUM of PRODUCTS
Truth Table(Look Up Table LUT)
Digital Logic Function
3 Inputs
Product AND (&)Sum OR (|)
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Digital Logic
Black BoxSUM of PRODUCTS
Truth Table(Look Up Table LUT)
Digital Logic Function
3 Inputs
Product AND (&)Sum OR (|)
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Programmable Logic Devices PLDs
Un-programmed State
SUM of PRODUCTS (Re-)Programmble Links Reconfigurable GLUE LOGIC
Logic Functions
Planes ofANDs, ORs
Inputs
Outputs
ANDs
ORs
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Programmable Logic Devices PLDs
Un-programmed State
SUM of PRODUCTS (Re-)Programmble Links Reconfigurable GLUE LOGIC
Logic Functions
Planes ofANDs, ORs
Inputs
Outputs
ANDs
ORs
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Programmable Logic Devices PLDs
Un-programmed State
SUM of PRODUCTS (Re-)Programmble Links Reconfigurable GLUE LOGIC
Logic Functions
Planes ofANDs, ORs
Inputs
Outputs
ANDs
ORs
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Programmable Logic Devices PLDs
Un-programmed State
SUM of PRODUCTS (Re-)Programmble Links Reconfigurable GLUE LOGIC
Logic Functions
Programmed PLD
Product Terms
Sums
Planes ofANDs, ORs
Inputs
Outputs
ANDs
ORs
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Programmable Logic Devices PLDs
Logic Functions
Programmed PLD
Product Terms
Sums
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Programmable Logic Devices PLDs
Logic Functions
Programmed PLD
Product Terms
Sums
x x
x x x
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Programmable Logic Devices PLDs
Logic Functions
Programmed PLD
Product Terms
Sums
x x
x x x x
x
GLUE LOGIC
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Complex PLDs
CPLDs Programmable PLD Blocks Programmable Interconnects Electrically Erasable links
CPLD Architecture
Feedback Outputs
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Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Sequential Circuits Combinational Logic (Larger circuits difficult to predict) Synchronous Logic driven by a CLOCK Registers, Flip Flops (Memory)
Inputs
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Sequential Circuits
RegisterCLOCK
New Output every clock edge
Combinational Logic (Larger circuits difficult to predict) Synchronous Logic driven by a CLOCK Registers, Flip Flops (Memory)
Inputs
Intermediate
EDGES
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Sequential Circuits
RegisterCLOCK
New Output every clock edge
Shift Registers,Pipelines,Finite State Machines…
Combinational Logic (Larger circuits difficult to predict) Synchronous Logic driven by a CLOCK Registers, Flip Flops (Memory)
Clock Rate determines speed
Comb Logic Must meet Timing=> Predictable circuits
Inputs
Intermediate
EDGES
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Field Programmable Gate Arrays FPGA
Field Programmable Gate Array ‘Simple’ Programmable Logic Blocks Massive Fabric of Programmable Interconnects Standard CMOS Integrated Circuit fabrication process as for
memory chips (Moore’s Law)
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Field Programmable Gate Arrays FPGA
Field Programmable Gate Array ‘Simple’ Programmable Logic Blocks Massive Fabric of Programmable Interconnects Standard CMOS Integrated Circuit fabrication process as for
SRAM memory chips (Moore’s Law)
Huge Density of Logic Block ‘Islands’
1,000 … 100,000’s
in a ‘Sea’ of Interconnects
FPGA Architecture
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Field Programmable Gate Arrays FPGA
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Logic Blocks
Logic Functions implemented in Look Up Table LUTs. Flip-Flops. Registers. Clocked Storage elements. Multiplexers (select 1 of N inputs)
16-bit SR
flip-flop
clock
muxy
qe
abcd
16x1 RAM
4-inputLUT
clock enable
set/reset
FPGA Fabric Logic Block
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Look Up Tables LUTs
LUT contains Memory Cells to implement small logic functions Each cell holds ‘0’ or ‘1’ . Programmed with outputs of Truth Table Inputs select content of one of the cells as output
16-bit SR
flip-flop
clock
muxy
qe
abcd
16x1 RAM
4-inputLUT
clock enable
set/reset
3 Inputs LUT -> 8 Memory Cells
SRAM
Static Random Access MemorySRAM cells
SRAM
3 – 6 Inputs
Multiplexer MUX
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Look Up Tables LUTs LUT contains Memory Cells to implement small logic functions Each cell holds ‘0’ or ‘1’ . Programmed with outputs of Truth Table Inputs select content of one of the cells as output Configured by re-programmable SRAM memory cells
16-bit SR
flip-flop
clock
muxy
qe
abcd
16x1 RAM
4-inputLUT
clock enable
set/reset
3 Inputs LUT -> 8 Memory Cells
SRAM
Static Random Access MemorySRAM cells
SRAM
3 – 6 Inputs
Multiplexer MUX
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Logic Blocks
Larger Logic Functions built up by connecting many Logic Blocks together
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Logic Blocks
Larger Logic Functions built up by connecting many Logic Blocks together
Determined by SRAM cells
SRAM SRAM cells
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Clocked Logic
Registers on outputs. CLOCKED storage elements. Synchronous FPGA Logic Design, Pipelined Logic. FPGA Fabric Pulse from Global Clock (e.g. LHC BX frequency)
16-bit SR
flip-flop
clock
muxy
qe
abcd
16x1 RAM
4-inputLUT
clock enable
set/reset
FPGA Fabric
Clock from Outside world (eg LHC bunch frequency)
Special Routing for Clocks
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Input Output I/O Getting data in and out
01
54
6
7
3
2
General-purpose I/Obanks 0 through 7Up to > 1,000 I/O “pins” (several 100 MHz)
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Input Output I/O Getting data in and out
01
54
6
7
3
2
General-purpose I/Obanks 0 through 7
FPGA
Differential pairs
Transceiver block
Up to > 1,000 I/O “pins” (several 100 MHz)
Special I/O SERIALISERS~ 10 Gbps transfer rates
Optical TRx
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Designing Logic with FPGAs
Design Capture. High level Description of Logic Design.
Graphical descriptions Hardware Description Language (Textual)
Graphical State Diagram
Graphical Flowchart
When clock rises If (s == 0) then y = (a & b) | c; else y = c & !(d ^ e);
Textual HDL
Top-levelblock-levelschematic
Block-level schematic
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Hardware Description Languages
Language describing hardware (Engineers call it FIRMWARE) Doesn’t behave like “normal” programming language ‘C/C++’ Describe Logic as collection of Processes operating in
Parallel Language Constructs for Synchronous Logic
Compiler (Synthesis) Tools recognise certain code constructs and generates appropriate logic
Not all constructs can be implemented in FPGA!
2 Popular languages are VHDL , VERILOG Easy to start learning… Hard to master!
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
VHDLENTITY Declaration Input Output to Module (STD LOGIC)
SIGNALS Declaration WIRES
CONCURRENT ASSIGNMENTS
CONDITIONAL ASSIGNMENTS => MULTIPLEXERS
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
VHDL
COMPONENT Declaration
PROCESS Declaration. CONCURRENT functions. Synchronous Logic.
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Designing Logic with FPGAs High level Description of Logic Design
Hardware Description Language (Textual)
Compile (Synthesis) into NETLIST. Boolean Logic Gates.
Target FPGA Device Mapping Routing
Bit File for FPGA
Commercial CAE Tools(Complex & Expensive)
Logic Simulation
Gate-levelnetlist
BEGIN CIRCUIT=TEST INPUT SET_A, SET-B, DATA, CLOCK, CLEAR_A, CLEAR_B; OUTPUT Q, N_Q; WIRE SET, N_DATA, CLEAR;
GATE G1=NAND (IN1=SET_A, IN2=SET_B, OUT1=SET); GATE G2=NOT (IN1=DATA, OUT1=N_DATA); GATE G3=OR (IN1=CLEAR_A, IN2=CLEAR_B, OUT1=CLEAR); GATE G4=DFF (IN1=SET, IN2=N_DATA, IN3=CLOCK, IN4=CLEAR, OUT1=Q, OUT2=N_Q);
END CIRCUIT=TEST;
Fully-routed physical(CLB-level) netlist
Schematiccapture
Mapping
Packing
Place-and-Route Timing analysis
and timing report
Gate-level netlistfor simulation
SDF (timing info)for simulation
Design Flow
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Designing Logic with FPGAs High level Description of Logic Design
Hardware Description Language (Textual)
Compile (Synthesis) into NETLIST. Boolean Logic Gates.
Target FPGA Device Mapping Routing
Bit File for FPGA
Commercial CAE Tools(Complex & Expensive)
Logic Simulation
Gate-levelnetlist
BEGIN CIRCUIT=TEST INPUT SET_A, SET-B, DATA, CLOCK, CLEAR_A, CLEAR_B; OUTPUT Q, N_Q; WIRE SET, N_DATA, CLEAR;
GATE G1=NAND (IN1=SET_A, IN2=SET_B, OUT1=SET); GATE G2=NOT (IN1=DATA, OUT1=N_DATA); GATE G3=OR (IN1=CLEAR_A, IN2=CLEAR_B, OUT1=CLEAR); GATE G4=DFF (IN1=SET, IN2=N_DATA, IN3=CLOCK, IN4=CLEAR, OUT1=Q, OUT2=N_Q);
END CIRCUIT=TEST;
Fully-routed physical(CLB-level) netlist
Schematiccapture
Mapping
Packing
Place-and-Route Timing analysis
and timing report
Gate-level netlistfor simulation
SDF (timing info)for simulation
Design Flow
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Designing Logic with FPGAs High level Description of Logic Design
Hardware Description Language (Textual)
Compile (Synthesis) into NETLIST. Boolean Logic Gates.
Target FPGA Device Mapping Routing
Bit File for FPGA
Commercial CAE Tools(Complex & Expensive)
Logic Simulation
Gate-levelnetlist
BEGIN CIRCUIT=TEST INPUT SET_A, SET-B, DATA, CLOCK, CLEAR_A, CLEAR_B; OUTPUT Q, N_Q; WIRE SET, N_DATA, CLEAR;
GATE G1=NAND (IN1=SET_A, IN2=SET_B, OUT1=SET); GATE G2=NOT (IN1=DATA, OUT1=N_DATA); GATE G3=OR (IN1=CLEAR_A, IN2=CLEAR_B, OUT1=CLEAR); GATE G4=DFF (IN1=SET, IN2=N_DATA, IN3=CLOCK, IN4=CLEAR, OUT1=Q, OUT2=N_Q);
END CIRCUIT=TEST;
Fully-routed physical(CLB-level) netlist
Schematiccapture
Mapping
Packing
Place-and-Route Timing analysis
and timing report
Gate-level netlistfor simulation
SDF (timing info)for simulation
Design Flow
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Configuring an FPGA Millions of SRAM cells holding LUTs and Interconnect Routing Volatile Memory. Lose configuration when board power is
turned off. Keep Bit Pattern describing the SRAM cells in non-Volatile
Memory e.g. PROM or Digital Camera card Configuration takes ~ secs
Configuration data in
Configuration data out
= I/O pin/pad
= SRAM cell
SRAM
JTAG Port
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Configuring an FPGA Millions of SRAM cells holding LUTs and Interconnect Routing Volatile Memory. Lose configuration when board power is
turned off. Keep Bit Pattern describing the SRAM cells in non-Volatile
Memory e.g. PROM or Digital Camera card Configuration takes ~ secs
Configuration data in
Configuration data out
= I/O pin/pad
= SRAM cell
SRAM
JTAG Testing
JTAG Port
ProgrammingBit File
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Field Programmable Gate Arrays FPGA
Large Complex Functions Re-Programmability, Flexibility.
Massively Parallel Architecture Processing many channels simultaneously cf MicroProcessor
Fast Turnaround Designs Standard IC Manufacturing Processes. Moore’s Law Mass produced. Inexpensive. Many variants. Sizes. Features.
PP Not Radiation Hard Power Hungry No Analogue
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Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
FPGA Trends
State of Art is 40nm on 300 mm wafers Top of range >500,000 Logic Blocks >1,000 pins (Fine Pitched BGA)
Logic Block cost ~ 1$ in 1990 Today < 0.1 cent
Problems Power. Leakage currents. Design Gap
CAE Tools 0.0001
0.001
0.01
0.1
1
1990 1995 2000 2005 2010 2015$
/ L
C
1.00E+02
1.00E+03
1.00E+04
1.00E+05
1.00E+06
1.00E+07
1.00E+08
1.00E+09
1985 1990 1995 2000 2005 2010 2015 2020 2025
Year
Nu
mb
er
of
LC
s
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Summary
Programmable Logic Devices Basics Evolution
FPGA Field Programmable Gate Arrays Architecture
Design Flow Hardware Description Languages Design Tools
Importance for Particle Physics Experiments
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
References
The Design Warrior’s Guide to FPGAs Clive Maxfield, Newnes Elsevier
VHDL for Logic Synthesis Andrew Rushden, Wiley
FPGA manufacturer web sites www.xilinx.com www.altera.com
FPGA Online www.pldesignline.com www.fpgajournal.com www.doulos.com
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Spare Slides
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
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System on a Chip
Add Embedded Micro-Processor Cores in Fabric e.g. RISC PowerPC Ethernet Interface
Run Operating System e.g. Linux
Combine Micro-Processor
& Massively Parallel Logic
Dual Design Flows Firmware HDL Software C
uP
(a) One embedded core (b) Four embedded cores
uP uP
uP uP
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Time line of Programmable devices
1945 1950 1955 1960 1965 1970 1975 1980 1985 1990 1995 2000
FPGAs
ASICs
CPLDs
SPLDs
Microprocessors
SRAMs & DRAMs
ICs (General)
Transistors
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Application Specific Integrated Circuits ASICs
PLDs ASICs
Standard Cell
Full Custom
Gate Arrays
Structured ASICs*
SPLDs
CPLDs
*Not available circa early 1980s
TheGAP
Large Complex Functions . Millions of GatesCustomised for Extremes of Speed, Low Power, Radiation Hardness
(Very) Expensive to Design (in small quantities) > $1 Million mask set(Very) Hard to Design.Long Design cycles.NOT Reprogrammable. FROZEN in Silicon. High Risk
Limited ComplexityThousands of Gates
CheapEasy to DesignReprogrammable.
Custom FabricatedDesign from Scratch
PrefabricatedProgrammed