Introduction to VLSI
Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; CAD MTS, Cypress Semiconductor 1
Baker Ch. 11 The Inverter
Chapter 11
– Inverter
• DC
• AC, Switching
– Ring Oscillator
– Dynamic Power Dissipation
• Layout
– LATCHUP
• Sizing
• PASS GATES (CHPT 10)
• Other Inverters
Introduction to VLSI
Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; CAD MTS, Cypress Semiconductor 2
Baker Ch. 11 The Inverter
Inverter – DC DESCRIPTION
– INPUT A > Vt, THEN OUT=NOT(IN)
– STATIC POWER ~ 0
– VOLTAGE SWING RAIL-TO-RAIL
– SIZED TO DRIVE LOADS
– SWITCHING CHAR VARIES BY W/L
VOLTAGE TRANSFER CURVES
– VOH, OUTPUT HIGH
• VIL DEFINED WHEN SLOPE=-1
– VOL, OUTPUT LOW
• VIH DEFINED WHEN SLOPE=-1
– IDEAL VIL=VIH
WHY?
Introduction to VLSI
Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; CAD MTS, Cypress Semiconductor 3
Baker Ch. 11 The Inverter
Inverter – NOISE, SP DESCRIPTION
– NOISE MARGIN
• NMH = VOH – VIH
• NML = VIL – VOL
– SWITCHING POINT
• BOTH IN SATURATION
• INPUT=OUTPUT, CURRENTS SAME
– bN/2 (VSP-VTHN)2=
bP/2(VDD-VSP-VTHP)2
– VSP=
[ SQRT(bN/bP) VTHN + (VDD-VTHP) ] /
[1 + SQRT(bN/bP) ]
Introduction to VLSI
Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; CAD MTS, Cypress Semiconductor 4
Baker Ch. 11 The Inverter
Inverter – AC DESCRIPTION
– CAPS DUE TO OVERLAP, CH, SD
– WHAT ARE SPIKES DUE TO?
• I = C dV / dt
• CLOCK FEEDTHROUGH
– INTRINSIC DELAY
• NO EXTERNAL LOAD
– PROPAGATION DELAY
• INTRINSIC + EXTRINSIC
– MEASURE INTRINSIC DELAY?
• RING OSCILLATOR
Introduction to VLSI
Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; CAD MTS, Cypress Semiconductor 5
Baker Ch. 11 The Inverter
Inverter – RING OSC DESCRIPTION
– RING OSCILLATOR
• ODD NUMBER OF STAGES
• INPUT STAGEN=OUTPUT STAGEN-1
– PROCESS CHARACTERIZATION
• INV FANOUT=1
• INV FANOUT=3
• METAL1 LOADED
• METAL2 LOADED
• NAND
• NOR
• WHAT IS THIS DOING?
– NEED TO TEST ON ALL WAFERS
1 0 1 0 1 0
Introduction to VLSI
Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; CAD MTS, Cypress Semiconductor 6
Baker Ch. 11 The Inverter
Inverter – POWER DISSIPATION DESCRIPTION
– DYNAMIC
• CHARGE, DISCHARGE CAPS
• I = C V / t
• P = V I = C V2 / t = C V2 fCLK
– STATIC
• REVERSE BIAS PN JUNCTION
• MODEL OF DIODE
– SHORT CIRCUIT
• BOTH N AND P ON DURING VSP
• RELATED TO RISE, FALL TIME
Vout Vin PCH NCH Power Dissipation
0 1 off on none
0->1 1->0 off->on on->off PCH charging cap
1 0 on off none
1->0 0->1 on->off off->on NCH discharging cap
So, in any one period, the total energy dissipated is:
The average power is Energy per Unit Time (period):
MARTIN
DYNAMIC
DYNAMIC
SHORT
CIRCUIT
Introduction to VLSI
Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; CAD MTS, Cypress Semiconductor 7
Baker Ch. 11 The Inverter
Inverter – LAYOUT, LATCHUP DESCRIPTION
– WHAT IS COMMON?
– WHAT IS DIFFERENT?
– WHAT IS THE IMPACT?
LATCHUP
– BIPOLAR EFFECT IN CMOS
• FEEDTHROUGH ON C2
• Q2 ON, FEEDS Q1 BASE
• Q1 FEEDBACK TO Q2 BASE
• THERMAL RUNAWAY
– ELIMINATE LATCHUP
• SLOWER RISE TIME
• REDUCE C1, C2 AREA
• REDUCE RW1, RS2 MORE TAPS
Introduction to VLSI
Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; CAD MTS, Cypress Semiconductor 8
Baker Ch. 11 The Inverter
Inverter – SIZING DESCRIPTION
– NEED TO DRIVE OUTPUT LOADS
– WHAT IS DRIVE?
• I = C dV / dt
• CURRENT NEEDED TO CHANGE VOLTAGE IN GIVEN TIME
– TRADEOFFS
• WHY NOT PUT HUGE W/L ?
– RESISTANCES DECREASE BY A
• R2 = R1 / A
• R3 = R2/A = R1 /A2
– INPUT, OUTPUT CAP INCR BY A
• CIN2=CIN1 * A
• CIN FINAL = CIN1 AN = CLOAD
• A = [ CLOAD / CIN1 ] 1/N
• N = ln [CLOAD / CIN1] NMB OF STAGES
• A IS IDEALLY e – EACH INVERTER DRIVES 2.718 INV
– WIDTHS OF NMOS X 2.718
T = 407ps
T = 580ps
T = 95ps
Introduction to VLSI
Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; CAD MTS, Cypress Semiconductor 9
Baker Ch. 11 The Inverter
PASS GATES (Chpt. 10) DESCRIPTION
– NMOS PASSES 0 (source is at gnd)
– PMOS PASSES 1 (source is at vdd)
• REASON IS LOCATION OF SOURCE
• Current only flows if Vgs > Vtn
• Vg – Vs = Vtn
• VDD – Vs = Vtn, manipulate terms
• VDD – Vtn = Vs, Vs= VDD – Vtn
• “DROP A Vt”, Source is not at zero
• Simliar for PMOS, Vs = Vtp (below)
Vg=VDD
Vd=VDD
Vs=?
Vg=0
Vs=VDD
Vsg=VDD
Vg=0
Vd=0
Vsg=?
Vs – Vg = Vtp
Vs – 0 = Vtp
Vs = Vtp
Introduction to VLSI
Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; CAD MTS, Cypress Semiconductor 10
Baker Ch. 11 The Inverter
PASS GATES (Chpt. 10) DESCRIPTION
– Combine NMOS, PMOS to pass 1/0
– If signal is a 1, PMOS passes it
– If signal is a 0, NMOS passes it
– Transmission Gates (no drop)
– Pass Gates (drops Vt)
Introduction to VLSI
Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; CAD MTS, Cypress Semiconductor 11
Baker Ch. 11 The Inverter
Inverter – Other Config DESCRIPTION
– (A) NMOS ONLY
• AVOIDS LATCHUP, NO PMOS
– (B), (C) PSUEDO-NMOS
• USEFUL FOR LARGE NMB INPUTS
• PMOS AS LOAD TRANSISTOR
• ASYMMETRIC SWITCHING
– TRADEOFFS
• DC CURRENT FLOW WITH LOGIC 1
• How to minimize this current?
• VOL != GROUND
• (C) VOH=VDD, OTHERS VDD-Vt
– BENEFITS
• LOWER CAP, SINCE NO PMOS
• REDUCED VOLTAGE SWING
• LOWER POWER AT HIGH FREQ
Introduction to VLSI
Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; CAD MTS, Cypress Semiconductor 12
Baker Ch. 11 The Inverter
on
1
on off
off
VDD-Vt
off
0
off on
on
0
Inverter – Other Config DESCRIPTION
– SUPER BUFFER
• No PMOS, no latchup
• Reduced voltage swing
• No direct path to GND
• IN = L, M1, M4 OFF; M2, M3 ON
• IN = H, M1, M4 ON; OUT=VDD-Vt – DROP A Vt
– TRI-STATE BUFFER
• S=H INVERSION, S=L HIGH-Z
• (A) FASTER, MORE POWER
• (B) SLOWER, LESS POWER
– PUMPED VOLTAGE BUFFER
• GENERATE ON CHIP VDD+VADD – NO LOSS OF Vt
Vdd+Vt
Vdd
Vdd GND