INV ITEDP A P E R
Nanoscale Thermal TransportandMicrorefrigeratorsonaChipDevices for cooling high power density and dynamic hot spots can be formed by
solid-state thin films on the chip, or they could be buried in, bonded to,
or mounted on substrates.
By Ali Shakouri
ABSTRACT | In this paper we review recent advances in
nanoscale thermal and thermoelectric transport with an
emphasis on the impact on integrated circuit (IC) thermal
management. We will first review thermal conductivity of low-
dimensional solids. Experimental results have shown that
phonon surface and interface scattering can lower thermal con-
ductivity of silicon thin films and nanowires in the sub-100-nm
range by a factor of two to five. Carbon nanotubes are
promising candidates as thermal vias and thermal interface
materials due to their inherently high thermal conductivities of
thousands of W/mK and high mechanical strength. We then
concentrate on the fundamental interaction between heat and
electricity, i.e., thermoelectric effects, and how nanostructures
are used to modify this interaction. We will review recent
experimental and theoretical results on superlattice and
quantum dot thermoelectrics as well as solid-state thermionic
thin-film devices with embedded metallic nanoparticles. Heat
and current spreading in the three-dimensional electrode
configuration, allow removal of high-power hot spots in IC
chips. Several III-V and silicon heterostructure integrated
thermionic (HIT) microcoolers have been fabricated and char-
acterized. They have achieved cooling up to 7 �C at 100 �C
ambient temperature with devices on the order of 50 �m in
diameter. The cooling power density was also characterized
using integrated thin-film heaters; values ranging from 100 to
680 W/cm2 were measured. Response time on the order of
20–40 ms has been demonstrated. Calculations show that
with an improvement in material properties, hot spots tens
of micrometers in diameter with heat fluxes in excess of
1000 W/cm2 could be cooled down by 20 �C–30 �C. Finally
we will review some of the more exotic techniques such as
thermotunneling and analyze their potential application to
chip cooling.
KEYWORDS | Carbon nanotubes (CNTs); embedded nanoparti-
cles; microrefrigeration; nanoscale heat transport; nanotech-
nology; quantum dots; superlattices; thermal boundary
resistance; thermionics; thermotunneling; thermoelectrics
I . INTRODUCTION
Individual micro- and nanoscale electronic devices cangenerate heat fluxes exceeding thousands of watts per
centimeter square in very small areas on the order of
micrometers in size. Typical integrated circuit (IC) chips
have millions of transistors. Variations in the activity of the
transistors for different functional units create hot spots
only a couple of hundred micrometers in diameter that can
be 10 �C–40 �C hotter than the rest of the chip. Most of
the conventional cooling techniques can be used to coolthe whole chip. Since thermal design requirements are
mostly driven by peak temperatures, reducing or elimi-
nating hot spots could alleviate the design requirements
for the whole package. In existing commercial silicon
chips, since the substrate thickness is several hundred
micrometers, and since silicon has a high thermal con-
ductivity, the extremely nonuniform power dissipation in
individual transistors and functional units gives rise to hotspots proportional in size to the silicon substrate’s
thickness (a couple of hundred micrometers to milli-
meters). This is substantially smaller than the size of the
whole chip, so hot spot removal is a key enabler for future
generation IC chips. On the other hand, as the silicon
wafer thickness is reduced and stacked chips or three-
dimensional (3-D) chips are investigated, there is less heat
spreading in the bulk silicon. This can create smaller hotspots on the order of 50–100 �m in size with more severe
temperature nonuniformity. In addition, when the device
dimensions shrink enough and new materials such as
Manuscript received May 4, 2006; revised June 5, 2006. This work was supported by
Packard Fellowship, Intel Corp., Canon Corp., DARPA HERETIC and ONR MURI
Thermionic Energy Conversion Center.
The author is with the Jack Baskin School of Engineering, University of California at
Santa Cruz, CA 95064 USA (e-mail: [email protected]).
Digital Object Identifier: 10.1109/JPROC.2006.879787
Vol. 94, No. 8, August 2006 | Proceedings of the IEEE 16130018-9219/$20.00 �2006 IEEE
carbon nanotubes (CNTs) are used, the conventional bulkdiffusive heat equation will not be valid; moreover,
boundary effects and ballistic heat conduction will need
consideration. In this paper we briefly review main nano-
scale heat transport issues and describe techniques to
remove small hot spots in IC chips with the use of solid-
state refrigerators.
Nanoscale engineering of material to provide desirable
properties is a key enabler for the future improvements ofIC thermal management. Nanotechnology and nanometer-
scale engineering can be broadly defined as Bworking at
atomic, molecular and supra molecular levels, in the
length scale of approximately 1–100 nm range, in order to
understand and create materials, devices and systems with
fundamentally new properties and functions due to their
small structure[ [1]. The usefulness of miniaturization has
been known for many years in various fields such as inmicroelectronics and more recently in microelectrome-
chanical systems (MEMS). Systems with faster perfor-
mance, less space, material, and energy can be realized. In
addition, in the nanometer domain there are new unique
effects due to quantum phenomena and enhanced surface
to volume ratios [2], [3]. We will first review nanoscale
thermal and thermoelectric transport and then concen-
trate on active solid-state devices for hot spot removal.Latest experimental results and the potential for improve-
ment in the long term will be discussed.
II . NANOSCALE THERMAL PROPERTIES
Research in nanoscale thermal properties is relatively
more recent compared to nanoscale electronic properties,
which started in the 1960s [4]. Perhaps this is becausemeasuring and modeling micro- and nanoscale thermal
properties accurately is very difficult [5], [6]. Only re-
cently several techniques have been introduced that allow
measuring temperature and heat flow at atomic scales.
Small thermocouples at the tip of atomic force micro-
scopes [also called scanning thermal microscopy (SThM)]
have been successfully used to measure temperatures with
G 100-nm resolution [7]. Scanning Seebeck voltage mea-surements have reached 2–3 nm spatial resolution with the
use of sharp heated metallic tips in ultrahigh vacuum
environment [8]. Femtosecond laser technology has
permitted the measurement of heat transfer and acoustic
velocities in thin-film submicrometer structures [9], [10].
Thermoreflectance imaging using visible wavelengths has
been used to measure the surface temperature of IC chips
with submicrometer spatial resolution and 1–100 mKtemperature resolution [11]–[15]. Heat transfer at the
nanoscale may differ significantly from that in the macro-
and microscales. When a device or structure’s dimensions
are comparable to the mean free path and wavelength of
heat carriers, classical laws are no longer valid and new
approaches must be taken to predict heat transfer at the
nanoscale. Before we continue the discussion of nanoscale
heat transport and the differences with bulk heat con-duction, we need to introduce the concept of phonons.
A. What Are Phonons?In analyzing the random thermal vibrations of atoms in
a solid, one typically uses the eigenmodes of the collective
vibrations, which are called phonons. Depending on the
type of these vibrations, we can have longitudinal and
transverse modes. Acoustic and optical phonons refer tothe case where neighboring atoms oscillate in phase or out
of phase, respectively. In the later case, an atomic dipole is
formed that could interact with photons, thus the name
optical phonon. Electron transport in devices often
generates optical phonons. Since these phonons have low
group velocities, they have to decay to acoustic phonons so
that heat is transported. When one area of the sample is
hot, the interaction between neighboring atoms causes therandom vibrations to propagate in the material. It is more
intuitive to write these random vibrations in terms of the
normal modes (phonons) and explain how different
phonons are transported. Heat conduction is usually
described by the bulk parameter of thermal conductivity,
which is of great importance in electronic thermal man-
agement. It has been recognized for some time that at the
microscale or at very short times, the parabolic heatconduction equation that assumes an instantaneous effect
of boundaries everywhere in the domain is not a good
approximation. The hyperbolic heat equation and the more
general phonon Boltzmann transport equation have been
investigated [16], [17], [142]. Additional parameters such
as heat drag are introduced in order to take into account
the finite propagation velocity of vibrations and non-
equilibrium effects [18]. In practice, the heat diffusionequation and thermal conductivity parameter can still
explain majority of thermal transport phenomena at
nanoscale. Under high drive conditions, different popula-
tions of electrons and phonons will not be in equilibrium
and one may not be able to define a single temperature.
For example, in short length transistors, the strong
nonequilibrium between electron and phonon populations
and between optical phonons and acoustic phonons leadsto submicrometer hot spots and heating in the electron gas
(see the paper by Pop et al. in this special issue [19]).
Ballistic electron and phonon transport without any
scattering over nanometer distances also has a strong
impact on heat generation in submicrometer electronic
devices [20], [21]. Furthermore, at an interface between
two solids, depending on the coupling between atoms,
there could be an extra thermal boundary resistance (thisis also called Kapitza resistance which was introduced in
the 1950s for liquid helium). There is no theory that can
reliably predict heat conduction across boundaries and in
nanometers-thick layers [22], [23]. Sometimes, phonons
are treated as particles and their transport across an
interface is described using a specular or diffuse reflec-
tance model. This depends on the roughness and scattering
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1614 Proceedings of the IEEE | Vol. 94, No. 8, August 2006
at the interface. In some other applications, heat andphonons are treated as waves and their transport across an
interface or a multilayer is described by the acoustic
mismatch model. Various experimental results have been
explained using these two theories [5], [24], [25]. Since
thermal conductivity is an average bulk effect involving
many lattice vibrations (phonons modes), it is hard to
differentiate between various contributions in order to
gain an accurate understanding of heat transport innanometer structures. In the case of electron transport,
charge carriers interact with both electric and magnetic
fields. Effects such as Hall voltage and Shubnikov–de Haas
oscillations are used to measure electron effective mass,
mobility, and number of free carriers. They are also used to
differentiate between electrons from different bands in the
solid. This has been extremely useful to study electron
transport in nanometer-thick layers. Lack of similarcomplementary measurements in the case of phonon
transport, and the added difficulty due to the fact that
phonons are Bquasi[ particles (eigenmodes) that could be
annihilated or created, makes detailed analysis very dif-
ficult. Very recently the phonon Hall effect under a
magnetic field has been observed. This could provide a
useful source of information about phonons and their
transport in solids [26].
B. Thermal Transport in Thin FilmsHeat conduction and phonon transport along single-
and polycrystalline monolayers is important for silicon-on-
insulator (SOI) circuits, novel 3-D multilayer electronics,
and MEMS with semiconducting or dielectric membranes.
The interface between silicon and silicon dioxide film
scatters phonons and can affect the thermal conductivity.For bulk material, interface effects only dominate at low
temperatures where the phonon mean free path is large.
However, in nanometer-scale thin films, the room
temperature thermal conductivity could be significantly
modified. Fig. 1 displays thermal conductivity along silicon
films of different thicknesses. At sub-100-nm scales, a
reduction of the conductivity by a factor of two to five
compared to bulk data is observed [27], [143], [162], [163].
C. Thermal Transport in Nanowires and CNTsOne-dimensional (1-D) nanostructures such as CNTs
and semiconductor nanowires have recently received a lot
of attention [28]. Phonons in nanowires can be different
from bulk material mainly because the dispersion relation
could be significantly modified due to confinement. In
addition, the presence of a surface can introduce surfacephonon modes and scattering. On one hand, in the case of
semiconducting silicon nanowires, a significant reduction
in the thermal conductivity along the wire was observed
due to phonon scattering at the boundaries [29]. On the
other hand, CNTs with their unique geometry made of
rolled two-dimensional (2-D) graphite sheets have high
mechanical strength and good thermal conductivity. First
theoretical predictions for high thermal conductivity weremade by Berber [30] and by Osman and Srivastava [144].
Recent calculations by Mingo and Broido have shown
that some of the earlier calculations overestimated ther-
mal conductance of CNTs [31]. An upper bound of
�4 � 109 W/m2K was found at room temperature. They
also found that phonon transport remains ballistic over
large distances. On the experimental side, the first attempts
to measure thermal conductivity of a collection of CNTsgave values much lower than predicted [32], [145], [146].
This is due to weak coupling between CNTs in the array
that can affect the thermal transport. Subsequent measure-
ments by Kim et al. [33], [147] were done on single CNTs
suspended between thin-film microheaters. Yu et al. [158]
have recently reported that the measured thermal conduc-
tance of a 2.76-�m single-wall carbon nanotube (SWCNT)
is very close to the calculated ballistic thermal conduc-tance of a 1-nm-diameter SWCNT, with an effective
thermal conductivity comparable to earlier measurement
results of a multiwall CNT (�3000 W/mK). Fig. 2 shows
the plot of the thermal conductivity of multiwall CNTs
(MWCN) as a function of temperature. The T2 tempera-
ture dependence suggests that MWCN behaves thermally
as a 2-D solid. Recently, there has been a lot of research on
the incorporation of CNTs arrays inside polymers, solders,or even copper in order to obtain high thermal conduc-
tivity thermal interface materials (TIMs) with good mech-
anical compliance properties [34]. The details of TIMs are
described in the paper by Prasher in this special issue [35].
III . NANOSCALE THERMOELECTRICPROPERTIES
Conventional thermoelectric (TE) coolers are described in
the article by Sharp et al. in this special issue [36]. The
Peltier effect is due to the fact that electron gas carries not
Fig. 1. Thermal conductivity of silicon thin films versus film thickness
at room temperature (courtesy of Prof. M. Asheghi [27], [159]).
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only a charge but also some average transport (kinetic)
energy. When electrons flow from a material to anothermaterial in which their average transport energy is higher,
they absorb thermal energy from the lattice, and this will
cool the junction between the two materials. One could
think of electron gas expanding in the energy space as they
enter the second material. This is the main reason for
refrigeration. This process is reversible, if the direction of
current is changed, energy is released to the lattice, and
there will be heating at the junction. When electrons moveunder an external electric field, their Baverage kinetic
energy with respect to the Fermi level[ is the exact
definition of the Peltier coefficient, which is the Seebeck
coefficient times absolute temperature.
The efficiency of a conventional thermoelectric cooler
is described by a dimensionless parameter ZT. It is given by
ZT ¼ �S2T=�, where T is the absolute temperature, � and
� are the electrical and thermal conductivities of thematerial, respectively, and S is the Seebeck coefficient.
[37], [38], [148].
A. Low-Dimensional ThermoelectricsIn 1993 the outstanding pioneering work of Hicks and
Dresselhaus renewed interest in thermoelectrics, becom-
ing the inspiration for most of the recent developments in
the field [39]. Dresselhaus and coworkers showed that
electrons in low-dimensional semiconductors such as
quantum wells and wires have an improved thermoelectric
power factor (Seebeck coefficient squared times electrical
conductivity) and ZT 9 2 � 3 can be achieved (see Fig. 3).
This is due to the fact that electron motion perpendicularto the potential barrier is quantized creating sharp features
in the electronic density of states (DOS) [40]. Sometimes
it is claimed that low-dimensional structures have an
Bincreased[ DOS. This is not strictly correct. The quantum
confinement of electrons eliminates some states that
electrons can occupy, since they do not obey the boundary
Fig. 2. Thermal conductivity of individual single-wall (SW) and multiwall (MW) CNTs as well as CNT bundles versus temperature
(courtesy of Prof. L. Shi [33], [147]).
Fig. 3. Thermoelectric figure-of-merit ZT of Bi quantum well and
quantum wire as a function of dimension [39]. Inset shows the density
of electronic states for 3-D, 2-D, 1-D and 0-D conductors.
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conditions for electronic wavefunction. Thus, the numberof available states (quantum numbers) associated with any
given energy is either reduced or unchanged. The main
benefit is that the quantum confinement changes the
energy of the bandedge of the semiconductor. Near this
bandedge, some sharp features in DOS are created. One
can use these sharp features to increase the asymmetry
between hot and cold electron transport and thus obtain a
large average transport energy and a large number ofcarriers moving in the material, i.e., a large Seebeck
coefficient square times electrical conductivity.
Despite the fact that the concept of low-dimensional
thermoelectrics is rigorously correct and proof-of-principle
has been demonstrated [41], the recent breakthroughs in
materials with ZT 9 1 (Venkatasubramanian et al. [42],
Harman et al. [43], or Kanatizidis et al. [44]) have mainly
benefited from reduced phonon thermal conductivity [45]with power factors similar to the existing state-of-the-art
material. There are two reasons why it is hard to improve
the thermoelectric power factor of quantum well materials
[46]–[48]. First, we live in a 3-D world and any low-
dimensional quantum well structure should be imbedded
in barriers. These barriers are electrically inactive but they
add to thermal heat loss between the hot and the cold
junctions. This can reduce the performance significantly[49]. One cannot make the barrier too thin, since the
tunneling between adjacent quantum wells will broaden
energy levels and reduce the improvement due to the DOS.
The second reason is that the sharp features in the DOS of
2-D nanostructures disappear quickly as soon as there is
size nonuniformity in the material.1 A natural extension of
quantum wells and superlattices is to quantum wires [50],
[51], [149]. Theoretical studies predict a large enhance-ment of ZT inside quantum wires due to additional elect-
ron confinement (see Fig. 3). Experimentally, different
quantum wire deposition methods have been explored
[52]–[58]. However, so far, there are no experimental
results indicating any significant enhancement of thermo-
electric properties due to quantum wires. This is because
contacting individual wires and making accurate thermo
electric measurements is difficult. Some progresses havebeen made in this direction recently. Zhou et al. [159]
reported the measurement of temperature-dependant
thermal conductivity, four-probe resistance, Seebeck
coefficient, and ZT of individual bismuth telluride nano-
wires. Most recently, a new microfabricated device has
been developed by Mavrokefalos et al. [160] to measure
the thermoelectric properties and to characterize the
crystal structure and chemical composition using trans-mission electron micrograph and energy dispersive
spectral analysis of the same individual nanowire assem-
bled on the microdevice so as to establish the structure-
thermoelectric property relationship. In the case of nano-wire arrays, the whole structure has been embedded in an
alumina template or in a polymer. The difficulty of ensuring
good electrical contact to all wires in an array and quantum
wire size variations has impeded, so far, the quantitative
characterization of low-dimensional properties.
Quantum dot structures have been proposed as the
zero-dimensional (0-D) extension of the low-dimensional
thermoelectrics [42]. However, there is a funda-mental difference. The original theory developed by
Dresselhaus et al. [39] does not rigorously apply to quan-
tum dots. The enhanced power factor in quantum confined
2-D and 1-D structures happens in the direction perpen-
dicular to the confinement. Thus, we benefit from sharp
features in the DOS, but we can still use free electron
approximation with an effective mass in the direction
where electric field is applied and heat is transported.However, in the case of a matrix of quantum dots, elec-
trons have to move between the dots in order to transfer
heat from one location to another. If the electronic bands
in the dots are very narrow, then electrons are highly
confined and it is not easy to take them out of the dots. On
the other hand, it is easy to take electrons out of shallow
quantum dots but at the same time the density of elec-
tronic states in the dot will have broad features.Recent theoretical analysis by Humphrey et al. has
shown that the electronic efficiency for thermoelectric
cooling or power generation can approach the Carnot limit
if electron transport between the hot and the cold re-
servoirs happens in a narrow energy band under a finite
temperature gradient and a finite external voltage [59].
This is due to the reduction in electronic thermal con-
ductivity, e.g., the breakdown of the Wiedermann–Franzlaw that relates thermal and electrical conductivities. This
could be achieved with an appropriately designed embed-
ded quantum dot material having a graded composition or
dot sizes from the hot to the cold junctions. As we will see
in the next section, another significant benefit of quantum
dots can be in hot electron filtering [60], [61]. It is also
possible to have increased phonon scattering and reduced
thermal conductivity, further increasing the ZT of mate-rials with embedded nanoparticles. Recent experimental
results by Kim et al. show that room temperature thermal
conductivity of InGaAs with embedded ErAs semimetallic
nanoparticles can be reduced by a factor of two compared
to the bulk alloy [62]. ErAs particles 2–4 nm in diameter
can effectively scatter long wavelength phonons and re-
duce the lattice thermal conductivity of the alloy sub-
stantially. Since the underlying InGaAs matrix is of highcrystalline quality, electron mobility in these structures is
only slightly lower than pure InGaAs crystals [63].
B. Physics of Electron Transport in Solid-StateThermionic Devices
Heterostructure integrated thermionic (HIT) coolers
have been fabricated and characterized for applications in
1Even though this makes sense intuitively, there are no detailedcalculations of the effect of size nonuniformity on low-dimensionalthermoelectric properties.
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the integrated cooling of optoelectronic and electronicdevices [64]–[67]. The idea of thermionic energy conver-
sion was first seriously explored in the mid-1950s during
the development of vacuum diodes and triodes. A vacuum
diode thermionic refrigerator was proposed by Mahan
[68] in 1994. In the early to mid-1990s, several groups
pointed out the advantage of electron energy filters in
bulk thermoelectric materials [69]–[71], [150]. To over-
come the limitations of vacuum thermionics at lowertemperatures, thermionic emission cooling in hetero-
structures was proposed by Shakouri and Bowers [64]. In
these structures, a potential barrier is used for the
selective emission of hot electrons and the evaporative
cooling of the electron gas. The HIT cooler can be based
on a single-barrier or a multibarrier structure (see Fig. 4).
In a single-barrier structure in the ballistic transport re-
gime, which is strongly nonlinear, electric current isdominated by the supply of electrons in the cathode layer
and large cooling power densities exceeding kW/cm2 can
be achieved [64], [65]. In this design, it is necessary to use
a barrier several micrometers thick with an optimum
barrier height at the cathode, on the order of the thermal
energy of electrons kBT, where kB is Planck’s constant. A
large barrier height at the anode to reduce reverse current
is also needed [65].A few single-barrier InGaAs/InGaAsP/InGaAs thin-film
devices that were lattice matched to InP substrate were
fabricated and characterized [72]. The InGaAsP barrier
ð�gap �1.3 �mÞ was 1 �m thick and �100 meV high. Even
though cooling by 1 �C and cooling power density
exceeding 50 W/cm2 were achieved [72], [73], it was not
possible to increase the bias current substantially there by
Fig. 4. Hot electron filtering and thermionic emission in single-barrier and superlattice structures.
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1618 Proceedings of the IEEE | Vol. 94, No. 8, August 2006
fully benefiting from the large thermionic emission
cooling. This is due to nonideal metal–semiconductor
contact resistance and Joule heating in the substrate. The
single-barrier HIT device in a nonlinear transport regime
was not anticipated to have an improved energy con-version efficiency. High efficiency typically requires small
perturbations from equilibrium. Electrons that are bal-
listically emitted release all their excess energy in the
anode and produce significant heating. The main motiva-
tion of the original study was to do temperature stabili-
zation of optoelectronic devices with monolithic structures
[67], [74].
In 1998 Mahan and Woods proposed to use thermionicemissions in multilayer structures in a linear transport
regime. They estimated an increase in the figure-of-merit
ZT by a factor of two [75]. Based on this idea, a few struc-
tures were synthesized by Kim et al.; however, due to the
poor material quality no improvement was reported [76].
Later calculations by Radtke et al. [77] showed that, in thelinear transport regime, the thermoelectric power factor in
multilayer thermionic devices is smaller than that of a
thermoelectric one; thus, the main advantage of super-
lattices is in the reduction of phonon thermal conductivity.
Mahan and Vining in a subsequent publication reached the
same conclusion [78]. This analysis was also based on
linearized ballistic transport over symmetric barriers.
In contrast to the previous publications, Shakouri et al.in 1999 proposed that tall barrier, highly degenerate
Fig. 5. Transmission electron micrograph of 3-�m-thick 200 � ð5 nm Si0:7Ge0:3=10 nm SiÞ superlattice grown symmetrically strained on a buffer
layer designed so that the in-plane lattice constant was approximately that of relaxed Si0:9Ge0:1. The n-type doping level (Sb) is 2 � 1019 cm�3.
The relaxed buffer layer has a ten-layer structure, alternating between 150-nm Si0:9Ge0:1 and 50-nm Si0:845Ge0:150C0:005. 0.3�m Si0:9Ge0:1 cap layer
was grown with a high doping to get a good ohmic contact.
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superlattice structures can achieve thermoelectric powerfactors (the square of the Seebeck coefficient times the
electrical conductivity) an order of magnitude higher than
bulk values [79]. In this analysis no assumption about
ballistic transport was made. The improvement was solely
due to the filtering of hot electrons in a highly degenerate
sample. For a multibarrier structure at small biases, one
can define an effective Seebeck coefficient and electrical
conductivity [80], [81]. In the linear transport regime,calculations based on effective thermoelectric materials or
based on solid-state thermionics will converge represent-
ing two points of view for the same electron transport
phenomena in superlattices. One can describe the effect of
potential barriers as a means to increase the thermoelec-
tric power factor.
Recently the theoretical analysis of electric and
thermoelectric transport perpendicular to the superlatticedirection has been expanded [80]–[82]. It is shown that
highly degenerate semiconductors and metallic-based
superlattices in the quasi-linear transport regime have
the potential to achieve thermoelectric power factors
significantly larger than bulk values. Assuming a lattice
contribution to thermal conductivity on the order of
1 W/mK, ZT values exceeding 5–6 are predicted. The
key requirement is nonconservation of lateral momentumduring the thermionic emission process. Basically, planar
barriers are only effective to filter out hot electrons movingwith large kinetic energy perpendicular to the barrier.
Many of the hot electrons with large in-plane kinetic
energy can not be selectively emitted. Nonconservation of
lateral momentum will allow a much larger number of hot
electrons to participate in the conduction process. This
could be achieved using nonplanar barriers or embedded
nanoparticles [40], [83]. It is important to note that the
role of nanoparticles in this case is quite different fromlow-dimensional thermoelectrics. Discrete energy states
are not directly used. Quantum dots act as 3-D scattering
centers and energy filters for electrons moving in the
material. Novel metallic-based superlattices with embed-
ded nano particles are synthesized by molecular beam
epitaxy (MBE) and by pulsed laser deposition systems.
These techniques allow a precise layer by layer growth
with a growth rate of 0.1–2 �m per hour. Large-scaleMBE growth of GaAs chips for cell phones and laser
diodes for compact disc applications have been demon-
strated [84], [151]. The epitaxial growth is done sim-
ultaneously on five to six wafers each 2–4 in in diameter.
Once the research phase is completed and electronic and
thermal properties of nanostructured materials opti-
mized, other techniques such as chemical vapor deposi-
tion could also be used for larger scale production ofmicrorefrigerators.
Fig. 6. Diagram showing current flow and heat exchange at various junctions in a single-element microrefrigerator.
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1620 Proceedings of the IEEE | Vol. 94, No. 8, August 2006
IV. HETEROSTRUCTURE INTEGRATEDTHERMIONIC MICROREFRIGERATORSON A CHIP
Using the idea of heterostructure electron energy filtering,
thin-film coolers based on various materials have been
fabricated and characterized. InGaAsP/InP [67], [72], [85],
and InGaAs/InP [86], were grown with metal–organic
chemical vapor deposition (MOCVD), and InGaAs/InAlAs[87], InGaAsSb/InGaAs [88], SiGe/Si [89], [90], and
SiGeC/Si [66]) were grown with MBE. These structures
were lattice matched to either InP or silicon substrates to
ease their monolithic integration. Si-based heterostruc-
tures are particularly useful for monolithic integration
with silicon-based electronics. The basic idea was to use a
band offset between the different layers as a hot carrier
filter. The superlattice structure has also the potential toreduce the lattice thermal conductivity. Different su-
perlattice periods (5–30 nm), dopings (1 � 1015–
7 � 1019 cm�3), and thicknesses (1–7 �m) were analyzed.
A typical SiGe/Si microrefrigerator shown in Fig. 5
consists of a 3-�m-thick superlattice layer with a
200 � ð3-nm Si=12-nm Si0:75Ge0:25Þ structure doped to
5e19 cm�3, a 1-�m Si0:8Ge0:2 buffer layer with the same
doping concentration as the superlattice, and a 0.3-�m
Si0:8Ge0:2 cap layer with doping concentration of
1.9e20 cm�3. Various microrefrigerator devices were fab-
ricated using standard thin-film processing technology
(photolithography, wet and dry etching, and metalliza-
tion). In the single-leg microcooler geometry, a gold or
aluminum metal contact was used to send current to the
cold side of the device (Fig. 6). The Joule heating and heat
conduction in this metal layer had a strong impact on the
overall cooler performance. An electrical contact on the
backside of the silicon substrate, or on the front surface
far away from the device, was used as the second elec-
trode. Thus, 3-D heat and current spreading in the
substrate helped the localized cooling of the device. Fig. 7
shows a scanning electron micrograph of thin-film coolers
of the various sizes (40 � 40–150 � 150 �m2). Fig. 8
illustrates typical cooling curves (maximum cooling below
ambient versus supplied current) for 60 � 60 �m2
microrefrigerators. For comparison, results for identical
devices based on bulk silicon and two different super-
lattice periods are shown [90], [91]. Bulk Peltier effect in
Fig. 7. Scanning electron micrograph of microrefrigerators on a chip. Device size ranges from 40 � 40 up to 150 � 150 �m2.
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silicon can produce G 1 �C cooling while superlattice
structures can increase the performance to 9 4 �C. By
increasing the current thermoelectric/thermionic cooling
increases linearly but at some point Joule heating, which
is proportional to the square of the current, dominates and
the net cooling is reduced. Fig. 9 shows the experimental
and theoretical cooling for different size microrefrigera-
tors. Calculations are based on commercial finite element3-D electrothermal simulations in which thermoelectric
cooling and heating with an effective Seebeck coefficient
was added [92]. Fig. 10 shows the calculated temperature
distribution of a 60 � 60 �m2 device at its maximum
cooling at room temperature. Fig. 11 shows the thermal
image of a microrefrigerator under operation. One can see
uniform cooling on top of the device. No significant
temperature rise on the metal contact layer adjacent to thedevice can be seen. A ring of localized heating around the
device is attributed to the Joule heating in the buffer layer
beneath the superlattice [93].
In Fig. 9 we can see that due to nonideal effects (Joule
heating in the substrate, at the metal–semiconductor
junction, and in the top metal contact layer), there is an
optimum device size on the order of 50–70 �m in
diameter that achieves maximum cooling [94], [95], [152].
This is due to the fact that various parameters scale
differently with the device size. For example, both of the
substrate’s 3-D thermal and electrical resistances scale asthe square root of the device area, while the Joule heating
from the metal–semiconductor contact resistance scales
directly proportional to it [93]–[95], [152]. Cooling tem-
perature in these miniature refrigerators was measured
using two techniques. First, a small �25–50-�m-diameter
type E thermocouple is placed on top of the device and
another thermocouple is placed farther away, on the heat
sink. Even though the thermocouple had the samediameter as the refrigerator, accurate temperature mea-
surements with �0.01 �C resolution was achieved on
devices with diameter larger than 50–60 �m. We also used
Fig. 8. Cooling versus supplied current for bulk silicon microrefrigerator and for 3-�m-thick superlattice devices with
two different superlattice periods. Device size is 60 � 60 �m2.
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an integrated thin-film resistor sensor on top of the
microcooler. To electrically isolate the thin-film resistor, a
0.1–0.3-�m-thick SiN layer was deposited on the top
electrode of the microrefrigerator. The resistance versus
temperature was calibrated on a variable temperature
heating stage and this was used to measure cooling on top
of the device. A resistor could also be used as heat load
directly on top of the device if a large current is applied
Fig. 9. Theoretical and experimental cooling versus supplied current for different microrefrigerator sizes. Microcooler devices consist of a 3-�m-
thick superlattice layer with the structure of 200 � ð3-nm Si=12-nm Si0:75Ge0:25Þ and doping concentration of 5e19 cm�3, a 1-�m Si0:8Ge0:2 buffer
layer with the same doping concentration as the superlattice; and a 0.3-�m Si0:8Ge0:2 cap layer with doping concentration of 1.9e20 cm�3.
Fig. 10. 3-D electrothermal simulation showing temperature distribution in the SiGe microrefrigerator under bias.
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(see Fig. 12 inset). The experimental results showed in
Fig. 12 illustrate the cooling temperature of a 40 � 40 �m
square microrefrigerator device as a function of heat load
density. During these measurements, we heat the heater
using a constant current; at the same time we also measurethe cooling of the microrefrigerators using a thermocouple
or the resistance value of the heater. By increasing the
constant current to the heaters, more heat load was added
on top of the refrigerators, and the cooling �T was
decreased. The maximum cooling power density of the
device was defined as the maximum heat flux per area that
device could absorb when �T ¼ 0. The maximum cooling
power density for different microrefrigerator with a devicesizes 40 � 40–100 � 100 �m2 is 600–120 W/cm2 as
indicated in Fig. 13. Maximum cooling values at zero heat
load shown in Fig. 13 are smaller than the ones presented
in Fig. 9. Placing resistive heaters on top of the
superlattice introduces parasitic heat conduction paths to
the substrate that reduce the maximum cooling of the
micro refrigerator.
It is interesting to note that contrary to the maximumcooling temperature results, the smallest samples (�30–
40 �m in diameter) had the largest cooling power densities
[96]. This was explained using theoretical models. It is due
to the fact that certain parasitic mechanisms, e.g., heat
conduction from the heat sink to the cold junction through
the metal contact layer, will reduce maximum cooling
below the ambient temperature, but, in fact, this can
improve the cooling power density of the microrefrigeratorby creating additional paths for heat spreading.
Attaching a metal contact directly to the cold surface of
the microcooler is a source of parasitic joule heating and
heat leak to the sink. This limits the maximum cooling of
the device by 10%–30% [95], [161]. However, fabrication
process of these single-leg devices is much simpler than
the conventional thermoelectric coolers where an array of
n-type and p-type semiconductors are used electrically in
series and thermally in parallel. The cooling power density
is only a function of the element leg length and it is
independent of the number of elements. The main reasonfor choosing array structures is that they benefit from
reduced heat loss in the metal leads, which stems from the
trade off between operation current and voltage. If the goal
is to remove a small hot spot, a single-element thermo-
electric cooler is much easier to integrate on top of a chip.
The ZT of bulk SiGe is about ten times smaller than
BiTe at room temperature. III-V semiconductors have also
a very low ZT of about 0.01–0.05 [57], [97]. The main useof the HIT coolers mentioned above is not to achieve high
efficiencies in order to cool big macroscopic size chips.
The key idea is to selectively cool small regions of the chip
removing hot spots locally. If a small fraction of the chip
power is dissipated in localized regions, low thermoelec-
tric efficiency is not the most important factor. It is more
critical to incorporate small-size refrigerators with high
cooling power density and with minimum additionalthermal resistances inside the chip package.
When comparing HIT microcoolers with bulk thermo-
electric modules, there are three primary advantages. First
of all, both microsize and standard microprocessor
fabrication methods make HIT refrigerators suitable for
monolithic integration inside IC chips. It is possible to put
the refrigerator near the device and cool the hot spot
directly. The 3-D geometry of a device with a small-sizecold junction and large-size hot junction allows heat
spreading from the small hot region to the heat sink [94],
[152]. Second, the high cooling power density surpasses
that of commercial bulk TE refrigerators. In fact, the
directly measured cooling power density, a figure exceed-
ing 680 W/cm2 [96], is one of the highest numbers
Fig. 11. Thermal image of a 50 � 50 �m2 microrefrigerator at an applied current of 500 mA. Stage temperature is 30 �C and
the device is cycled at a frequency of �1 kHz.
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reported so far and it is similar to the best values achieved
by thin-film BiTe/PbTe superlattice coolers having a
ZT �2.4 [42]. Third, the transient response of the currentSiGe/Si superlattice refrigerator is several orders of
magnitude better than the bulk TE refrigerators. This is
due to their small thermal mass. The standard commercial
TE refrigerator has a response on the order of tens of
seconds. The measured transient response of a typical HIT
superlattice sample is on the order of �20-40 �s, again
very similar to BiTe/PbTe superlattices (see Fig. 14, [98],
[99], and [153]). Thus, microcoolers could be used toremove dynamic hot spots in the chip.
According to the theoretical simulation, the current
limitation of the superlattice coolers comes from the con-
tact resistance at the metal/semiconductor interface and
the resistance of the buffer layer, which are on the order of
10�6 �cm2. Detailed modeling predicts that 15 �C–20 �C
of cooling with a cooling power density exceeding several
thousand W/cm2 is possible with optimized SiGe super-lattice structures [94], [95], [100], [152].
A. SiGe and SiGeC Superlattice OptimizationMicrorefrigerators based on superlattices of Si1�xGex=Si
[89], [90], Si1�xGex=Si1�yGey [101], and Si/Ge [101] have
been demonstrated. Since the lattice constant of Si1�xGex
ðx 9 0:1Þ is substantially different from silicon substrate, a
graded buffer layer was used in order to gradually changethe lattice constant to that of the average value of the two
superlattice layers. This buffer layer, which is �1–2 �m
thick, can accommodate lots of dislocations and it allows
growth of very high quality 3–5-�m-thick superlattice on
top of it. Maximum cooling of 4.5 �C at room temperature,
Fig. 12. The maximum cooling temperature versus heat load. Inset shows the fabricated thin-film heater on top of
the SiGe superlattice microrefrigerator.
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7 �C at 100 �C [90], [101], and 14 �C at 250 �C have been
demonstrated [102]. Detailed thermal imaging of thesestructures have shown that Joule heating in the buffer layer
is one of the key nonideal effects that limit the maximum
performance [14], [93], [95]. In addition, since the average
lattice constant of the superlattice corresponds to SiGe
alloy with x � 0.1–0.2, only electronic devices based on
SiGe could be monolithically integrated on top of these
refrigerators.
The addition of 1%–2% carbon to SiGe can decreaseits lattice constant and make it matched to that of
silicon. High-quality 3-�m-thick SiGeC/Si superlattices
have been grown without any buffer layer (see Fig. 15).
Room temperature cooling was lower, about 2.5 �C for
60 � 60 �m square device [66]. However, the cooling
performance increased substantially with temperature and
7 �C cooling at 100 �C ambient temperature was similar to
the best SiGe/Si superlattice devices (see Fig. 16).
An important question is: what is the role of the
superlattice and its effect on the thermoelectric figure-of-merit ZT? Superlattice structures could lower lattice
thermal conductivity and increase the thermoelectric power
factor (Seebeck coefficient square times electrical conduc-
tivity). Huxtable et al. characterized the thermal conduc-
tivity of various SiGe superlattices [103], [154]. The 3!technique was used to measure the thin-film thermal
conductivity in the direction perpendicular to super-
lattice plane [104]. Thermal conductivity scaled almostlinearly with interface density and approached that of
the alloy SiGe, but was never lower than that of the
alloy (�8–9 W/mK). With a larger difference in the
germanium content of the layers, e.g., with Si0:2Ge0:8=Si0:8Ge0:2 and Si/Ge, a larger acoustic impedance mismatch
could be achieved. This resulted in lattice thermal conduc-
tivity lower than that of the alloy (�3 W/mK) [103], [154].
However, there were large amounts of dislocations in the
Fig. 13. The maximum cooling power density at zero net cooling (solid circles) and the maximum cooling temperature at zero heat load (open
squares) versus device size for the SiGe superlattice microrefrigerator (see Fan [101] and Zeng et al. [96]).
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3-�m-thick sample that reduced the electrical conductivity.
Microrefrigerator devices based on this material with low
thermal conductivity did not show substantial cooling (only
�1 �C), thus a good crystalline quality of the material isessential for high thermoelectric performance [101].
In order to characterize the electron filtering (effective
Seebeck coefficient) of SiGe superlattices, test structures
were fabricated that included thin-film heaters on top of
the device. This is similar to the structures used for cooling
power density characterization. This thin-film heater
could create a temperature difference across the super-
lattice and the substrate. By measuring the resultingthermovoltage, the combined Seebeck coefficients of the
thin film (perpendicular to the layers) and the substrate
could be obtained [105]. Using a reference based on a
similar test structure on the substrate, the superlattice
Seebeck coefficient could be deduced. Measurement of
electrical conductivity of the superlattice perpendicular to
the layers is more difficult; no reliable measurements have
been presented to date for highly conductive materialwhich is typically used in thermoelectric applications.
Full microrefrigerators devices based on bulk thin-film
SiGe alloy and based on SiGe/Si superlattice were
fabricated and their cooling characterized. Similar metal-
lization and device geometry was used in order tofacilitate the comparison between material properties
(see Table 1). Room temperature cooling of the super-
lattice was about 5% larger than the bulk alloy film [106].
Given the fact that the thermal conductivity of the alloy
was 30% lower than the superlattice (measured indepen-
dently using the 3! technique), we anticipate that the hot
electron filtering in the superlattice had increased the
thermoelectric power factor by �37%. This shows thatunless techniques for suppressing the lattice thermal
conductivity of SiGe superlattices below that of alloys are
found (without degradation in the electrical perfor-
mance), the SiGe alloy films have good cooling perfor-
mance compared to superlattices and they may be easier
to grow and integrate on top of silicon chips.
Recently, the transient Harman technique has been
applied to measure the ZT of the thin film directly [42],[107], [108]. An electrical pulse is applied to the
Fig. 14. Microrefrigerator’s cooling response as a function of frequency for different device sizes (see Dilhaire et al. [93]).
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thermoelectric device. This current pulse creates thermo-
electric cooling and heating at the junctions and Joule
heating in the bulk of the material. Subsequently, a
temperature difference develops across the thin film. As
the electrical pulse is turned off, the voltage across the
device is monitored. Ohmic voltage drops almost instan-
taneously (in subpicosecond time scale) while the
thermoelectric voltage disappears with the time scale ofheat diffusion in the device (10 ns–10 �s for thin films). If
the device is under the adiabatic conditions (heat flow
from the hot to the cold junction through the contact leads
could be neglected), one can obtain the ZT of the device by
comparing the thermoelectric voltage pulses when the
polarity of the current changes. Joule heating in the
material is independent of current direction while Peltier
cooling or heating at interfaces depend on the currentdirection [108]. Using this technique, the ZT of BiTe [42]
and ErAs : InGaAs/InGaAlAs [109] superlattices have
been measured. This has not been applied to SiGe
superlattices. It is hoped that with the use of identical
devices with different superlattice thicknesses and with
reference structures, ZT at various temperatures could be
obtained. This can help to further optimize SiGe micro-
refrigerators.
B. Microrefrigerators in a Packaged IC ChipSo far, we have described the cooling performance of
microrefrigerators without considering the package effect.
In real packaged ICs, the thermal resistance of the heat
sink and that of the thermal interface material can
significantly affect the cooling performance of microre-
frigerators. To study this, an electrothermal model was
developed to calculate the hot spot temperature with and
without a microrefrigerator in a packaged IC [110], [111].In this calculation, the superlattice thickness and its
operation current are optimized in order to minimize the
Fig. 15. Transmission electron micrograph of Si0:89Ge0:1C0:01=Si superlattice structure grown directly on silicon substrate (see Fan et al. [66]).
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1628 Proceedings of the IEEE | Vol. 94, No. 8, August 2006
hot spot temperature. We assumed a 50 � 50 �m2 SiGe/Si
superlattice microrefrigerator was fabricated at the center
of the silicon substrate ð1 mm � 1 mm � 500 �mÞ. A
package thermal resistance of 6 � 10�5 m2K/W is as-
sumed. On top of the microrefrigerator the same size hot
spot is placed. Heat flux at the hotspot is assumed to be ten
times larger than the background heating applied every-
where else on the chip. The material parameters ofSi/SiGe superlattice and Si substrate used for the cal-
culation are listed in Table 1. The contact resistance be-
tween metal and semiconductor is assumed to be
10�6 �cm2. Fig. 17 shows the relationships between hot
spot heat flux Qh and the hot spot temperature Thotspot for
the model with and without a microrefrigerator. As it can
be seen from the graph, the superlattice microrefrigerator
is able to lower the Thotspot value below what was obtainedfrom the model without a microrefrigerator (standard IC
package), although the effectiveness of thin-film micro-
refrigerator is reduced as Qh increases. By embedding the
thin-film superlattice in a packaged IC, a 7.5 �C reduction
in hot spot temperature can be achieved at a heat flux
Qh ¼ 300 W/cm2. The optimum superlattice thickness for
cooling is �10 �m. The microrefrigerator will consume a
power of 30 mW compared to the power dissipation in the
whole chip of �300 mW.
For most thermoelectric applications, a higher ZT
translates directly to either a larger cooling temperaturedifferences ð�TÞ or a higher cooling efficiency. As shown
in the equation for Z, it is possible to change it by con-
trolling three material properties: �, S and �. To under-
stand how each parameter affects the cooling performance,
when one parameter is varied to increase Z, the other two
parameters are kept constant. Fig. 18 shows the predicted
cooling performance of microrefrigerators with various ZT
values (T ¼ 300 K, room temperature). For the purpose ofcomparison, the plot for the microrefrigerator with
ZT ¼ 0:125 (a value which should be possible with SiGe/Si
superlattices) is shown in the same graph. A large
Fig. 16. Cooling versus current at different ambient temperatures for Si0:89Ge0:1C0:01=Si superlattice microrefrigerators.
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reduction in hot spot temperature can be seen when ZT isimproved. We can see that the effect of decreasing thermal
conductivity or increasing electrical conductivity on
Thotspot is identical, but the effect of increasing Seebeck
coefficient is much larger. This result indicates that the
Seebeck coefficient of thin-film materials is a more im-
portant factor to maximize the cooling performance for a
3-D superlattice microrefrigerator in a packaged chip
[112]. It can be seen that with moderate improvement inmaterial properties (i.e. a ZT � 0.6), hot spots in tens of
micrometers in diameter with heat fluxes in excess of
1000 W/cm2 could be cooled down by 20 �C–30 �C.
C. Active Coolers Embedded Inside the SubstrateAs we have seen in the previous section, the optimum
thickness of SiGe microrefrigerators in a packaged IC is on
the order of 10 �m. In the short term, for conventional
silicon complementary metal–oxide–semiconductor
(CMOS) circuits, it is quite challenging to include such
thick SiGe layers in a processing which is optimized tomake hundreds of millions of nanoscale silicon transistors
on a chip. The main application could be in future high-
performance nanoelectronic chips or in optoelectronic ICs
for the temperature stabilization of individual elements.
On the other hand, it is possible to use buried microcoolers
inside the substrate as a smart heat sink. One can bond a
microrefrigerator chip at the back of silicon substrate
[113], [155]. For example, gold–gold fusion bonding can beused, which has very low thermal interface resistance.
Since the two chips are made from the same siliconmaterial, there are no issues due to the thermal expansion
coefficient mismatch. In such two-chip configurations, the
embedded microcoolers inside the composite substrate
provide a means to actively control the temperature of the
hot spots. Initial results showed only a cooling of 0.4 �C at
the hot spot with cooling power densities of 20–40 W/cm2
[114]. The problem is due to the high thermal conductivity
of silicon and even with 50-�m-thick top silicon IC, thecooling of the embedded refrigerator could not be
localized at the hot spot. A trenched structure inside the
silicon substrate was used to improve the localize cooling,
and 1.7 �C cooling with cooling power density of
�110 W/cm2 was demonstrated for a hot spot of
130 � 130 �m2 [115].
D. Bulk Silicon 3-D MicrocoolersIf large cooling temperature is not required, micro-
coolers placed directly on bulk silicon substrates could
provide cooling on the order of 1 �C [116], [117]. This usesthe inherent Seebeck coefficient of silicon. Silicon ZT is
very low �0.01, but the thermoelectric power factor of
silicon (Seebeck coefficient square times electrical con-
ductivity) is comparable to that of best thermoelectric
materials such as BiTe. The thermoelectric power factor
determines the capacity of electron gas to absorb thermal
energy from one contact and move it to the other one. In
addition, the unique asymmetric geometry of microrefri-gerator device with a small area cold junction and a large
Table 1 Material Parameters for BiTe Alloy, p-Type Silicon, SiGe Alloys and Si/SiGe Superlattices. Maximum Cooling Temperature of Microrefrigerator
Devices Based on Some of the Material Is Also Given. Typical Microrefrigerator Device Size is 60 � 60 �m square and Alloy or Thin-Film Thickness Is
�3 �m. ðkÞ Refers to In-Plane Material Properties and ð?Þ Refers to Cross-Plane Material Properties. The Estimated Cross-Plane Power Factors and ZTs
for Superlattices are Based on the Measured Maximum Cooling of Microrefrigerators and the Comparison With Identical Thin-Film Devices Based on
Alloy Material
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1630 Proceedings of the IEEE | Vol. 94, No. 8, August 2006
area hot junction allows 3-D heat and current spreading in
the substrate. This can result in large cooling power
densities exceeding 300 W/cm2 (see Fig. 19). In making a
bulk microcooler, we need to define a small metallic
electrode on top of the substrate. It is quite helpful to
ensure that the current flows perpendicular to themetal/semiconductor interface; i.e., a small mesa with
the height of 0.2–0.5 �m should be defined at the cold
side. Peltier cooling is proportional to the flux of elec-
trons going through the interface. If there is a component
of the current moving in the plane of the interface, it will
create additional Joule heating without any benefit for
cooling. We thus used dry etching to make 0.2–0.5-�m
mesas even with bulk silicon microcoolers.If one wants to make devices that use the heat pumping
capability of the electron gas, there are some metals such
as Co and Ni and some alloys that have a thermoelectric
power factor twice larger than BiTe [118]. Such metal-
based devices could be helpful for waste heat recovery
(generate electricity from temperature differences) or in
3-D microrefrigerator configuration (small cold side and
large hot side). One should note that in 1-D device
geometry, thermoelectric heat pumping is not very
effective. In configurations where the cold side of the
thermoelectric device is hotter than the hot side (due tolarge heat load), a high lattice thermal conductivity
material is much more important than a good electron
heat pumping. Peltier cooling could improve the perfor-
mance of 1-D heat pumps (with large thermal conductiv-
ity) by only a couple of degrees.
E. Recent Advances in Nonsilicon MicroscaleThermoelectric Refrigerators
During the last couple of years, significant advances in
thin-film thermoelectric coolers have been demonstrated
at various research laboratories. Venkatasubramanian et al.at Research Triangle Institute have demonstrated 3–5-�m-
thick, 100-�m-diameter BiTe/PbTe superlattice coolers
Fig. 17. Hot spot temperature for packaged IC chip with and without SiGe microrefrigerator. For comparison the effect of replacing silicon
substrate entirely with copper is shown (see Fukutani et al. [110]).
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with maximum cooling of �30 �C and cooling power
density exceeding 500 W/cm2 (this cooling power densityis an estimated value and not directly measured) [42].
These values have been achieved with the use of electron
transmitting, phonon blocking superlattices. Ultralow
metal/semiconductor contact resistance on the order of
10�8 �cm2 has been obtained. In addition, the thin-film
device was mounted on 10-�m-thick metal on top of the
silicon substrate in order to improve heat spreading at the
hot junction. A variable thickness transient Harman tech-nique was used to estimate the thermoelectric figure-of-
merit. ZT values on the order of 2.4 for p-type devices have
been obtained at room temperature. Bottner et al. at
Fraunhofer Institute have been working on the monolithic
integration of conventional BiTe and BiSbTe bulk materi-
als on a silicon substrate [119]. They have been able to
deposit 20-�m-thick legs using sputtering and IC fab-
rication techniques to produce coolers on large scales (on4-in silicon wafers). They have demonstrated a maximum
cooling of �35–45 �C with a 3 p- and n-leg for a current of
�1 A. The estimated cooling power density is �100 W/cm2.Uttam Ghoshal et al. demonstrated improved thermoelectric
performance with bulk p-type Bi0:5Sb1:5Te3 and n-type
Bi2Te2:9Se0:1 material systems with the use of sharp
nanometer-size point contacts at the cathode electrode.
The mechanism for improvement is not yet known but a
cooling enhancement by about a factor of two at low current
values compared to the bulk modules has been achieved
[120]. Snyder, Fleurial et al. at the NASA Jet PropulsionLaboratory have used an electrochemical deposition tech-
nique to form thousands of n- and p-type ðBi; SbÞ2Te3 legs
with a diameter of 60 �m and a thickness of 20 �m.
Maximum cooling on the order of 2 �C has been measured
[121]. Even though electrochemical deposition is very cheap
and that the JPL group has been able to grow thousands of n-
and p-legs directly on top of the array of electrode contacts,
it seems that the material quality is not very good and themaximum cooling is quite low.
Fig. 18. The effect of the improvement in material properties on the hot spot cooling. In each case the thin-film thickness and the
microrefrigerator device operation current are optimized for maximum cooling (see Fukutani et al. [110]).
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F. Prospect of Bulk Thermoelectric Materials forChip Cooling
Since the early 1990s, there has been a lot work in the
area of bulk thermoelectric materials such as skutterudites,
clathrates, half-hausler materials, oxides, etc. [122], [123].
Even though thin-film deposition techniques are not used,
the main idea is to engineer nanoscale atomic properties to
have a material with good electrical conductivity and low
thermal conductivity. This is also called electron crystal
phonon glass material following the pioneering work ofSlack [38], [124], [148]. For example, the concept of a
heavy rattler atom in a cage of covalently bonded crystal is
used to scatter dominant phonon modes in heat conduc-
tion but ensure good electrical conductivity for electrons.
High ZT values on the order of 1.5–2 at high temperatures
9 500 K have been achieved [124]. The performance of
thermoelectric coolers for cryogenic applications has also
been improved. ZT �0.8 at 225 K is obtained for CsBi4Te6
material [125]. Kanatzitis et al. have demonstrated
ZT 9 1:5 at 500 K with AgPbSbTe material [44]. Most of
the developments today are for high temperature powergeneration applications. When a suitable material for room
temperature is identified, it is possible to use similar bulk
growth techniques for IC chip cooling. A potential
candidate could be HgCdTe material, which has a very
low thermal conductivity at room temperature and at
cryogenic temperatures. The thermoelectric power factor
is also low due to very small electron effective mass.
However, it has recently been suggested tall barrier super-lattices based on HgxCd1�xTe=HgyCd1�yTe can benefit
from hot electron filtering and achieve ZT 9 3 both at
room temperature and at cryogenic temperatures [126].
V. PROSPECT OF VACUUM THERMIONICEMISSION FOR CHIP COOLING
Thermionic energy conversion is based on the idea that ahigh-work-function cathode in contact with a heat source
Fig. 19. The maximum cooling power density at zero net cooling (solid circles) and the maximum cooling temperature at zero heat load (open
squares) versus device size for bulk silicon microrefrigerators (see Zhang et al. [117] and Fan [101]). The bulk silicon is p-type boron doped at a
doping concentration of 1019 cm�3; its resistivity is �0.001� 0.006 �cm.
Shakouri: Nanoscale Thermal Transport and Microrefrigerators on a Chip
Vol. 94, No. 8, August 2006 | Proceedings of the IEEE 1633
will emit electrons [127]. These electrons are absorbed bya cold, low-work-function anode separated by a vacuum
gap. They can flow back to the cathode through an
external load where they do useful work. A vacuum is the
best electrical conductor (electrons do not have any
collisions in the gap) and the worst thermal conductor,
since there are no atoms to transmit random vibrations
and heat is only transported via radiation. Practical
vacuum thermionic generators are, however, limited bythe work function of available metals or other materials
that are used for cathodes. Another important limitation
is caused by the space charge effect. The presence of
charged electrons in the otherwise neutral space between
the cathode and anode will create an extra potential
barrier between the cathode and anode, which reduces
the thermionic current. The materials currently used for
cathodes have work functions 9 0.7 eV, which limits thegenerator applications to high temperatures 9 500 K.
Mahan [68] proposed these vacuum diodes for thermionic
refrigeration. Basically, the same vacuum diodes that are
used for the generators will work as a cooler on the
cathode side and a heat pump on the anode side under an
applied bias. Mahan predicted efficiencies of over 80% of
the Carnot value, but still these refrigerators only work at
high temperatures (9 500 K). There has been recentresearch to make efficient thermionic refrigerators at room
temperature with the use of nanometers-thick vacuum
gaps [128], [129]. This is sometimes called thermotunnel-
ing. This idea is based on the fact that electron tunneling
increases exponentially as a function of barrier thickness.
Use of G 5–10-nm barriers will allow conventional metal
electrodes to achieve appreciable emission currents
(hundreds of A/cm2) and cooling power densities(hundreds of W/cm2) at room temperature. There have
been detailed theoretical studies and some preliminary
experimental results [129]; however, the measured cooling
is very small (0.3 mK). The main difficulty to achieve
substantial cooling is to produce uniform nanometer size
vacuum gaps over large areas. In addition, this narrow
gap should be maintained as temperature difference
develops and cathode and anode undergo thermalexpansion and mechanical stress. In another approach,
sometimes called the inverse Nottingham effect, resonant
tunneling at an appropriately engineered cathode band
structure has been proposed to enhance vacuum emission
currents [130], [131]. Use of enhanced field emissions at
nanostructured surfaces, such as CNTs or sharp tips, has
also been investigated theoretically and experimentally
[132], [133], [156]. While significantly increased vacuumcurrents have been obtained [134], [135], there are no
experimental results on refrigeration near room temper-
ature. An important problem with CNTs field emitters is
that we do not have yet direct control of the nanotubes
chirality, i.e., its electrical conductivity, thus both
metallic and semiconducting nanotubes are grown at
the same time. It is also important to note that the
Bselective[ emission of hot electrons (energies higherthan the Fermi level) compared to cold electrons
(energies lower than the Fermi level) is necessary in
order to achieve refrigeration. Since at room temperature
the energy distribution of electrons inside the Fermi
window is on the order of 25–50 meV, a precise
engineering of tunneling is necessary to achieve appre-
ciable energy conversion. Recently, Koeck et al. have
demonstrated vacuum power generation with a nanos-tructured nitrogen-doped diamond emitter separated by
�80-�m gap from the collector. At a cathode tempera-
ture of 825 �C, substantially below conventional vacuum
thermionic modules, 120-mV thermo voltage was gener-
ated [136]–[138], [157]. It is anticipated that vacuum
thermionic emitters could be useful for high-temperature
power generation. However, applications to cooling at
room temperature will probably not be available anytime soon.
An interesting question is raised by Fig. 4, which
displays cooling by thermionic emission: is it necessary to
have a hot junction at the anode side of the device? By
bandgap engineering and appropriate doping, it should be
possible to enhance interaction of electrons with, for
example, photons, so that hot carriers at the anode side
loose their energy by emitting light rather than heatingthe lattice. This does not violate the second law of
thermodynamics, since light emission could be inco-
herent and the total entropy of the electron and photon
system is still increasing. The light emission could occur
in a conventional pn junction or in a more elaborated
unipolar quantum cascade laser configuration [139].
Calculation by Pipe et al. showed that semiconductor
laser structures could be designed to have heterostructureenergy filtering near the active region [140]. This can
provide internal cooling by hundreds of W/cm2 under
typical operating conditions. This method of cooling can
be viewed as electrically pumped version of the con-
ventional laser cooling which have been used for atom
trapping and recently for cooling of macroscopic
objects [141].
VI. SUMMARY
An overview of recent advances in nanoscale thermal
transport and in solid-state and vacuum thermionic devices
was given. The main emphasis was how key physical
mechanisms and nanoscale material engineering change
bulk heat conduction and improve the efficiency and
maximum cooling of microrefrigerator devices.
Acknowledgment
The experimental and theoretical data presented in
Fig. 5–19 are the results of the work of outstanding
students and postdocs: C. Labounty, X. Fan, G. Zeng,
D. Vashaee, J. Christofferson, Y. Zhang, Z. Bian,
Shakouri: Nanoscale Thermal Transport and Microrefrigerators on a Chip
1634 Proceedings of the IEEE | Vol. 94, No. 8, August 2006
K. Fukutani, R. Singh, A. Fitting, Y. Ezzahri, andS. Huxtable. The author would like to acknowledge
a very fruitful collaboration with Profs. J. Bowers,
A. Gossard, S. Stemmer (UCSB), A. Majumdar,
P. Yang (Berkeley), V. Narayanamurti (Harvard),
R. Ram (MIT), T. Sands (Purdue), B. Nemanich, B. Davis,Z. Sitar, G. Bilbro (NCSU), A. Bar-Cohen (Maryland),
S. Dilhaire (Univ. Bordeaux), L. Shi (Univ. Texas),
K. Pipe (Univ. Michigan), and Dr. E. Croke (HRL
Laboratories LLC).
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Shakouri: Nanoscale Thermal Transport and Microrefrigerators on a Chip
1636 Proceedings of the IEEE | Vol. 94, No. 8, August 2006
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Shakouri: Nanoscale Thermal Transport and Microrefrigerators on a Chip
Vol. 94, No. 8, August 2006 | Proceedings of the IEEE 1637
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ABOUT THE AUT HOR
Ali Shakouri received the undergraduate degree
from Ecole Nationale Superieure des Telecommu-
nications de Paris, France, in 1990 and the Ph.D.
from the California Institute of Technology, Pasa-
dena, in 1995.
He is Professor of Electrical Engineering at
University of California Santa Cruz (UCSC). He was
the Technical Director for DARPA Heretic project
that demonstrated SiGe-based microrefrigerators
on a chip. He is currently the Director of the
Thermionic Energy Conversion Center, an Office of Naval Research
multiuniversity research initiative aiming to improve direct thermal to
electric energy conversion technologies. His current research is on
nanoscale heat and current transport in semiconductor devices, sub-
micrometer thermal and ac imaging, microrefrigerators on a chip, and
novel optoelectronic ICs.
He received the Packard Fellowship in 1999, the NSF Career award in
2000, and the UCSC School of Engineering FIRST Professor Award in
2004.
Shakouri: Nanoscale Thermal Transport and Microrefrigerators on a Chip
1638 Proceedings of the IEEE | Vol. 94, No. 8, August 2006