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ISA
Karan Sachdev 5935219
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ISA simulation CPU
• 24-bit
• Written in Python
Opcode
5-bits
Operand-1
3-bits
Binary Number
16-bits
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Registers
• 8 registers
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Binary of Opcode
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Clock Cycle of Opcode
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mov
• Operand 1 and Operand 2
mov r1 r3 means move register 1 into register 3
• Operand 1 and Value
mov r1 -6 means move the value -6 into register 1
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add
• Operand 1 and Operand 2
add r4 r2 means add the value of register 4 and register 2, then store the
value in register 4.
• Operand 1 and Value
add r2 1 means add the value of register 4 with 1 and store the value in
register 4
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sub
• Operand 1 and Operand 2
sub r3 r2 means subtract value of register 3 with register 2 and store the
value in register 3.
• Operand 1 and Value
sub r3 5 means subtract the value of register 3 with 5 and store the value
in register 3.
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mul
• Operand 1 and Operand 2
mul r6 r7 means multiply the value in register 6 and register 7 and store the
32-bit binary number of the multiplication in register 6
• Operand 1 and Value
mul r6 8 means multiply the value in register 6 with 8 and store the 32-bit
binary number of the multiplication
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Div
• Operand 1 and Operand 2
div r7 r3 means divide the value of register 7 and register 3 and store the
divided value in register 7
• Operand 1 and Value
div r2 4 means divide the value of register 2 with 4 and store the divided
value in register 2
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Sample Input
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Sample Output
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Final Register Result/CPI
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Sample Code
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Sample Code
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Sample Code