James Watt Nanofabrication Centre @Glasgow@ Glasgow
Contact: [email protected] @g g
James Watt Nanofabrication Centre @ Glasgow
In School of Engineering University of Glasgow
Smallest electron‐beam lithography pattern – 3 nmWorld Bests:
In School of Engineering, University of Glasgow
Best layer‐to‐layer alignment accuracy 0.46 nm rms
Smallest diamond transistor (50 nm gate length)
Lowest loss silicon optical waveguide (< 0 9 dB/cm)Lowest loss silicon optical waveguide (< 0.9 dB/cm)
Fastest mode locked laser (2.1 THz)
Highest Q silicon nanowire cavity
>30 Years Nanofabrication at Glasgow
1978 – EBL on convertedSEM i b t
1989 – our first dedicatedSEM f t l
1990 – Leica EBPG5Fi t UK U i l b tSEM in basement SEM for metrology First UK Uni lab to runprofessional installation
2005 – New James WattNanofabrication Centre built
2006 – New EBL toolState‐of‐the‐art
2007 – Nanoforum formedCross‐disciplinary groupof researchersa o ab cat o Ce t e bu t State o t e a t of researchers
James Watt Nanofabrication Centre @Glasgow
750m2 cleanroom ‐ pseudo‐industrial operationVistec VB6 & EBPG5
18 technicians + 5 research technologists
Large number of process modules
(PhD level process engineers)
E‐beam lithography
Large number of process modules
Processes include: GaAs/AlGaAs, InGaAs/InP,III V CMOS MMIC t l t i t t i l
/ l d l h
III‐V CMOS, MMICs, optoelectronics, metamaterials
http://www.jwnc.gla.ac.uk
9 RIE / PECVD 4 Metal dep tools 4 SEMs: Hitachi S4700
Süss MA6 optical &nanoimprintlithographyg p y
Electron Beam Lithography @ GlasgowVistec VB6 electron beam lithography:
maximum 200 mm wafer
<10 nm minimum feature size (≥4 nm spot)
0.46 nm proprietary layer‐to‐layer alignment
0 k d 100 k i50 keV and 100 keV operation
extra wide field of 1.3 mm
l i t f t t t 0 62laser interferometer stage to 0.62 nm
50 MHz pattern generator
automated alignmentautomated alignment
multi‐substrate load locked
Vistec EBPG5 electron beam lithography:g p y
maximum 150 mm wafer
<10 nm minimum feature size
0 46 nm proprietary layer to layer alignment0.46 nm proprietary layer to layer alignment
E‐beam Lithography with HSQ Resist Stephen Thoms
e‐beamCoat HSQ with tungsten
tungstentungsten
HSQ
SEM backscatter detector
tungstentungstensubstrate
7
8
9Measured linewidth vs dose
5
6
7
50 nm
3
4
16000 20000 24000 28000
Dose ( µC cm -2)
E b L t L C l ti Ali tE‐beam Layer‐to‐Layer Correlation AlignmentPenrose tile
Normal alignmentmarks ‐ 4 squares
Problems: Low statistics& errors from defects
For correlated alignment –>For correlated alignment >sharply peaked autocorrelation(i.e. ideal is 2D δ‐function)
nmWiener–Khintchine theorem –>ideal alignment from perfectly aperiodic pattern
nm
K.E. Docherty et al., Microelect. Eng. 85, 761 (2008)
nm0.46 nm rms layer‐to‐layer alignment
K.E. Docherty et al., Microelect. Eng. 85, 761 (2008)
Optical and Nanoimprint Lithography
Süss MA6 optical i‐line lithography &UV nanoimprint lithography – up to 150 mm substrates
Obducat nanoimprint lithography up to 75 mm substrates
Reactive Ion Etch
6 tools for different etch chemistries / applications
Load‐locked Cl chemistry for GaN& GaAs/AlGaAs etching
CH4/H2 : for selective InGaAs/InP etching
Low damage processes (no reductionin µ or ns in InGaAs HEMTs)
Dry etches for Al, Ti, W, Au, Pt, Pd metals
Dry etches for Si3N4 and SiO2
ICP Deep Si Bosch process for III‐V on Si/SOI
Dielectric Deposition3 tools: PECVD SiO2
PECVD Si3N4
Room temperature ICP PECVD low stress Si3N4
4.6x106 V/cm breakdown for 5 nm films
Complementary selective dry etches for (In)GaAs
Universities of Sheffield, Cambridge, Glasgow, Nottingham
National Centre for III-V Technologies
Wet Chemical Processing
Metallisation
Plassys I: Load‐locked electron beam evaporator, ion‐beam surface prep with 6 sources for Au, Ge, Ni, Pd, NiCr, Ti
Plassys II: Electron beam evaporatorPlassys II: Electron beam evaporator with 6 sources for Au, Ge, Ni, NiCr, Al, Pt
Pl III d d f tt t l ithPlassys III: dc and rf sputter tool with 6 sources for V, Cr, Cu, W, Al, W/Ti
Thermal evaporator: for non standard materialsThermal evaporator: for non‐standard materials
Metrology4 SEMs: Hitachi S900, S3000, S4700 with EDX and Nova NanoSEM S600
2 Digital Instruments AFM, Veeco Dektak
For dry etch / deposition: ellipsometerQuickTime™ and a
decompressorare needed to see this picture.
Miscellaneous Tools
Jipelec JetFirst Rapid Thermal Annealler (RTA)p p ( )
Up to 1000 ˚C anneal in N2
Veeco Dektak 6M
Ellipsometer
Electroplating kit
Ellipsometer
Wire bonder – deep access ultrasonic wedge bonder
Wafer scribe
Wafer saw
Process Integration
Process integration is key to obtain functioning devices
Not all individual processes can be integrated for complete devices
Heterolayer design must be integrated with full process to maximise device yielddevice yield
Heterolayers optimised for etch stop, Schottky barriers and Ohmic y p p, ycontact are available for many III‐V materials
MMICs Technology50 nm InGaAsT‐gate HEMT process on 100mm wafers
Maximum ID = 0.9 A/mmMaximum gm = 1.6 S/mmffT = 550 GHzfmax = 440 GHz
P i l d i b id h l
10 nm T‐gate process in development
D i (d i & i i ) MBE h f d
Process includes: airbridge technologyspiral inductors, capacitorswaveguides, antenna
Design (device & circuit), MBE growth, foundry, test
Circuit demonstrators: 94 & 140 GHz LNAs, 94 GHz mixers
140 GHz LNA
I Thayne et al
22 nm
I. Thayne et al., Thin Solid Films 515, 4373 (2007)
Scaling T gate Process to 22 nmScaling T‐gate Process to 22 nm
Ti/Pt/Au
50 SiN50 nm SiN
S. Bentley et al., Microelect. Eng. 85, 1375 (2008)
22 nm T‐gatesZEB resistprofile
SiN RIE SF6/N2
@ 20W
Metal 1b l d d
S. Bentley et al., Microelect. Eng. 85, 1375 (2008)
lift‐offMobility and carrier density measurementsused to confirm low damage SiN etching
S. Bentley et al., Microelect. Eng. 85, 1375 (2008)
III‐V CMOS
Statistical variationof 90 nm devicesof 90 nm devices
Channel mobilityoptimisationAtomic scale optimisationAtomic scale
interfacecharacterisation
Oxide
Predictedperformance
Semiconductor
pcalibrated
using experimentalp
data
30 nm RIE Tungsten Gates for III‐V CMOSCMOS
Low damage W RIE Low damage spacer RIE300 K ICP‐CVD Si3N4
spacer depositionNEB31 resistNEB31 resist
RIE SF6:N2ICP SF6:C4F8
X Li et al Microelec Eng 85 996 (2008)X Li et al Microelec Eng 85 996 (2008)
RIE SF6:N2
5:55 sccm20 W, 15 mTorr
ICP SF6:C4F825:15 sccm200 W, 5 mTorr
X. Li et al., Microelec. Eng. 85, 996 (2008)X. Li et al., Microelec. Eng. 85, 996 (2008)
Electrical TestIn cleanroom:
Probe station with Agilent dc test
On‐wafer probing
On‐wafer probing up to 150 mm substrates
Outside cleanroom:
DC to 325 GHz (Agilent B1500 and VNAs)
p g p
In situ CV and variable duty cycle pulsed to 50 ns
Microwave/Millimetre Wave Test & Measurement
In‐situ CV and variable duty‐cycle pulsed to 50 ns
20 GHz nearfield test range ‐ anechoic chamber
VNA suite from MHz to 325 GHz
Quantum Cascade LasersMIR and THz QCLs fabricated
GaAs/AlGaAs and InP/InGaAs(Sb) supported
Ridge, plasmon and racetrack waveguides demonstrated
Semiconductor LasersSemiconductor lasers: ridge, ring, microdiscGaAs/AlGaAs, InGaAs(P)/InP, GaN/ , ( )/ ,
G. Mezosi et al., IEEE Phot. Technol. Lett. 21, 88 (2009)
2.0
1 CRTFastest mode locked laser at 2.1 THz
Sig 1.4
1.6
1.8
1 CRT
2.1 THz
Delay, ps0 5 10 15
gnal, A.U
.
1.0
1.2
D.A. Yanson et al., IEEE J. Quant. Electron. 38, 244 (2002)
y p
Optoelectronics
Integrated technologies(GaAs/AlGaAs;InGaAs/InP;
GaN)
Pulse shaping using Bragg gratings
GaN)
L.M. Rivas et al., Opt. Lett. 33, 2425 (2008)
Optoelectronic ModulatorsMach‐Zendermodulators
Photonic crystalsand nanophotonicmodulatormodulator
RIE dry etching of gallium nitride (GaN)SiCl4/SF6/Ar RIE (physical to chemical etching 1:1), 120W, 40mTorr: 650nm HSQ resist
2-D FDTD simulation resultsProc SPIE Vol 7713 77131N (2010)Proc. SPIE, Vol. 7713, 77131N (2010)
RIE dry etching of gallium nitride (GaN)SiCl4/SF6/Ar RIE (physical to chemical etching 1:1), 120W, 40mTorr: 650nm HSQ resist
QuickTime™ and aGIF decompressor
are needed to see this picture.
2 D FDTD simulation results 2-D FDTD simulation results Proc. SPIE, Vol. 7713, 77131N, 2010.
ICP dry etching of indium phosphide (InP)InP/InGaAsP ICP‐RIE: Cl2/Ar/N2 gas mixture
Highly anisotropic process resulted in near‐vertical sidewallsHighly anisotropic process resulted in near vertical sidewalls on deeply etched structures, for a single HSQ hard‐mask used.
Nano-sized features in InP/InGaAsP-based material: SEM micrograph of high aspect ratio (~30) etching. Deeply etched (3.2 µm) and highly recessed first-order sidewall grating fabricated simultaneously with a ridge waveguide.
ICP dry etching of indium phosphide (InP)
Deep ICP dry etching of InP/AlGaInAs: Cl2/Ar/N2 ICP‐RIESmooth transition between InGaAs capping layer and InP, InGaAsP AlGaInAs layers (equal rate etching process)InGaAsP, AlGaInAs layers (equal‐rate etching process).