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Lecture 17Lecture 17
Digital Circuits (I)
THE INVERTER
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1. Introduction to digital circuits:
the inverter
1. Introduction to digital circuits:
the inverterIn digital circuits, digitally-encoded information is
represented by means of two distinct voltage ranges:
The Static Definition
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The Static Definition
Logic 0: VMIN
~ VOL
Logic 1: VOH
~ VMAX
Undefined logic value: VOL
~ VOH
Logic operations are performed using
logic gates. Simplest logic operation
of all: inverter
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Ideal inverter
Circuit representation and ideal transfer function: Circuit representation and ideal transfer function:
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Ideal inverter
input voltage for which
For 0
M OUT INV V V
V V V V +
≡ =
≤ < ⇒ =
Define switching point or logic threshold:
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Ideal inverter returns well defined logical outputs (0 or V+)
even in the presence of considerable noise in VIN (from voltage
spikes, crosstalk, etc.)
→Signal is regenerated!
For 0
For 0
IN M OUT
M IN OUT
V V V V
V V V V
+
+
≤ < ⇒ =
< ≤ ⇒ =
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“Real” inverter
• Logic 0: –VMIN output voltage for which VIN = V+
–VOL smallest output voltage where slope = -1
• Logic 1: –VOH largest output voltage where slope = -1
–VMAX output voltage for which VIN = 0
In a real inverter, valid logic levels defined as follows:
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Two other important voltages:
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smallest input voltage where slope =-1
highest input voltage where slope =-1
IL
IH
V
V
≡
≡
If range of output values V to V is wider than the range of
Define:
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If range of output values VOL to VOH is wider than the range of
input values VIL to VIH, then the inverter exhibits some noise
immunity. (|Voltage gain|>1)
Quantify this through noise margins.
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Chain of two inverters:
Define noise margins:
NMH= V - VNMH= VOH- VIH
noise margin high
NML=VIL – VOL
noise margin low
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Simplifications for hand calculations:
Logic levels and noise margins
It is hard to compute points in transfer function with slope = -1.
Approximate in the following way:
• Assume VOL=VMIN
and VOH=VMAX and VOH=VMAX
• Trace tangent of transfer
function at VM
– Slope = small signal
voltage gain (Av) at VM
•VIL intersection of tangent with
VOUT = VMAX
•VIH intersection of tangent
with VOUT = VMIN
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Transient Characteristics Inverter switching in the time domain:
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tR rise time between 10% and 90% of total swing
tF fall time between 90% and 10% of total swing
tPHL propagation delay from high-to-low between 50% points
tPLH propagation delay from low-to-high between 50% points
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1Propagation delay: ( )
2p PHL PLHt t t= +
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Simplifications for hand calculations: Propagation delay
• Consider input waveform is an ideal square wave
• Propagation delay times = delay times to 50% point
• SPICE essential for accurate delay analysis 12
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2. NMOS inverter with “pull-up” resistor
Essential features:
•VBS = 0 (typically not shown)
•CL summarizes capacitive
loading of the following stages
(other logic gates, interconnect
lines, etc.) lines, etc.)
Basic Operation:
• If VIN < VT, MOSFET is OFF => VOUT = VDD
• If VIN > VT, MOSFET is ON => VOUT small – Value set by resistor /
NMOS divider
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Transfer function obtained by solving:
Can solve graphically: I–V
characteristics of load:
R DI I=
characteristics of load:
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Overlap I–V characteristics of resistor pull-up on I–V
characteristics of transistor:
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Transfer function:
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Logic levels:
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MAX DDV V=
For VMAX, transistor is cut-off, ID=0:
For VMIN, transistor is in linear regime; solve:
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( )2
2
DD MD N ox M T R
V VWI C V V I
L Rµ
−= − = =
2
MIN DD MIND N ox DD T MIN R
V V VWI C V V V I
L Rµ
− = − − = =
For VM, transistor is in saturation; solve:
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Noise Margins:
OH IN
MAX IN
IL OL
IL MIN
NMH V V
V V
NML V V
V V
= −
= −
= −
= −
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Small signal equivalent circuit model at VM
(transistor in saturation):
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0( / / )
( )
outv m m
in
M T
vA g r R g R
v
k V V R
= = − ≈ −
= − −
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What did we learn?What did we learn?
� Logic circuits must exhibit immunity to noise in the input
signal
– Noise margins
� Logic circuits must be regenerative
– Able to restore clean logic values even if input is noisy.
� Propagation delay: time for logic gate to perform its function.
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� Concept of load line: graphical technique to visualize transfer
characteristics of inverter.
� First-order solution (by hand) of inverter figures-of merit easy
if regions of operation of transistor are correctly identified. if regions of operation of transistor are correctly identified.
� For more accurate solutions, use SPICE (or other CAD tool).
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