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Lecture 030 – DSM CMOS Technology (3/24/10) Page 030-1
CMOS Analog Circuit Design © P.E. Allen - 2010
LECTURE 030 - DEEP SUBMICRON (DSM) CMOS TECHNOLOGYLECTURE ORGANIZATION
Outline• Characteristics of a deep submicron CMOS technology• Typical deep submicron CMOS technology• SummaryCMOS Analog Circuit Design, 2nd Edition ReferenceNew material
Lecture 030 – DSM CMOS Technology (3/24/10) Page 030-2
CMOS Analog Circuit Design © P.E. Allen - 2010
CHARACTERISTICS OF A DEEP SUBMICRON CMOS TECHNOLOGYIsolation of TransistorsThe use of reverse bias pn junctions to isolate transistors becomes impractical as thetransistor sizes decrease.
Lecture 030 – DSM CMOS Technology (3/24/10) Page 030-3
CMOS Analog Circuit Design © P.E. Allen - 2010
Use of Shallow Trench Isolation TechnologyShallow trench isolation (STI) allows closer spacing of transistors by eliminating thedepletion region at the surface.
p+ p p- MetalSaliciden- n n+Oxide Poly
070330-03
PolycideGate Ox
n+
n-well
n+
p-well
n+
Substrate
n+
ShallowTrench
Isolation
n+
ShallowTrench
Isolation
ShallowTrench
Isolation
p+p+ n+n+
Substrate Salicide
Well Salicide Decreasedspacing
Substrate Salicide
Shal
low
Trench Isolation
Isol
atio
n
Shal
low
Tre
nch
Lecture 030 – DSM CMOS Technology (3/24/10) Page 030-4
CMOS Analog Circuit Design © P.E. Allen - 2010
Comparison of STI and LOCOSWhat are the differences between a LOCOS and STI technology?
Comments:
• If the n+ to p+ spacing is large, the Bird’s beak can be compensated using techniquessuch as poly buffered LOCOS
• At some point as the n+ to p+ spacing gets smaller, the restricted bird’s beak leads toundesirable stress effects in the transistor.
• An important advantage of STI is that it minimizes the heat cycle needed for n+ or p+isolation compared to LOCOS. This is a significant advantage for any process wherethere are implants before STI.
Lecture 030 – DSM CMOS Technology (3/24/10) Page 030-5
CMOS Analog Circuit Design © P.E. Allen - 2010
Shallow Trench Isolation (STI)
060203-01
Nitride
Silicon(1)
(2)
(3)
(4)
(5)
(6)
1.) Cover the wafer with pad oxide and silicon nitride.
2.) First etch nitride and pad oxide. Next, an anisotropicetch is made in the silicon to a depth of 0.4 to 0.5 microns.
3.) Grow a thin thermal oxide layer on the trench walls.
4.) A CVD dielectric film is used to fill the trench.
5.) A chemical mechanical polishing (CMP) step is used topolish back the dielectric layer until the nitride is reached.The nitride acts like a CMP stop layer.
6.) Densify the dielectric material at 900°C and strip thenitride and pad oxide.
Lecture 030 – DSM CMOS Technology (3/24/10) Page 030-6
CMOS Analog Circuit Design © P.E. Allen - 2010
Illustration of a Deep Submicron (DSM) CMOS Technology
n+
p-substrate
Metal Layers
NMOSTransistor
PMOSTransistor
031211-02
M1M2M3M4M5M6M7M80.8μm
0.3μm 7μm
Deep n-wellDeep p-well
n+
STI�p+ p+
STI STI
Salicide
Polycide
Salicide
PolycideSidewall Spacers
Salicide
Source/drainextensions
Source/drainextensions
��
In addition to NMOS and PMOS transistors, the technology provides:1.) A deep n-well that can be utilized to reduce substrate noise coupling.2.) A MOS varactor that can serve in VCOs3.) At least 6 levels of metal that can form many useful structures such as inductors,
capacitors, and transmission lines.
Lecture 030 – DSM CMOS Technology (3/24/10) Page 030-7
CMOS Analog Circuit Design © P.E. Allen - 2010
TransistorsfT as a function of gate-source overdrive, VGS-VT (0.13μm):
100 200 300 400 500
20
30
40
50
60
70
10
00
Typical, 25°C
Slow, 70°CPMOS
Typical, 25°C
Slow, 70°CNMOS
f T (
GH
z)
|VGS-VT| (mV) 030901-07
The upper frequency limit is probably around 40 GHz for NMOS with an fT in thevicinity of 60GHz with an overdrive of 0.5V and at the slow-high temperature corner.
Lecture 030 – DSM CMOS Technology (3/24/10) Page 030-8
CMOS Analog Circuit Design © P.E. Allen - 2010
Resistors1.) Diffused and/or implanted resistors.2.) Well resistors.3.) Polysilicon resistors.4.) Metal resistors.
Lecture 030 – DSM CMOS Technology (3/24/10) Page 030-9
CMOS Analog Circuit Design © P.E. Allen - 2010
CapacitorsPolysilicon-polysiliconcapacitors:
Metal-metal capacitors:
060530-01
Third levelfrom top metal
Second level from top metalInter-
mediateOxideLayers
Top Metal
Protective Insulator Layer
Metal Via
Capacitor Top Metal
Capacitor bottom plate
Capacitordielectric
Fourth levelfrom top metal
Vias connecting bottom plate to lower metal
Vias connecting top plate to top metal
Vias connecting bottom plate to lower metal
Lecture 030 – DSM CMOS Technology (3/24/10) Page 030-10
CMOS Analog Circuit Design © P.E. Allen - 2010
InductorsTop view and cross-section of a planar inductor:
W
S
D
D
Top Metal
Next LevelMetal
Top Metal
Next LevelMetal
Vias
Oxide
Oxide
Silicon Substrate
N turns
030828-01
Lecture 030 – DSM CMOS Technology (3/24/10) Page 030-11
CMOS Analog Circuit Design © P.E. Allen - 2010
TYPICAL DEEP SUBMICRON (DSM) CMOS FABRICATION PROCESSMajor Fabrication Steps for a DSM CMOS Process 1.) p and n wells 2.) Shallow trench isolation 3.) Threshold shift and anti-punch through implants 4.) Thin oxide and gate polysilicon 5.) Lightly doped drains and sources 6.) Sidewall spacer 7.) Heavily doped drains and sources 8.) Siliciding (Salicide and Polycide) 9.) Bottom metal, tungsten plugs, and oxide10.) Higher level metals, tungsten plugs/vias, and oxide11.) Top level metal, vias and protective oxide
Lecture 030 – DSM CMOS Technology (3/24/10) Page 030-12
CMOS Analog Circuit Design © P.E. Allen - 2010
Starting MaterialThe substrate should be highly doped to act like a good conductor.
p+ p p- MetalSaliciden- n n+Oxide Poly 060118-02PolycideGate Ox
Substrate
Lecture 030 – DSM CMOS Technology (3/24/10) Page 030-13
CMOS Analog Circuit Design © P.E. Allen - 2010
Step 1 - n and p wellsThese are the areas where the transistors will be fabricated - NMOS in the p-well andPMOS in the n-well.Done by implantation followed by a deep diffusion.
p+ p p- MetalSaliciden- n n+Oxide Poly 060118-03PolycideGate Ox
p+ n+
n-well p-well
Substrate
n well implant and diffusion p well implant and diffusion
Lecture 030 – DSM CMOS Technology (3/24/10) Page 030-14
CMOS Analog Circuit Design © P.E. Allen - 2010
Step 2 – Shallow Trench IsolationThe shallow trench isolation (STI) electrically isolates one region/transistor fromanother.
p+ p p- MetalSaliciden- n n+Oxide Poly 060118-04PolycideGate Ox
p+ n+
n-well
ShallowTrench
Isolation
p-well
ShallowTrench
Isolation
ShallowTrench
Isolation
Substrate
Lecture 030 – DSM CMOS Technology (3/24/10) Page 030-15
CMOS Analog Circuit Design © P.E. Allen - 2010
Step 3 – Threshold Shift and Anti-Punch Through ImplantsThe natural thresholds of the NMOS is about 0V and of the PMOS is about –1.2V. An p-implant is used to make the NMOS harder to invert and the PMOS easier resulting inthreshold voltages balanced around zero volts.
p+ p p- MetalSaliciden- n n+Oxide Poly 060118-05PolycideGate Ox
n+
n-well p-well
ShallowTrench
Isolation
Substrate
p threshold implant p threshold implant
n+ anti-punch through implant p+ anti-punch through implant
ShallowTrench
Isolation
ShallowTrench
Isolation
Also an implant can be applied to create a higher-doped region beneath the channels toprevent punch-through from the drain depletion region extending to source depletionregion.
Lecture 030 – DSM CMOS Technology (3/24/10) Page 030-16
CMOS Analog Circuit Design © P.E. Allen - 2010
Step 4 – Thin Oxide and Polysilicon GatesA thin oxide is deposited followed by polysilicon. These layers are removed where theyare not wanted.
p+ p p- MetalSaliciden- n n+Oxide Poly 060118-06PolycideGate Ox
p+ n+
n-well p-well
Substrate
ShallowTrench
Isolation
ShallowTrench
Isolation
ShallowTrench
Isolation
Lecture 030 – DSM CMOS Technology (3/24/10) Page 030-17
CMOS Analog Circuit Design © P.E. Allen - 2010
Step 5 – Lightly Doped Drains and SourcesA lightly-doped implant is used to create a lightly-doped source and drain next to thechannel of the MOSFETs.
p+ p p- MetalSaliciden- n n+Oxide Poly 070321-01PolycideGate Ox
p+ n+
n-well
ShallowTrench
Isolationp-well
ShallowTrench
Isolation
ShallowTrench
Isolation
Substrate
Shallow n-
ImplantShallow n-
ImplantShallow p-
ImplantShallow p-
Implant
Lecture 030 – DSM CMOS Technology (3/24/10) Page 030-18
CMOS Analog Circuit Design © P.E. Allen - 2010
Step 6 – Sidewall Spacers
p+ p p- MetalSaliciden- n n+Oxide Poly 070321-02PolycideGate Ox
p+ n+
n-well
ShallowTrench
Isolationp-well
ShallowTrench
Isolation
ShallowTrench
Isolation
Substrate
SidewallSpacers
SidewallSpacers
A layer of dielectric is deposited on the surface and removed in such a way as to leave“sidewall spacers” next to the thin-oxide-polysilicon-polycide sandwich. Thesesidewall spacers will prevent the part of the source and drain next to the channel frombecoming heavily doped.
Lecture 030 – DSM CMOS Technology (3/24/10) Page 030-19
CMOS Analog Circuit Design © P.E. Allen - 2010
Step 7 – Implantation of the Heavily Doped Sources and DrainsNote that not only does this step provide the completed sources and drains but allows forohmic contact into the wells and substrate.
p+ p p- MetalSaliciden- n n+Oxide Poly 070321-03PolycideGate Ox
n+
n-well
n+
ShallowTrench
Isolationp-well
p+
ShallowTrench
Isolation
Substrate
p+
implantn+
implantn+
implantn+
implantp+
implantp+
implant
ShallowTrench
Isolation
p+p+ n+ n+
Lecture 030 – DSM CMOS Technology (3/24/10) Page 030-20
CMOS Analog Circuit Design © P.E. Allen - 2010
Step 8 – Siliciding (Salicide and Polycide)This step reduces the resistance of the bulk diffusions and polysilicon and forms an ohmiccontact with material on which it is deposited.Salicide = Self-aligned silicide
p+ p p- MetalSaliciden- n n+Oxide Poly 070321-04PolycideGate Ox
SalicideSalicideSalicide
Polycide
p+ n+
n-well
n+
ShallowTrench
Isolationp-well
p+
Salicide
ShallowTrench
Isolation
Substrate
Polycide
ShallowTrench
Isolation
n+ n+p+ p+
Lecture 030 – DSM CMOS Technology (3/24/10) Page 030-21
CMOS Analog Circuit Design © P.E. Allen - 2010
Step 9 – Intermediate Oxide LayerAn oxide layer is used to cover the transistors and to planarize the surface.
Lecture 030 – DSM CMOS Technology (3/24/10) Page 030-22
CMOS Analog Circuit Design © P.E. Allen - 2010
Step 10- First-Level MetalTungsten plugs are built through the lower intermediate oxide layer to provide contactbetween the devices, wells and substrate to the first-level metal.
Lecture 030 – DSM CMOS Technology (3/24/10) Page 030-23
CMOS Analog Circuit Design © P.E. Allen - 2010
Step 11 – Second-Level MetalThe previous step is repeated for the second-level metal.
Lecture 030 – DSM CMOS Technology (3/24/10) Page 030-24
CMOS Analog Circuit Design © P.E. Allen - 2010
Completed FabricationAfter multiple levels of metal are applied, the fabrication is completed with a thicker top-level metal and a protective layer to hermetically seal the circuit from the environment.Note that metal is used for the upper level metal vias. The chip is electrically connectedby removing the protective layer over large bonding pads.
Lecture 030 – DSM CMOS Technology (3/24/10) Page 030-25
CMOS Analog Circuit Design © P.E. Allen - 2010
Scanning Electron Microscope of a MOSFET Cross-section
Fig. 2.8-20
TEOS
TEOS/BPSG
Tungsten Plug
SOG
Polycide
PolyGate
SidewallSpacer
Lecture 030 – DSM CMOS Technology (3/24/10) Page 030-26
CMOS Analog Circuit Design © P.E. Allen - 2010
Scanning Electron Microscope Showing Metal Levels and Interconnect
Fig.180-11
Metal 1
Metal 2
Metal 3
TungstenPlugs
AluminumVias
Transistors
Lecture 030 – DSM CMOS Technology (3/24/10) Page 030-27
CMOS Analog Circuit Design © P.E. Allen - 2010
SUMMARY• DSM technology typically has a minimum channel length between 0.35μm and 0.1μm• DSM technology addresses the problem of excessive depletion region widths in
junction isolation techniques by using shallow trench isolation• DSM technology may have from 4 to 8 levels of metal• Lightly doped drains and sources are a key aspect of DSM technology