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Lecture 26: Reconfigurable Computing May 11, 2004
ECE 669
Parallel Computer Architecture
Reconfigurable Computing
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Lecture 26: Reconfigurable Computing May 11, 2004
What is Reconfigurable Computing?
• Computation using hardware that can adapt at the logic level to solve specific problems
° Why is this interesting?• Some applications are poorly suited to
microprocessor.
• VLSI “explosion” provides increasing resources.
• Hardware/Software
• Relatively new research area.
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Lecture 26: Reconfigurable Computing May 11, 2004
Background needed
• Basic VLSI – transistors, delay models.
• Basic algorithms – graph algorithms, seaches
• Computer Architecture – ALU, microprocessor
• Digital Design – adder, counter, etc.
Topic self-contained!
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Lecture 26: Reconfigurable Computing May 11, 2004
Microprocessor-based Systems
• Generalized to perform many functions well.
• Operates on fixed data sizes.
• Inherently sequential.
Data Storage(Register File)
ALU
A B C
64
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Lecture 26: Reconfigurable Computing May 11, 2004
Reconfigurable Computing
• Create specialized hardware for each application.
• Functional units optimized to perform a special task.
Functional Unit
A B
H L
If (A > B) { H = A; L = B;}Else { H = B; L = A;}
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Lecture 26: Reconfigurable Computing May 11, 2004
Example: Bubblesort
• Adapt interconnect to problem.
• Take advantage of parallelism.
A B
H L
A B
H L
A B
H L
A B
H L
A B
H L
Smallest Largest
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Lecture 26: Reconfigurable Computing May 11, 2004
Implementation Spectrum
• ASIC gives high performance at cost of inflexibility.
• Processor is very flexible but not tuned to the application.
• Reconfigurable hardware is a nice compromise.
Microprocessor Reconfigurable Hardware
ASIC
What does it look like?
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Lecture 26: Reconfigurable Computing May 11, 2004
Reconfigurable Hardware
• Each logic element operates on four one-bit inputs.
• Output is one data bit.
• Can perform any boolean function of four inputs
2 = 64K functions!
Logic Element
ABCD
Out
A B C D = out
2 4
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Lecture 26: Reconfigurable Computing May 11, 2004
Field-Programmable Gate Array
• Each logic element outputs one data bit.
• Interconnect programmable between elements.
• Interconnect tracks grouped into channels.
LE LE
LE LE
LE LE LE LE
LE LE
LE LE
Logic Element Tracks
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Lecture 26: Reconfigurable Computing May 11, 2004
FPGA Architecture Issues
• Need to explore architectural issues.
• How much functionality should go in a logic element?
• How many routing tracks per channel?
• Switch “population”?
LogicElement
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Lecture 26: Reconfigurable Computing May 11, 2004
Real World Physical Issues
• Modelling FPGA delay.
• Improving performance through buffering/segmentation.
• Technology dependent.
• The cost of reconfigurability.
S S
Wires have real cost
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Lecture 26: Reconfigurable Computing May 11, 2004
Translating a Design to an FPGA
• CAD to translate circuit from text description to physical implementation well understood.
• CAD to translate from C program to circuit not well understood.
• Very difficult for application designers to successfully write high-performance applications
C program
. . C = A+B .
Circuit
AB + C
Array
Need for design automation!
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Lecture 26: Reconfigurable Computing May 11, 2004
High-level Compilers
• Difficult to estimate hardware resources.
• Some parts of program more appropriate for processor (hardware/software codesign).
• Compiler must parallelize computation across many resources.
• Engineers like to write in C rather than pushing little blocks around.
C = A+B
A B
+
C
for (i = 0; i<n, i++){ . .}
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Lecture 26: Reconfigurable Computing May 11, 2004
Circuit Compilation
1. Technology Mapping
2. Placement
3. Routing
LUT
LUT
?
Assign a logical LUT to a physical location.
Select wire segmentsAnd switches forInterconnection.
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Lecture 26: Reconfigurable Computing May 11, 2004
Two Bit Adder
FA
A B
Co Ci
S
Made of Full Adders
A+B = D
Logic synthesis tool reduces circuit to SOP form
Co = ABCi + ABCi + ABCi + ABCi
S = ABCi + ABCi + ABCi + ABCi
LUT CoCi
BA
LUT SCi
BA
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Lecture 26: Reconfigurable Computing May 11, 2004
Processor + FPGA
1. FPGA serves as coprocessor for data intensive applications – possible project.
Three possibilities
Backplane bus(e.g. PCI)
Proc
chip
daughtercard
FPGA
chipFPGAProc
2. FPGA serves as embedded computer for low latency transfer.“Reconfigurable Functional Unit”
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Lecture 26: Reconfigurable Computing May 11, 2004
Processor + FPGA (cont..)
• FPGA logic embedded inside processor.
• A number of problems with 2 and 3.
- Process technology an issue.
- ALU much faster than FPGA generally.
- FPGA much faster than the entire processor.
RF
ALU FPGA
Processor
3. Processor integration
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Lecture 26: Reconfigurable Computing May 11, 2004
Multi-FPGA Systems
• Most applications don’t fit on one device.
• Create need for partitioning designs across many devices.
• Effectively a “netlist computer”
Each FPGA is a logic processor interconnected in a given topology.
F
F
F
F
F
F
F
F
F
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Lecture 26: Reconfigurable Computing May 11, 2004
Dynamic Reconfiguration
• What if I want to exchange part of the design in the device with another piece?
• Need to create architectures and software to incrementally change designs.
• Effectively a “configuration cache”
Examples: encryption, filtering.
L L
L L
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Lecture 26: Reconfigurable Computing May 11, 2004
Research Areas
• Storing configuration info inside device.
• Architecture evaluation.
- Size and performance tradeoff.
• Layout of a new logic element.
• Algorithm for place and route.
• Apply an application to FPGA logic.
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Lecture 26: Reconfigurable Computing May 11, 2004
Versatile Place and Route
• Written by Vaughn Betz at the University of Toronto
• Performs FPGA placement and routing.
• Written in C
• Runs on Suns, Alphas, Linux
• Estimates device sizes and performance.
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Lecture 26: Reconfigurable Computing May 11, 2004
Xilinx XC4000 Cell
• 2 4-input look-up tables
• 1 3-input look-up table
• 2 D flip flops
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Lecture 26: Reconfigurable Computing May 11, 2004
Xilinx XC4000 Routing
25
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Lecture 26: Reconfigurable Computing May 11, 2004
Altera Flex10K
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Lecture 26: Reconfigurable Computing May 11, 2004
Altera Flex10K
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Lecture 26: Reconfigurable Computing May 11, 2004
Xilinx Virtex-II Pro
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Lecture 26: Reconfigurable Computing May 11, 2004
Altera Stratix
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Lecture 26: Reconfigurable Computing May 11, 2004
Xilinx Virtex CLB
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Lecture 26: Reconfigurable Computing May 11, 2004
Embedded RAM
° Xilinx – Block SelectRAM• 18Kb dual-port RAM arranged in columns
° Altera – TriMatrix Dual-Port RAM• M512 – 512 x 1
• M4K – 4096 x 1
• M-RAM – 64K x 8
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Lecture 26: Reconfigurable Computing May 11, 2004
Xilinx: Embedded Multipliers
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Lecture 26: Reconfigurable Computing May 11, 2004
aSoC Architecture
MultiplierFPGAFPGA
uProc
Multiplier
ctrl
South Core
West
North
East
tile
West
North
South
East
Ctrl
Core
Communication
Interface
Heterogeneous Cores
Point-to-point connections
Communication Interface
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Lecture 26: Reconfigurable Computing May 11, 2004
Summary
° Reconfigurable computing relies heavily on new VLSI technology
° Device architectures maturing
° Application development progressing at rapid pace
° Integration of hardware and software a difficult challenge
° Active area of research at UMass.