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Chap.10 Digital Integrated Circuits
Content10-1 Introduction10-2 Feature 10-3 Feature of BJT 10-4 RTL and DTL10-5 TTL 10-6 ECL 10-7 MOS 10-8 CMOS10-9 MOS transmission gate
Integration Levels
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• Gate/transistor ratio is roughly 1/10– SSI < 12 gates/chip– MSI < 100 gates/chip– LSI …1K gates/chip– VLSI …10K gates/chip– ULSI …100K gates/chip– GSI …1Meg gates/chip
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Logic Family DefinitionA circuit configuration or approach used
to produce a type of digital integrated circuit.
Consequence: different logic functions, when fabricated in the form of an IC with the same approach, or in other words belonging to the same logic family, will have identical electrical characteristics.
the set of digital ICs belonging to the same logic family are electrically compatible with each other
10-1 IntroductionIC digital logic families
◦RTL ( Resistor-transistor logic)◦DTL ( Diode-transistor logic)◦TTL ( Transistor -transistor logic)◦ECL ( Emitter-coupled logic)◦MOS(Metal-oxide semiconductor)◦CMOS ( Complementary Metal-
oxide semiconductor)
Moore’s law
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• A prediction made by Moore (a co-founder of Intel) in 1965: “… a number of transistors to double every 2 years.”
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Common Characteristics of the Same Logic Family
Supply voltage range, speed of response, power dissipation, input and output logic levels, current sourcing and sinking capability, fan-out, noise margin, etc.
Consequence: choosing digital ICs from the same logic family guarantees that these ICs are compatible with respect to each other and that the system as a whole performs the intended logic function.
Positve logic and Negative logic
Positive logic: H is set to be binary 1
Negative logic: L is set to be binary 1
10-2 Feature
The feature to be concerned of IC logic families:◦ fan-out
The no. of standard loads can be connected to the output of the gate without degrading its normal operation
Sometimes the term loading is used◦ Power dissipation
The power needed by the gate Expressed in mW
◦ Propagation delay The average transition-delay time for the signal to
propagate from input to output when the binary signal changes in value
◦ Noise margin The unwanted signals are referred to as noise Noise margin is the maximum noise added to an input
signal of a digital circuit that does not cause an undesirable change in the circuit output
Computing fan-out
),min(IL
OL
IH
OH
I
I
I
IoutFan
William KleitzDigital Electronics with VHDL, Quartus® II Version
Copyright ©2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458
All rights reserved.
Computing fan-out ( High-level output)
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Input and output current specifications
William KleitzDigital Electronics with VHDL, Quartus® II Version
Copyright ©2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458
All rights reserved.
Computing fan-out ( Low-level output)
Power dissipation
CCCCD
CCLCCHCC
VavgIavgP
IIavgI
)()(2
)(
?7400)(
?)(
3,1
TTL standardFor
ICinavgPTotal
avgP
mAImAI
D
D
CCLCCH
Propagation delay
50% VH
50% VH
50% VH
50% VH
For standard TTL
?)(
11,7
avgt
nstnst
P
PLHPHL
Other delay times
◦Rise Time from 10% up to 90% level
◦Fall Time from 90% down to 10% level
Noise margin
Noise margin
High-state noise margin=0.4
Low-state noise margin=0.4
In the beginning…
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Diode Logic (DL)• simplest; does not scale• NOT not possible (need
an active element)=
=
Resistor-Transistor Logic (RTL) • replace diode switch
with a transistor switch• can be cascaded• large power draw
was…
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=
Diode-Transistor Logic (DTL) • essentially diode logic with transistor amplification• reduced power consumption• faster than RTL
DL AND gate Saturating inverter
10-3 Feature of BJT BJT
◦ npn or pnp ◦Si or Ge◦Si is used mainly◦npn is most popular
Table 10-1 Typical npn Transistor Parameters
Region VBE (V) VCE (V) Current Relation
Cutoff < 0.6 Open circuit
IB=IC=0
Active 0.6-0.7 > 0.8 IC =hFEIB
Saturation 0.7-0.8 0.2 IB ≥IC/hFE
Feature of npn-type BJT
HVLV
V
VLh
VHkR
VVkR
ii
o
FE
B
CCC
and for
? Find
2.0,50
5,22
5,1
Diode – symbol and characteristic
10-4 RTL and DTL circuits RTL
◦ Resistor TL◦ L: 0.2V, H: 1~3.6V
DTL◦ Diode TL◦ L: 0.2V, H: 4~5V
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DL Example
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RTL Example
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DTL Example
RTL--NOR
DTL--NAND
Modified DTL
10-5 Transistor-Transistor Logic (TTL)
The original basic TTL gate was a slight improvement over the DTL gate.
There are several TTL subfamilies or series of the TTL technology.
Eight TTL series appear in Table 10-2.Has a number start with 74 and follows
with a suffix that identifies the series type, e.g 7404, 74S86, 74ALS161.
Three different types of output configurations:◦ 1. open-collector output◦ 2. Totem-pole output◦ 3. Three-state (or tristate) output
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TTL Subfamilies
TTL family evolution
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Legacy: don’t use in new designs
Widely used today
Open-collector TTL Gate
Wired-AND of Two Open-Collector
Open-Collector Gates Forming a Common Bus Line
In this case
Y = ?
TTL Gate with Totem-Pole Output
Schottky TTL Gate
Three-state TTL Gate
10-6 Emitter-Coupled Logic (ECL) Nonsaturated digital logic familyPropagation rate as low as 1-2nsUsed mostly in high speed circuitsNoise immunity and power dissipation
is the worst of all logic families. High level -0.8V, Low level -1.8VIncluding
◦ Differential input amplifier◦ Internal temperature and voltage
compensated bias network◦ Emitter-follower outputs
ECL Basic Gate
Graphic Symbols of ECL Gates