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Timothy O. Dickson and Sorin P. Voinigescu
Edward S. Rogers, Sr. Dept of Electrical and Computer Engineering
University of Toronto
CSICS
November 15, 2006
Low-Power Circuits for a 2.5-V, 10.7-to-86-Gb/s Serial Transmitter
in 130-nm SiGe BiCMOS
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Dickson & Voinigescu 2006 CSICS November 15, 2006
OutlineOutline
Motivation
High-speed, low-power design techniques
2.5-V, 80-Gb/s BiCMOS Transmitter
Measurement results
Conclusions
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Dickson & Voinigescu 2006 CSICS November 15, 2006
Next Generation High-Speed Wireline: Next Generation High-Speed Wireline: 100-Gb/s Ethernet100-Gb/s Ethernet
New design challenges as fundamentalfrequencies enter mm-wave regime
1 x 100-Gb/s
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Dickson & Voinigescu 2006 CSICS November 15, 2006
Power ConsumptionPower Consumption
State-of-the-art High-Speed Transceivers
Technology 130-nm CMOS SiGe (120-GHz fT)
Data Rate 3.125-to-10.7-Gb/s
2.7-to-43-Gb/s
Integration Single-chip Chip set
Power consumption
800 mW 12 W
Reference Aeluros, ISSCC 2004
Big Bear, ISSCC 2003
should consume lesspower than100 Gb/s
10 x 10 Gb/s
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Dickson & Voinigescu 2006 CSICS November 15, 2006
Power ConsumptionPower Consumption
100-Gb/s 4:1 MUX?
Technology SiGe (210-GHz fT)
Data Rate 132-Gb/s
Supply Voltage -3.3V
Power consumption
1.45 W
Reference IBM, ISSCC 2004
should consume lesspower than
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Dickson & Voinigescu 2006 CSICS November 15, 2006
MOSFETs vs HBTsMOSFETs vs HBTs
• HBT @ peak-fT VBE = 900mV… and does not scale!• 130-nm nMOS @ peak-fT VGS = 750mV… and decreasing!
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Dickson & Voinigescu 2006 CSICS November 15, 2006
Power reduction techniquesPower reduction techniques
43-GHz latch consumes only 20mW
BiCMOS logic family reduces supply voltage
Reduce tail current with inductive peaking
LP = CLV2
3.1 IT2
Stacked inductors
10 m
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Dickson & Voinigescu 2006 CSICS November 15, 2006
Transmitter Block DiagramTransmitter Block Diagram
8:1 MUX
Output Driver
On-chipPRBS for
BIST
40-GHz PLL
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Dickson & Voinigescu 2006 CSICS November 15, 2006
2.5-V, 87-Gb/s BiCMOS Selector2.5-V, 87-Gb/s BiCMOS Selector
EF for higher bandwidth
SF for voltage headroom
86-Gb/s selector consumes 60mW
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Dickson & Voinigescu 2006 CSICS November 15, 2006
2.5-V, 80-Gb/s BiCMOS Pre-Emphasis Driver2.5-V, 80-Gb/s BiCMOS Pre-Emphasis Driver
MOS gm and input
capacitance relatively
constant as bias
current changes.
Excellent for output
stages with adjustable
amplitude control.
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Dickson & Voinigescu 2006 CSICS November 15, 2006
2.5-V, 80-Gb/s BiCMOS Pre-Emphasis Driver2.5-V, 80-Gb/s BiCMOS Pre-Emphasis Driver
130-nm MOSFETsswitching at 80-Gb/s!
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Dickson & Voinigescu 2006 CSICS November 15, 2006
2.5-V, 80-Gb/s BiCMOS Pre-Emphasis Driver2.5-V, 80-Gb/s BiCMOS Pre-Emphasis Driver
Adjustable pre-emphasis for operation up to 80-Gb/s
Boosts high-frequency content to compensate for line losses.
Output match S22 < -10dB up to 94 GHz.
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Dickson & Voinigescu 2006 CSICS November 15, 2006
36-43 GHz Colpitts VCO36-43 GHz Colpitts VCO
SiGe HBTs used as negative resistance generators.
Differential tuning to reject common-mode noise.
Maximize tank swing, bias HBTs at NFMIN for low phase noise
-105 dBc/Hz @ 1-MHz offset
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Dickson & Voinigescu 2006 CSICS November 15, 2006
Die PhotographDie Photograph1.5 m
m
1.8 mm
PRBS + 8:4 MUX4:1 MUX +
Output Driver
PLL
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Dickson & Voinigescu 2006 CSICS November 15, 2006
Measured Results: 80-Gb/sMeasured Results: 80-Gb/s
Running for more than 1 hour continuously in the lab.
Jitter: 560 fs (rms) , Rise/fall time: 4-5 ps, Amplitude: 300 mV
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Dickson & Voinigescu 2006 CSICS November 15, 2006
Verification of Correct MultiplexingVerification of Correct Multiplexing
Using pattern capture capabilities of the Agilent 86100C DCA
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Dickson & Voinigescu 2006 CSICS November 15, 2006
Verification of Correct MultiplexingVerification of Correct Multiplexing
Examine the tone spacing usingAgilent E4448A PSA
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Dickson & Voinigescu 2006 CSICS November 15, 2006
80-Gb/s: Amplitude Control80-Gb/s: Amplitude Control
Little degradation in eye quality as amplitude varies from 100mV to 300 mV per side
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Dickson & Voinigescu 2006 CSICS November 15, 2006
Maximum Data Rate: 87-Gb/sMaximum Data Rate: 87-Gb/s
87 GHz
127= 685 MHz
685 MHz
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Dickson & Voinigescu 2006 CSICS November 15, 2006
Maximum Data Rate vs. Temp.Maximum Data Rate vs. Temp.
92-Gb/s @ 0oC
71-Gb/s @ 100oC
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Dickson & Voinigescu 2006 CSICS November 15, 2006
ComparisonComparison
Technology
fT/fMAX Data RateSupply
Voltage
Power
130-nm CMOS 85/90 GHz 40-Gb/s (half-rate) 1.5 V 2.7 W
InP HBT 150/150 GHz 43-Gb/s (full-rate) -3.6/ -5.2 V 3.6 W
180-nm SiGe BiCMOS
HBT: 120/100 GHz 43-Gb/s (half-rate) -3.6 V 1.6 W
180-nm SiGe BiCMOS
HBT: 120/100 GHz 43-Gb/s (full-rate) -3.6 V 2.3 W
130-nm SiGe BiCMOS
MOS: 85/90 GHz
HBT: 150/150 GHz87-Gb/s (half-rate) 2.5 V 1.36 W
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Dickson & Voinigescu 2006 CSICS November 15, 2006
ConclusionsConclusions
Described methods for power reduction in high-speed building blocks.
Use BiCMOS topology to lower supply voltage.
Trade off bias current for inductive peaking.
Applied these principles to the design of the first 87-Gb/s serial transmitter, which consumes less power than any 40-Gb/s TX reported to date.
As compared with state-of-the-art CMOS, this work shows that you can achieve double the data rate with half the power dissipation simply by adding the SiGe HBT option.
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Dickson & Voinigescu 2006 CSICS November 15, 2006
AcknowledgementsAcknowledgements
STMicroelectronics Crolles for chip fabrication
STMicroelectronics, Gennum, CITO, and NSERC for
financial support
CMC for CAD tools
CFI and OIT for equipment and test support
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Dickson & Voinigescu 2006 CSICS November 15, 2006
Questions?Questions?
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Dickson & Voinigescu 2006 CSICS November 15, 2006
BackupsBackups
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Dickson & Voinigescu 2006 CSICS November 15, 2006
DC ConsiderationsDC Considerations
VGS
VGS
VBE
VBE
VDS = 0V!
Need CM resistor in43-GHz clock buffer
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Dickson & Voinigescu 2006 CSICS November 15, 2006
Future Directions: Futher Power SavingsFuture Directions: Futher Power Savings
Reduce supply voltage to 1.8V by removing current sources.
38% power savings would result in 86-Gb/s TX that consumes 825 mW.
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Dickson & Voinigescu 2006 CSICS November 15, 2006
SiGe Building Block Supply VoltageSiGe Building Block Supply Voltage
DC drops dictate at least 3.3-V supply voltage
150 mV IR
900 mV VBE
900 mV VBE
750 mV VCE
600 mV VCE + IR
Unlike CMOS, supply voltage does not scale!!
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Dickson & Voinigescu 2006 CSICS November 15, 2006
CMOS vs. SiGe BiCMOSCMOS vs. SiGe BiCMOS
SiGe HBT has 2-generation speed advantageSiGe HBT has 2-generation speed advantage