5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
x16
Oscillators(50M + programmable)
1Gb LPDDR2 (x16)
x36
ButtonsSwitches
LEDs
x4x6x5
x29
Mini-USB2.0
x5 JTAG
10M50 F484 Package
x19 USB Interface
MIPI CSI-2 TX D-PHY(interface LI-MIPI-USB3-
TESTER module)
x31
On-BoardUSB BlasterTM II& USB Interface
x31
x22
PMOD x 2 User GPIO
HDMI CONN
MIPI CSI-2 RX D-PHY(interface OV10640 module)
MIPI CSI-2 RX D-PHY(interface OV5640 module)
x16
User LVDS I/O Array
ADV7513
x10
512Mb QSPI Flash
x7
x5
JTAG Header
100-0321404-A1.1110-0321404-A1.1120-0321404-A1.1130-0321404-A1.1140-0321404-A1.1150-0321404-A1.1160-0321404-A1.1170-0321404-A1.1180-0321404-A1.2210-0321404-A1.1220-0321404-A1.1320-0321404-A1.1
MAX 10 FPGA 10M50 Evaluation Kit Board
DESCRIPTIONREV DATE PAGESInitial Revision A Release.A1 Jun 19 2015 AllProject Drawing Numbers:
Raw PCB Gerber Files PCB Design Files Assembly Drawing Fab Drawing Schematic Drawing PCB Film Bill of Materials Schematic Design Files Functional Specification PCB Layout Guidelines Assembly Rework
1.
NOTES:
56
2
DESCRIPTIONPAGE
Title, Notes, Block Diagram, Rev. History
43
1
87
9
121110
15
1413
16
1817
21
2019
2322
24
Altera Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
Power Tree
MAX10 Banks 1 & 2Clock Tree
MAX10 Banks 7 & 8MAX10 Banks 5 & 6MAX10 Banks 3 & 4
LPDDR2 SDRAMMAX10 ConfigurationMAX10 Clocks
MIPI CSI-2 Rx D-PHY OV10640MIPI CSI-2 Tx D-PHY LI-USB3
On-Board USB Blaster II -2On-Board USB Blaster II -1HDMI (VIDEO ONLY)
QSPI FlashClocking
PMOD, GPIO, LVDS UserIO
Power 2.5 V & 1.8VHot Swap and Power 3.3 V
MAX 10 Power & GroundDecoupling
Copyright (c) 2015, Altera Corporation. All Rights Reserved.
25
MIPI CSI-2 Rx D-PHY OV5640
Pushbutton, Switch, LED
Power 1.2V
A1.1 Sep 15 2015
10 Delete C12.
222325
Change the value of C219 from DNI to 47uF.Add R315 to 1.2V_VCCIO.Change the value of C232 from 100uF to DNI.
18 Add note for SW2.4 MAX10_BYPASSn.
21 Update block diagram.
Update power tree.
A1.2 Dec 23 2015 10 Change LPDDR2_IS43LD16640A-3BL(333MHz part) to IS43LD16640A-25BL (400MHz part)due to Altera IP recommendation.
Title
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Title
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B
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5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
EN5329QI2A
5.0V @ 55mA
3.3V_OV5640 @ 182mA3.3V_OV10640 @ 145mA3.3V_PMOD @ 200mA3.3V_ADV7513@ 0.5mA3.3V_CY7C68013A @ 85mA3.3V_VCCIO_MAXII @ 9mA3.3V_VCCIO_MAX10 @ 16.5mA3.3V_Si510 @ 26 mA3.3V_Si5338_VDD @60 mA3.3V_Si5338_VDDO @ 96 mA
3.3V @ 820mA
5V_HDMI @ 55mA
2.5V_VCCA @ 61mA
2.5V_VCCIO_MAX10 @ 71mA
2.5V_VCCINT_MAXII @ 84mA
2.5V_VCCIO_MAXII @ 4.41mA
1.8V_VCCIO_MAX10 @ 2.81mA
1.8V_OV10640 @40mA
1.8V_ADV7513 @ 143mA
1.8V_LPDDR2_VDD @ 6mA
55 mm2
2.5V @ 221mA
1.2V @ 243mA 1.2V_VCCIO_MAX10 @ 32.5mA
1.2V_LPDDR2_VDD @ 210mA
DC_IN ( 5V@ 10W )
EP5348UI0.4A
14 mm2
EP5358HUI0.6A
14 mm2
EN5339QI3A
55 mm2
1.2V_VCC_MAX10 @ 1511mA
1.2V_VCCD_PLL_MAX10 @ 45mA
1.2V_VCCINT_MAX10 @ 0.02mA
1.8V @ 192mA
1.2V @ 1557mA
EP5348UI0.4A
14 mm2
3
4
1
5
2
1
2
3
4
5
Power UP SequencIng‐ 5V available to all regulators through DC plug or USB cable 1.8V
1.2V_VCCIO_MAX10, 1.2V_LPDDR2_VDD
3.3V
2.5V
1.2V_VCC_MAX10, 1.2V_VCCD_PLL_MAX10, 1.2V_VCCINT_MAX10
Altera Corporation, 301, Bibo Rd #888, Shanghai, China, 201203Copyright (c) 2015, Altera Corporation. All Rights Reserved.
POWER TREE
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5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CypressCY7C68013AUSB Controller 1 3
4
2
On-BoardUSB BlasterTM II
1A
1B2 5
6
3 4
8 7
FA‐12824MHz XTAL
USB_CLKCypressCY7C68013AUSB Controller
Note *: Not included, purchase and assembly required
MIPI LI‐USB3.0 Tester*MIPI_TX_CLK24MHz MIPI_TX_CLKP
MIPI_TX_CLKN
MIPI CSI‐2 Camera ModuleOV5640 *
MIPI CSI‐2 Camera ModuleOV10640 *
OV5640_CLK24MHzOV5
640_HS_CLKP
OV5
640_HS_CLKN
OV1
0640_H
S_CLKP
OV1
0640_H
S_CLKN
8Y‐25MHzXTAL
CLK24M
Si51050MHz Osc
CLK50M_MAXII
CLK50M_MAX10
CLK100M_LPDDR2
CLK125M
CLKOUT_LVDS_PCLKOUT_LVDS_N User LVDS I/O
Si5338
Default LVCMOS 100MHz CLK3
Default LVCMOS 125MHz CLK2
Default LVCMOS 24MHz CLK1
Default LVCMOS24MHz CLK0
Altera Corporation, 301, Bibo Rd #888, Shanghai, China, 201203Copyright (c) 2015, Altera Corporation. All Rights Reserved.
CLOCK TREE
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5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Copyright (c) 2015, Altera Corporation. All Rights Reserved.Altera Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
MAX10 BANKS 1 & 2
( VCCIO = 3.3V )
( VCCIO = 3.3V )
( VCCIO = 1.8V )
MAX10 USB Interface
OV5640 CSI-2 RX Interface
OV10640 CSI-2 RX Interface
LI-USB3 CSI-2 TX Interface
Misc
User DIP Switch
OV10640_CMOS_RSTOV10640_CMOS_SCLK
OV10640_G_RDYOV10640_XM_INT2
MIPI_TX_DATA_HS_P3MIPI_TX_DATA_HS_N3
USB_FULLUSB_DATA2USB_DATA3
USB_EMPTYUSB_DATA6USB_RDnUSB_DATA0USB_ADDR1
USB_DATA7
USB_SDAUSB_SCLUSB_RESETnOV5640_CAM_PWRON
USB_ADDR0USB_OEnUSB_DATA5USB_WRnUSB_DATA4USB_DATA1OV5640_CAM_RESETBOV5640_SDCJTAG_SAFEOV5640_SDA
MIPI_TX_DATA_HS_N2MIPI_TX_DATA_HS_P2
OV10640_GYRO_INT
MIPI_TX_CMOS_RST_1V8MIPI_TX_GPIO2
MIPI_TX_GPIO3MIPI_TX_GPIO4MIPI_TX_GPIO1MIPI_TX_GPIO5OV10640_FSINOV10640_XM_INT1MIPI_TX_DATA_HS_N4MIPI_TX_DATA_HS_P4MIPI_TX_CLK_HS_NMIPI_TX_CLK_HS_P
MIPI_TX_CMOS_SCLK_1V8
MIPI_TX_DATA_HS_P1MIPI_TX_DATA_HS_N1
MIPI_TX_CMOS_SDATA_1V8
OV10640_CMOS_SDATA
USER_DIPSW5
USER_DIPSW4
VREF_1V8HSTL
1.8V
VREF_1V8HSTL
USB_FULL 16
USB_EMPTY 16
USB_SCL 16
USB_SDA 16
USB_DATA[7:0] 16
USB_ADDR[1:0] 16
USB_RESETn 15
USB_OEn 16
USB_RDn 16
USB_WRn 15
JTAG_SAFE 15
OV5640_CAM_PWRON 13
OV5640_SDC 13
OV5640_CAM_RESETB 13
OV10640_CMOS_SCLK 12
OV10640_FSIN 12
OV5640_SDA 13
OV10640_CMOS_RST 12
OV10640_CMOS_SDATA 12
OV10640_GYRO_INT 12
OV10640_G_RDY 12
OV10640_XM_INT2 12
OV10640_XM_INT1 12
MIPI_TX_CMOS_SDATA_1V8 11
MIPI_TX_CLK_HS_P 11
MIPI_TX_CLK_HS_N 11
MIPI_TX_DATA_HS_P[1:4] 11
MIPI_TX_DATA_HS_N[1:4] 11
MIPI_TX_CMOS_RST_1V8 11
MIPI_TX_GPIO1 11
MIPI_TX_GPIO2 11
MIPI_TX_GPIO3 11
MIPI_TX_GPIO4 11
MIPI_TX_GPIO5 11
MIPI_TX_CMOS_SCLK_1V8 11
USER_DIPSW[4:5] 18
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MAX 10 FPGA 10M50 Evaluation Kit (6XX-44364R)
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C10.1uF
R1
1.00k
MAX 10 LEFT BANKS
BANK-2BANK-1A
BANK-1B
10M50DAF484
U1A
DIFFIO_RX_L1N/ADC1IN1F5
DIFFIO_RX_L1P/ADC1IN2F4
DIFFIO_RX_L2N/ADC2IN1E4
DIFFIO_RX_L2P/ADC2IN8E3
DIFFIO_RX_L3N/ADC1IN3J8
DIFFIO_RX_L3P/ADC1IN4J9
DIFFIO_RX_L4N/ADC2IN3G4
DIFFIO_RX_L4P/ADC2IN4F3
DIFFIO_RX_L5P/ADC1IN6H3
DIFFIO_RX_L5N/ADC1IN5J4
DIFFIO_RX_L6N/ADC2IN5H4
DIFFIO_RX_L6P/ADC2IN6G3
DIFFIO_RX_L7N/ADC1IN7K5
DIFFIO_RX_L7P/ADC1IN8K6
DIFFIO_RX_L8P/ADC2IN2J3
DIFFIO_RX_L8N/ADC2IN7K4
DIFFIO_RX_L15NK8
VREFB1N0C1
DIFFIO_RX_L19NK2
DIFFIO_RX_L19PL2
DIFFIO_RX_L23NG1
DIFFIO_RX_L21PF2
DIFFIO_RX_L23PF1
DIFFIO_RX_L21NE1
DIFFIO_RX_L24NM4
DIFFIO_RX_L24PM3
DIFFIO_RX_L25NK1
DIFFIO_RX_L25PL1
DIFFIO_RX_L16PD2
TBD1D1
DIFFIO_RX_L29NP4
DIFFIO_RX_L29PP5
DIFFIO_RX_L37NN3
DIFFIO_RX_L37PN2
DIFFIO_RX_L39NR4
DIFFIO_RX_L39PR5
DIFFIO_RX_L40NT1
DIFFIO_RX_L40PT2
DIFFIO_RX_L41NN8
DIFFIO_RX_L41PN9
DIFFIO_RX_L42NP1
DIFFIO_RX_L42PN1
DIFFIO_RX_L43NT3
DIFFIO_RX_L43PU2
DIFFIO_RX_L44NU1
DIFFIO_RX_L44PV1
DIFFIO_RX_L45NU4
DIFFIO_RX_L45PU5
DIFFIO_RX_L46NU3
DIFFIO_RX_L46PV3
DIFFIO_RX_L47NP8
DIFFIO_RX_L47PR7
DIFFIO_RX_L48NW1
DIFFIO_RX_L48PW2
DIFFIO_RX_L60NR1
DIFFIO_RX_L60PR2
VREFB2N0M2
TBD2M1
DIFFIO_RX_L16ND3
DIFFIO_RX_L20NL8
DIFFIO_RX_L20PL9
DIFFIO_RX_L22NH1
DIFFIO_RX_L22PJ1 C3
0.1uF
R2
1.00k
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Copyright (c) 2015, Altera Corporation. All Rights Reserved.Altera Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
MAX10 BANKS 3 & 4
( VCCIO = 2.5V ) ( VCCIO = 2.5V )
OV10640 Interface
OV5640 Interface
User LVDS IO
LI-USB3 CSI-2 TX InterfaceUSER_LVDS_N1USER_LVDS_P1
USER_LVDS_N7USER_LVDS_P7
MIPI_TX_DATA_LP_P3MIPI_TX_DATA_LP_N3
MIPI_TX_DATA_LP_N4MIPI_TX_DATA_LP_P4
MIPI_TX_DATA_LP_P2MIPI_TX_DATA_LP_N2
MIPI_TX_DATA_LP_P1MIPI_TX_DATA_LP_N1
MIPI_TX_CLK_LP_NMIPI_TX_CLK_LP_P
USER_LVDS_N4USER_LVDS_P4
USER_LVDS_N8USER_LVDS_P8USER_LVDS_N6USER_LVDS_P6USER_LVDS_N0USER_LVDS_P0
USER_LVDS_N5USER_LVDS_P5
USER_LVDS_N2USER_LVDS_P2
OV5640_DATA_HS_P2OV5640_DATA_HS_N2
OV5640_DATA_HS_N1OV5640_DATA_HS_P1
OV10640_DATA_HS_P1OV10640_DATA_HS_N1
OV10640_DATA_HS_N2OV10640_DATA_HS_P2
OV10640_DATA_HS_N3OV10640_DATA_HS_P3
OV10640_DATA_HS_P4OV10640_DATA_HS_N4
USER_LVDS_N3USER_LVDS_P3
OV10640_DATA_HS_P[1:4] 12
OV10640_DATA_HS_N[1:4] 12
OV5640_DATA_HS_P[1:2] 13
OV5640_DATA_HS_N[1:2] 13
USER_LVDS_P[0:8] 17
USER_LVDS_N[0:8] 17
MIPI_TX_CLK_LP_P 11
MIPI_TX_CLK_LP_N 11
MIPI_TX_DATA_LP_P[1:4] 11
MIPI_TX_DATA_LP_N[1:4] 11
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BANK-3 BANK-4
MAX 10 BOTTOM BANKS
10M50DAF484
U1B
DIFFIO_RX_B10NY7
DIFFIO_RX_B10PY8
DIFFIO_RX_B12NAB2
DIFFIO_RX_B12PAB3
DIFFIO_RX_B14NY3
DIFFIO_RX_B14PY4
DIFFIO_RX_B17NAA5
DIFFIO_RX_B17PAB5
DIFFIO_RX_B19NAB6
DIFFIO_RX_B19PAB7
DIFFIO_RX_B21NAA8
DIFFIO_RX_B21PAB8
DIFFIO_RX_B23NAA9
DIFFIO_RX_B23PAB9
DIFFIO_RX_B2NV4
DIFFIO_RX_B2PV5
DIFFIO_RX_B4NY1
DIFFIO_RX_B4PY2
DIFFIO_RX_B6NAA1
DIFFIO_RX_B6PAA2
DIFFIO_RX_B8NY5
DIFFIO_RX_B8PY6
DIFFIO_TX_RX_B11NW9
DIFFIO_TX_RX_B11PW10
DIFFIO_TX_RX_B13NW7
DIFFIO_TX_RX_B13PW8
DIFFIO_TX_RX_B15NR10
DIFFIO_TX_RX_B15PP10
DIFFIO_TX_RX_B16NAA6
DIFFIO_TX_RX_B16PAA7
DIFFIO_TX_RX_B1NW5
DIFFIO_TX_RX_B1PW6
DIFFIO_TX_RX_B22NY10
DIFFIO_TX_RX_B22PAA10
DIFFIO_TX_RX_B3NU6
DIFFIO_TX_RX_B3PU7
DIFFIO_TX_RX_B5NW4
DIFFIO_TX_RX_B5PW3
DIFFIO_TX_RX_B7NV7
DIFFIO_TX_RX_B7PV8
DIFFIO_TX_RX_B9NR9
DIFFIO_TX_RX_B9PP9
VREFB3N0AA3
TBD3AB4
DIFFIO_RX_B25NW11
DIFFIO_RX_B25PY11
DIFFIO_RX_B27NAB10
DIFFIO_RX_B27PAB11
DIFFIO_RX_B29NAB12
DIFFIO_RX_B29PAB13
DIFFIO_RX_B35NW12
DIFFIO_RX_B35PW13
DIFFIO_RX_B38NAA14
DIFFIO_RX_B38PAB15
DIFFIO_RX_B40NAA15
DIFFIO_RX_B40PY16
DIFFIO_RX_B42NAB16
DIFFIO_RX_B42PAA16
DIFFIO_RX_B44NAB19
DIFFIO_RX_B44PAB20
DIFFIO_RX_B46NAA19
DIFFIO_RX_B46PY18
DIFFIO_RX_B50NAB21
DIFFIO_RX_B50PAA20
DIFFIO_RX_B58NAB17
DIFFIO_RX_B58PAB18
DIFFIO_TX_RX_B24NV11
DIFFIO_TX_RX_B24PV12
DIFFIO_TX_RX_B26NR12
DIFFIO_TX_RX_B26PP12
DIFFIO_TX_RX_B28NAA11
DIFFIO_TX_RX_B28PAA12
DIFFIO_TX_RX_B34NV13
DIFFIO_TX_RX_B34PW14
DIFFIO_TX_RX_B36NR13
DIFFIO_TX_RX_B36PP13
DIFFIO_TX_RX_B37NY13
DIFFIO_TX_RX_B37PY14
DIFFIO_TX_RX_B39NV14
DIFFIO_TX_RX_B39PW15
DIFFIO_TX_RX_B41NU15
DIFFIO_TX_RX_B41PV16
DIFFIO_TX_RX_B43NAA17
DIFFIO_TX_RX_B43PY17
DIFFIO_TX_RX_B45NV15
DIFFIO_TX_RX_B45PW16
DIFFIO_TX_RX_B49NY19
DIFFIO_TX_RX_B49PW18
VREFB4N0AA13
TBD4AB14
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Altera Corporation, 301, Bibo Rd #888, Shanghai, China, 201203Copyright (c) 2015, Altera Corporation. All Rights Reserved.
MAX10 BANKS 5 & 6
( VCCIO = 1.2V ) ( VCCIO = 1.2V )
LPDDR2 Interface
OV10640 Interface
OV5640 Interface
User Pushbuttons
Reference Voltages of 1.2V HSTL and LPDDR2
User DIP Switch
U22 and U21 are restricted pinswhile implementating LPDDR2.
L22 and M21 are restricted pinswhile implementating LPDDR2.
F21 and F20 are restricted pinswhile implementating LPDDR2.
F18 and E19 are restricted pinswhile implementating LPDDR2.
E17 and F17 are restricted pinswhile implementating LPDDR2.
OV5640_CLK_LP_P
MAX10_RUPMAX10_RDN
OV5640_CLK_LP_N
LPDDR2_DQ3LPDDR2_DQ5
LPDDR2_DQ7
LPDDR2_DQ0LPDDR2_DQ2LPDDR2_DQ1
LPDDR2_DQ4LPDDR2_DQ6
LPDDR2_DQ15LPDDR2_DQ10LPDDR2_DQ8LPDDR2_DQ9
LPDDR2_DQ14
LPDDR2_DQ11LPDDR2_DQ12
LPDDR2_CA3LPDDR2_CA4LPDDR2_CA1LPDDR2_CA0
LPDDR2_CA2LPDDR2_CSn
LPDDR2_CKELPDDR2_CA7
LPDDR2_CA8
LPDDR2_CA9
LPDDR2_CA6LPDDR2_CA5
LPDDR2_DM1
LPDDR2_DQS1LPDDR2_DQS1n
LPDDR2_DQ13
LPDDR2_DM0
LPDDR2_CKLPDDR2_CKn
OV10640_DATA_LP_N3OV10640_DATA_LP_P3OV5640_DATA_LP_N1OV5640_DATA_LP_P1
OV10640_DATA_LP_N2OV10640_DATA_LP_P2
OV10640_CLK_LP_NOV10640_CLK_LP_P
OV10640_DATA_LP_N4OV10640_DATA_LP_P4OV5640_DATA_LP_N2OV5640_DATA_LP_P2OV10640_DATA_LP_N1OV10640_DATA_LP_P1
USER_DIPSW1USER_DIPSW2
USER_DIPSW0
USER_DIPSW3
USER_PB3
USER_PB2USER_PB1
USER_PB0
1.2V_VCCIO
VREF_1V2HSTL
1.2V_VCCIO
VREF_LPDDR2
1.2V_VCCIO
VREF_1V2HSTL
VREF_LPDDR2
LPDDR2_DQ[0:15] 10
LPDDR2_DQS1 10
LPDDR2_DQS1n 10
LPDDR2_CK 10
LPDDR2_CKn 10
LPDDR2_CKE 10
LPDDR2_CSn 10
LPDDR2_DM[0:1] 10
LPDDR2_CA[0:9] 10
OV10640_CLK_LP_P 12
OV10640_CLK_LP_N 12
OV10640_DATA_LP_P[1:4] 12
OV10640_DATA_LP_N[1:4] 12
OV5640_CLK_LP_P 13
OV5640_CLK_LP_N 13
OV5640_DATA_LP_P[1:2] 13
OV5640_DATA_LP_N[1:2] 13
USER_PB[0:3] 18
USER_DIPSW[0:3] 18
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MAX 10 FPGA 10M50 Evaluation Kit (6XX-44364R)
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R121.00k
C6
0.1uF
R111.00k
R8 47.5
C8
0.1uF
BANK-5 BANK-6
MAX 10 RIGHT BANKS
10M50DAF484
U1C
DIFFIO_RX_R19NU19
DIFFIO_RX_R19PV18
DIFFIO_RX_R1N/RDNU17 DIFFIO_RX_R1P/RUPU18
DIFFIO_RX_R20NW22
DIFFIO_RX_R20PY22
DIFFIO_RX_R21NW20
DIFFIO_RX_R21PW19
DIFFIO_RX_R22NY21
DIFFIO_RX_R22PY20
DIFFIO_RX_R23NU20
DIFFIO_RX_R23PV20
DIFFIO_RX_R24NV22
DIFFIO_RX_R24PV21
DIFFIO_RX_R25N/DQ1RR14
DIFFIO_RX_R25P/DQ1RR15
DIFFIO_RX_R26NT22
DIFFIO_RX_R26PT21
DIFFIO_RX_R27N/DM1RT18
DIFFIO_RX_R27P/DQ1RT19
DIFFIO_RX_R28N/DQ1RR20
DIFFIO_RX_R28P/DQ1RT20
DIFFIO_RX_R29NU22
DIFFIO_RX_R29PU21
DIFFIO_RX_R2NAA22
DIFFIO_RX_R2PAA21
DIFFIO_RX_R30N/DQ1RP14
DIFFIO_RX_R30P/DQ1RP15
DIFFIO_RX_R31NN22
DIFFIO_RX_R31PP21
DIFFIO_RX_R32N/DQSN1RP18
DIFFIO_RX_R32P/DQS1RR18
DIFFIO_RX_R33N/DQ1RP20
DIFFIO_RX_R33P/DQ1RP19
DIFFIO_RX_R34NL22
DIFFIO_RX_R34PM21
DIFFIO_RX_R35NM22
DIFFIO_RX_R35PN21
TBD5R22 VREFB5N0P22
DIFFIO_RX_R39NH21
DIFFIO_RX_R39PH22
DIFFIO_RX_R41NJ21
DIFFIO_RX_R41PJ22
DIFFIO_RX_R42NG19
DIFFIO_RX_R42PG20
DIFFIO_RX_R43NF22
DIFFIO_RX_R43PG22
DIFFIO_RX_R44N/DQ2RM14
DIFFIO_RX_R44P/DQ2RM15
DIFFIO_RX_R45NE21
DIFFIO_RX_R45PE22
DIFFIO_RX_R46N/DM2RN19
DIFFIO_RX_R46P/DQ2RN18
DIFFIO_RX_R47P/DQ2RM20
DIFFIO_RX_R47N/DQ2RN20
DIFFIO_RX_R48NF20
DIFFIO_RX_R48PF21
VREFB6N0D21
DIFFIO_RX_R49PD22
DIFFIO_RX_R51N/DQ2RL18
DIFFIO_RX_R51P/DQ2RM18
DIFFIO_RX_R52N/DQ2RL20
DIFFIO_RX_R52P/DQ2RL19
DIFFIO_RX_R53NF18
DIFFIO_RX_R53PE19
DIFFIO_RX_R54NE20
DIFFIO_RX_R54PF19
DIFFIO_RX_R55N/DQSN3RK15
DIFFIO_RX_R55P/DQS3RK14
DIFFIO_RX_R56ND19
DIFFIO_RX_R56PC20
DIFFIO_RX_R57N/DQ3RJ18
DIFFIO_RX_R57P/DQ3RK18
DIFFIO_RX_R58N/DQ3RK20
DIFFIO_RX_R58P/DQ3RK19
DIFFIO_RX_R59NE17
DIFFIO_RX_R59PF17
DIFFIO_RX_R60NB21
DIFFIO_RX_R60PB22
DIFFIO_RX_R61N/DM3RJ15
DIFFIO_RX_R61P/DQ3RJ14
DIFFIO_RX_R62NA21
DIFFIO_RX_R62PB20
DIFFIO_RX_R63N/DQ3RH18
DIFFIO_RX_R63P/DQ3RH19
DIFFIO_RX_R64N/DQ3RH20
DIFFIO_RX_R64P/DQ3RJ20
DIFFIO_RX_R70N/CK#_6E18
DIFFIO_RX_R70P/CK_6D18
DIFFIO_RX_R49NC22
TBD6C21
R91.00k
C4
0.1uF
C9
0.1uF
R7 47.5
R101.00k
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Altera Corporation, 301, Bibo Rd #888, Shanghai, China, 201203Copyright (c) 2015, Altera Corporation. All Rights Reserved.
( VCCIO = 3.3V ) ( VCCIO = 3.3V )
MAX10 BANKS 7 & 8
PMOD
User IO
HDMI TX
Flash
LI-USB3 CSI-2 TX Interface
User LED
HDMI_VIDEO_DIN14
HDMI_VIDEO_DIN15
FLASH_D3
FLASH_D1FLASH_D2
HDMI_VIDEO_DIN16
HDMI_VIDEO_DIN0
HDMI_VIDEO_DATA_EN
HDMI_HSYNC
HDMI_VSYNC
USER_IO3
USER_IO6USER_IO5
USER_IO1
USER_IO7
USER_IO8USER_IO9
USER_IO4
USER_IO2HDMI_VIDEO_DIN3
HDMI_VIDEO_DIN2
HDMI_VIDEO_DIN4
HDMI_VIDEO_DIN1
HDMI_VIDEO_DIN22
HDMI_VIDEO_DIN21
HDMI_VIDEO_DIN18
HDMI_VIDEO_DIN19
HDMI_VIDEO_DIN23
HDMI_VIDEO_DIN20HDMI_VIDEO_DIN17
HDMI_SCL
HDMI_SDA
HDMI_INTRUSER_IO0
HDMI_VIDEO_DIN5HDMI_VIDEO_DIN6
HDMI_VIDEO_DIN7
HDMI_VIDEO_DIN8HDMI_VIDEO_DIN9
HDMI_VIDEO_DIN10HDMI_VIDEO_DIN12
HDMI_VIDEO_DIN11
HDMI_VIDEO_DIN13
PMODA_D0PMODA_D4
PMODA_D6PMODA_D3
PMODB_D3PMODB_D2PMODB_D4PMODA_D2
PMODB_D6PMODB_D7PMODB_D5
PMODA_D7
MIPI_TX_CMOS_SCLK_3V3MIPI_TX_CMOS_SDATA_3V3
FLASH_RESETn FLASH_RESETn_MAX10
FLASH_CSn
FLASH_D0
FLASH_CLK
USER_LED0
USER_LED1
USER_LED2USER_LED3
USER_LED4
PMODA_D1
PMODA_D5
PMODB_D1
PMODB_D0
MIPI_TX_CMOS_RST_3V3
PMODB_D[7:0] 17
PMODA_D[7:0] 17
USER_IO[0:9] 17
HDMI_VIDEO_DIN[23:0] 14
HDMI_HSYNC 14
HDMI_VSYNC 14
HDMI_VIDEO_DATA_EN 14
HDMI_INTR 14
HDMI_SDA 14
HDMI_SCL 14
FLASH_D[0:3] 25
FLASH_CSn 25
FLASH_CLK 25
FLASH_RESETn 15,25
MIPI_TX_CMOS_SDATA_3V3 11
MIPI_TX_CMOS_SCLK_3V3 11
USER_LED[0:4] 18
MIPI_TX_CMOS_RST_3V3 11
Title
Size Document Number Rev
Date: Sheet o f
<Doc> A1.2
MAX 10 FPGA 10M50 Evaluation Kit (6XX-44364R)
A3
7 25Thursday, March 24, 2016
Title
Size Document Number Rev
Date: Sheet o f
<Doc> A1.2
MAX 10 FPGA 10M50 Evaluation Kit (6XX-44364R)
A3
7 25Thursday, March 24, 2016
Title
Size Document Number Rev
Date: Sheet o f
<Doc> A1.2
MAX 10 FPGA 10M50 Evaluation Kit (6XX-44364R)
A3
7 25Thursday, March 24, 2016
BANK-7 BANK-8
MAX 10 TOP BANKS
10M50DAF484
U1D
DIFFIO_RX_T10NA17
DIFFIO_RX_T10PA18
DIFFIO_RX_T15NC15
DIFFIO_RX_T15PC16
DIFFIO_RX_T16NA16
DIFFIO_RX_T16PB16
DIFFIO_RX_T17NJ13
DIFFIO_RX_T17PH14
DIFFIO_RX_T18NC13
DIFFIO_RX_T18PC14
DIFFIO_RX_T19NB14
DIFFIO_RX_T19PA14
DIFFIO_RX_T1NE15
DIFFIO_RX_T1PE16
DIFFIO_RX_T20NE13
DIFFIO_RX_T20PD14
DIFFIO_RX_T21PE12
DIFFIO_RX_T21ND13
DIFFIO_RX_T22NJ12
DIFFIO_RX_T22PH13
DIFFIO_RX_T23NA12
DIFFIO_RX_T23PA13
DIFFIO_RX_T24ND12
DIFFIO_RX_T24PC12
DIFFIO_RX_T25NA10
DIFFIO_RX_T25PA11
DIFFIO_RX_T26NC10
DIFFIO_RX_T26PC11
DIFFIO_RX_T27NB11
DIFFIO_RX_T27PB12
DIFFIO_RX_T28NJ11
DIFFIO_RX_T28PH12
DIFFIO_RX_T31NB8
DIFFIO_RX_T31PA9
DIFFIO_RX_T2NC17
DIFFIO_RX_T2PD17
DIFFIO_RX_T30NC9
DIFFIO_RX_T30PB10
DIFFIO_RX_T29PA7
DIFFIO_RX_T29NA8
DIFFIO_RX_T5NF15
DIFFIO_RX_T5PF16
DIFFIO_RX_T6NB19
DIFFIO_RX_T6PC19
DIFFIO_RX_T7NB17
DIFFIO_RX_T7PC18
DIFFIO_RX_T8NA19
DIFFIO_RX_T8PA20
DIFFIO_RX_T9NE14
DIFFIO_RX_T9PD15
TBD7A15 VREFB7N0B15
DIFFIO_RX_T39NC7
DIFFIO_RX_T39PC8
DIFFIO_RX_T41NA6
DIFFIO_RX_T41PB7
DIFFIO_RX_T42PD8
DIFFIO_RX_T43NA4
DIFFIO_RX_T43PA5
DIFFIO_RX_T44NE9
DIFFIO_RX_T45PA2
DIFFIO_RX_T45NA3
DIFFIO_RX_T46PB3
DIFFIO_RX_T46NB4
DIFFIO_RX_T49ND5
DIFFIO_RX_T49PC5
DIFFIO_RX_T51NB1
DIFFIO_RX_T51PB2
DIFFIO_RX_T53PC3
VREFB8N0D7
TBD8C6
DIFFIO_RX_T47PB5
DIFFIO_RX_T47NC4
DIFFIO_RX_T48PE8
DIFFIO_RX_T53NC2
R250 0
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Altera Corporation, 301, Bibo Rd #888, Shanghai, China, 201203Copyright (c) 2015, Altera Corporation. All Rights Reserved.
( VCCIO = 1.8V )
( VCCIO = 2.5V )
( VCCIO = 2.5V )
( VCCIO = 1.2V )
( VCCIO = 3.3V )
MAX10 CLOCKS
LPDDR2 Interface
Si5338
HDMI
USB Blaster II
User LVDS
OV5640 Interface
OV10640 Interface
Note: CLK125M_LVDS is the clocksource provided to external LVDS user interface.USER_CLKIN_P is used for external sigle-endedclock input.USER_CLKIN_P/N is used for external differentialclock input.
LPDDR2_DQS0LPDDR2_DQS0n
CLK24M
HDMI_VIDEO_CLK
CLK100M_LPDDR2_BKDIV
CLK125M_DIV_R
CLK125M
OV10640_24MHz
CLK100M_LPDDR2USB_CLK
CLK100M_LPDDR2_BK
CLKOUT_LVDS_NCLKOUT_LVDS_P
USER_CLKIN_N_MAX10
CLK50M_MAX10
USER_CLKIN_P_MAX10
USER_CLKIN_P
OV5640_CLK_HS_NOV5640_CLK_HS_POV10640_CLK_HS_NOV10640_CLK_HS_P
LPDDR2_DQS0 10
LPDDR2_DQS0n 10
CLK50M_MAX10 19
CLK24M 19
CLK125M 19
CLK100M_LPDDR2 19
CLK100M_LPDDR2_BK 19
HDMI_VIDEO_CLK 14
USB_CLK 15
OV10640_24MHz 12
CLKOUT_LVDS_P 17
CLKOUT_LVDS_N 17
OV5640_CLK_HS_P 13
OV5640_CLK_HS_N 13
OV10640_CLK_HS_P 12
OV10640_CLK_HS_N 12
USER_CLKIN_P 17
USER_CLKIN_N_MAX10 17
Title
Size Document Number Rev
Date: Sheet o f
<Doc> A1.2
MAX 10 FPGA 10M50 Evaluation Kit (6XX-44364R)
A3
8 25Thursday, March 24, 2016
Title
Size Document Number Rev
Date: Sheet o f
<Doc> A1.2
MAX 10 FPGA 10M50 Evaluation Kit (6XX-44364R)
A3
8 25Thursday, March 24, 2016
Title
Size Document Number Rev
Date: Sheet o f
<Doc> A1.2
MAX 10 FPGA 10M50 Evaluation Kit (6XX-44364R)
A3
8 25Thursday, March 24, 2016
R18100.0
R17200
R270
0
R271
DNI
R19200
R20100.0
BANK-2
MAX 10 CLOCK
BANK-3
BANK-4
BANK-6
BANK-8
10M50DAF484
U1E
DIFFIO_RX_L28N/CLK0NN4
DIFFIO_RX_L28P/CLK0PN5
DIFFIO_RX_L36N/CLK1NM8
DIFFIO_RX_L36P/CLK1PM9
DIFFIO_TX_RX_B18N/CLK6NV9
DIFFIO_TX_RX_B18P/CLK6PV10
DIFFIO_TX_RX_B20N/CLK7NR11
DIFFIO_TX_RX_B20P/CLK7PP11
DIFFIO_RX_R38N/CLK2NN15
DIFFIO_RX_R38P/CLK2PN14
DIFFIO_RX_R40N/CLK3NK21
DIFFIO_RX_R40P/CLK3PK22
DIFFIO_RX_T38N/CLK4NE10
DIFFIO_RX_T38P/CLK4PE11
DIFFIO_RX_T40P/CLK5PJ10
DIFFIO_RX_T40N/CLK5NH11
DIFFIO_RX_L38N/DPCLK0P3
DIFFIO_RX_L38P/DPCLK1R3
DIFFIO_RX_L59N/PLL_L_CLKOUTNT5
DIFFIO_RX_L59P/PLL_L_CLKOUTPT6
DIFFIO_TX_RX_B57N/PLL_B_CLKOUTNW17
DIFFIO_TX_RX_B57P/PLL_B_CLKOUTPV17
DIFFIO_RX_R50N/DPCLK2/DQSn2RL15
DIFFIO_RX_R50P/DPCLK3/DQS2RL14
DIFFIO_RX_R69N/PLL_R_CLKOUTNG17
DIFFIO_RX_R69P/PLL_R_CLKOUTPH17
DIFFIO_RX_T52N/PLL_T_CLKOUTNE6
DIFFIO_RX_T52P/PLL_T_CLKOUTPD6
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Altera Corporation, 301, Bibo Rd #888, Shanghai, China, 201203Copyright (c) 2015, Altera Corporation. All Rights Reserved.
( VCCIO = 3.3V ) ( VCCIO = 3.3V )
MAX10 CONFIGURATION
Configuration
MAX10_RESETn
MAX10_nSTATUS
MAX10_JTAG_TCK
MAX10_JTAG_TDO_3V3
MAX10_JTAG_TMSMAX10_CONFIG_SELMAX10_nCONFIG
MAX10_CONF_DONE
MAX10_JTAG_TDI
MAX10_JTAGEN
MAX10_JTAG_TDO
3.3V
2.5V
MAX10_nCONFIG 18
MAX10_RESETn 18
MAX10_CONFIG_SEL 18
MAX10_nSTATUS 15
MAX10_CONF_DONE 15
MAX10_JTAGEN 16
MAX10_JTAG_TCK 16
MAX10_JTAG_TMS 16
MAX10_JTAG_TDI 16
MAX10_JTAG_TDO 16
Title
Size Document Number Rev
Date: Sheet o f
<Doc> A1.2
MAX 10 FPGA 10M50 Evaluation Kit (6XX-44364R)
A3
9 25Thursday, March 24, 2016
Title
Size Document Number Rev
Date: Sheet o f
<Doc> A1.2
MAX 10 FPGA 10M50 Evaluation Kit (6XX-44364R)
A3
9 25Thursday, March 24, 2016
Title
Size Document Number Rev
Date: Sheet o f
<Doc> A1.2
MAX 10 FPGA 10M50 Evaluation Kit (6XX-44364R)
A3
9 25Thursday, March 24, 2016
R27 10.0K
R21 10.0K
R25 10.0K
R28 10.0K
R314 22.0
MAX 10 Configuration
BANK-1B BANK-8
10M50DAF484
U1F
DIFFIO_RX_L15P/JTAGENK9
DIFFIO_RX_L17P/TCKG2
DIFFIO_RX_L17N/TMSH2
DIFFIO_RX_L18N/TDIL4
DIFFIO_RX_L18P/TDOM5
DIFFIO_RX_T42N/DEV_CLRND9
DIFFIO_RX_T44P/DEV_OED10
NCONFIGH9
BOOT_SELH10
DIFFIO_RX_T48N/CRC_ERRORF7
DIFFIO_RX_T50P/NSTATUSG9
DIFFIO_RX_T50N/CONF_DONEF8
R23 1.00k
R22DNI
R24 10.0K
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Altera Corporation, 301, Bibo Rd #888, Shanghai, China, 201203Copyright (c) 2015, Altera Corporation. All Rights Reserved.
LPDDR2 SDRAM x 16
CAD Note:Place resistors near LPDDR2 VREFCA and VREFDQ pins
LPDDR2 Interface
LPDDR2 Power Decoupling
CAD Note:Place decoupling caps near LPDDR2.
CAD Note:Place decoupling caps near LPDDR2.
LPDDR2_CA0LPDDR2_CA1LPDDR2_CA2LPDDR2_CA3LPDDR2_CA4LPDDR2_CA5LPDDR2_CA6LPDDR2_CA7LPDDR2_CA8LPDDR2_CA9
LPDDR2_CKELPDDR2_CKLPDDR2_CKn
LPDDR2_CSn
LPDDR2_DM0LPDDR2_DM1
LPDDR2_DQS0LPDDR2_DQS0n
LPDDR2_DQS1LPDDR2_DQS1n
LPDDR2_DQ0LPDDR2_DQ1LPDDR2_DQ2LPDDR2_DQ3LPDDR2_DQ4LPDDR2_DQ5LPDDR2_DQ6LPDDR2_DQ7LPDDR2_DQ8LPDDR2_DQ9LPDDR2_DQ10LPDDR2_DQ11LPDDR2_DQ12LPDDR2_DQ13LPDDR2_DQ14LPDDR2_DQ15
LPDDR2_ZQ
LPDDR2_VREFCALPDDR2_VREFDQ
1.8V
1.2V_VCCIO
1.2V_VCCIO
1.2V_VCCIO
1.8V1.2V_VCCIO
LPDDR2_DQ[0:15] 6
LPDDR2_CA[0:9] 6
LPDDR2_CKE 6
LPDDR2_CK 6
LPDDR2_CKn 6
LPDDR2_CSn 6
LPDDR2_DM[0:1] 6
LPDDR2_DQS0 8
LPDDR2_DQS1 6
LPDDR2_DQS1n 6
LPDDR2_DQS0n 8
Title
Size Document Number Rev
Date: Sheet o f
<Doc> A1.2
MAX 10 FPGA 10M50 Evaluation Kit (6XX-44364R)
A3
10 25Thursday, March 24, 2016
Title
Size Document Number Rev
Date: Sheet o f
<Doc> A1.2
MAX 10 FPGA 10M50 Evaluation Kit (6XX-44364R)
A3
10 25Thursday, March 24, 2016
Title
Size Document Number Rev
Date: Sheet o f
<Doc> A1.2
MAX 10 FPGA 10M50 Evaluation Kit (6XX-44364R)
A3
10 25Thursday, March 24, 2016
C241
0.1uF
C23
4.7nF
R291.00k
C22
4.7nF
R341.00k
C244
0.1uF
C247
0.1uF
C242
0.1uF
LPDDR2_IS43LD16640A-25BL
U2B
VDD2B5
VDD1B6
VDD1C1
VSSC2
VSSC5
VSSD1
VDD2D2
VDD2G1
VSSH2
VDD2J7
VSSJ8
VSSP1
VDD2P2
VDD1R1
VSSR2
VSSR5
VDD2T5
VDD1T6
VSSQC6
VDDQC7
VSSQC9
VDDQC10
VDDQD5
VSSQD10
VSSCAE1
VDDQE9
VSSQE10
VDDCAF1
VSSQF5
VDDQF10
VREFCAG3
VSSQG10
VDDCAH1
VDDQH6
VSSCAJ1
VSSQJ5
VDDQJ6
VREFDQJ9
VDDQK6
VSSQL10
VSSQM5
VDDQM10
VSSCAN1
VDDCAN2
VDDQN9
VSSQN10
VDDQP5
VSSQP10
VSSQR6
VDDQR7
VSSQR9
VDDQR10
C27
0.1uF
C110.1uF
C14
4.7UF
C16
0.1uF
C21
0.01uF
C15
0.1uF
R33DNI
C18
22nF
C246
0.1uF
C25
2200pF
C100.1uF
C19
22nF
R314.7k
R301.00k
LPDDR2_IS43LD16640A-25BL
U2A
DNU0A1
DNU1A2
DNU2A9
DNU3A10
DNU4B1
NC0B2
NC1B3
NC2B7
NC3B8
NC4B9
DNU5B10
NC5C8
ZQD3
NC6D6
NC7D7
NC8D8
NC9D9
CA9E2 CA8E3
NC10E5
NC11E6
NC12E7
CA6F2
CA7F3
CA5G2
CK#H3
DM1H5
NC13J2
CKJ3 CKEK1
DM0K5
CS#L1
CA4M1 CA3M2 CA2M3 CA1N3
NC14N5
NC15N6
NC16N7
CA0P3
NC17P6
NC18P7
NC19P8
NC20P9
NC21R3
NC22R8
DNU6T1
NC23T2
NC24T3
NC25T7
NC26T8
NC27T9
DNU7T10
DNU8U1
DNU9U2
DNU10U9
DNU11U10
RFU0C3
DQ15E8
DQ11F6
DQ13F7
DQ14F8
DQ12F9
DQS1G6
DQS1#G5
DQ10G7DQ9G8DQ8G9
RFU1K2
RFU2K3
RFU3L2
RFU4L3
DQS0#L5DQS0L6
DQ5L7
DQ6L8
DQ7L9
DQ4M6
DQ2M7DQ1M8
DQ3M9
DQ0N8
C245
0.1uF
R321.00k
C17
0.1uF
R35
240
C13
10uF
C243
0.1uF
C20
0.01uF
C26
4.7UF
C24
2200pF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Altera Corporation, 301, Bibo Rd #888, Shanghai, China, 201203Copyright (c) 2015, Altera Corporation. All Rights Reserved.
MIPI CSI-2 TX D-PHY
LI-USB3 CSI-2 TX Interface
CAD Note:Place C29 and C30 near J1 connector.
CAD Note:Place resistors near FPGA side.
CAD Note:Place resistors near FPGA side.
CAD Note:Place resistors near FPGA side.
CAD Note:Place resistors near FPGA side.
CAD Note:Place resistors near FPGA side.
Pull-up Options for MIPI TX
MIPI_TX_DATA1PMIPI_TX_DATA1N
MIPI_TX_CLKPMIPI_TX_CLKN
MIPI_TX_DATA2PMIPI_TX_DATA2N
MIPI_TX_DATA3PMIPI_TX_DATA3N
MIPI_TX_DATA4PMIPI_TX_DATA4N
MIPI_TX_CMOS_RST_IOMIPI_TX_CMOS_SDATAMIPI_TX_CMOS_SCLKMIPI_TX_CLK24MHz
1.8V_MIPITX
3.3V_MIPITX
MIPI_TX_GPIO1MIPI_TX_GPIO2
MIPI_TX_GPIO3MIPI_TX_GPIO4MIPI_TX_GPIO5
MIPI_TX_GPIO1_IOMIPI_TX_GPIO2_IO
MIPI_TX_GPIO3_IOMIPI_TX_GPIO4_IOMIPI_TX_GPIO5_IO
MIPI_TX_DATA1P
MIPI_TX_DATA1N
MIPI_TX_DATA2P
MIPI_TX_DATA2N
MIPI_TX_CLK_HS_P
MIPI_TX_CLK_LP_P
MIPI_TX_CLK_LP_N
MIPI_TX_CLK_HS_N
MIPI_TX_DATA_HS_P1
MIPI_TX_DATA_LP_P1
MIPI_TX_DATA_LP_N1
MIPI_TX_DATA_HS_N1
MIPI_TX_DATA_HS_P2
MIPI_TX_DATA_LP_P2
MIPI_TX_DATA_LP_N2
MIPI_TX_DATA_HS_N2
MIPI_TX_CLKP
MIPI_TX_CLKN
MIPI_TX_DATA4P
MIPI_TX_DATA4N
MIPI_TX_DATA_HS_P3
MIPI_TX_DATA_LP_P3
MIPI_TX_DATA_LP_N3
MIPI_TX_DATA_HS_N3
MIPI_TX_DATA_HS_P4
MIPI_TX_DATA_LP_P4
MIPI_TX_DATA_LP_N4
MIPI_TX_DATA_HS_N4
MIPI_TX_DATA3P
MIPI_TX_DATA3N
MIPI_TX_CMOS_SCLK
MIPI_TX_CMOS_SCLK_1V8
MIPI_TX_CMOS_SCLK_3V3
MIPI_TX_CMOS_SDATA
MIPI_TX_CMOS_SDATA_1V8
MIPI_TX_CMOS_SDATA_3V3
MIPI_TX_CMOS_RST_1V8
MIPI_TX_CMOS_RST_IOMIPI_TX_CMOS_RST_3V3
3.3V
1.8V
1.8V
3.3V
3.3V1.8V
3.3V1.8V
MIPI_TX_GPIO1 4
MIPI_TX_GPIO2 4
MIPI_TX_GPIO3 4
MIPI_TX_GPIO4 4
MIPI_TX_CMOS_RST_1V8 4
MIPI_TX_CMOS_SDATA_1V8 4
MIPI_TX_GPIO5 4
MIPI_TX_CLK_HS_P 4
MIPI_TX_CLK_HS_N 4
MIPI_TX_DATA_HS_P[1:4] 4
MIPI_TX_DATA_HS_N[1:4] 4
MIPI_TX_CLK_LP_P 5
MIPI_TX_CLK_LP_N 5
MIPI_TX_DATA_LP_P[1:4] 5
MIPI_TX_DATA_LP_N[1:4] 5
MIPI_TX_CLK24MHz 19
MIPI_TX_CMOS_SCLK_1V8 4
MIPI_TX_CMOS_SCLK_3V3 7
MIPI_TX_CMOS_SDATA_3V3 7
MIPI_TX_CMOS_RST_3V3 7
Title
Size Document Number Rev
Date: Sheet o f
<Doc> A1.2
MAX 10 FPGA 10M50 Evaluation Kit (6XX-44364R)
A3
11 25Thursday, March 24, 2016
Title
Size Document Number Rev
Date: Sheet o f
<Doc> A1.2
MAX 10 FPGA 10M50 Evaluation Kit (6XX-44364R)
A3
11 25Thursday, March 24, 2016
Title
Size Document Number Rev
Date: Sheet o f
<Doc> A1.2
MAX 10 FPGA 10M50 Evaluation Kit (6XX-44364R)
A3
11 25Thursday, March 24, 2016
R47 100.0
TP16
C30DNI
R294 DNI
J1
FFC_CONN_1x36
11 22 33 44 55 66 77 88 99 10
10 1111 1212 1313 1414 1515 1616 1717 1818 1919 2020 2121 2222 2323 2424 2525 2626 2727 2828 2929 3030 3131 3232 3333 3434 3535 3636
SP1G1SP2G2
SP3G3SP4G4
R308DNI
R51100.0
TP20
TP34
TP25
R312 DNI
R56 150
R302 DNI
R304 DNI
TP13
R44 150
R66100.0
R37 100.0
R52100.0
R306DNI
R41 150
R45100.0
R303DNI
R62 150
C28
DNI
TP22
R36 100.0
TP27
R50 150
R60 100.0
R43100.0
TP15
TP19
TP33
R63100.0
R48 100.0
TP31
TP10
TP8
R61 DNI
R49 100.0
R305DNI
R59 100.0
R273 DNI
R307 DNI
R313 DNI
R39100.0
R277 DNI
R53 150
TP7
R55100.0
TP21
R40 150
TP26
R65 150
R309DNI
R276 DNI
TP14
R67 100.0
R68DNI
R54 150
TP32
R275 DNI
R58 100.0
R42 150
R274 DNI
R38100.0
R57100.0
C29
DNI
TP28
R46 100.0TP11
R64 DNI
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Altera Corporation, 301, Bibo Rd #888, Shanghai, China, 201203Copyright (c) 2015, Altera Corporation. All Rights Reserved.
MIPI CSI-2 RX D-PHY OV10640
OV10640 CSI-2 RX Interface
CAD Note:Place capacitors near J2 connector.
CAD Note:Place resistors near FPGA side.
CAD Note:Place resistors near FPGA side.
CAD Note:Place resistors near FPGA side.
CAD Note:Place resistors near FPGA side.
CAD Note:Place resistors near FPGA side.
OV10640_CMOS_SDATA
OV10640_CMOS_SCLK
OV10640_CMOS_RST
3.3V_OV10640
1.8V_OV10640
OV10640_CMOS_RSTOV10640_CMOS_SDATAOV10640_CMOS_SCLKOV10640_24MHz_IOOV10640_GYRO_INTOV10640_G_RDY
OV10640_XM_INT2OV10640_XM_INT1OV10640_FSIN
OV10640_DATA_HS_N1OV10640_DATA_HS_P1
OV10640_CLK_HS_POV10640_CLK_HS_N
OV10640_DATA_HS_P2OV10640_DATA_HS_N2
OV10640_DATA_HS_P3OV10640_DATA_HS_N3
OV10640_DATA_HS_P4OV10640_DATA_HS_N4
OV10640_24MHz
OV10640_DATA_HS_P1
OV10640_DATA_HS_N1
OV10640_DATA_HS_P2
OV10640_DATA_HS_N2
OV10640_CLK_HS_N
OV10640_DATA_LP_P1
OV10640_DATA_LP_N1
OV10640_DATA_LP_P2
OV10640_DATA_LP_N2
OV10640_DATA_HS_P3
OV10640_DATA_HS_N3
OV10640_DATA_HS_P4
OV10640_DATA_HS_N4
OV10640_DATA_LP_P3
OV10640_DATA_LP_N3
OV10640_DATA_LP_P4
OV10640_DATA_LP_N4
OV10640_CLK_HS_P
OV10640_CLK_LP_P
OV10640_CLK_LP_N
1.8V
3.3V
1.8V
OV10640_GYRO_INT 4
OV10640_G_RDY 4
OV10640_XM_INT2 4
OV10640_XM_INT1 4
OV10640_CMOS_RST 4
OV10640_CMOS_SCLK 4
OV10640_CMOS_SDATA 4
OV10640_FSIN 4
OV10640_CLK_LP_P 6
OV10640_CLK_LP_N 6
OV10640_DATA_LP_P[1:4] 6
OV10640_DATA_LP_N[1:4] 6
OV10640_CLK_HS_P 8
OV10640_CLK_HS_N 8
OV10640_DATA_HS_P[1:4] 5
OV10640_DATA_HS_N[1:4] 5
OV10640_24MHz 8
Title
Size Document Number Rev
Date: Sheet o f
<Doc> A1.2
MAX 10 FPGA 10M50 Evaluation Kit (6XX-44364R)
A3
12 25Thursday, March 24, 2016
Title
Size Document Number Rev
Date: Sheet o f
<Doc> A1.2
MAX 10 FPGA 10M50 Evaluation Kit (6XX-44364R)
A3
12 25Thursday, March 24, 2016
Title
Size Document Number Rev
Date: Sheet o f
<Doc> A1.2
MAX 10 FPGA 10M50 Evaluation Kit (6XX-44364R)
A3
12 25Thursday, March 24, 2016
R86 100.0
TP48
R94 DNI
C33100 pF
R75200
TP57
R912.0K
C171
10uF
R72 100.0
R80 100.0
C34100 pF
TP67
R74200
C31100 pF
TP50
R82200
C36
DNI
R71 100.0
R892.0K
J2
FFC_CONN_1x36
11 22 33 44 55 66 77 88 99 10
10 1111 1212 1313 1414 1515 1616 1717 1818 1919 2020 2121 2222 2323 2424 2525 2626 2727 2828 2929 3030 3131 3232 3333 3434 3535 3636
SP1G1SP2G2
SP3G3SP4G4
R247 0
R88200
R87 100.0
R79 100.0
R73200
C35100 pF
R81200
R78 100.0
R84200
R85 100.0
TP63
R76200
C32100 pF
TP68
R246 0
R922.0K
C172
10uF
TP66
TP54
TP60
R83200
R90200
R93 100.0
TP45
R77 100.0
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
OV5640 CSI-2 RX Interface
MIPI CSI-2 RX D-PHY OV5640
CAD Note:Place near J3 connector.
CAD Note:Place resistors near FPGA side.
CAD Note:Place resistors near FPGA side.
CAD Note:Place resistors near FPGA side.
OV5640_DATA_HS_N2OV5640_DATA_HS_P2
OV5640_CLK_HS_NOV5640_CLK_HS_P
OV5640_DATA_HS_N1OV5640_DATA_HS_P1
OV5640_CAM_PWRONOV5640_CLK24MHzOV5640_SDCOV5640_SDAOV5640_CAM_RESETB3.3V_OV5640
OV5640_SDC
OV5640_SDA
OV5640_CAM_PWRON
OV5640_CAM_RESETB
OV5640_CLK_HS_P
OV5640_CLK_LP_P
OV5640_CLK_HS_N
OV5640_CLK_LP_N
OV5640_DATA_HS_P1
OV5640_DATA_LP_P1
OV5640_DATA_HS_N1
OV5640_DATA_LP_N1
OV5640_DATA_HS_P2
OV5640_DATA_LP_P2
OV5640_DATA_HS_N2
OV5640_DATA_LP_N2
3.3V
3.3V
OV5640_CLK_HS_P 8
OV5640_CLK_HS_N 8
OV5640_DATA_HS_P[1:2] 5
OV5640_DATA_HS_N[1:2] 5
OV5640_CAM_RESETB 4
OV5640_SDA 4
OV5640_CLK24MHz 19
OV5640_SDC 4
OV5640_CAM_PWRON 4
OV5640_CLK_LP_P 6
OV5640_CLK_LP_N 6
OV5640_DATA_LP_P[1:2] 6
OV5640_DATA_LP_N[1:2] 6
Title
Size Document Number Rev
Date: Sheet o f
<Doc> A1.2
MAX 10 FPGA (10M50) Evaluation Kit
A3
13 25Thursday, March 24, 2016
Title
Size Document Number Rev
Date: Sheet o f
<Doc> A1.2
MAX 10 FPGA (10M50) Evaluation Kit
A3
13 25Thursday, March 24, 2016
Title
Size Document Number Rev
Date: Sheet o f
<Doc> A1.2
MAX 10 FPGA (10M50) Evaluation Kit
A3
13 25Thursday, March 24, 2016
R109200
R101DNI
R2480
C38
DNI
R100DNI
R98DNI
R107 100.0
R103 100.0
C41100 pF
R96200
R104200
R95 100.0
C37100 pF
R108200
C173
10uF
C39
DNI
J3
FFC CONN 1x16
11
22
33
44
55
66
77
88
99
1010
1111
1212
1313
1414
1515
1616 17
17
1818
R110 100.0
R106 100.0
R97200
R99DNI
R105200
R102 100.0
C40100 pF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Note:Place 0.1uF capacitor near ADV7513 DVDD pins
Note:Place 0.1uF capacitor near ADV7513 AVDD pins
Note:Place 0.1uF capacitor near ADV7513 DVDD_3V pin
Note:Place 0.1uF capacitor near ADV7513 PVDD and BGVDD pin
HDMI TX
HDMI (VIDEO ONLY)
Copyright (c) 2015, Altera Corporation. All Rights Reserved.Altera Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
HDMI Power Decoupling
HDMI_VIDEO_DIN0HDMI_VIDEO_DIN1HDMI_VIDEO_DIN2HDMI_VIDEO_DIN3HDMI_VIDEO_DIN4HDMI_VIDEO_DIN5HDMI_VIDEO_DIN6HDMI_VIDEO_DIN7
HDMI_VIDEO_DIN8HDMI_VIDEO_DIN9HDMI_VIDEO_DIN10HDMI_VIDEO_DIN11HDMI_VIDEO_DIN12HDMI_VIDEO_DIN13HDMI_VIDEO_DIN14HDMI_VIDEO_DIN15
HDMI_VIDEO_DIN16HDMI_VIDEO_DIN17HDMI_VIDEO_DIN18
HDMI_VIDEO_CLKHDMI_VIDEO_DATA_ENHDMI_HSYNCHDMI_VSYNCHDMI_IREF
TMDS_CLK_PTMDS_CLK_N
TMDS_DATA_N0TMDS_DATA_P0
HDMI_INTR
HDMI_SDA
TMDS_DATA_P1
TMDS_DATA_P2TMDS_DATA_N1
TMDS_DATA_N2
HDMI_SCLHDMI_DDCSDAHDMI_DDCSCL
CEC_CLKCEC_IO
3.3V_DVDD
1.8V_DVDD
1.8V_PVDD
1.8V_AVDD
1.8V_AVDD
1.8V_DVDD
1.8V_AVDD
HDMI_DDCSCL
HDMI_DDCSDA
HDMI_HPD
1.8V_PVDD
3.3V_DVDD
TMDS_DATA_P2TMDS_DATA_N2
TMDS_DATA_P1
TMDS_CLK_P
TMDS_DATA_N1
TMDS_CLK_N
HDMI_HPD
TMDS_DATA_P0TMDS_DATA_N0
HDMI_DDCSCLHDMI_DDCSDA
HDMI_SCL
HDMI_SDA
HDMI_INTR
3.3V_DVDD
HDMI_VIDEO_DIN19HDMI_VIDEO_DIN20HDMI_VIDEO_DIN21HDMI_VIDEO_DIN22HDMI_VIDEO_DIN23
HDMI_HPD
5V 5V
1.8V
1.8V
1.8V
3.3V
5V
5V
HDMI_VIDEO_CLK 8
HDMI_HSYNC 7
HDMI_VSYNC 7
HDMI_VIDEO_DATA_EN 7
HDMI_SCL 7
HDMI_INTR 7
HDMI_SDA 7
HDMI_VIDEO_DIN[23:0] 7
Title
Size Document Number Rev
Date: Sheet o f
<Doc> A1.2
MAX 10 FPGA 10M50 Evaluation Kit (6XX-44364R)
A3
14 25Thursday, March 24, 2016
Title
Size Document Number Rev
Date: Sheet o f
<Doc> A1.2
MAX 10 FPGA 10M50 Evaluation Kit (6XX-44364R)
A3
14 25Thursday, March 24, 2016
Title
Size Document Number Rev
Date: Sheet o f
<Doc> A1.2
MAX 10 FPGA 10M50 Evaluation Kit (6XX-44364R)
A3
14 25Thursday, March 24, 2016
R1110
C50
0.1uF
C430.1uF
R1120
C44
10uF
R118 2.0K
R121 2.0K
ADV7513BSWZ
U3
DVDD1
VSYNC2
SPDIF3
MCLK4
I2S05
I2S16
I2S27
I2S38
SCLK9
LRCLK10
DVDD11
PVDD12
BGVDD13
R_EXT14
AVDD15HPD
16
DDCSCL33DDCSDA34SCL35SDA36
D2337 D2238 D2139 D2040 D1941 D1842 D1743 D1644
D1545 D1446 D1347 D1248 D1149 D1050
DVDD51
D952
CLK53
D854
D755 D656 D557 D458 D359 D260 D161 D062
DE63
HSYNC64
TXC-17TXC+18
AVDD19
TX0-20TX0+21
PD22
TX1-23TX1+24
AVDD25
TX2-26TX2+27
INT28
DVDD_3V29
CEC30
DVDD31
CEC_CLK32
EPAD_GND65
R122 2.0K
L4 10uH1 2
C52
10uF
R120 2.0K
L3 10uH1 2
L2 10uH1 2
C53
0.1uF
L1 10uH1 2
C46
0.1uF
C48
0.1uF
C420.1uF
R113 DNI
C45
0.1uF
R116 887
VDD GND IO6 IO5
IO3 IO4IO2IO1
D1
82401646
7
4
81 2 3
56
C49
10uF
R119 DNI
C54
0.1uF
C51
0.1uF
R114 2.0KR115 2.0K
C57
0.1uF
C56
10uF
VDD GND IO6 IO5
IO3 IO4IO2IO1
D2
82401646
7
4
81 2 3
56
R117 10.0K
C47
0.1uF
C55
0.1uF
HDMI 19-Pin Connector
J4685119134923
TMDS_DATA_N23 TMDS_DATA_P21
TMDS_DATA_N16 TMDS_DATA_P14
TMDS_DATA_N09 TMDS_DATA_P07
5V_VCC18
SCL15
TMDS_CLK_P10
TMDS_DATA_SHLD22
RESERVED_NC14
MTG
2G
2
TMDS_DATA_SHLD15
TMDS_DATA_SHLD08
SDA16
MTG
1G
1
TMDS_DATA_SHLD_CLK11 TMDS_CLK_N12
CEC13
DDC_CEC_GND17
HOT_PLUG_DETECT19
MTG
3G
3
MTG
4G
4
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Si510
Configuration
ON-BOARD USB BLASTER II-1
USB Blaster II
IFCLK = 48MHz
Altera Corporation, 301, Bibo Rd #888, Shanghai, China, 201203Copyright (c) 2015, Altera Corporation. All Rights Reserved.
( VCCIO = 3.3V )
( VCCIO = 3.3V )
Flash
JTAG Interface
EN5339
Note:Place 0.1uF capacitors near CY7C68013A.
CLK50M_MAXII
C_USB_MAX_TDOC_USB_MAX_TMS
C_USB_MAX_TCK
C_USB_MAX_TDI
FX2_WAKEUP
FX2_D_NFX2_D_P
FX2_PD4FX2_PD3
FX2_PD0FX2_PD1FX2_PD2
FX2_PD5FX2_PD6FX2_PD7
FX2_PB6FX2_PB7
24M_XTALIN24M_XTALOUT
FX2_PB0
FX2_PB2FX2_PB3FX2_PB4
USB_CLK
FX2_RESETn
FX2_FLAGCFX2_FLAGB
FX2_WAKEUP
FX2_SLWRnFX2_SLRDn
FX2_FLAGA
FX2_SCLFX2_SDA
FX2_RESETn
FX2_PD2FX2_PD0C_USB_MAX_TCK
C_USB_MAX_TDIFX2_PD3C_USB_MAX_TDOFX2_PD1C_USB_MAX_TMS
USB_CLK
FX2_SCL
FX2_PA0FX2_PA1FX2_PA2FX2_PA3FX2_PA4FX2_PA5FX2_PA6FX2_PA7
FX2_PB5
FX2_PB1
FX2_RESETn
FX2_PB0
FX2_PB1
FX2_PB2
FX2_PB3
FX2_PB4
FX2_PB5
FX2_PB6
FX2_PB7
MAX_SDA
FX2_PA4
FX2_PA5
FX2_PA6
FX2_PA7
FX2_PA0
FX2_PA1
FX2_PA3
FX2_PA2
FX2_FLAGB
FX2_FLAGC
FX2_FLAGA
FX2_PD5FX2_PD4FX2_PD6FX2_PD7FX2_SLRDn
FX2_SLWRnJTAG_LOCK1.2V_LED
1.2V_CORE_POK
FLASH_RESETn FLASH_RESETn_MAXII
JTAG_SAFEUSB_RESETnUSB_WRn
MAX10_nSTATUS
MAXII_CONF_DONE
MAX10_CONF_DONE
FX2_SDA
3.3V3.3V
3.3V3.3V
3.3V
3.3VVBUS_5V
VBUS_5V
USB_CLK 8
CLK50M_MAXII 19
MAX10_nSTATUS 9
MAX10_CONF_DONE 9
MAXII_CONF_DONE 18
FLASH_RESETn 7,25
JTAG_SAFE 4
JTAG_LOCK 16
USB_RESETn 4
USB_WRn 4
1.2V_CORE_POK 22
1.2V_LED 18
Title
Size Document Number Rev
Date: Sheet o f
<Doc> A1.2
MAX 10 FPGA 10M50 Evaluation Kit (6XX-44364R)
A3
15 25Thursday, March 24, 2016
Title
Size Document Number Rev
Date: Sheet o f
<Doc> A1.2
MAX 10 FPGA 10M50 Evaluation Kit (6XX-44364R)
A3
15 25Thursday, March 24, 2016
Title
Size Document Number Rev
Date: Sheet o f
<Doc> A1.2
MAX 10 FPGA 10M50 Evaluation Kit (6XX-44364R)
A3
15 25Thursday, March 24, 2016
R123 0
R130 0
R136 1.00K
R132 0
C70
0.1uF
C58 0.1uF
MAX IIBANK4
U4D
EPM1270_M256FBGA
IOB4/DEV_CLRnY13
IOB4/DEV_OEW12
IOB4_1U13
IOB4_2U14
IOB4_3U15
IOB4_4U16
IOB4_5U4
IOB4_6U5
IOB4_7U6
IOB4_8U7
IOB4_9U8
IOB4_10V14
IOB4_11V15
IOB4_12V16
IOB4_13V17
IOB4_14V18
IOB4_15V4
IOB4_16V5
IOB4_17V6
IOB4_18V7
IOB4_20W11
IOB4_21W13
IOB4_22W14
IOB4_23W15
IOB4_24W16
IOB4_25W17
IOB4_26W18
IOB4_27W3
IOB4_28W4
IOB4_29W5
IOB4_30W6
IOB4_32W8
IOB4_33W9
IOB4_34Y1
IOB4_35Y10
IOB4_36Y11
IOB4_37Y12
IOB4_38Y14
IOB4_39Y15
IOB4_40Y16
IOB4_41Y17
IOB4_42Y18
IOB4_43Y19
IOB4_44Y2
IOB4_45Y3
IOB4_46Y4
IOB4_47Y5
IOB4_48Y6
IOB4_49Y7
IOB4_50Y8
IOB4_51Y9
IOB4_31W7
IOB4_19W10
R126100K
C68
0.1uF
R129 0
C59 4.7nF
R131 0
C64
0.1uF
VBUSD-D+ID
J5USB MINI-B
12345
6789
C66
0.1uF
R128 2.0K
C62
0.1uF
R127 2.0K
C69
0.1uF
C67
0.1uF
C60
12pF
U7
CY7C68013A_QFN
RDY01
RDY12
XTALIN5
AVCC3
DMINUS9
AGND6
VCC11
GND12
PD752
CLKOUT54
XTALOUT4
AVCC7
DPLUS8
AGND10
IFCLK13
RESERVED14
PD550PD449
PD651
SCL15
SDA16
PB018
GND26
GND28
GND41
PB119
PB321PB220
VCC17
VCC27
PB624PB523PB422
PD348PD247
PA740
PA437
PA134
PB725
PD146
WAKEUP44
PA639
GND53
VCC43
PA336
CTL130CTL029
PD045
RESET42
PA538
GND56
VCC55
PA235
PA033
CTL231
VCC32
EXPOSED_PAD57
R133 10.0K
U5
MAX811
GND1
RESET2
VCC4
MR3
R124 DNI
U6
TPD2EUSB30D-
2D+1
GND3
C63
0.1uF
R135 1.00K
C61
12pF
R249 0
R125 1M
Y1
24.00MHz
1 3
24
C65
0.1uF
MAX IIBANK1
U4A
EPM1270_M256FBGA
IOB1_21G4
IOB1_22H1
IOB1_23H2
IOB1/GCLK0K1
IOB1/GCLK1L1
IOB1_1B1
IOB1_2C1
IOB1_3C2
IOB1_4C3
IOB1_5C4
IOB1_6D1
IOB1_7D2
IOB1_8D3
IOB1_9D4
IOB1_10E1
IOB1_11E2
IOB1_12E3
IOB1_13E4
IOB1_14F1
IOB1_15F2
IOB1_16F3
IOB1_17F4
IOB1_18G1
IOB1_19G2
IOB1_20G3
IOB1_24H4
IOB1_25J1
IOB1_26J2
IOB1_27K2
IOB1_28L2
IOB1_29M1
IOB1_30M2
IOB1_31N1
IOB1_32N2
IOB1_33N4
IOB1_34P1
IOB1_35P2
IOB1_36P3
IOB1_37P4
IOB1_38R1
IOB1_39R2
IOB1_40R3
IOB1_41R4
IOB1_42T1
IOB1_43T2
IOB1_44T4
IOB1_45U1
IOB1_46U3
IOB1_47V1
TMST3TDOV2TDIU2TCKW2
IOB1_48V3
IOB1_49W1
J6
DNI
11
33
55
77
22
44
66
88
99
1010
R134
20.0K
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
MAX10 USB Interface
JTAG Interface
USB Blaster Programming Header(uses JTAG mode only)
Copyright (c) 2015, Altera Corporation. All Rights Reserved.Altera Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
ON-BOARD USB BLASTER II-2
( VCCIO = 2.5V )( VCCIO = 3.3V )
MAX II Decoupling
Note:Place decoupling capacitors near MAXII
EXT_JTAG_TCKEXT_JTAG_TDOEXT_JTAG_TMSJTAG_LOCKEXT_JTAG_TDI
EXT_JTAG_TMS_R
EXT_JTAG_TDI_RJTAG_LOCK_R
EXT_JTAG_TCK
EXT_JTAG_TCK_REXT_JTAG_TDO_R
EXT_JTAG_TCK
SI5338_INTR
USB_DISABLEn
USB_SDA
MAX10_JTAG_TDI
USB_DISABLEn
EXT_JTAG_TDO
EXT_JTAG_TMS
EXT_JTAG_TDI
USB_DATA7USB_DATA5
USB_DATA4
USB_OEn
USB_DATA1
USB_ADDR0
USB_DATA3
USB_RDn
USB_DATA6
USB_ADDR1
USB_DATA0
USB_EMPTY
USB_FULL
USB_DATA2
USB_SCL
MAX10_BYPASSn
I2C_MAXII_SDAI2C_MAXII_SCL
MAX10_JTAG_TMSMAX10_JTAG_TCKMAX10_JTAGEN
MAX10_JTAG_TDO
3.3V 3.3V
3.3V
3.3V
2.5V
2.5V
2.5V
3.3V
3.3V
3.3V
3.3V 3.3V
2.5V
3.3V 2.5V
3.3V
MAX10_BYPASSn 18
I2C_MAXII_SDA 19
I2C_MAXII_SCL 19
MAX10_JTAGEN 9
USB_RDn 4
SI5338_INTR 19
MAX10_JTAG_TMS 9
MAX10_JTAG_TDI 9
MAX10_JTAG_TCK 9
MAX10_JTAG_TDO 9
USB_DATA[7:0] 4
USB_ADDR[1:0] 4
USB_FULL 4USB_EMPTY 4USB_SCL 4USB_SDA 4
USB_OEn 4
JTAG_LOCK 15
Title
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Date: Sheet o f
<Doc> A1.2
MAX 10 FPGA 10M50 Evaluation Kit (6XX-44364R)
A3
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Title
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Date: Sheet o f
<Doc> A1.2
MAX 10 FPGA 10M50 Evaluation Kit (6XX-44364R)
A3
16 25Thursday, March 24, 2016
Title
Size Document Number Rev
Date: Sheet o f
<Doc> A1.2
MAX 10 FPGA 10M50 Evaluation Kit (6XX-44364R)
A3
16 25Thursday, March 24, 2016
C74
0.1uF
C71
DNI
R149 22.0
R1441.00k
R148 22.0
R139 4.7k
C79
0.1uF
C81
0.1uF
C76
0.1uF
C72
0.1uF
R141 1.00k
R143 DNI
C75
0.1uF
MAX IIBANK2
U4B
EPM1270_M256FBGA
IOB2_1A1
IOB2_2A10
IOB2_3A11
IOB2_4A12
IOB2_5A13
IOB2_6A14
IOB2_7A15
IOB2_8A16
IOB2_9A17
IOB2_10A18
IOB2_11A19
IOB2_12A2
IOB2_13A20
IOB2_14A3
IOB2_15A4
IOB2_16A5
IOB2_17A6
IOB2_18A7
IOB2_20A9
IOB2_21B10
IOB2_22B11
IOB2_23B12
IOB2_24B13
IOB2_25B14
IOB2_26B15
IOB2_27B16
IOB2_28B17
IOB2_29B18
IOB2_30B19
IOB2_31B2
IOB2_32B3
IOB2_33B4
IOB2_34B5
IOB2_36B7
IOB2_37B8
IOB2_38B9
IOB2_39C14
IOB2_40C15
IOB2_41C16
IOB2_42C17
IOB2_43C5
IOB2_44C6
IOB2_45C7
IOB2_46D13
IOB2_47D14
IOB2_48D15
IOB2_49D16
IOB2_50D5
IOB2_51D6
IOB2_52D7
IOB2_53D8
IOB2_19A8
IOB2_35B6
J7
2X5_100mil
11
33
55
77
22
44
66
88
99
1010 R152 22.0
R151 22.0
R147 1.00k
C73
0.1uF
R137 4.7k
R150 22.0
R140 1.00k
MAX IIBANK3
U4C
EPM1270_M256FBGA
IOB3/GCLK3L20
IOB3_24J19
IOB3_1B20
IOB3_2C18
IOB3_3C19
IOB3_4C20
IOB3_5D17
IOB3_6D18
IOB3_7D19
IOB3_8D20
IOB3_9E17
IOB3_10E18
IOB3_11E19
IOB3_12E20
IOB3_13F17
IOB3_14F18
IOB3_15F19
IOB3_16F20
IOB3_17G17
IOB3_18G18
IOB3_19G19
IOB3_20G20
IOB3_21H17
IOB3_23H20
IOB3/GCLK2M20
IOB3_25J20
IOB3_26K19
IOB3_27K20
IOB3_28L19
IOB3_29M19
IOB3_30N17
IOB3_31N19
IOB3_32N20
IOB3_33P17
IOB3_35P19
IOB3_36P20
IOB3_37R17
IOB3_38R18
IOB3_39R19
IOB3_40R20
IOB3_41T17
IOB3_42T18
IOB3_43T19
IOB3_44T20
IOB3_45U17
IOB3_46U18
IOB3_47U19
IOB3_48U20
IOB3_49V19
IOB3_50V20
IOB3_51W19
IOB3_52W20
IOB3_53Y20
IOB3_22H19
IOB3_34P18
R142 1.00k
C77
0.1uF
R138 1.00k
C78
0.1uF
C80
0.1uF
R1461.00k
MAX IIPower
U4E
EPM1270_M256FBGA
GNDINTJ4
GNDINTU12
GNDINTM17
GNDINTD12
GNDIOH3
GNDIOJ3
GNDIOM4
GNDION3
GNDIOU9
GNDIOV8
GNDIOV9
GNDIOV13
GNDIOH18
GNDIOJ17
GNDION18
GNDIOC8
GNDIOD9
GNDIOC12
GNDIOC13
GNDIOM18
VCCINTD11VCCINTL17VCCINTU11VCCINTK4
VCCIO1K3
VCCIO1L3
VCCIO1L4
VCCIO1M3
VCCIO2C9
VCCIO2C10
VCCIO2D10
VCCIO2C11
VCCIO3J18
VCCIO3K17
VCCIO3K18
VCCIO3L18
VCCIO4U10
VCCIO4V10
VCCIO4V11
VCCIO4V12
R1451.00k
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Copyright (c) 2015, Altera Corporation. All Rights Reserved.Altera Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
PMOD, GPIO, LVDS USER IO
PMOD
User LVDS IO
User IO
LVDS
User GPIO
User LVDS IO
LVDS Termination
Note: USER_CLKIN_IO_Pis used if external single-endedclk needs to use on-chip PLLresource.USER_CLKIN_IO_P/N is usedfor external differential clk input.Values of R179,R180,R268, and R269 might be adjustedaccording to user input voltage.
PMOD Note: Place near MAX 10 side.
USER_IO9
USER_IO0USER_IO1
USER_IO2USER_IO3
USER_IO4
USER_IO5USER_IO6
USER_IO7USER_IO8
USER_LVDS_P0USER_LVDS_N0
USER_LVDS_P1USER_LVDS_N1
USER_LVDS_P2USER_LVDS_N2
USER_LVDS_P3USER_LVDS_N3
USER_LVDS_P4USER_LVDS_N4
USER_LVDS_P5USER_LVDS_N5
USER_LVDS_P6USER_LVDS_N6
USER_LVDS_P7USER_LVDS_N7
USER_LVDS_P8USER_LVDS_N8
CLKOUT_LVDS_PCLKOUT_LVDS_N
USER_CLKIN_PUSER_CLKIN_N_MAX10
USER_LVDS_N7USER_LVDS_P7
USER_LVDS_N6USER_LVDS_P6
USER_LVDS_N5USER_LVDS_P5
USER_LVDS_N3USER_LVDS_P3
USER_LVDS_P2USER_LVDS_N2
USER_LVDS_P1USER_LVDS_N1
USER_LVDS_P0USER_LVDS_N0
USER_LVDS_N8USER_LVDS_P8
USER_CLKIN_IO_N
USER_CLKIN_N_MAX10
USER_CLKIN_IO_P
USER_CLKIN_P
PMODA_IO3PMODA_IO7PMODA_IO6PMODA_IO2
PMODA_IO4PMODA_IO0PMODA_IO1PMODA_IO5
PMODA_IO3PMODA_IO2PMODA_IO1PMODA_IO0 PMODA_IO4
PMODA_IO5PMODA_IO6PMODA_IO7
PMODB_IO0
PMODB_IO0
PMODB_IO1
PMODB_IO1
PMODB_IO4
PMODB_IO2
PMODB_IO2
PMODB_IO3
PMODB_IO6
PMODB_IO4
PMODB_IO5
PMODB_IO5
PMODB_IO7
PMODB_IO6
PMODB_IO3
PMODB_IO7
3.3V 3.3V
3.3V 3.3V
PMODA_D0PMODA_D1PMODA_D2PMODA_D3
PMODA_D4PMODA_D5PMODA_D6PMODA_D7
PMODB_D0PMODB_D1PMODB_D2PMODB_D3
PMODB_D4PMODB_D5PMODB_D6PMODB_D7
CLKOUT_LVDS_NCLKOUT_LVDS_P
USER_LVDS_P4USER_LVDS_N4
3.3V 3.3V
2.5V 2.5V
2.5V 2.5V
3.3V
3.3V 3.3V
3.3V
PMODA_D[7:0] 7
PMODB_D[7:0] 7
USER_LVDS_P[0:8] 5
USER_LVDS_N[0:8] 5
USER_IO[0:9] 7
CLKOUT_LVDS_P 8
CLKOUT_LVDS_N 8
USER_CLKIN_P 8
USER_CLKIN_N_MAX10 8
Title
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MAX 10 FPGA 10M50 Evaluation Kit (6XX-44364R)
A3
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MAX 10 FPGA 10M50 Evaluation Kit (6XX-44364R)
A3
17 25Thursday, March 24, 2016
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<Doc> A1.2
MAX 10 FPGA 10M50 Evaluation Kit (6XX-44364R)
A3
17 25Thursday, March 24, 2016
Header 2x7 (DNI)
J14
IO11
IO33
IO55
IO77
IO99
IO22
IO44
IO66
IO88
IO1010
IO1111
IO1212
IO1313
IO1414
R172 200J9
2x6 PMOD Connector
11
77
22
88
33
99
44
1010
55
1111
66
1212
R175 200
R153 DNI
R272 DNI
R2691.00k
R177 200
U11
824013
IO11
IO23
IO34
IO46
VDD5
GND2
R1792.0K
R1801.00k
R161 200
R167 DNI
U8
824013
IO11
IO23
IO34
IO46
VDD5
GND2
R164 200
R166 DNI
R158 200
U9
824013
IO11
IO23
IO34
IO46
VDD5
GND2
J13
Header 2x10 (DNI)
11
33
55
77
99
1111
1313
1515
1717
1919
22
44
66
88
1010
1212
1414
1616
1818
2020
R160 200
R178 200
R2682.0K
R165 DNI
R174 200
R154 DNI
R173 200
J12
Header 2x10 (DNI)
11
33
55
77
99
1111
1313
1515
1717
1919
22
44
66
88
1010
1212
1414
1616
1818
2020
R155 DNI
R162 DNI
R171 200
U10
824013
IO11
IO23
IO34
IO46
VDD5
GND2
R168 DNI
R169 DNI
R159 200
R170 DNI
R163 200
J8
2x6 PMOD Connector
11
77
22
88
33
99
44
1010
55
1111
66
1212
R157 200R156 200
R176 200
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PUSHBUTTON, SWITCH, LED
Altera Corporation, 301, Bibo Rd #888, Shanghai, China, 201203Copyright (c) 2015, Altera Corporation. All Rights Reserved.
User LED
User Pushbutton
User DIP Switch
MAXII
ON = 0OFF = 1
USER DIPSWITCH
ON = 0OFF = 1
BOARD SETTINGS DIPSWITCH
Logic 0 = Device JTAG BypassLogic 1 = Device JTAG Enable
User LED
Power LED
User DIP Switch
User Pushbutton
Note: MAX10_BYPASSn is used to bypassthe virtual JTAG device provided within theOn-Board USB-Blaster II.
USER_PB1
MAXII_CONF_DONE_RMAXII_CONF_DONE
MAX10_nCONFIG
MAX10_RESETn
USER_DIPSW1USER_DIPSW0
USER_DIPSW2USER_DIPSW3
USER_DIPSW5MAX10_CONFIG_SEL
USER_DIPSW4
MAX10_BYPASSn
USER_LED0
USER_LED1
USER_LED3
USER_LED4
USER_LED0_R
USER_LED1_R
USER_LED2_RUSER_LED2
USER_LED3_R
USER_LED4_R
1.2V_LED_R1.2V_LED
2.5V_LED_R
5V_LED_RUSER_PB2
USER_PB0
USER_PB3
3.3V
1.2V_VCCIO
3.3V
5V
2.5V
1.2V_VCCIO
3.3V
3.3V
USER_LED[0:4] 7
USER_PB[0:3] 6
MAX10_nCONFIG 9
MAX10_RESETn 9
USER_DIPSW[0:3] 6
MAX10_CONFIG_SEL 9
MAX10_BYPASSn 16
MAXII_CONF_DONE 15
1.2V_LED 15
USER_DIPSW[4:5] 4
Title
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MAX 10 FPGA 10M50 Evaluation Kit (6XX-44364R)
A3
18 25Thursday, March 24, 2016
Title
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MAX 10 FPGA 10M50 Evaluation Kit (6XX-44364R)
A3
18 25Thursday, March 24, 2016
Title
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<Doc> A1.2
MAX 10 FPGA 10M50 Evaluation Kit (6XX-44364R)
A3
18 25Thursday, March 24, 2016
R185 10.0K
D6 GREEN_LED
S7
PB Switch
1 32 4
R198 10.0K
R203 10.0K
D11 YELLOW_LED
S3
PB Switch
1 32 4
D3 GREEN_LED
D5 GREEN_LED
R200 150
R191 10.0K
R195 10.0K
D4 GREEN_LED
OPEN
SW2
DIPSWITCH4
1234 5
678
D8 GREEN_LED
S1
PB Switch
1 32 4
R204 10.0K
D7 GREEN_LED
R189 10.0K
R199 1.00k
S2
PB Switch
1 32 4
OPEN
SW1
DIPSWITCH4
1234 5
678
R194 390
R202 10.0K
R188 150
R183 150
R196 10.0K
R187 150
R186 150
R193 150R192 10.0K
R190 10.0K
D9YELLOW_LED
R181 10.0KR182 10.0K
S4
PB Switch
1 32 4
R278 390
S6
PB Switch
1 32 4
D10YELLOW_LED
R184 10.0K
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Altera Corporation, 301, Bibo Rd #888, Shanghai, China, 201203Copyright (c) 2015, Altera Corporation. All Rights Reserved.
CLOCKING
Notes:Use Clock Control GUI to program Si5338 oscillator outputs.(Defaults 100MHz, 125MHz, 24MHz, 24MHz)
I2C Address 70 HEX
Programmable ClockMAX 10
MAXII
DM385 CSI-2 TX Interface
3.3V CMOS complimentary
1.8V CMOS complimentary
3.3V Single-Ended CMOS
3.3V Single-Ended CMOS
3.3V CMOS3.3V CMOS
I2C_MAXII_SDA
I2C_MAXII_SCL
Si5338A_XTAL_25M_P
SI5338_INTR
Si5338A_XTAL_25M_N
CLK125M_R
CLK100M_LPDDR2_BK_RCLK100M_LPDDR2_R
CLK100M_LPDDR2_BKCLK100M_LPDDR2
1.8V_SI5338
CLK125M
CLK50M_MAX10CLK50M_MAXII
CLK50M_MAX10_RCLK50M_MAXII_R
3.3V_SI5338
OV5640_CLK24MHz_R OV5640_CLK24MHz
CLK24MCLK24M_RMIPI_TX_CLK24MHzMIPI_TX_CLK24MHz_R
CLK50M_EN
3.3V_SI510
3.3V
1.8V
3.3V
2.5V
CLK50M_MAXII 15
CLK50M_MAX10 8
CLK24M 8
CLK125M 8
CLK100M_LPDDR2 8
CLK100M_LPDDR2_BK 8
SI5338_INTR 16
I2C_MAXII_SDA 16
I2C_MAXII_SCL 16
OV5640_CLK24MHz 13
MIPI_TX_CLK24MHz 11
Title
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MAX 10 FPGA 10M50 Evaluation Kit (6XX-44364R)
A3
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Title
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MAX 10 FPGA 10M50 Evaluation Kit (6XX-44364R)
A3
19 25Thursday, March 24, 2016
Title
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<Doc> A1.2
MAX 10 FPGA 10M50 Evaluation Kit (6XX-44364R)
A3
19 25Thursday, March 24, 2016
C84
0.1uF
R207 0
L9
BLM15AG221SN1300mA
R210 0
C88
0.1uF
R213 0
C85
0.1uF
C87 DNI
R208 0
R211 0
Y225.00MHz
13
24
R216 22.0
C86
0.1uF
L6
BLM15AG221SN1300mA
C89 DNI
U14
Si5338C-CUSTOM
CLKIN_P1
CLKIN_N2
CLKIN3
I2C_LSB4
FDBK_P5
FDBK_N6
VDD17
VDD224
VDDO311
VDDO215
VDDO116
VDDO020
INTR8
CLK3B9
CLK3A10SCL
12
CLK2B13
CLK2A14
CLK1B17
CLK1A18
SDA19
CLK0B21
CLK0A22
RSVD_GND23
EPAD25
R205 4.7k
R214 1.00k
U15
510MCA50M0000AAGR
VDD6
GND3
NC1
CLKp4
CLKn5
OE2
R215 22.0
C82
0.1uF
L5
BLM15AG221SN1300mA
R206 22.0
R209 22.0
R212 DNI
C83
0.1uF
C240
0.1uF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Altera Corporation, 301, Bibo Rd #888, Shanghai, China, 201203Copyright (c) 2015, Altera Corporation. All Rights Reserved.
HOT SWAP and POWER 3.3V
5VDC Input
Hot Swap Controller Circuit
POWER 3.3VHot Swap for DC Plug
EN5329
CAUTION:When NOT using jumpers,solder R292 for power input from DC Jack,or solder R293 for USB power.SOLDER ONLY ONE POWER OPTION,AND SUGGEST NOT TO USE WITH JUMPER.
Notes:Place C90 near PVIN pin.
Notes:Place C96 near AVIN pin.
Notes:Place C91, R223 and R229 near EN5329QI VFB pin.
3.3V_VFB5V_P
5V_G
ATE
5V_P
G
5V_IMON
5V_F
B
5V_UV5V_OV
5V_N
5V_UV
5V_R3.3
3.3V_EN
3.3V_POK3.3V
5V_DCIN
5V_DCIN
5V_MONITOR
VBUS_5V
5V_MONITOR
5V
5V1.8V
3.3V
5V
3.3V_POK 21
Title
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A3
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A3
20 25Thursday, March 24, 2016
Title
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Date: Sheet o f
<Doc> A1.2
MAX 10 FPGA 10M50 Evaluation Kit (6XX-44364R)
A3
20 25Thursday, March 24, 2016
R2790
C96
1.0UF
C94
150uF
C92
22uF
R260 0
C91
6.8pF
R232
20.0K
R22660.4K
V2
RS
NS
1S
NS
2
U18
LTC4218CGN
NC1
VDD2
UV3
OV4
TIMER5
INTVCC6
GND7
SOURCE8
GATE9PG10/FLT11FB12IMON13ISET14SENSE-15SENSE+16
C97
0.1uF
R293 DNIR292 DNI
R284
DNI
C207
DNI
R225
10
TP2
C93
22uFC95
22uF
R223
348K
J11
HEADER, 1x3-PIN
123
R280DNI
TP1
R231 1.00k
R264 0C220
47uF
R233
20.0K
R228
1K
R21740.2K
V1
RS
NS
1S
NS
2
C98
0.01uF
R230
20.0K
R22469.8K
R222 0.005
R227
10.0K
C90
22uF
J10
DC Input Jack 2.0 mm
123
R221
20.0K
U16FDMC8878
5
123
4R281 10.0K
C99
0.1uF
R229
78.7K
XJ1
609002115121
EN5329QI
U17
PGND2
PGND3
PGND8
PGND9
TST210
TST111
TST012
NC
13
AGND15
AVIN16
ENABLE18
PVIN19
PVIN20
NC
(SW
)01
NC
(SW
)121
NC
(SW
)222
NC
(SW
)323
NC
(SW
)424
VOUT4
VOUT5
VOUT6
VOUT7
VFB14
POK17
PG
ND
25
PG
ND
26
SW3
POWER SW
32
1
45
6
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Altera Corporation, 301, Bibo Rd #888, Shanghai, China, 201203Copyright (c) 2015, Altera Corporation. All Rights Reserved.
POWER 2.5V & 1.8V
POWER 2.5V
POWER 2.5V_VCCA POWER 1.8V
EN5329
Notes:Place caps near EP5348UI.
Notes:Place caps near EP5348UI.
Notes:Place C104 close to EP5358.
Notes:Place caps near EP5358HUI.
Note:Possible adjustment within15% VID setting by parallelRC combination.
1.8V_ENABLE
5V_R1.8
2.5V_ENABLE3.3V_POK
2.5V 1.8V2.5V_CORE 2.5V_VCCA5V
5V_R2.55V 2.5V
3.3V_POK 20
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R258 0
C105
DNI
L7 7427920221 2
R291
63.0K
R235
0
R255
DNI
C215
2.2uF
C176DNI
R289 0
C218
DNI
R236 0.1
C106
10uF
C211
2.2uF
C107
10uF
C212
0.1uF
U20
EP5358HUI
NC11
PGND2
PGND3
VFB/NC44
VSENSE5
AGND6
VOUT7
VOUT8
VS29 VS1
10 VS011
ENABLE12
AVIN13
PVIN14
NC1515
NC1616
C104
2.2uF
R290
200k
C216
5 pF
C175
DNI
TP3
C213
10uF
C219
47uF
TP4
C217
DNI
R2570
R282 0
C109
0.1uF
U19
EP5348UI
NC
(SW
)01
NC
(SW
)113
NC
(SW
)214
NC
03
PGND2
VFB4
AGND5
VOUT6
VOUT7
NC
18
NC
29
ENABLE10
AVIN11
PVIN12
C108
10uF
C251
2.2uF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Altera Corporation, 301, Bibo Rd #888, Shanghai, China, 201203Copyright (c) 2015, Altera Corporation. All Rights Reserved.
POWER 1.2V
Notes:Place the 10uF capacitor close to ferrite bead.Place the 0.1uF capacitor close to MAX 10 pin.
Place a 1μ F capfrom the AVIN pinto AGND pin.
EN5339
POWER 1.2V_CORE
POWER 1.2V_VCCIO
POWER 1.2V_VCCD_PLL
Notes:Place caps near EP5348UI.
Notes:Place caps near EP5348UI.
Notes:Place C112, R240 and R243 near EN5329QI VFB pin.
Notes:Place C111 close to PVIN pin.
1.2V_CORE_VFB
1.2V_CORE_ENABLE
1.2V_VCCIO_ENABLE
1.2V_CORE_POK
5V_R1.2CORE
1.2V_VCCIO_VFB
1.2V_VCCIO
1.8V
1.2V_CORE 1.2V_VCCD_PLL
1.2V_CORE_SENSE 1.2V_CORE
5V_R1.2VCCIO
3.3V
5V
2.5V
5V_R1.2VCCIO5V
1.2V_CORE_POK 15
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TP6
R238 0.01
C209
2.2uF
C112
15pF
C174
DNI
C119
DNI
C250
2.2uF
C113
47uF
C249
DNI
R254 0
C210
0.1uF
EN5339QI
U21
PGND2
PGND3
PGND8
PGND9
TST210
TST111
TST012
NC
13
AGND15
AVIN16
ENABLE18
PVIN19
PVIN20
NC
(SW
)01
NC
(SW
)121
NC
(SW
)222
NC
(SW
)323
NC
(SW
)424
VOUT4
VOUT5
VOUT6
VOUT7
VFB14
POK17
PG
ND
25
PG
ND
26
C115
2.2uF
C116
DNI
C122
0.1uF
C118
10uF
TP5
C208
5 pF
C111
22uF
R253 0
R285
200k
C121
10uF
R23910.0K
L8 7427920221 2
C248
DNI
R241DNI
R2420
C120
1.0UF
U22
EP5348UI
NC
(SW
)01
NC
(SW
)113
NC
(SW
)214
NC
03
PGND2
VFB4
AGND5
VOUT6
VOUT7
NC
18
NC
29
ENABLE10
AVIN11
PVIN12
C114
47uF
R315
51
R252DNI
R243
348K
R283 0
R286
200k
R240
348K
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Altera Corporation, 301, Bibo Rd #888, Shanghai, China, 201203Copyright (c) 2015, Altera Corporation. All Rights Reserved.
MAX 10 POWER & GROUND
Note:According to MAX 10 pinconnection guideline PCG-01018-1.2,"Tie the VCCINT pin to any1.2V power domain if you are not using ADC."Therefore, connect VCCINTto 1.2V_CORE for DC or DFproduction device migration.
Note:According to MAX 10 pinconnection guideline PCG-01018-1.2,"Tie the VCCA_ADC pinto any 2.5V power domainif you are not using ADC, and do not tie the VCCA_ADCpin to GND."Therefore, connect VCCA_ADCto 2.5V_CORE for DC or DFproduction device migration.
Note:For ES device, connect ADC_VREF to NCwhen not using external voltage reference.For DC/DF production device, ADC_VREFpin is migrated to VCCA according to MAX10 Errata.
ADC_VREF
3.3V1.2V_CORE
1.2V_VCCD_PLL
2.5V_VCCA
1.2V_CORE2.5V_VCCA
1.8V
2.5V
2.5V
1.2V_VCCIO
1.2V_VCCIO
3.3V
3.3V
2.5V_VCCA
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MAX 10 POWER
10M50DAF484
U1G
VCCN12
VCCN10
VCCM13
VCCM12
VCCM11
VCCL12
VCCL11
VCCL10
VCCK13
VCCK11
VCCD_PLL1T7
VCCD_PLL2G16
VCCD_PLL3G7
VCCD_PLL4U16
VCCA1R8
VCCA2H15
VCCA3H8
VCCA4T15
VCCINTJ7
VCCA_ADCH7
ADC_VREFH6
ANAIN1G5
ANAIN2J5
VCCIO1AL6
VCCIO1AK7
VCCIO1BM6
VCCIO1BL7
VCCIO2R6
VCCIO2P7
VCCIO2N7
VCCIO2N6
VCCIO3U9
VCCIO3U8
VCCIO3T9
VCCIO3T11
VCCIO3T10
VCCIO4U14
VCCIO4U12
VCCIO4U11
VCCIO4T13
VCCIO4T12
VCCIO5T17
VCCIO5R17
VCCIO5R16
VCCIO5P16
VCCIO5N16
VCCIO6N17
VCCIO6M17
VCCIO6L16
VCCIO6K17
VCCIO6K16
VCCIO6J17
VCCIO6H16
VCCIO7G14
VCCIO7G13
VCCIO7G12
VCCIO7F14
VCCIO7F12
VCCIO8G11
VCCIO8G10
VCCIO8F9
VCCIO8F11
MAX 10 GROUND
10M50DAF484
U1H
GNDY9
GNDY15
GNDY12
GNDW21
GNDV6
GNDV2
GNDV19
GNDU13
GNDU10
GNDT8
GNDT4
GNDT16
GNDT14
GNDR21
GNDR19
GNDP6
GNDP2
GNDP17
GNDN13
GNDN11
GNDM7
GNDM19
GNDM16
GNDM10
GNDL5
GNDL21
GNDL17
GNDL13
DNUL3
GNDK3
GNDK12
GNDK10
GNDJ6
GNDJ2
GNDJ19
GNDJ16
GNDG8
GNDG6
GNDG21
GNDG18
GNDG15
GNDF13
GNDF10
GNDE7
GNDE2
GNDD4
GNDD20
GNDD16
GNDD11
GNDB9
GNDB6
GNDB18
GNDB13
GNDAB22
GNDAB1
GNDAA4
GNDAA18
GNDA22
GNDA1
NC2F6NC1E5
REFGNDH5
R267 DNI
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Altera Corporation, 301, Bibo Rd #888, Shanghai, China, 201203Copyright (c) 2015, Altera Corporation. All Rights Reserved.
DECOUPLING
Notes:Place capacitor near MAX 10 pins.
Notes:Place these capacitors close to each MAX 10 VCCA pin.
Notes:Place a 0.1uF capacitor close to each MAX 10 VCCD pin.
Notes:Place these capacitors close to MAX 10 VCCIO7 and VCCIO8 pins.Notes:
Place these capacitors close to MAX 10 VCCIO2.
Notes:Place 100uF near LPDDR2 or between LPDDR2 and MAX10.Place 1.0uF and 0.1uF capacitors close to MAX 10 VCCIO5 and VCCIO6 pins.
Notes:Place these capacitors close to MAX 10 VCCIO3 and VCCIO4 pins.Place one 0.1uF close to MAX 10 VCCA_ADC pin.
2.5V3.3V
1.2V_VCCD_PLL
2.5V_VCCA1.8V
1.2V_VCCIO1.2V_CORE
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C155
0.1uFC239
0.1uF
C148
0.1uF
C146
0.1uF
C235
0.1uF
C206
0.1uF
C230
0.1uF
C233
0.1uF
C222
1.0UF
C228
0.1uF
C124
0.1uF
C226
0.1uF
C144
0.1uF
C237
0.1uF
C224
0.1uF
C197
0.22uF
C194
1.0UF
C156
0.1uF
C149
0.1uF
C147
0.1uF
C231
0.1uF
C145
0.1uF
C236
0.1uF
C196
4.7uF
C234
0.1uF
C223
1.0UF
C229
0.1uF
C227
0.1uF
C221
1.0UF
C225
0.1uF
C232
DNI
C238
0.1uF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Altera Corporation, 301, Bibo Rd #888, Shanghai, China, 201203Copyright (c) 2015, Altera Corporation. All Rights Reserved.
QSPI FLASH
QSPI FLASH
Notes:Place the two caps near QSPI flash
FLASH_D0FLASH_D1FLASH_D2FLASH_D3
FLASH_RESETn
FLASH_CLK
FLASH_CSn
3.3V
3.3V
FLASH_CSn 7
FLASH_D[0:3] 7
FLASH_CLK 7
FLASH_RESETn 7,15
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R245DNI
C170
0.1uF
U23
N25Q512A83GSF40F
PART_NUMBER = N25Q512A83GSF40FManufacturer = Micron
DQ015
DQ18
DQ2/VPP/W#9
DQ3/HOLD#1
C16
S#7
RESET3
DNU24
DNU35
DNU46
DNU511
DNU612
DNU713
DNU814
VSS10
VCC2
R2442.0K
C169
4.7uF