Download - Max - DARPA | ERI Summit
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DISTRIBUTION STATEMENT A. Approved for public release
MAX
ASSISTANT PROFESSOR
SHULAKER
MIT
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DISTRIBUTION STATEMENT A. Approved for public releaseDISTRIBUTION STATEMENT A. Approved for public release
1001010101010101010101010110010100101010101010011010101010101001110100110001010101010110010100011100101001010101011000101110101010101010100110100101010101010101011010100110010101100101010101011010010110101010101010011111001111101110100100101110101011010101101010101010101010101110010010010101010101001010100011101010001001101010100110010101100001110101010101010101010001101001010101010100
Abundant-dataInternet of Everything
Smart Cities
Military Science
Finance
Security
Government
Genomics
Health Care
WORLD RELIES ON ELECTRONICS
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DISTRIBUTION STATEMENT A. Approved for public releaseDISTRIBUTION STATEMENT A. Approved for public release
1001010101010101010101010110010100101010101010011010101010101001110100110001010101010110010100011100101001010101011000101110101010101010100110100101010101010101011010100110010101100101010101011010010110101010101010011111001111101110100100101110101011010101101010101010101010101110010010010101010101001010100011101010001001101010100110010101100001110101010101010101010001101001010101010100
Abundant-dataInternet of Everything
Smart Cities
Military Science
Finance
Security
Government
Genomics
Health Care
WORLD RELIES ON ELECTRONICS
STOP
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DISTRIBUTION STATEMENT A. Approved for public releaseDISTRIBUTION STATEMENT A. Approved for public release
MANY CHALLENGES SIMULTANEOUSLY
Power Wall Memory WallExecution time
Compute
Memory access
Also:Communication wall, interconnect wall,
complexity wall, resilience wall…
10M
Hz
5G
Hz
1980 2010
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DISTRIBUTION STATEMENT A. Approved for public releaseDISTRIBUTION STATEMENT A. Approved for public release
HOW TO IMPROVE COMPUTING?sy
stem
inte
grat
ion
device performance
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DISTRIBUTION STATEMENT A. Approved for public releaseDISTRIBUTION STATEMENT A. Approved for public release
OPTION 1: BETTER DEVICESsy
stem
inte
grat
ion
device performance
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OPTION 2: DESIGN TRICKSsy
stem
inte
grat
ion
device performance
Multi-cores
Power management
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DISTRIBUTION STATEMENT A. Approved for public releaseDISTRIBUTION STATEMENT A. Approved for public release
HOW TO IMPROVE COMPUTINGsy
stem
inte
grat
ion
device performance
Multi-cores
Power management
New innovations required!
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COMPUTING TODAY
memory
compute
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DISTRIBUTION STATEMENT A. Approved for public releaseDISTRIBUTION STATEMENT A. Approved for public release
3DSOC: OUR GOAL
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DISTRIBUTION STATEMENT A. Approved for public releaseDISTRIBUTION STATEMENT A. Approved for public release
3DSOC
Compute Memory
Conventional BEOL nano-scale vias
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DISTRIBUTION STATEMENT A. Approved for public releaseDISTRIBUTION STATEMENT A. Approved for public release
3DSOC
Compute Memory
Conventional BEOL nano-scale vias
BUT…
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• Low-temperature fabrication: <400 °C• Major obstacle for silicon CMOS
REALIZING MONOLITHIC 3D
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DISTRIBUTION STATEMENT A. Approved for public releaseDISTRIBUTION STATEMENT A. Approved for public release
• Low-temperature fabrication: <400 °C• Major obstacle for silicon CMOS
REALIZING MONOLITHIC 3D
Carbon Nanotubes Resistive RAM
<200 °C <200 °C
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• Combine device + architectural benefits
REALIZING MONOLITHIC 3D
+ +Emerging
LogicEmerging Memory
Monolithic 3D Integration
Naturally enabled
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MAJOR BENEFITS
>50× energy efficiencyvs. state-of-the-art 7 nm Si-CMOS
for challenging abundant-data applications
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DISTRIBUTION STATEMENT A. Approved for public releaseDISTRIBUTION STATEMENT A. Approved for public release
CARBON NANOTUBE (CNT)
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DISTRIBUTION STATEMENT A. Approved for public releaseDISTRIBUTION STATEMENT A. Approved for public release
CNT FET (CNFET)
d~1nmCNT
high-kgate oxide
100 nm
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DISTRIBUTION STATEMENT A. Approved for public releaseDISTRIBUTION STATEMENT A. Approved for public release
CNFET CMOS
Metal gates
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DISTRIBUTION STATEMENT A. Approved for public releaseDISTRIBUTION STATEMENT A. Approved for public release
CNFET CMOS
High-k dielectric
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DISTRIBUTION STATEMENT A. Approved for public releaseDISTRIBUTION STATEMENT A. Approved for public release
CNFET CMOS
Low temperature
Solution CNT deposition
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DISTRIBUTION STATEMENT A. Approved for public releaseDISTRIBUTION STATEMENT A. Approved for public release
CNFET CMOS
Channel definition
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DISTRIBUTION STATEMENT A. Approved for public releaseDISTRIBUTION STATEMENT A. Approved for public release
CNFET CMOS
Source/ drain metal
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DISTRIBUTION STATEMENT A. Approved for public releaseDISTRIBUTION STATEMENT A. Approved for public release
Work function engineering
CNFET CMOS
Source/ drain metal
NMOS PMOS
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DISTRIBUTION STATEMENT A. Approved for public releaseDISTRIBUTION STATEMENT A. Approved for public release
Work function engineeringWork function engineering + electrostatic doping
CNFET CMOS
Encapsulation
NMOS PMOS
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DISTRIBUTION STATEMENT A. Approved for public releaseDISTRIBUTION STATEMENT A. Approved for public release
-1.8 -0.9 0 0.9 1.8
VDS
(V)
0
1
2
3
4
5
6
7
I D (
A)
PMOS NMOS
Work function engineeringWork function engineering + electrostatic doping
CNFET CMOS
NMOS PMOS
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MAJOR BENEFITS
• Enables new monolithic 3D architectures• Unique low-temperature fabrication
• >10× energy efficiency • vs. silicon CMOS
• Future opportunities• Sub-3nm node experimental demo
energy efficiency: energy-delay product (EDP)
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DISTRIBUTION STATEMENT A. Approved for public releaseDISTRIBUTION STATEMENT A. Approved for public release
Robust doping; CNFET CMOS
materials processing design manufacturing
VIN
V OU
T
Si-compatible;>99.99% purity
Commercial facilities
Immune to metallic CNTs
CNFETS: FROM “LAB” TO “FAB”
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DISTRIBUTION STATEMENT A. Approved for public releaseDISTRIBUTION STATEMENT A. Approved for public releaseMIT, ISSCC ‘18
WORLD’S FIRST: CNFET CMOS MIXED-SIGNAL
SAR ADC (~100s CNFETs)
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DISTRIBUTION STATEMENT A. Approved for public releaseDISTRIBUTION STATEMENT A. Approved for public release
~100s CNFETs
MIT, VLSI ‘19light
ComputeLogicImagerPre-processing
ComputingHighly-processed information
WORLD’S FIRST: MONOLITHIC 3D IMAGER
Transforms Raw Data Information (~2800 CNFETs)
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DISTRIBUTION STATEMENT A. Approved for public releaseDISTRIBUTION STATEMENT A. Approved for public releaseMIT, VLSI ‘19
WORLD’S FIRST: CNFET CMOS SRAM
Kbit 6T SRAM (6144 CNFETs)
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DISTRIBUTION STATEMENT A. Approved for public release
Monolithic 3D integration
Non-volatile
\
Multiple bits-per-cell
Low Resistance State
High ResistanceState
SetReset
RESISTIVE RAM (RRAM) TECHNOLOGY
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DISTRIBUTION STATEMENT A. Approved for public releaseDISTRIBUTION STATEMENT A. Approved for public release[Le, IEEE TED 19; Wu, ISSCC 19] Collaborator: CEA-LETI
Bits-per-cell RRAM2 3 6
Cherry-picked cells
Full system
RR
AM
cel
ls
Existing methods ad hoc
First multiple bits-per-cell RRAM systemNew RRAM read & write algorithms key
NEW RESULT: MULTIPLE BITS-PER-CELL RRAM
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DISTRIBUTION STATEMENT A. Approved for public releaseDISTRIBUTION STATEMENT A. Approved for public release
Multiple bits-per-cell RRAM array
• Flash techniques don’t work for RRAM
• Correct read & write despite RRAM variations
Cel
l cou
nt
Measured resistance (kOhm)
3 bits-per-cell RRAM arrays with new algorithms
3 4 5 7 10 16 35
7 6 5 4 3 2 1 01500
1000
500
0
NEW RRAM READ & WRITE ALGORITHMS KEY
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DISTRIBUTION STATEMENT A. Approved for public releaseDISTRIBUTION STATEMENT A. Approved for public release
Non-volatile IoT edge microcontroller
Deep learningOptimized weight encoding
RRAM arrays multiple bits-per-cell
Cross-layer optimization
Bigger neural net on same hardware
2.3× improved inference accuracy
FIRST MULTIPLE BITS-PER-CELL RRAM SYSTEM
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DISTRIBUTION STATEMENT A. Approved for public releaseDISTRIBUTION STATEMENT A. Approved for public release
Without ENDURER
10-year lifetime with ENDURER(measured)
Mea
sure
d de
ep le
arni
ng
infe
renc
e ac
cura
cy
100%
50%
0%1 hour 1 day 1 month 10 years1 minute1 second
Non-volatile IoT edge microcontroller
System test setup
Continuous deep learning inference
ENDURER: 10-YEAR SYSTEM LIFETIME ACHIEVED
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TECHNOLOGY TRANSFER: U.S. FOUNDRY
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TECHNOLOGY TRANSFER: U.S. FOUNDRY
• 90 nm technology node• Enables relaxed technology requirements
• All process modules
• CNFET CMOS + RRAM + monolithic 3D
• Foundry MPW capabilities• End-to-end design infrastructure
MPW = multi-project wafer
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DISTRIBUTION STATEMENT A. Approved for public releaseDISTRIBUTION STATEMENT A. Approved for public release
• 1st foundry integration• Beyond-Si nanotech
FOUNDRY CNFET CMOS
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DISTRIBUTION STATEMENT A. Approved for public releaseDISTRIBUTION STATEMENT A. Approved for public release
FOUNDRY CNFET CMOS
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DISTRIBUTION STATEMENT A. Approved for public releaseDISTRIBUTION STATEMENT A. Approved for public release
• RRAM integration in back-end-of-line
• 2 bits-per-cell RRAM feasibility demonstrated
• Smart writes for yield boost demonstrated
FOUNDRY RRAM
Automated test setup Packaged DUTRRAM array
RRAM Cell
RRAM cell
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DISTRIBUTION STATEMENT A. Approved for public releaseDISTRIBUTION STATEMENT A. Approved for public release
FOUNDRY DESIGN INFRASTRUCTURE
Models + Calibration
PMOS
I D I DVDS VDS
experimentalmodel
NMOSexperimentalmodel
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DISTRIBUTION STATEMENT A. Approved for public releaseDISTRIBUTION STATEMENT A. Approved for public release
FOUNDRY DESIGN INFRASTRUCTURE
Models + Calibration Process Design Kit
rr1_met1rr1_via
rr1_cell
rr1_viarr1_met2
rr1_via2rr2_met1
rr2_via
rr2_cell
rr2_viarr2_met2
rr2_via2cnt1_gate
cnt1_activecnt1_sd
cnt1_pp
cnt1_met1cnt1_via
cnt1_met2cnt1_via2
met1via
met2via2
met3via3
met4via4
met5
!(cnt1_goxcut)
cnt1_sdcnt1_sdp
rr2_via2cnt1_gate
rr2_via2cnt1_gate
cnt1_activecnt1_sd
!(cnt1_goxcut)
cnt1_sd!(cnt1_dopecut)!(cnt1_dopecut)
cnt1_con
!(cnt1_dopecut)
cnt1_pp1cnt1_pp !(cnt1_dopecut)
!cnt1_dopecut
cnt2_gate
cnt2_activecnt2_sd
cnt2_pp
!(cnt2_goxcut)
cnt2_sdcnt2_sd
cnt2_gate cnt2_gate
cnt2_activecnt2_sd
!(cnt2_goxcut)
cnt2_sd!(cnt2_dopecut)!(cnt2_dopecut)
cnt2_con
!(cnt2_dopecut)
cnt2_ppcnt2_pp !(cnt2_dopecut)
!cnt2_dopecut
cnt1_via2 cnt1_via2
• Commercial-grade process design kit:• 3D Design rule checker (DRC)• 3D Layout-versus-schematic (LVS)• 3D Parasitic extraction (PEX)• Electromigration + voltage drop (EMIR)• 3D Thermal analysis• 3D Place-and-route (P&R)
• Monolithic 3D standard cell libraries• >1000 standard cells• Experimentally validated
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DISTRIBUTION STATEMENT A. Approved for public releaseDISTRIBUTION STATEMENT A. Approved for public release
FOUNDRY DESIGN INFRASTRUCTURE
Models + Calibration Process Design Kit Design Flow
Logic synthesisClock tree generation
Metal + via fillOptical proximity correction
Mask generation
Industry standard design tools
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DISTRIBUTION STATEMENT A. Approved for public releaseDISTRIBUTION STATEMENT A. Approved for public release
• Layer 1: 90 nm node CNFET CMOS logic• compute
3DSOC: FABRICATION
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DISTRIBUTION STATEMENT A. Approved for public releaseDISTRIBUTION STATEMENT A. Approved for public release
• Conventional interconnects• dense nano-scale vias
3DSOC: FABRICATION
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DISTRIBUTION STATEMENT A. Approved for public releaseDISTRIBUTION STATEMENT A. Approved for public release
• Layer 2: CNFET CMOS logic• compute
3DSOC: FABRICATION
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DISTRIBUTION STATEMENT A. Approved for public releaseDISTRIBUTION STATEMENT A. Approved for public release
• Conventional interconnects• dense nano-scale vias
3DSOC: FABRICATION
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DISTRIBUTION STATEMENT A. Approved for public releaseDISTRIBUTION STATEMENT A. Approved for public release
• Layer 3: CNFET CMOS logic• memory access
3DSOC: FABRICATION
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DISTRIBUTION STATEMENT A. Approved for public releaseDISTRIBUTION STATEMENT A. Approved for public release
• Conventional interconnects• dense nano-scale vias
3DSOC: FABRICATION
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DISTRIBUTION STATEMENT A. Approved for public releaseDISTRIBUTION STATEMENT A. Approved for public release
• Layer 4+: >4GB RRAM on-chip memory
3DSOC: FABRICATION
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DISTRIBUTION STATEMENT A. Approved for public releaseDISTRIBUTION STATEMENT A. Approved for public release
FOUNDRY MONOLITHIC 3D
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DISTRIBUTION STATEMENT A. Approved for public releaseDISTRIBUTION STATEMENT A. Approved for public release
3DSOC TEAM
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3DSOC: TRANSFORMING IDEAS TO REALITY