Download - Micron DDR
1
DDR System DesignConsiderations
Integrated Technology GroupMicron
2
DDR Overview
December, 00 3
SSTL2 Signal Levels
Driver
Receiver
December, 00 4
SSTL2 Double Ended Termination V
TT T
ermination Island
Address / Command
VTT/VREF
Generator
Data/Strobe/Mask
Chip Selects
SSTL_2
SSTL_2PC266
SDRAMReg.DIMM
PC266
SDRAMReg.DIMM
VTTTermination Island
Address/Cmnd
Chipset“NorthBridge”
December, 00 5
SSTL2 Single Ended Termination V
TT Termination Island
Address/Command
VTT/VREF
Generator
Data/Strobe/Mask
Chip Selects
SSTL_2
SSTL_2 PC266SDRAM
Reg.DIMM
PC266
SDRAMReg.DIMM
Address/Cmnd
Chipset“NorthBridge”
December, 00 6
Use Single Parallel TerminationResistor With Series Resistor
m Lower system cost
m Easier motherboard route
m Improved bandwidth
m Lower skew due to ISI
m Reduced skew due to crosstalk if doneproperly– Consider crosstalk effects in the connector pinout
December, 00 7
Double Data Rate MotherboardComponents
NBNBNB
CLKCLKCLK
VDDVVDDDD
VDD generatorswitching regulator
VTT/REF activetermination voltageswitching regulator
VTTVVTTTT
ProcessorProcessorProcessor
VTT voltage islandde-couple thoroughlyVDD and VSS
Series terminationresistor packs
Series terminationresistor packs
Four-layer motherboardFour-layer motherboard
Differentialclock synthesizerDifferentialclock synthesizer
VTT/REF activetermination voltageswitching regulator
VTT voltage islandde-couple thoroughlyto VSS
December, 00 8
Typical Signaling forDDR Main Memory
m The values for the series and termination resistors varydepending on the system design
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VTT/VREF Implementation
December, 00 10
Goals of VTT and VREFDesign
m Minimize timing skew due to– Asymmetric logic highs versus logic lows
– Noise on VREF or VTT
– Offset of VTT relative to VREF
– Drift of VREF or VTT over voltage and temperature
– External component mismatch
m Minimize cost
m Minimize power dissipation
December, 00 11
VREF Requirements
m Track 50% of (VDDQ-VSSQ) over– Voltage
– Temperature
– Noise
m Supplies minimal DC current (input leakage only)and only small transient currents– Input to NFET gates of a differential pair
December, 00 12
VREF Tracking to VDDQ
VDDQ
VREF
VSSQ
VDDQ
VREF
VSSQ
A
A
B
B
VDDQ
VREF
VSSQ
C
C
December, 00 13
VREF Recommendations
m Use global VREF distribution scheme– Eliminates variation and tracking of multiple generators
– Best performance if kept clean
m Use simple resistor divider with 1% or better accuracy– Inexpensive to use
– Tracks voltage and temperature well
m Use VREFOUT pin of ML6554– Resistor divider is integrated on-chip
– Fewer external components
– Best accuracy and matching to VTT due to trimming
– Minimizes DC error caused by the load current ofmultiple device input leakage
December, 00 14
VREF Generation
VDD VDDQ VDDQ VDDQ
VSS VSS VSS VSS
R
R
Discrete Resistors or VREF (OUT) of ML6654
VREF
m Example of VREF generation using a resistor divider
December, 00 15
VREF Layout Recommendations
m Maintain a 15-20 mil clearance from other netsm Use distributed decoupling scheme
– Minimizes capacitor ESL– Localizes transient currents and returns
m Simple implementation by routing on top signallayer trace– VREF is at connector pin 1– Isolate VREF and/or shield with VDDQ and VSSQ
December, 00 16
VREF PCB Routing
December, 00 17
VTT Requirements
m Track 50% of (VDDQ-VSSQ) over– Voltage– Temperature– Noise
m Maintain <40mV offset from VREF over theseconditions
m Source and sink DC current for signal termination– Absolute maximum current is 2.6-2.9A for a 64/72-bit
channel
December, 00 18
VTT Recommendations
m Several solutions exist that are tradeoffs of cost,integration, and performance– Standard analog components (Motorola, National,
Fairchild, etc.)
• High current output, good accuracy
– Switching regulator with discrete MOSFETs (such asLTC1430)
• High current output (10A), good accuracy, semi-integrated
– Switching regulator with integrated MOSFETs (such asML6554)
• Adequate current output (3A) and accuracy, highestintegration, lowest cost
December, 00 19
VTT Recommendations(continued)
m Use global VREF as input reference to minimize
tracking error and offset
m Use high-quality filter components
– Low Rs on filter inductor
– Low ESR and ESL on filter capacitor to minimize DC and
dynamic offset
• Recommend the use of multiple parallel capacitors and/or
Sanyo OS-CONs to minimize ESR and ESL
December, 00 20
VTT Regulation Circuit
m VTT regulation circuit using Micro Linear ML6554
December, 00 21
VTT Layout Recommendations
m Decouple to VSSQ
– Decouple at both ends, and distribute decouplingacross the island to localize transient currents andminimize ESL
m Place termination resistors on a top layer VTT
island– Island is at the end of the bus and non-obstructing
– Use wide-island trace for current capacity
– Place VTT generator as close to termination resistors aspossible to minimize impedance (inductance)
December, 00 22
VTT Island PCB Layout
ML6554Regulator
Vtt PowerPlane
DecouplingCapacitors
TerminationResistors
December, 00 23
2.5 Volt Regulation
m 2.5 volt regulation circuit using Linear TechnologyLTC1530-2.5
December, 00 24
2.5 Volt Regulation Layout
m Regulated V2.5 ties to solid power plane under DIMM’s and DRAMcontroller portion of Samurai DDR
VccInput
RegulatedV2.5
LTC1530Regulator
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Voltage Margining
December, 00 26
VREF/VTT Margining
VREF In On ML6554VDD
100 ohm Variable Resistor
1K
1K 0.1uF
0.1uF
m Use the VREF In pin on the ML6554 to margin VREF and VTT
– VTT and VREF out follow VREF In
m VREF specification is 0.49*VDD to 0.51*VDD
m VTT specification is VREF +/- 40mVm Use simple resistor divider below connected to VREF In pin on
ML6554
December, 00 27
VDD Margining
m VDD specification is 2.3 to 2.7 voltsm To margin VDD change LTC1530-2.5 to LTC1530-ADJm Adjust VDD with resistor divider R1/R2.
December, 00 28
VDD Margining
+5 volts input
2.5 Volt Vdd output
R1
R2
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Board Implementation
December, 00 30
Registered-OnlyMotherboard Topology
VT
T Term
ination Island
APC266
SDRAMReg.DIMM
APC266
SDRAMReg.DIMM
APC266
SDRAMReg.DIMM
A
VTT/VREF
Generator
Data/Strobe/Mask
Chip Selects
PC266SDRAM
Reg.DIMM
Mem Clock
DifntlClk Drvr
VREF
Address/Cmnd
SSTL_2
SSTL_2
CK/CK#
Chipset“NorthBridge”
December, 00 31
Unbuffered/RegisteredMotherboard Topology
Add/Comnd B
Address/Command A
Data/DM/DQS
PC2100DDRDIMM
APC2100
DDRDIMM
Add/Comnd A
Chip Selects
Clocks
VT
T Term
ination Island
Vtt/VrefGenerator
PC2100DDRDIMM
BPC2100
DDRDIMM
Address/Command B
Chipset“NorthBridge”
Vref
December, 00 32
PCB Considerations
m PC2100 DDR can be implemented in a low-costPCB (standard PC100 motherboard technology)
m Standard pad, anti-pad and via sizes can beused
m No additional PCB test requirements relative toPC100
December, 00 33
PCB Routing
m DDR channel can be implemented in a 2S 2Pboard– Controller BGA ballout determines whether a four-layer
board can be used, not the memory channel
– Two signal layers to get from controller to seriesresistor
– The channel can be routed on one signal layer from theseries termination resistor out, with the exception ofpoint-to-point signals
December, 00 34
Reference Motherboard Routingm Maintain signal reference through DDR channel
– Route signals on layers adjacent to a commonreference plane.
– Route each data group (8 x DQ + DQS + DM) on samelayer to match propagation delays and minimize skew.
– Address and control matching is less critical.
– Separate data and control nets to minimize crosstalk.
m Routing Rules– 5 mil trace/15 mil space on all in group SSTL nets
– Connector rules: 5 mil trace, 2 mil space from antipad,7 mils from trace
December, 00 35
Micron Samurai DDRTrace length matching rules
m Match trace lengths for each data group (8 x DQ +DQS + DM) to 0.1 inch from controller to firstDIMM.
m Match trace lengths to +/- 500 mils across theentire channel.
m Match composite length from controller bond pad tofirst DIMM pad• LBGA + Lcontroller-R + LR-DIMM = matched
m Length matching from last DIMM pad to paralleltermination resistor is less critical
December, 00 36
Length Matching from Controller to1st DIMM Pin
RT
RT
RS
RS
LBGA1 + LC-R1 + LR-D1 = LBGA2 + LC-R2 + LR-D2
LC-R1
LC-R2
LBGA1
LBGA2
LR-D2
LR-D1
December, 00 37
PCB Channel RoutingThrough the DIMMs
m A 5-mil width / 7-mil space board will yield:
– Three vertical signal-routing channels
– Two diagonal signal-routing channels
– Second layer void except for point-to-point signals
– Lowest skew due to propagation-velocity mismatch betweendifferent signal layers
December, 00 38
Routing Through DIMMs
Two Diagonal Signals Three Vertical Signals
Series Resistors
December, 00 39
Termination Resistor Placement
m Motherboard series resistors should be close to thefirst DIMM– Best performance for READ from last module
• Limiting case
– Simplifies routing and controller congestion
December, 00 40
System Design Examples
December, 00 41
DDR Memory Route 1st Layer
December, 00 42
DDR Memory Route2nd Layer
December, 00 43
Reference MotherboardStack-Up
mReference board stack-up• 6 Layer Board
Signal 4
Signal 1
Signal 2
GND
Power
Signal 3
4.5-Mils
30-Mils
6.5-Mils
4.5-Mils
6.5-Mils
December, 00 44
Questions and Answers