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ìComputer Systems and NetworksECPE170– JeffShafer– UniversityofthePacific
MIPSAssembly
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Lab Schedule
Activitiesì ThisWeek
ì MIPSdiscussionì Practiceproblems
(whiteboard)ì UsingtheQtSPIM
simulatorì Discussavailableresources
AssignmentsDueì Lab10
ì DuebyApr12th 5:00am
ì Lab11ì DuebyApr19th 5:00am
ì Lab12ì DuebyMay3rd 5:00am
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Person of the Day – John Cocke
ì Computerarchitecturepioneerì “FatherofRISCArchitecture”ì DevelopedIBM801processor,
1975-1980
ì Winner,ACMTuringAward,1987
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RISC=ReducedInstructionSetComputing
Achievehigherperformancewithsimpleinstructionsthatexecutefaster
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Person of the Day – John Hennessy
ì Computerarchitecturepioneer
ì PopularizedRISCarchitectureinearly1980’s
ì FounderofMIPSComputerSystemsin1984
ì Currentlypresidentofanobscureschool:StanfordUniversity
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Class to Date
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Human(CCode)
Compiler(Assemblycode)
Compiler(Objectfile/binarycode)
Linker(Executableprogram)
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Class Now
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Human(Assemblycode)
Assembler(Objectfile/binarycode)
Linker(ExecutableProgram)
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ìMIPS
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MIPS Overview
ì Familyofcomputerprocessorsfirstintroducedin1981
ì MicroprocessorwithoutInterlockedPipelineStagesì Originalacronymì NowMIPSstandsfornothingatall…
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MIPS Products
ì Embeddeddevicesì Cisco/Linksysroutersì Cableboxesì MIPSprocessorisburiedinsideSystem-on-a-Chip(SOC)
ì Gaming/entertainmentì Nintendo64ì Playstation,Playstation 2,PSP
ì Computers?ì Notsomuchanymore…ì SGI/DEC/NECworkstationsbackin1990’s
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MIPS Products
ì NASANewHorizonsprobeì LaunchedJanuary2006
ì MIPS“Mongoose-V”chipì 12MhZ (2006,remember?)
ì RadiationHardenedì BasedonR3000
(PlayStationCPU)
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http://blog.imgtec.com/mips-processors/mips-goes-to-plutohttp://synova.com/proc/MongooseV.pdf
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MIPS Design
ì RISC–Whatdoesthismean?ì ReducedInstructionSetComputingì Simplifieddesignforinstructionsì Usemoreinstructionstoaccomplishsametask
ì Buteachinstructionrunsmuchfaster!
ì 32bits(originally)–Whatdoesthismean?ì 1“word”=32bitsì Sizeofdataprocessedbyanintegeraddinstructionì New(er)MIPS64designis64bits,butwewon’t
focusonthat
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ìMIPS Assembly Programming
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Quotes – Donald Knuth
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“People who are more than casually interested in computers should have at least some idea of what the underlying hardware is like. Otherwise the programs they write will be pretty weird.” – Donald Knuth
Thisisyourmotivationintheassemblylabs!
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Why Learn Assembly Programming?
ì ComputerSciencetrackì Understandcapabilities(andlimitations)ofphysical
machineì Abilitytooptimizeprogramperformance(or
functionality)attheassemblylevelifnecessary
ì ComputerEngineer trackì Futurecourses(e.g.ECPE173)willfocusonprocessor
designì Startattheassemblyprogramminglevelandmoveinto
hardwareì How doestheprocessorimplementtheadd instruction?ì How doestheprocessorknowwhatdatatoprocess?
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Instruction Set Architecture
ì InstructionSetArchitecture(ISA)istheinterfacebetweenhardwareandsoftwareì Specifiestheformatofprocessorinstructionsì Specifiestheformatofmemoryaddresses
(andaddressingmodes)ì Specifiestheprimitiveoperationstheprocessorcan
perform
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Instruction Set Architecture
ì ISAisthe“contract”betweenthehardwaredesignerandtheassembly-levelprogrammer
ì Documentedinamanualthatcanbehundredsorthousandsofpageslongì Example:Intel64andIA-32ArchitecturesSoftware
DevelopersManualì http://www.intel.com/content/www/us/en/process
ors/architectures-software-developer-manuals.htmlì Nojoke– themanualPDFfromDecember2015
is3883pageslong!
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Instruction Set Architecture
ì ProcessorfamiliessharethesameISA
ì ExampleISAs:ì Intelx86ì Intel/AMDx86-64ì IntelItaniumì ARMì IBMPowerPCì MIPS
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Allcompletelydifferent,inthewaythatC++,Java,Perl,andPHParealldifferent…
…andyetlearningonelanguagemakeslearningthenextonemucheasier
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Why MIPS?
ì WhychooseMIPS?ì TheMIPSISAmanual(volume1,atleast)isasvelte
108pages!ì ExtremelycommonISAintextbooksì Freelyavailablesimulatorì Commonembeddedprocessorì Goodbuilding-blockforotherRISC-styleprocessorsì AlignswithECPE173course
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Arithmetic Instructions
ì Addition
ì Subtraction
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add <result>, <input1>, <input2>
sub <result>, <input1>, <input2>
Operation/“Opcode” Operands
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Task : Write Code
ì WriteMIPSassemblyfor
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f=(g+h)– (i+j)
add temp0, g, hadd temp1, i, jsub f, temp0, temp1
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Congratulations!
You’renowanassemblyprogrammingexpert!
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Data Sources
ì Previousexamplewas(justalittlebit) fake…ì Wemadeupsomevariables:
temp0,temp1,f,g,h,i,andjì ThisiswhatyoudowhenprogramminginC++
(oranyhighlevellanguage)
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Problem:Youcan’tmakeupvariablesinassembly!(asleast,notinthisfashion)
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Data Sources
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Wherecanweexplicitly placedatainassemblyprogramming?
CPU
ALU
1. Registersì OntheCPUitselfì VeryclosetoALUì Tinyì Accesstime:1cycle
2. Memoryì Off-chipì Largeì Accesstime:100+cycles
Cache Memory
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Aside – Cache
ì Review:Doestheprogrammerexplicitlymanagethecache?
ì Answer:No!ì Theassemblyprogrammerjustreads/writes
memoryaddressesì Cacheismanagedautomaticallyinhardwareì Result:Memoryappears tobefasterthanitreallyis
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ECPE 71
ì FromyourknowledgeofECPE71(DigitalDesign),howwouldyouconstructaregister?
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FlipFlops!(DFlipFlopshown)
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ECPE 71 – Group of Registers
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Registers
ì MIPSdesign:32integerregisters,eachholding32bitsì “Wordsize”=32bits
ì Thisisonly19– wherearetherestofthe32?ì Reservedbyconvention forotherusesì We’lllearnafewmorelater…
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Name Use
$zero Constantvalue:ZERO
$s0-$s7 Localvariables
$t0-$t9 Temporaryresults
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Task : Write Code
ì WriteMIPSassemblyusingregisters for:
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f=(g+h)– (i+j)
Code:add $t0, $s0, $s1add $t1, $s2, $s3sub $s4, $t0, $t1
Map:$s0=g$s1=h$s2=i$s3=j$s4=f
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More Arithmetic Instructions
ì AddImmediate
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addi <result>, <input1>, <constant>
Canbeapositiveornegativenumber!
RegisterRegister
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Task : Write Code
ì WriteMIPSassemblyusingregisters for:
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f=g+20
Code:addi $s0, $s1, 20
Map:$s0=f$s1=g
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Memory
ì Challenge:Limitedsupplyofregistersì Physicallimitation:Wecan’tputmoreonthe
processorchip,andmaintaintheircurrentspeedì ManyelementscompeteforspaceintheCPU…
ì Solution:Storedatainmemory
ì MIPSprovidesinstructionsthattransferdatabetweenmemoryandregisters
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Memory Fundamentals
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MIPScannot directlymanipulatedatainmemory!
Datamustbemovedtoaregisterfirst!(Andresultsmustbesavedto
aregisterwhenfinished)
ThisisacommondesigninRISC-stylemachines:aload-store architecture
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Memory Fundamentals
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Yes,it’sapain tokeepmovingdatabetweenregistersandmemory.
Butconsiderityourmotivationtoreducethenumberofmemoryaccesses.Thatwillimproveprogramperformance!
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Memory Fundamentals
ì Fourquestionstoaskwhenaccessingmemory:1. Whatdirection doIwanttocopydata?
(i.e.tomemory,orfrommemory?)2. Whatisthespecificmemoryaddress?3. Whatisthespecificregistername?(ornumber)4. HowmuchdatadoIwanttomove?
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CPU
Memory – Fundamental Operations
Loadì Copydatafrom
memorytoregister
Storeì Copydatafrom
registertomemory
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CPUMemory Memory
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Memory – Determining Address
ì Therearemanywaystocalculatethedesiredmemoryaddressì Thesearecalledaddressingmodesì We’lljustlearnonemodenow:
base+offset
ì ThebaseaddresscouldbeHUGE!(32bits)ì We’llplaceitinaregister
ì Theoffsetistypicallysmallì We’lldirectlyincludeitinthe
instructionasan“immediate”
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Memory
0
1
2
3
4
Base
Offset
MIPSnotation:offset(base)
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Memory – Register Name
ì Whatisthenameoftheregistertouseaseitherthedatadestination(foraload)oradatasource(forastore)?
ì Usethesameregisternamespreviouslylearned
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Memory - Data Transfer Size
ì HowmuchdatadoIwanttoloadorstore?ì Afullword?(32bits)ì A“halfword”?(16bits)ì Abyte?(8bits)
ì We’llhaveadifferentinstructionforeachquantityofdata
ì Nooptiontoloadanentirearray!ì Willneedaloopthatloads1elementatatime…
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Memory – Data Transfer Instructions
ì Load (copyfrommemorytoregister)
ì Store (copyfromregistertomemory)
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lw <reg>, <offset>(<base addr reg>)
lb <reg>, <offset>(<base addr reg>)
sw <reg>, <offset>(<base addr reg>)
sb <reg>, <offset>(<base addr reg>)
Word:
Byte:
Word:
Byte:
Register MemoryLocation
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Example
ì Whatwillthisinstructiondo?
ì Loadwordcopiesfrommemorytoregister:ì Baseaddress:storedinregister$s2ì Offset:20bytesì Destinationregister:$s1ì Amountofdatatransferred:1word(32bits)
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lw $s1, 20($s2)
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Task : Write Code
ì WriteMIPSassemblyfor:
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g=h+array[16](Arrayofwords.Canleavegandhinregisters)
Code:# Assume $s3 is already set
lw $t0, 16($s3)add $s1, $s2, $t0
Map:$s1=g$s2=h$s3=baseaddressofarray
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Memory Address
ì Slightflaw inprevioussolutionì Theprogrammerintendedtoloadthe16th array
elementì Eachelementis4bytes(1word)ì Theoffsetisinbytesì 16*4=64
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Correct Code:# Assume $s3 is already set
lw $t0, 64($s3)add $s1, $s2, $t0
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Task : Write Code
ì WriteMIPSassemblyfor:
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array[12]=h+array[8](Arrayofwords.Assumehisinregister)
Code:# Assume $s3 is already set
lw $t0, 32($s3)add $t1, $s2, $t0sw $t1, 48($s3)
Map:$s2=h$s3=baseaddressofarray$t1=temp
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Task : Write Code
ì WriteMIPSassemblyfor:
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g=h+array[i](Arrayofwords.Assumeg,h,andi areinregisters)
Code:# "Multiply" i by 4add $t1, $s4, $s4 # x2add $t1, $t1, $t1 # x2 again# Get addr of array[i]add $t1, $t1, $s3# Load array[i]lw $t0, 0($t1)# Compute addadd $s1, $s2, $t0
Map:$s1=g$s2=h$s3=baseaddressofarray$s4=i
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Aside – Compiler
ì WhenprogramminginC/C++,areyourvariables(int,float,char,…)storedinmemoryorinregisters?
ì Answer:Itdepends
ì Compilerwillchoosewheretoplacevariablesì Registers:Loopcounters,frequentlyaccessedscalar
values,variableslocaltoaprocedureì Memory:Arrays,infrequentlyaccesseddatavalues
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ìMIPS Branches / Loops
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Branches, Tests, Jump
ì BranchonEqual(if$1==$2,goto dest)
ì SetonLessThan(if$2<$3,set$1=1,otherwise0)
ì Jump(goto dest)
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beq <reg1>, <reg2>, <destination>
slt <reg1>, <reg2>, <reg3>
j <destination>
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Task : Write Code
ì WriteMIPSassemblyfor:
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if(A==B){
<equal-code>}else{
<not-equal-code>}<after-if-code>
A==B?
… …
True False
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Task : Write Code
ì WriteMIPSassembly:
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Code:beq $s0,$s1,equal<not-equal-code>j done
equal: <equal-code>j done
done: <after-if-code>
Map:$s0=A$s1=B
![Page 50: MIPS Assembly - University of the Pacificecs-network.serv.pacific.edu/ecpe-170/slides/14mipsassembly.pdfì Computer Systems and Networks ECPE 170 –Jeff Shafer –University of the](https://reader031.vdocument.in/reader031/viewer/2022022511/5adef46b7f8b9a1c248b6ea0/html5/thumbnails/50.jpg)
Task : Write Code
ì WriteMIPSassemblyfor:
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while(A!=B){
<loop-body>}
<post-loop-code>
A!=B?
…
…
True
False
![Page 51: MIPS Assembly - University of the Pacificecs-network.serv.pacific.edu/ecpe-170/slides/14mipsassembly.pdfì Computer Systems and Networks ECPE 170 –Jeff Shafer –University of the](https://reader031.vdocument.in/reader031/viewer/2022022511/5adef46b7f8b9a1c248b6ea0/html5/thumbnails/51.jpg)
Task : Write Code
ì WriteMIPSassembly:
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Code:
start: beq $s0,$s1,done<loop-body>j start
done: <post-loop-code>
Map:$s0=A$s1=B
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Therearemany,many,variationsofbranchortestinstructionsintendedtosimplifyprogramming
1. Show:AppendixAReference
2. Discuss:InstructionversusPseudo-Instruction
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Resources
ì ResourcesonWebsite– view“Resources”pageì MIPSInstructionSet(partialguide)
ì ResourcesavailableinSakaisite(underECPE170)ì HP_AppA.pdf
ì AppendixAfromfamousHennessy&PattersonComputerOrganization textbook
ì Assemblers,Linkers,andtheSPIMsimulatorì Startingonpage51isanoverviewoftheMIPSassembly
commands!ì MIPS_Green_Sheet.pdf
ì “Cheatsheet”forexpertprogrammersì MIPScommands,registers,memoryconventions,…
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ìMIPS Simulator Walkthrough
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SingleStepButton!
(Advanceby1instruction)
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