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MAMBO III
Monolithic Active Pixel
Matrix with Binary Counters
Farah Khalid
Alpana Shenai
Gregory Deptuch
Raymond Yarema1
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Presentation OutlineApplications
Previous Work: MAMBO II
Design
Results
MAMBO III development
Goals
Schematic
Layout
T-Micro (ZyCube) 3D Integration
MAMBO IV: Future work2
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POSSIBLE APPLICATIONS
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Possible applications
E.g.
X-ray autoradiography
Fluorescence X-ray spectroscopy
Low energy applications up to 12kEv
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PREVIOUS WORK
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Ch
Design details of pixel imaging detector „MAMBO”
MAMBO = Monolithic Active Pixel Matrix with Binary Counters
• each pixel:
integrating CSA w/ p-z network,
shaping filter CR-RC2 with
tp=200ns; gain=~200 mV/e- for
small Q, multiple diodes/pixel,
ripple counter reconfigurable
into shift register
• compact design excluding use of physical resistors
Cc=28 fF, Cfs=3.3 fF, Rfs=50 MW, Gm=5.8 mS, Ch=30 fF,
MAMBO II architecture
MAMBO2
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Design details of pixel imaging detector „MAMBO”
47m
m
47 mm MAMBO II pixel layout
Single pixel test structure is a fully functional
ciruit allowing monitoring: shaper output,
discriminator output, counter output
Multiple p-taps (used as signal electrodes) present per
pixel for reduction of shifts of threshold voltages.
Partial success: adjustment of bias voltages and
currents (referred to VGS) up to several tens of mV still
required for Vback from the range from 0 to 10V.
MAMBO II chip layout
single pixel
test
structrue
13 diodes
in parallel
connection
94×94
pixels
array
8×10 20×20 mm2 3T pixel matrices for
x-talk and test charge collection tests
MAMBO2: PREVIOUS WORK….
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Achievements, observations and investigations
MAMBO II single pixel test
Monitoring of the shaper and discriminator outputs (transient signals )
55Fe 109Cd
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• the OKI process offers enhancements: through BOX contacts and diode and ohmic
implants in the substrate material for the first time in a commercial approach!
L
J
K• matrices using 3T-type pixels can succesfully be built (NMOS/PMOS switches may
be used); – some progress but not too much beyond bulk MAPS.
• mutual influence of CMOS circuitry and the detector is affecting designs of more
advanced circuits for imaging.
credo: strength of the SOI monolithic active pixel technology is integration of
whole processing circuitry directly into ‘the focal plane’
• FD-SOI represents challenges for precise analog circuits, one would prefer different
flavor!
• the properties of the substrate material and how it is depleted is far from being
understood. The depletion may depend on transient and statically hold voltage states
in the CMOS circuitry!
• observed high sensitivity to irradiation; overnight exposure under 100 mCi 109Cd
under full operation causes ~100 mV voltage levels shifts.
• the process must be enhanced.
The first priorities are to separate substrate and CMOS circuitry
Conclusions
9
• monolithic detector structures can operate depleted for the first time succesfully!
J
L
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MAMBO III
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GoalsR&D
Detector and electronics on different layers (to avoid coupling)
Diodes with PPLUS with BPW to reduce leakage
Diode of the same size as the pixel to obtain parallel electric field in active volume, and avoid potential pockets
Shielding on detector layer
Possibility of changing gated diode voltage to enhance performance of the diode
Explore 3D IC technology with T-Micro
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3D : MAMBO 3
Tier 1 contains only diodes and shielding metal MAMBO 3
bottom
ASIC
MAMBO 3
top ASIC
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3D Model: Diode (Bottom Pixel)
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Top ASIC: PIXEL Design
PREAMP SHAPER BLR WINDOW
COMPARATOR
4b DAC H
4b DAC L
DDL Logic
COUNTER/
SHIFT
REGISTER
12b
ANALOG
BUFFER
DIGITAL
BUFFER
VthH
VthL Baseline
PREVIOUS
PIXEL
NEXT
PIXEL
Test
Output
Configuration Register -DAC setup (8bits) -Test setup (3bits)
NEXT
PIXEL
PREVIOUS
PIXEL
2
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Preamplifier
Cfs=5fF, Gm=6.5µS, Rfs=28MΩ, Ch=25fF,
Cc=35fF
• Regulated Cascode
• Leakage current compensation
• 1.7fF I/P test capacitance
15
Test Setup
Protection
diode
Feedback Capacitor
Coupling Capacitor
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Shaper and Baseline Restorer
BASELIN E R ESTO RER
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Analog Test Buffer
SO URC E
FO LLOW ERSO U RC E
FO LLOW ER
•Source
Followers
using Zero Vt
DMOS
transistors
• Single Stage
amplifier
•Disconnected
during normal
mode of
operation
•10 µA current
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Comparator
• Hysteresis Comparator
• Connected to Vref during normal operation
OR
•Connected to baseline for trimming
OR
•Connected to gnd! when disabled
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Trimming DAC current
outputs
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Window Comparator
VthL – Lower
Threshold
VthH –Upper
Threshold
VthL < Signals < VthH
is recorded as HIT
Comparators are
independently
trimmed to cancel
offsets
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Double Discriminator Logic
• Output of the Lower Threshold
comparator behaves as a clock
• Output of the Upper Threshold
comparator behaves as a Reset
• When both comparators fire the
hit is not counted
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Current Steering DAC (4 bits)
M = 1 M = 2M = 4 M = 8
• Binary weighted current mirrors
•Switches are also binary weighted
• Current can be steered either to positive or negative output
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Cascode
current source
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DAC Layout
4 3 4 3 4
4 2 1 2 4
4 3 4 3 4
Conventional symmetrical common
centroid geometry for current mirrors
Helps to average out global errors
•Matching is critical for monotonic
performance
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Trimming DACs
Offset distribution after digital compensation
Offset distribution before compensation
•Gaussian distribution
•Depends on component matching
• Uniform distribution
• Residual offset depends on DAC resolution
Matching is expected to be worse for SOI, Data here corresponds to a typical bulk CMOS process
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Configuration RegisterSerial In Parallel Load
(4b x 2) for DAC settings
3 bit test setup
Test Control block used as decoder to control switches for test
FlipFlop2Q
CD
FlipFlop1Q
CD
FlipFlop11Q
CD
Latch2Q
CD
Latch11Q
CD
Latch1Q
CD
Serial Clk
Parallel Load
Setup
000 Normal Operation
001 Analogue Output for test calibration
010 Test Input, counter connected
011 Calibrate DAC L
100 Calibrate DAC H
101 xx
110 xx
111 Pixel Disabled24
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1bit Counter
SH IFT
C O U N T
Can be configured as:
Counter (s1 is ON)
Shift Register (s2 is
ON)
s1 and s2 are non-
overlapping clocks
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Counter /Shift Register
12 bit ripple counter
Count switch disconnects counter from comparator while shifting
CK_READ is external clock used for shifting data
Shift switch applied shifting clock
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s1 and s2 are non-
overlapping clocks
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Simulation result
PREAMP INPUT
PREAMP OUTPUT
SHAPER OUTPUT
Comparator : Lower Threshold
Comparator : Upper Threshold
DDL Output
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I/P charge of 2000e-
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LAYOUT
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MAMBO3: top pixel
• 100µ x 100µm
•Transistor count ~ 950
•Analogue and Digital
buffers only active
during single pixel testC
on
fig
ura
tio
n R
eg
iste
r
DACs
Test
Control
Logic
Double
Discriminator
Logic
Comparators
Shaper
Preamplifier
Analogue
Buffer
Co
un
ter / S
hift R
eg
iste
r
Dig
ital B
uffe
r
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Upper Chip
• 5mm x 5mm
• 1936 pixel matrix (44
x44)
• Each column has
additional buffering of
analog and digital
signals
• Pads with back metal
opening
• Alignment markers
on all 4 corners
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Lower chip: Diode Pixel
DIODE
100µ x 100µ
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Lower Chip
• 5mm x 5mm
• 1936 pixel matrix (44 x44)
• 4 guard rings around the
matrix
• No bond Pads contains only
micro bump pads, aligned
with the top chip.
• Alignment markers on all 4
corners
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Chip connectionMICROBUMP (5µmx5µm)
-Diode connection per
pixel
-Dummy connections
-guard rings
-diode shielding (gnd!)
-gate control33
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Protection
Shielding per pixel using back metal
• After handle wafer is
removed the bodies of
transistors and sensitive
nodes are exposed to
electrical coupling from
external environment
•Backplane connected to
Analogue Ground per pixel
•Peripheral digital logic
connected to Digital ground
plane exposed transistor
34
BMetal
Slot in BMetal
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INTEGRATION
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3D Model
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T-Micro 3D Integration process
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µ-bump process
38 © T-Micro, VIPS2010
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Cross sectional view
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Cross sectional view:
Test chip with adhesive
40
© T-Micro , VIPS 2010
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MAMBO IV: FUTURE WORK
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Back to 2D Availability of nested
well option
BNW layer inside a
deeper BPW implant
Isolation of diode and
electronics
Increased parasitic
junction capacitance
(currently undetermined)
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BPW
BNW
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MAMBO IV
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MAMBO IV
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Thank you
45