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Puneet Gupta ([email protected])
Non-Rectangular Gates: Models and Use
Puneet [email protected]
http://www.ee.ucla.edu/~puneet
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Puneet Gupta ([email protected])
Agenda
•
Introduction•
Modeling Polysilicon Imperfections
•
Modeling Diffusion Imperfections•
Modeling Line-End Imperfections
•
Integration into Design Flow•
Conclusions
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Puneet Gupta ([email protected])
Contour-Based Design Analyses
•
Design timing/power analysis based on assumption of perfect printing–
Subwavelength lithography rectangles print as contours Need new set of models, algorithms and methodologies to handle non-rectilinear shapes
•
Address both devices and interconnect; both cells and full-chip
What designer sees What silicon shows
1mW, 200MHz 1.3mW, 180MHz
Contour-based{RC Extraction,
Device modeling}
Power, Performance
Analysis
1.3mW, 180MHz
[SPIE’05, SPIE’06]
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Puneet Gupta ([email protected])
Is Interconnect Modeling Important ?
•
Probably not..–
Litho impacts wire width↑↓
(w)
•
w↑ Rwire↓, Cg↑, Cc↑
–
Wire_Delay ~ 0.5*Rwire
*(Cg
+ Cc
+ CL
) ~ –
Gate_Delay ~ Rgate
*(Cg
+ Cc
+ CL
) ~ –
Wires are long averaging effects
–
Semi-global and global wiring (M3+) is wide and regular patterning less of an issue
–
M1/M2 impact on power/performance is small–
Caveat: contacts (and via) R variation may be non-
negligible
•
Let us concentrate on devices
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Puneet Gupta ([email protected])•5
Device Imperfections
•
Shape imperfections to be modeled electrically–
Polysilicon gate shape contours [SPIE’06]–
Diffusion rounding [ASPDAC’08]•
Usually on “source-side”
to make PWR/GND connection–
Line-end shortening gate not completely formed [DAC’07]–
Line-end rounding “tapering”, “necking” or “bulging” [PMJ’08]•
Possibly model these across lithographic process variations: focus, exposure, overlay
Figure courtesy Blaze DFM
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Puneet Gupta ([email protected])
Agenda
•
Introduction•
Modeling Polysilicon Imperfections
•
Modeling Diffusion Imperfections•
Modeling Line-End Imperfections
•
Integration into Design Flow•
Conclusions
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Puneet Gupta ([email protected])
Contour-Based Current Calculation
•
Poly overlapping active area represents transistor gate
•
Equivalent gate length (Leq
) can be used to represent the current behavior of the transistor to communicate to SPICE
x
L(x)
Wseg
I(x) = f(L(x))Ishape
= ∑I(x)Wseg
Leq = f-1(Ishape
/W)
Slicing Technique for Contour-Based Ion
Prediction
x=0
Figure courtesy Praveen Elakkumanan, IBM Corp
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Puneet Gupta ([email protected])•8
The Model
•
Threshold voltage modeled as a function of location along channel width–
Dopant densities, well-proximity effects, line-end capacitive coupling change, etc with distance from STI edge
–
Leads to Ion/Ioff vs. W plot to be not perfectly linear•
The extent and kind of behavior is very process-dependent
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Puneet Gupta ([email protected])
Fitting the Model
•
Can be done purely in SPICE regime–
NWE effect in BSIM Ioff vs. w plot can be used to fit Vth vs. location
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Puneet Gupta ([email protected])
Results
Length of Protrusion/Depression 82 86 90 94 98Location(nm)
Davinci 0 1.477 1.163 1 0.919 0.87Proposed Model 1.543 1.194 1 0.911 0.838Flat Model 1.133 1.04 1 0.978 0.967
Davinci 20 1.247 1.083 1 0.982 0.971Proposed Model 1.197 1.061 1 0.97 0.954Flat Model 1.133 1.04 1 0.978 0.967
Davinci 40 1.124 1.042 1 0.991 0.984Proposed Model 1.088 1.024 1 0.989 0.984Flat Model 1.133 1.04 1 0.978 0.967
Davinci 60 1.092 1.031 1 0.993 0.989Proposed Model 1.079 1.021 1 0.991 0.986Flat Model 1.133 1.04 1 0.978 0.967
Davinci 80 1.082 1.027 1 0.994 0.991Proposed Model 1.079 1.021 1 0.991 0.986Flat Model 1.133 1.04 1 0.978 0.967
Width of Protrusion/Depression = 20nm Z = 400nm
∆L/2
W’
Z = 0
W
L
Z’
Good agreement with TCAD
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Puneet Gupta ([email protected])
Agenda
•
Introduction•
Modeling Polysilicon Imperfections
•
Modeling Diffusion Imperfections•
Modeling Line-End Imperfections
•
Integration into a Design Flow•
Conclusions
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Puneet Gupta ([email protected])
Diffusion Rounding
•
Diffusion rounding: more of a concern than poly rounding•
Amount: depends on poly gate to the diffusion spacing
•
Not negligible impact: several 10s of nm of rounding under the gate in 90nm node
•
Location: source (common) or drain side of devices–
E.g., to make VDD/GND connections•
Avoidance: metal only connections
VDD
GND60nm
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Puneet Gupta ([email protected])•1
TCAD Simulation Results
•
Ion
(Performance)–
Small increase in in both cases increase in Weq
•
Ioff
(Leakage)–
Decreases with source-side diffusion
rounding increase in Leqat edge
–
Increases with drain-side rounding
DS
W’
W
L
DS
W’
W
L
Source side nominal 5nm 10nm 20nm 30nm 40nm 20nm both 40nm both
NMOS
Ion (µA) 232 235 236 237 238 241 245 255Ioff (pA) 249 241 232 217 206 198 259 269Ion_norm 1.00 1.01 1.01 1.02 1.03 1.04 1.06 1.10Ioff_norm 1.00 0.96 0.93 0.87 0.83 0.79 1.04 1.08
Drain side nominal 5nm 10nm 20nm 30nm 40nm
NMOS
Ion (µA) 232 234 235 237 239 240Ioff (pA) 249 289 279 254 255 245Ion_norm 1.00 1.01 1.01 1.02 1.03 1.04Ioff_norm 1.00 1.16 1.12 1.02 1.02 0.98
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Puneet Gupta ([email protected])•14
•
For Ion
, effective gate area change
•
For Ioff
, exponential function of Leff
at the edge
•
Only source-side rounding (common)
•
Ignore drain-side diffusion rounding
Simple Models for Diffusion Rounding
_( '/ 2)* 1on on nomwI IW
⎡ ⎤= +⎢ ⎥⎣ ⎦
_ 1* *exp( )'
nomoff off nom
LI I KL
=
DS
w’
W
Lnom
L’
2 2
where, is fitting parameters (NMOS: 0.33, PMOS: 0.34)
is effective channel length at the edge ( = ' )
1
nom
K
L' w L+
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Puneet Gupta ([email protected])
Model Accuracy
0 10 20 30 40
0.8
0.9
1.0
Ion
nom
norm
aliz
ed c
urre
nt
size (nm)
NMOS Ion(sim) NMOS Ioff(sim) NMOS Ion(model) NMOS Ioff(model) PMOS Ion(sim) PMOS Ioff(sim) PMOS Ion(model) PMOS Ioff(model)Ioff
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Puneet Gupta ([email protected])
Model Verification
device#
Wdrawn(nm)
nominal litho-contour(TCAD)
contour2nom(%) model model2contour
(%)
Ion(µA)
Ioff(pA)
Ion(µA)
Ioff(pA) Ion Ioff
W’(nm)
Ion(µA)
Ioff(pA) Ion Ioff
1 274 136.15 6.53 137.48 4.88 0.98 -25.24 15 139.88 4.95 1.74 1.41
2 164 85.33 5.87 90.63 3.59 6.21 -38.85 20,15 91.40 3.71 0.85 3.503 164 85.33 5.87 87.81 5.20 2.91 -11.36 19 88.62 5.12 0.93 -1.51
4 164 85.33 5.87 88.96 5.43 4.25 -7.41 11 87.23 5.22 -1.94 -4.02
5 234 117.66 6.29 120.09 5.43 2.07 -13.71 15 120.17 5.55 0.07 2.18
6 209 106.11 6.14 108.64 5.70 2.38 -7.19 19 109.33 5.36 0.63 -5.92
(1)
(2) (3) (4) (5) (6)
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Puneet Gupta ([email protected])
Case Study (DFFX1)
nominal(w/o diffusion rounding) w/ diffusion rounding delta (%)
leakage (nW) 138.69 83.49 39.8
clk→q (ps)
fall 70.57 68.54 2.9rise 76.07 74.07 2.6
setup time (ps)
fall 20.43 18.08 11.5rise 42.71 35.01 18.0
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Puneet Gupta ([email protected])
Agenda
•
Introduction•
Modeling Polysilicon Imperfections
•
Modeling Diffusion Imperfections•
Modeling Line-End Imperfections
•
Integration into a Design Flow•
Conclusions
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Puneet Gupta ([email protected])
Line-End Shortening: Not Always a Failure
•
Line-end shortening (LES) causes–
Misalignment between poly and diffusion
–
Litho patterning problems•
LES considered a catastrophic
failure in circuits–
Line-end extension (LEE) applied to prevent it at the expense
of cell area•
This work: a device with some LES still can function correctly
S D
LEE
LES
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Puneet Gupta ([email protected])
VTC of LES vs. Non-LES Inverters
0.0 0.2 0.4 0.6 0.8 1.0 1.20.0
0.2
0.4
0.6
0.8
1.0
1.2
Vout
(V)
Vin (V)
5nm LES non-LES 30nm LES •
Less than rail-to-rail swing–
~120mV drop << Vth not enough to
cause spurious transition in next stage
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Puneet Gupta ([email protected])
A Circuit Perspective on LES
LES (nm)
∆VDD3 (mV)
Nominal 0.05
0 0.05
5 1.04
10 3.20
20 7.50
30 13.30
Structure Rise(ps) Fall(ps)Nominal 25.59 26.11
5nm Symmetrical 25.30 25.79
5nm PMOS Only 22.60 27.06
5nm NMOS Only 27.26 23.22
VDD degradation
Delay
•
LES on both PMOS and NMOS short-circuit current reduces impact of increased Ion• Significant speed up with only one LES device • LES inverter works! not a functional failure
2:LES1:NOM 3:NOM
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Puneet Gupta ([email protected])
Electrical Metrics for Line-end Tapers
. Worst DOF
(b) Slope
(c) Bulge
(a) Typical
Moderate
(d) Asymmetry
Best DOF
Active
Poly
Aggressive
•
Line end imperfections “taper”–
Impact•
Worsened impact under misalignment•
Major RET concern•
Line-end extension rule: major cause of area increase–
Metrics•
Geometric: pullback, CD at gate edge•
Electrical: currently non-existent
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Puneet Gupta ([email protected])
Super-Ellipse Representation•
Goal: To explore varied line-
end shapes systematically without OPC and simulation
•
Model: Super-ellipse–
Tapering, bulging, necking can be modeled
–
Closed-form CD model
1=−+
nn
bky
ax
a x
y
o kb
1
2 3
Small a Large aSmall n Large n
(a) Tapering (b) Bulge
b
a
MinimumNecking Location
Small b
Mirroring
Large bb
b
k
Mirroring
(c) Necking
lminklmin
LnomLnom Lnom Lnom
ylmin
Super-Ellipse
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Puneet Gupta ([email protected])
Electrical Impact of Line-EndLEE vs. CapacitanceLine-end extension increases Cg because there exist fringe capacitance between line-
end extension and channel.
Capacitance vs. Vth
Cg
affects Vth
, following Vth model equation.Cg increase Vth decreaseCg decrease Vth increase
Vth
vs. CurrentIon
and Ioff are functions of VthVth increase Ion, Ioff decreaseVth decrease Ion, Ioff increase
140
160
180
200
220
240
0 10 20 30 40 50 60 70 80 90 100
Line-End Extension (nm)
Cur
rent
(Ion
: uA
)
100
120
140
160
180
200
220
240
Cur
rent
(Iof
f: pA
)
Ion(uA)
Ioff(pA)
Increasing LEE
Cg
Vth
BfbV ψ2+
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Puneet Gupta ([email protected])
Misalignment ModelThere exists misalignment error between
gate and diffusion processes. Overlapping region (=actual channel) can
be varied by misalignment error.Increase linewidth variation
Misalignment has a probability, P(m).
3σ-3σ
P(-3σ <x<-3*(3/5)σ)
P(-3*(3/5)σ <x <-(3/5)σ) P(-3*(3/5)σ <x <(3/5)σ)
P(3*(3/5)σ <x<3σ)
P(-(3/5)σ <x <(3/5)σ)
∑=
⋅=5
1exp )()(
mmImPI
Active
Poly
θr
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Puneet Gupta ([email protected])
Impact on Standard CellStandard Cell Layout vs. Line-End Design Rule
(Line-End Length, Sharpness) vs. (Leakage, Area)
Height constraint graph:-Longest path determines the height of a cell
a/2 b
e/2 c2 c1d d
fg
f
e/2
b a/2
Height constraint graph:-Longest path determines the height of a cell
a/2 b
e/2 c2 c1d d
fg
f
e/2
b a/2
Poly
Diffusion
NWellContact
ae b
c1
c2
ddf
fg
bae
H
a
a
3.00E-10
3.50E-10
4.00E-10
4.50E-10
5.00E-10
5.50E-10
6.00E-10
6.50E-10
7.00E-10
7.50E-10
8.00E-10
100 90 80 70 60 50 40 30 20
LEE (nm)
Ioff
(A)
0
1
2
3
4
5
6
7
8
9
10
Are
a R
educ
tion
(%)
n=2.5n=3.0n=3.5n=4.0n=4.5n=5.0Area Reduction (%)
Small ‘n’
Large ‘n’
Small ‘n’
Large ‘n’
Misalignment: ±11nm
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Puneet Gupta ([email protected])
Impact on SRAM BitcellSRAM Bitcell Layout vs. Line-End Design Rule
(Line-End Length, Sharpness) vs. (Leakage, Area)Poly Diffusion NWell
a b c1 d d
c2
e
c2 d
b c3 f
f c3
b
b dh
ha
aac1 b
Contact
Wg
gPG
PD
PU
Width constraint graph:- Longest path determines the width of a bitcell- LEE(b) is common for all possible path
g/2 f c3 b h
ab c1 d
dc2
ec2
abc1dd
h
b c3 fg/2
3.00E-10
3.50E-10
4.00E-10
4.50E-10
5.00E-10
5.50E-10
6.00E-10
6.50E-10
7.00E-10
7.50E-10
8.00E-10
100 90 80 70 60 50 40 30 20
LEE (nm)
Ioff
(A)
0
1
2
3
4
5
6
7
8
9
10
Are
a R
educ
tion
(%)
n=2.5n=3.0n=3.5n=4.0n=4.5n=5.0Area Reduction (%)Small ‘n’
Large ‘n’
Small ‘n’
Large ‘n’
Misalignment: ±11nm
Large n is better for leakage variation↔ it increases OPC and Mask costs.
According to the taper shape, the LEE design rule can be optimized to reduce the bitcell size.
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Puneet Gupta ([email protected])
Agenda
•
Introduction•
Modeling Polysilicon Imperfections
•
Modeling Diffusion Imperfections•
Modeling Line-End Imperfections
•
Integration into Design Flow•
Conclusions
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Puneet Gupta ([email protected])
Design Flow Integration
•
Full-custom/Analog designs–
SPICE or SPICE-like analyses flows
–
Weq, Leq per transistor is sufficient•
Cell-based digital designs–
Static analysis flows based on standard cell abstraction
•
One cell is 2-100 transistors•
Timing/power views stored in pre-characterized “.lib”
files
–
Analysis done at PVT “corners”–
State of art 45nm logic designs have 10M+ cells and 50M+ transistors Hierarchy preservation essential
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Puneet Gupta ([email protected])
Adoption Challenge #1: Simulation Runtime
•
“Expected”
runtime ~ 1M instances/2 hrs–
~1nm accuracy needed for timing analysis–
Multiple focus, exposure, overlay conditions ?•
Tricks to play–
Simulate only the gate area on Poly and Diff–
Parallelization–
Leverage pre-simulated cells–
Mix of rule-based and model-based approaches–
Filter simulation areas•
Timing criticality: simulate only near critical instances •
Geometric criticality: pattern-based or graph-based filtering
•
Added complication: need for incrementality–
Timing/power optimization incrementally resimulate after change–
Trick: use methods which do not require (significant) layout change.•
E.g., multi-Vt
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Puneet Gupta ([email protected])
Adoption Challenge #2: Uniquification
•
Lithography simulation + NRG model potentially all instances of a cell master may be different–
E.g., 10 Leq steps, 10 transistors in a cell 1010 unique cell instances possible
–
Typical cell library size = 1000 cells–
Typical design size = 10M instances–
Uniquification and flattening 10000X increase in library size intractable STA, etc runtimes; data management nightmare
•
Solutions/research needs: –
Smart pruning of cell variants•
Snap to pre-chosen set of variants; or•
Generate minimal set of additional variants•
Design-context (power/timing) aware–
Incremental characterization/estimation of variants•
Transistor-level analysis methods to leverage pre-existing “.libs”•
Similar problems for any systematic variation analysis–
RTA, strain, etch…
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Puneet Gupta ([email protected])
Adoption Challenge #3: SPICE vs. Litho Corners
•
Typical BSIM corner methodology–
Based on a reference pattern context •
FF, SS, TT correspond to the device placed in the reference context•
Within this context, parameters (tox, Vt0, etc.) are fitted from
silicon over multiple L and W bins
–
Litho-dependency in the pattern contexts outside the reference pattern is not accounted for
•
Prohibitive to cover all contexts•
Some limited context-dependent “re-centering”
of the model
•
Typical litho process window–
Across focus, exposure with multiple patterns•
No explicit connection between L/W variation in litho vs. SS-FF L/W variation in SPICE No way to connect litho simulation across PW to circuit power/performance analysis
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Puneet Gupta ([email protected])
An Extreme Example
CD (= gate length) variation assumed can overestimate focus dependent component by 2X
Defocus
Line Width
Width of dense lines increases (SMILE)
Width of isolated lines decreases (FROWN)
Assumed variation if layout pattern is assumed to be random
Actual variation if dense-
ness of lines is taken into account
Actual variation if iso-
ness of lines is taken into account
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Puneet Gupta ([email protected])
A Unified Corner Methodology
•
Need to establish SPICE corner models that both lithography and SPICE communities can agree on–
Filter out systematic, litho-dependent variation–
Compatible with current SPICE corner model•
Possible solutions–
Generate context-dependent BSIM corner models•
Too many contexts complex model extraction•
No need for litho simulation–
Ignores complicated 2D, long range effects–
Reference context based correlation of litho corners and SPICE corners
•
Use SPICE calibration test patterns to calibrate F/E skew•
BSIM corner model to contain only random and unmodeled systematic variation
•
Need some silicon-qualified decomposition of L/W variation into simulatable systematics vs. everything else
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Puneet Gupta ([email protected])
Agenda
•
Introduction•
Modeling Polysilicon Imperfections
•
Modeling Diffusion Imperfections•
Modeling Line-End Imperfections
•
Integration into Design Flow•
Conclusions
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Puneet Gupta ([email protected])
The Future•
Validity–
Scenario 1: sufficient advancement in patterning equipment (EUV,
hyper-NA immersion..) lithographic printing will at least not worsen benefit from litho-aware design optimization stagnates at 45nm
–
Scenario 2: more sophisticated RET (e.g., DPL) patterning quality may be retained but modeling of RET corner cases will still be needed
litho-aware design benefits will increase beyond 45nm–
Scenario 3: no new RET or equipment litho-aware design optimization will become part of standard flows and tools beyond 45nm
–
Adoption•
Will start with libraries and IP. E.g., S2E for standard library
cells•
PD will use a mix of RDR and S2E
•
Extensions–
Additional layout-dependent manufacturing and physical effects•
Etching, Stress
–
Analysing and reducing litho-induced variability •
Focus, exposure, overlay–
Driving OPC itself using design metrics Electrical OPCBefore we end: some speculation
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Puneet Gupta ([email protected])
Draw Non-Rectangular Transistors ?
•
Conventional transistors–
Shaped as perfect rectangles
–
SPICE device models (e.g., BSIM) allow for rectangles (W x L) only
•
This work–
Explore other non-rectangular transistor shapes
•
Main goal: leakage power reduction•
Main concern: lithographic patterning
•
How: Use non-rectangular device models to arrive at optimal shape
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Puneet Gupta ([email protected])
Leakage Power Reduction•
Conventional methods delay-leakage tradeoff require design re-optimization substantial overhead–
Threshold voltage assignment
–
Gate length biasing–
Width sizing
•
Proposed alternative: shape the transistor channel to create a dominant device–
Lower leakage
–
Faster delay–
Smaller capacitanceJust replacement no optimization needed at design-
level
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Puneet Gupta ([email protected])
Why are Rectangular Gate Channels Suboptimal ?
•
Ion/Ioff densities depend on distance from device (STI) edge–
Line-end capacitance, dopant scattering, well proximity effects lowered Vth near edges Better delay-leakage tradeoff at the center than at edges Uniform channel length suboptimal
–
Longer L at edges and shorter L in center lower leakage for same delay
0 100 200 300 4003x107
4x107
5x107
6x107
7x107
8x107
9x107
1x108
1x108
Jon(A/cm2) Joff(A/cm2)
Width location(nm)
Jon(
A/cm
2 )
102
103
104
Joff(A/cm2)
0 100 200 300 400
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
ΔJo
ff/Δ
Jon
(1e-
3)
W id th Location(nm )
ΔJoff/ΔJon
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Puneet Gupta ([email protected])
Results: Device-Level
•
A commercial 90nm technology•
Results shown are for NMOS (PMOS similar)–
Ioff reduction with constant Ion
200 400 600 800 10002
4
6
8
10
12
14
Leak
age
Impr
ovem
ent (
%)
Width (nm)
Leakage Improvement vs Width
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Puneet Gupta ([email protected])
Results: Design-Level
•
ISCAS85 and MCNC Benchmarks•
Average 4.9% reduction
Circuit Name
Orig. Delay (ns)
Opt. Delay (ns)
Orig. Leakage
(uW)
Opt. Leakage
(uW)
% Imp.
C432 1.87 1.87 9.60 9.11 5.1C1908 2.24 2.24 11.98 11.38 5.0C2670 1.55 1.55 18.62 17.68 5.0C3540 2.84 2.84 4.44 4.22 4.9C5315 1.96 1.95 31.93 30.46 4.6C6288 5.62 5.61 39.66 38.38 3.2C7552 3.19 3.19 36.78 35.08 4.6
i2 0.86 0.86 13.55 12.80 5.5i3 0.45 0.45 6.07 5.74 5.4i4 0.58 0.58 5.46 5.21 4.6i5 0.52 0.52 9.22 8.77 4.9i6 0.59 0.59 10.72 10.23 4.8i7 0.72 0.72 14.22 13.50 5.1i8 1.01 1.01 25.19 23.98 4.8i9 1.37 1.37 16.28 15.40 5.4
i10 2.27 2.27 55.82 53.06 4.9