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Operating SystemsOperating SystemsCSE 411CSE 411
Introduction and OverviewIntroduction and Overview
Sept. 8 2006 - Lecture 2Sept. 8 2006 - Lecture 2
Instructor: Bhuvan UrgaonkarInstructor: Bhuvan Urgaonkar
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• Last class:– Course administration– OS definition, some history
• Today: – Background on Computer
Architecture
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Canonical System Hardware
• CPU: Processor to perform computations
• Memory: Programs and data
• I/O Devices: Disk, monitor, printer, …
• System Bus: Communication channel between the above
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CPU• CPU
– Semiconductor device, digital logic (combinational and sequential)– Can be viewed as a combination of many circuits
• Clock– Synchronizes constituent circuits
• Registers– CPU’s scratchpads; very fast; loads/stores– Most CPUs designed so that a register can store a memory
address• n-bit architecture
• Cache– Fast memory close to CPU– Faster than main memory, more expensive– Not seen by the OS
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Memory/RAM• Semiconductor device
– DIMMs mounted on PCBs– Random access: RAM– DRAM: Volatile, need to refresh
• Capacitors lose contents within few tens of msecs
• OS sees and manages memory– Programs/data need to be brought to RAM
• Memory controller: Chip that implements the logic for
• Reading/Writing to RAM (Mux/Demux)• Refreshing DRAM contents
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I/O Devices• Large variety, varying speeds
– Disk, tape, monitor, mouse, keyboard, NIC– Serial vs parallel
• Each has a controller– Hides low-level details from OS– Manages data flow between device and
CPU/memory
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Hard Disk• Secondary storage• Mechanically
operated– Sequential access
• Cheap => Abundant• Very slow
– Orders of magnitude
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Interconnects• A bus is an interconnect for flow of
data and information– Wires, protocol
– Data arbitration
• System Bus• PCI Bus
– Connects CPU-memory subsystem to
• Fast devices• Expansion bus that connects slow
devices
• SCSI, IDE, USB, …– Will return to these later
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Interlude• Recap of OS goals
– Resource management– Services to programs/applications
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Functionality Expected from a Modern OS
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Libertarian View• Everyone should get to do
whatever they want– As long as they let others
live
• Processes should feel they have the entire computer– Infinite CPU, RAM, …– No threat of someone
harming them
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Socialistic View• To each acc. to his
needs– Co-operative
existence enforced by govt/OS
– Fair allocation of resources
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OS as a Communist Govt.
• Centralized control and monitoring
• Allocate resources efficiently
• Misbehavior => Termination
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Theory vs. Practice• Performance
– Efficient and fair resource allocation, illusion of unlimited resources
• Isolation– Protect everyone from each other and from
the OS
• Secure communication• How to do this efficiently?
– Hardware support
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Architectural Support Expected by Modern
OSes
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Services & Hardware Support
• Protection: Kernel/User mode, Protected Instructions, Base & Limit Registers
• Scheduling: Timer• Interrupts: Interrupt Vectors• System Calls: Trap Instructions• Efficient I/O: Interrupts, Memory-mapping • Synchronization: Atomic Instructions• Virtual Memory: Translation Lookaside Buffer (TLB)
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Kernel/User Mode• A modern CPU has at least two modes
– Indicated by status bit in protected CPU register– OS runs in privileged mode
• Also called kernel or supervisor mode– Applications run in normal mode – Pentium processor has 4 modes
• Events that need the OS to run switch the processor to priv. mode– E.g., division by zero
• OS can switch the processor to user mode• OS definition: Software than runs in priv.
mode
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Protected Instructions
• Privileged instructions & registers:– Direct access to I/O– Modify page table pointers, TLB– Enable & disable interrupts– Halt the machine, etc.
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Base and Limit Registers
• Hardware support to protect memory regions– Loaded by OS before starting
program
• CPU checks each reference– Instruction & data addresses
• Ensures reference in range
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Interrupts• Polling = “are we there yet?” “no!”
(repeat…)– Inefficient use of resources– Annoys the CPU
• Interrupt = silence, then: “we’re there”– I/O device has own processor– When finished, device sends interrupt on
bus– CPU “handles” interrupt
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CPU Interrupt Handling
• Handling interrupts: relatively expensive• CPU must:
– Save hardware state• Registers, program counter
– Disable interrupts (why?)– Invoke via in-memory interrupt vector (like trap
vector, soon)– Enable interrupts– Restore hardware state– Continue execution of interrupted process
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Traps• Special conditions detected by architecture
– E.g.: page fault, write to read-only page, overflow, system call
• On detecting trap, hardware must:– Save process state (PC, stack, etc.)– Transfer control to trap handler (in OS)
• CPU indexes trap vector by trap number• Jumps to address
– Restore process state and resume
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Synchronization• How can OS synchronize concurrent
processes?– E.g., multiple threads, processes &
interrupts, DMA
• CPU must provide mechanism for atomicity– Series of instructions that execute as
one or not at all
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Synchronization: How-To
• One approach:– Disable interrupts– Perform action– Enable interrupts
• Advantages:– Requires no hardware support– Conceptually simple
• Disadvantages:– Could cause starvation
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Synchronization: How-To, II
• Modern approach: atomic instructions– Small set of instructions that cannot be
interrupted– Examples:
• Test-and-set (“TST”)if word contains given value, set to new value
• Compare-and-swap (“CAS”)if word equals value, swap old value with new
• Intel: LOCK prefix (XCHG, ADD, DEC, etc.)
• Used to implement locks
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Timer
• OS needs timers for– Time of day– CPU scheduling
• Interrupt vector for timer
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Memory-mapping• Direct access to I/O controller through
memory• Reserve area of memory for
communication with device (“DMA”)– Video RAM:
• CPU writes frame buffer• Video card displays it
• Fast and convenient
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Virtual Memory• Provide the illusion of infinite memory• OS loads pages from disk as needed
– Page: Fixed sized block of data
• Many benefits– Allows the execution of programs that may
not fit entirely in memory (think MS Office)
• OS needs to maintain mapping between physical and virtual memory– Page tables stored in memory
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Translation Lookaside Buffer (TLB)
• Initial virtual memory systems used to do translation in software– Meaning the OS did it– An additional memory access for each memory access!
• S.l.o.w.!!!
• Modern CPUs contain hardware to do this: the TLB– Fast cache– Modern workloads are TLB-miss dominated– Good things often come in small sizes
• We have see other instances of this
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Summary• Modern architectures provide lots of features to help
the OS do its job– TLB– Base and Limit registers– Multiple modes– Interrupts– Timers– Atomic instructions
• Otherwise impossible or impractically slow in software• Which of these are essential? Which are useful but not
essential?
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• Next time: CPU Management