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Past and Future of Micro/Nano CMOSDevices
IEEE EDS MQ @ Inter Continental Hotel, Shanghai
H. IwaiTokyo Inst. Tech.
1
November 1, 2010
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Founded in 1881, Promoted to Univ. 1929Tokyo Institute of Technology
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International StudentsInternational Students
Asia 847Europe 78 North America 12
South America 24Oceania 5
Africa 16
Total 982
Country Students
China 403
S. Korea 130
Indonesia 64
Thailand 55
Vietnam 60
Malaysia 28
(As of May. 1, 2005)
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5
大学院生のみ
岩井研究室が属している組織
物理電子システム創造専攻
他に10の専攻
先端ナノエレクトロニクスコアユニット
5つの研究所
フロンティア研究機構
ソリューション研究機構
G-COE「フォトニクス集積コアエレクトロニクス」
他に8つのG-COE
大学院
統合研究院
総合理工学研究科
他に5つの研究科 複合創造領域
他に3つのコアユニット
イノベーション研究推進体
超低消費電力・超高速情報通信用ナノデバイス集積回路の研究
他に24の推進体
東京工業大学
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石原宏 岩井洋 筒井一生大見俊一郎
杉井信之徳光英輔
益一哉
菅原聡宗片比呂夫
梶川浩太郎半那純一
小山二三夫 宮本智之植之原裕行
浅田雅洋
渡辺 正裕
伊藤治彦
強誘電体メモリ Si MOS技術 Si MOS技術共鳴トンネル素子
Si MOS技術
強誘電体メモリ Si MOS技術
回路設計技術
スピントロニクス
センサ有機半導体/SiGeデバイス
近接場光
共鳴トンネル素子
THzデバイス
光エレクトロニクス光集積デバイス フォトニックスネットワーク
スピントロニクス
東京工業大学大学院 総合理工学研究科物理電子システム創造専攻 (准教授以上)
Siデバイスの研究Si MOSFET
町田克之
寳迫巌
西山彰Si MOS技術
博(3)修(4)
博(2)修(8)学(1)
博(10)修(11)学(1) 博(6)修(5)学(1)博(1)修(6)学(1)
博(8)修(9)学(2)
修(3)学(1)
石橋幸治THzデバイス THzデバイス
修(4)学(1) 博(1)修(5)学(1)
博(4)修(4)学(1)
博(2)修(7)学(2) 博(1)
LSI/MEMS集積博(1)修(8)学(1)
博(3)修(9)学(1)
博(4)修(8)学(1) 博(1)修(9)学(1) 博(1)修(7)学(1)
修(3)修(2)
博(2)
井筒雅之光エレクトロニクス
教員数22名, 博士課程50名, 修士課程112名, 学部生17名
回路設計の研究 光デバイスの研究
その他のナノ電子デバイスの研究
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複合創造領域 先端ナノエレクトロニクス研究コアユニット研究室メンバー
Innovative Platform for Education and Research Nanoelectronics Research Frontier Core Unit
総合理工学研究科
教員
博士学生
川那子高暢 佐藤創志
幸田みゆきMaimaitirexiatiMaimaiti
AbudukelimuAbudureheman
冨田隆治
李映勲
佐々木雄一朗 舘喜一
韓熙成佐野貴洋宋永旭 廖敏
服部健雄 名取研二 角嶋邦之杉井信之 西山彰Simon Min Sze
修士学生
ダリウス・ハサンザデMokhammadSholihul Hadi
神田高志小柳友常 小澤健児 澤田剛伸 茂森直登 向井弘樹
来山大祐呉研 Dou Chunmeng 小山将央
細井隆司 中島一祐 金田翼 鈴木拓也 Li Wei (10月より) 吉村泰彦 神野浩介
石川純平
大西峻人
木村雄一郎
Rena Saimaiti久保田透
(15人)
(10人)
(28人)
物理電子システム創造専攻教授 岩井 洋
Electronics and Applied Physics Professor Hiroshi Iwai
物理電子システム創造専攻教授 筒井 一生
Electronics and Applied Physics Professor Kazuo Tsutsui
物理電子システム創造専攻准教授 大見 俊一郎
Electronics and Applied Physics Associate Professor Shunichiro Ohmi
フロンティア研究機構特任准教授アヘメト パールハットFrontier Research Center Associate Professor Parhat Ahmet
高橋慶太
佐藤寿紀 田中正興 齊藤昇
宮田陽平
萱沼良介 金原潤 林優士
東京工業大学大学院
(客員教授) (客員教授) (特任教授) (連携教授) (連携教授) (助教)
山口成幸
庄司大
(1人)技術員
(D3) (D3) (D3) (D3) (D2)高峻(D3)
(D2) (D2) (D2) (D2) (D1) (D1) (D1) (D1) (D1)
博士研究員
(1人)
学部生(3人)
研究生(1人)
(M2) (M2) (M2) (M2) (M2) (M2) (M2)(M2)
(M2) (M2) (M1) (M1) (M1) (M1) (M1)(M2)(M2)
(M1) (M1) (M1) (M1) (M1) (M1) (M1)(M1)(M1)
(B4) (B4) (B4)(M1)(M1)
Milan Kumar Bera
(2010年5月26日現在)
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研究風景
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PreparationRoom
E-Beam Evaporation8 different target
Flash LampAnnealMicro to mille-seconds
Sputter for metal5 different target
Robot room
Cluster tool for high-k thin film deposition
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10
研究設備(岩井研究室の専有装置)1
クラスタチャンバMBE(x4)+スパッタ(x2)
クラスタチャンバMBE(x7)
クラスタチャンバMBE(x8)+スパッタ(x5)+FLA
5元スパッタ装置 アーク成膜装置 蒸着装置
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研究設備(岩井研究室の専有装置)2
熱酸化炉(6本)
ランプ加熱炉2インチ
ランプ加熱炉超高速型
ランプ加熱炉6インチ
プラズマドーピング装置 反応性イオンエッチング装置 反応性イオンエッチング装置
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研究設備(岩井研究室の専有装置)3
低ノイズプローバ6インチ
プローバ8インチ
高周波プローバ8インチ
プローバ6インチ
電界放出型走査電子顕微鏡 エリプソメータ マスクアライナ
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研究設備(専攻の共同利用機器)
マスクアライナ3インチ
ドラフタイオン注入機200kV
低温プローバ
透過型電子顕微鏡200kV
反応性イオンエッチング装置
反応性イオンエッチング装置
反応性イオンエッチング装置
原子間力顕微鏡
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First Computer Eniac: made of huge number of vacuum tubes 1946Big size, huge power, short life time filament
Today's pocket PCmade of semiconductor has much higher performance with extremely low power consumption
dreamed of replacing vacuum tube with solid‐state device
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1900 1950 1960 1970 2000
VacuumTube
Transistor IC LSI ULSI
10 cm cm mm 10 µm 100 nm
In 100 years, the size reduced by one million times.There have been many devices from stone age.We have never experienced such a tremendous reduction of devices in human history.
10-1m 10-2m 10-3m 10-5m 10-7m
Downsizing of the components has been the driving force for circuit evolution
15
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1616
Scaling Method: by R. Dennard in 1974
1
1Wdep
1 1
I
00 V 1
X , Y , Z : K, V : K, Na : 1/K
K
K
KWdep
Wdep V/Na: K
KI00 KV
I : K
K=0.7 for example
Wdep: Space Charge Region (or Depletion Region) Width
Wdep has to be suppressedOtherwise, large leakagebetween S and D
Leakage current
S D
By the scaling, Wdep is suppressed in proportion,and thus, leakage can be suppressed.
Good scaled I-V characteristics
Potential in space charge region ishigh, and thus, electrons in source areattracted to the space charge region.
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1717
Drive current
Power per chip
Integration (# of Tr)
Scaling K : K=0.7 for example
Id = vsatWgCo (Vg‐Vth)
N
K‐1(αK‐2)K (K1 )2= α
Switching speed KK/K= K
Id per unit Wg = Id / Wg= 1
Wg (tox –1)(Vg‐Vth)= Wgtox
‐1(Vg‐Vth)= KK‐1K=Kin saturation
Co: gate C per unit area
Cg = εoεoxLgWg/tox
Id per unit Wg
Clock frequency
K
1
τ
Id
K
Id/µm
f 1/K f = 1/τ = 1/K
N α/K2
P α
Gate capacitance Cg K
Chip area Achip α
Lg, WgTox, Vdd
Geometry &Supply voltage
K
KK/K = K
τ= CgVdd/Id
α: Scaling factor
α/K2
fNCV2/2
= 1/K2 , when α=1
= 1, when α=1
Downscaling merit: Beautiful!
In the past, α>1 for most cases
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1818
k= 0.72 =0.5 and α =1
Vdd 0.7Single MOFET
Lg 0.7Id 0.7Cg 0.7P (Power)/Clock
0.73 = 0.34 τ (Switching time) 0.7
Chip N (# of Tr) 1/0.72 = 2
P (Power)
k= 0.7 and α =1
Vdd 0.5Lg 0.5Id 0.5Cg 0.5P (Power)/Clock
0.53 = 0.125 τ (Switching time) 0.5
1/0.7 = 1.4f (Clock)1
N (# of Tr) 1/0.52 = 4
P (Power)1/0.5 = 2f (Clock)1
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Integrated Circuits Technologies are still very important for Green or power saving!
1. Green by Integrated Circuits
2. Green of Integrated Circuits
Power saving by Microprocessor control for all the human systems
Power saving of Integrated Circuits by Down Scaling of MOSFETs in PC, Data Center, Router, etc.
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It has been always discussed about the limit of downscaling, but the down scaling of MOSFETs is still possible for another 10 or 20 years!
1. Thinning of high-k beyond 0.5 nm
2. Metal S/D
3. Si-Nanowire FET
3 important technological items for DS.
Down scaling is the most effective way ofPower saving.
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How far we can go with downscaling?
Question:
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Late 1970’s 1µm: SCE
Early 1980’s 0.5µm: S/D resistance
Early 1980’s 0.25µm: Direct‐tunneling of gate SiO2
Late 1980’s 0.1µm: ‘0.1µm brick wall’(various)
2000 50nm: ‘Red brick wall’ (various)
2000 10nm: Fundamental?
Period Expected Cause limit(size)
Many people wanted to say about the limit. Past predictions were not correct!!
22
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Historically, many predictions of the limit of downsizing.
VLSI text book written 1979 predict that 0.25 micro‐meter would be the limit because of direct‐tunneling current through the very thin‐gate oxide.
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VLSI textbook
Finally, there appears to be a fundamental limit 10 of approximately quarter micron channel length, where certain physical effects such as the tunneling through the gate oxide ..... begin to make the devices of smaller dimension unworkable.
24
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Potential Barrier
Wave function
Direct‐tunneling effect
25
G
SD
Gate Oxide
Gate OxideGate Electrode
Si Substrate
Direct tunneling leakage current start to flow when the thickness is 3 nm.
Direct tunnelingcurrent
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Direct tunneling leakage was found to be OK! In 1994!
Vg = 2.0V
1.5 V
1.0 V
0.5 V
0.0 V
1.6
1.2
0.8
0.4
0.0
‐0.4
0.0 0.5 1.0 1.5
Vd (V)
Vg = 2.0V
1.5 V
1.0 V
0.5 V
0.0 V
0.4
0.3
0.2
0.1
0.0
‐0.1
0.0 0.5 1.0 1.5
Vd (V)
Vg = 2.0V
1.5 V
1.0 V
0.5 V
0.0 V
0.08
0.06
0.04
0.02
0.00
‐0.02
0.0 0.5 1.0 1.5
Vd (V)
Vg = 2.0V
1.5 V
1.0 V
0.5 V
0.0 V
0.03
0.02
0.01
0.00
0.01
‐0.4
0.0 0.5 1.0 1.5
Vd (V)
Id (m
A / μ
m)
Lg = 10 µm Lg = 5 µm Lg = 1.0 µm Lg = 0.1µm
Gate electrode
Si substrate
Gate oxide
MOSFETs with 1.5 nm gate oxide
26
G
S D
Lg
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Vg = 2.0V
1.5 V
1.0 V
0.5 V
0.0 V
1.6
1.2
0.8
0.4
0.0
-0.40.0 0.5 1.0 1.5
Vd (V)
Vg = 2.0V
1.5 V
1.0 V
0.5 V
0.0 V
1.6
1.2
0.8
0.4
0.0
-0.40.0 0.5 1.0 1.5
Vd (V)
Vg = 2.0V
1.5 V
1.0 V
0.5 V
0.0 V
0.4
0.3
0.2
0.1
0.0
-0.10.0 0.5 1.0 1.5
Vd (V)
Vg = 2.0V
1.5 V
1.0 V
0.5 V
0.0 V
0.4
0.3
0.2
0.1
0.0
-0.10.0 0.5 1.0 1.5
Vd (V)
Vg = 2.0V
1.5 V
1.0 V
0.5 V
0.0 V
0.08
0.06
0.04
0.02
0.00
-0.020.0 0.5 1.0 1.5
Vd (V)
Vg = 2.0V
1.5 V
1.0 V
0.5 V
0.0 V
0.08
0.06
0.04
0.02
0.00
-0.020.0 0.5 1.0 1.5
Vd (V)
Vg = 2.0V
1.5 V
1.0 V
0.5 V
0.0 V
0.03
0.02
0.01
0.00
0.01
-0.40.0 0.5 1.0 1.5
Vd (V)
Id (m
A/ μ
m)
Vg = 2.0V
1.5 V
1.0 V
0.5 V
0.0 V
0.03
0.02
0.01
0.00
0.01
-0.40.0 0.5 1.0 1.5
Vd (V)
Id (m
A/ μ
m)
Lg = 10 µm Lg = 5 µm Lg = 1.0 µm Lg = 0.1µm
Gate leakage: Ig ∝ Gate Area ∝ Gate length (Lg)
Id
Drain current: Id ∝ 1/Gate length (Lg)
Lg small, Then, Ig small, Id large, Thus, Ig/Id very small
27
G
S D
Ig Id
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5 nm gate length CMOS
H. Wakabayashi et.al, NEC
IEDM, 2003
Length of 18 Si atoms
Is a Real Nano Device!!
5 nm
28
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Tunnelingdistance
3 nm
Atomdistance
0.3 nm
MOSFET operation
Lg = 3 nm?
Below this, no one knows future!
Predicted limit now
29
S D
UltimateLimit
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ITRS expect Lg less than 10nm2009 ITRS Technology Trend: MPU gate length
MPU physical gate length
ITRS
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How far can we go?
8µm 6µm 4µm 3µm 2µm 1.2µm 0.8µm 0.5µm0.35µm 0.25µm 180nm 130nm 90nm 65nm 45nm
1973年
32nm 22nm 16nm 11.5 nm 8nm 5.5nm? 4nm? 2.9 nm?
Past 0.7 times per 3 years
Now
In 40 years: 15 generations,Size 1/200, Area 1/40,000
Future
・At least 5,6 generations, for 15 ~ 20 years
・Hopefully 8 generations, for 30 years
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ITRS/JEITA
CMOS remains as the mainsream
More Than Moore:Hybrid device integration
More Moore:CMOS Mainstream
Beyond CMOS:New functional
CMOS scaling is the mainstream
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33
ITRS
Year
Vd
d (
V)
0
0.2
0.4
0.6
0.8
1
1.2
2004 2007 2010 2013 2016 2019 2022
2008up (bulk)2008up (UTB)2008up (DG)2007 (bulk)2007 (UTB)2007 (DG)2005 (bulk)2005 (UTB)2005 (DG)200320011999
20082003, 2005, 2007
1999
2001
2008 update
0.4
0.6
0.8
1
1.2
2004 2007 2010 2013 2016 2019 2022
2008up (bulk)2008up (UTB)2008up (DG)2007 (bulk)2007 (UTB)2007 (DG)2005 (bulk)2005 (UTB)2005 (DG)2003 (bulk)20011999
YearEO
T (n
m)
Is 0.5nm real limit?
for H
P Lo
gic
DelaySaturation
0.4
0.6
0.8
1
1.2
2004 2007 2010 2013 2016 2019 2022
2008up (bulk)2008up (UTB)2008up (DG)2007 (bulk)2007 (UTB)2007 (DG)2005 (bulk)2005 (UTB)2005 (DG)2003 (bulk)20011999
YearEO
T (n
m)
Is 0.5nm real limit?
for H
P Lo
gic
DelaySaturation
Vdd stay high ITRS EOT limit = 0.5 nm?
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Power of FET = CV2/2 ∝D3 (=L3)
No
rma
lize
d σ
Vth
No
rma
lize
d σ
Vth
ITRS2007
ゲート絶縁膜
リーク電流閾値ばらつき
ゲート絶縁膜厚もゲート長と同時に縮小する必要がある
ProblemsSCEVariation in VthIncrease in Off-leakage current
Solution
Scaling of high beyond 0.5 nm is important
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35
Direct contact of high‐k to Si
Year
Pow
er p
er M
OSF
ET (P
)
P∝L
g 3
(Scaling)
EOT Limit0.7~0.8 nm
EOT=0.5nm
TodayEOT=1.0nm
Now
45nm nodeLg=22nm
One order of Magnitude
Si
HfO2
Metal
SiO2/SiON
Si
High-k
Metal
Direct ContactOf high-k and Si
Si
MetalSiO2/SiON
0.5~0.7nm
Introduction of High-kStill SiO2 or SiONIs used at Si interface
For the past 45 yearsSiO2 and SiON
For gate insulator
EOT can be reduced further beyond 0.5 nm by using direct contact to SiBy choosing appropriate materials and processes.
SiO2/SiON interfacial layer
Direct contactHigh-k/Si
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PreparationRoom
E-Beam Evaporation8 different target
Flash LampAnnealMicro to mille-seconds
Sputter for metal5 different target
Robot room
Cluster tool for high-k thin film deposition
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37
Challenge to EOT~0.3nm
1
EOT<0.5nm with Gain in Drive Current
14% of Id increase is observed even at saturation region
EOT below 0.4nm is still useful for scaling
0 0.2 0.4 0.6 0.8 1 0 0.2 0.4 0.6 0.8 1 0 0.2 0.4 0.6 0.8 1
Dra
in c
urre
nt (m
A) 3.5
2
1
0
3
(a) EOT=0.37nm (b) EOT=0.43nm (c) EOT=0.48nm
W/L=2.5/50µmPMA 300oC (30min)
Vth=-0.04V Vth=-0.03V Vth=-0.02V
14%up4%up
0 0.2 0.4 0.6 0.8 1Drain voltage (V)
0 0.2 0.4 0.6 0.8 1Drain voltage (V)
0 0.2 0.4 0.6 0.8 1Drain voltage (V)
compensation regioninsufficient
W/L=50/2.5µm
0 0.2 0.4 0.6 0.8 1 0 0.2 0.4 0.6 0.8 1 0 0.2 0.4 0.6 0.8 1
Dra
in c
urre
nt (m
A) 3.5
2
1
0
3
(a) EOT=0.37nm (b) EOT=0.43nm (c) EOT=0.48nm
W/L=2.5/50µmPMA 300oC (30min)
Vth=-0.04V Vth=-0.03V Vth=-0.02V
14%up4%up
0 0.2 0.4 0.6 0.8 1Drain voltage (V)
0 0.2 0.4 0.6 0.8 1Drain voltage (V)
0 0.2 0.4 0.6 0.8 1Drain voltage (V)
compensation regioninsufficient
W/L=50/2.5µm
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38
Si Nanowire FET
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Planar Fin Nanowire
Source DrainGate
Wdep
1
Leakage current
S D
Planar FETFin FET Nanowire FET
Because of off-leakage control,
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Nanowire FETNanowire FET
Nanowire FET
ITRS 2009
Multiple Gate (Fin)FET
Bulk → Fin → Nanowire
Siナノワイヤ
FinBulk or SOI
Si Nanowire
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41
Si nanowire FET as a strong candidate
1. Compatibility with current CMOS process
2. Good controllability of IOFF
3. High drive current
1D ballisticconduction
Multi quantumChannel High integration
of wires
k
E
量子チャネル
量子チャネル量子チャネル量子チャネル
バンド図
Quantum channelQuantum channel
Quantum channelQuantum channel
k
E
量子チャネル
量子チャネル量子チャネル量子チャネル
バンド図
Quantum channelQuantum channel
Quantum channelQuantum channel
Off電流のカットオフ
Gate:OFFDrain Source
cut-off
Gate: OFFdrainsource
Off電流のカットオフ
Gate:OFFDrain Source
cut-off
Gate: OFFdrainsource
Wdep
1
Leakage current
S D
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1
10
100
1000
10000
0 1000 2000 3000 4000
bulkFinFETSiNWFETGeNWFETITRS(Planer)ITRS(SOI)ITRS(DG)
Bulk
DG
dia~3nm
dia~10nm
ITRS (SOI)
ITRS (DG)
ITRS(Bulk)
Si Nanowire
Ion (uA/um)
Ioff
(nA
/um
)
1
10
100
1000
10000
0 1000 2000 3000 4000
bulkFinFETSiNWFETGeNWFETITRS(Planer)ITRS(SOI)ITRS(DG)
1
10
100
1000
10000
0 1000 2000 3000 4000
bulkFinFETSiNWFETGeNWFETITRS(Planer)ITRS(SOI)ITRS(DG)
Bulk
DG
dia~3nm
dia~10nm
ITRS (SOI)
ITRS (DG)
ITRS(Bulk)
Si Nanowire
Ion (uA/um)
Ioff
(nA
/um
)Off Current
42
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Increase the Number of quantum channels
Energy band of Bulk Si
Eg
By Prof. Shiraishi of Tsukuba univ.
Energy band of 3 x 3 Si wire
4 channels can be used
Eg
43
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Maximum number of wires per 1 µm
Surrounded gate type MOS
Front gate type MOS 165 wires /µm
33 wires/µm
High-k gate insulator (4nm)Si Nano wire (Diameter 2nm)
Metal gate electrode(10nm)
Surrounded gate MOS
30nm
6nm6nm pitchBy nano-imprint method
30nm pitch: EUV lithograpy
44
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Device fabrication
Si/Si0.8Ge0.2superlatticeepitaxy on SOI
Anisotropicetchingof these layers
Isotropicetchingof SiGe
Gate depositions S/D implantationSpacer formationActivation annealSalicidation
BOXSi
SiGeSi
SiGeSi
SiGeSiN
BOX BOX
BOX
Gate
BOX
Gate
Gate etchingStandardBack-Endof-LineProcess
HfO2 (3nm)TiN (10nm)Poly-Si (200nm)
C. Dupre et al.,IEDM Tech. Dig., p.749, 2008
7
SiN HM
Process Details :
The NW diameteris controllabledown to 5 nm by self limited oxidation.
( )
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Cross-section
50nm
SiN HM
Wire direction : <110>50 NWs in parallel3 levels vertically-stackedTotal array of 150 wires EOT ~2.6 nm
NWs
8
3D-stacked Si NWs with Hi-k/MG
BOX
500 nm
Sou
rce
Dra
in
Gate
Top view
<110>
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SiNW Band structure calculation
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Cross section of Si NW
[001] [011] [111]D=1.96nm D=1.94nm D=1.93nm
First principal calculation,
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Si nanowire FET with 1D Transport[001] [011] [111]0.86 0.94 0.89
OrientationDiameter (nm)
[001] [011] [111]3.00 3.94 1.93
OrientationDiameter (nm)
ZG G GZ ZWave Number
ZG G GZ ZWave Number
Ener
gy (e
V)
0
-1
0
1
Ener
gy (e
V)
0
-1
0
1
(a)
(b)
Small mass with [011]
Large number of quantum channels with [001]
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10 nm diameter Si(100)NW( 2341 atoms)
20 nm diameter Si(100)NW ( 8941 atoms )
Atomic models of a Si quantum dot and Si nanowires
6.6 nm diameter SiQD( 8651 atoms)
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2 6
26
( , , ) ( , , )n m nm
x y z C x m x y zx
ψ ψ=−
∂≈ + ∆
∂ ∑
1( ) ( ) ( ) ( )
Mesh
m n m i n ii
d x y zψ ψ ψ ψ=
≈ ∆ ∆ ∆∑∫ r r r r r
Real-Space Finite-DifferenceSparse MatrixFFT free (FFT is inevitable in the conventional plane-wave code)
Kohn-Sham eq. (finite-difference)
3D grid is divided by several regionsfor parallel computation.
Higher-order finite difference
Integration
MPI_ISEND, MPI_IRECV
MPI_ALLREDUCE
RSDFT – suitable for parallel first-principles calculation -
MPI ( Message Passing Interface ) library
)()()(ˆ)]([21 2 rrrr nnn
PPnlocs vv φεφρ =⎟
⎠⎞
⎜⎝⎛ ++∇−
CPU0
CPU8CPU7CPU6
CPU5CPU4CPU3
CPU2CPU1
Higher-order finite difference pseudopotential methodJ. R. Chelikowsky et al., Phys. Rev. B, (1994)
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10-10
10-9
10-8
10-7
10-6
10-5
10-4
10-3
10-2
10-1
|Vnew-Vold|^2
50403020100iteration
Convergence behavior for Si10701H1996
e.g.) The system over 10,000 atoms → Si10701H1996(7.6 nm diameter Si dot)
Massively Parallel Computing
Computational Time (with 1024 nodes of PACS-CS
6781 sec. × 60 iteration step = 113 hour
Based on the finite-difference pseudopotential method (J. R. Chelikowsky et al., PRB1994)
Highly tuned for massively parallel computers
Computations are done on a massively-parallel cluster PACS-CS at University of Tsukuba.
(Theoretical Peak Performance = 5.6GFLOPS/node)
with our recently developed code “RSDFT”
Iwata et al, J. Comp. Phys., to be publishedReal-Space Density-Functional Theory code (RSDFT)
Grid points = 3,402,059Bands = 22,432
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1.0
0.9
0.8
0.7
0.6
0.5
(eV
)
-0.6
-0.4
-0.2
0.0
(eV
)
1.2
1.1
1.0
0.9
0.8
0.7
(eV
)
-0.8
-0.4
0.0
0.4
(eV
)
3.4
3.2
3.0
2.8
2.6
(eV
)
-1.5
-1.0
-0.5
0.0
0.5
(eV
)
1.0
0.8
0.6
0.4
0.2
0.0DO
S ( S
tate
s / e
V a
tom
)
-12 -10 -8 -6 -4 -2 0 2(eV)
1.0
0.8
0.6
0.4
0.2
0.0DO
S ( S
tate
s / e
V a
tom
)
-12 -10 -8 -6 -4 -2 0 2(eV)
1.0
0.8
0.6
0.4
0.2
0.0DO
S ( S
tate
s / e
V a
tom
)
-10 -8 -6 -4 -2 0 2 4 6(eV)
Band Structure and DOS of Si(100)NWs (D=1nm, 4nm, and 8nm)
D = 4 nmSi341H84(425 atoms)KS band gap = 0.81eV
D=4nm D=8nmD=1nm
D=8 nmSi1361H164 (1525 atoms)KS band gap=0.61eV
D=1 nmSi21H20(41 atoms)KS band gap=2.60eV
KS band gap of bulk (LDA) = 0.53eV
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Band structure of 8-nm-diameter Si nanowire near the CBM
1.0
0.9
0.8
0.7
0.6
0.5
(eV
)
0.300.250.200.150.100.050.00
・KS band gap = 0.608 eV (@Γ)
kz
kx
ky
82 meV (96 meV)
kx
Each band is4-dgenerate. 23 meV (24 meV)
)()()(22 2
2
*
2
2
2
2
2
*
2
rr Φ−=Φ⎥⎦
⎤⎢⎣
⎡
∂∂
−⎟⎟⎠
⎞⎜⎜⎝
⎛∂∂
+∂∂
− CBMlt zmyxm
εεhh
Effective mass equation
The band structure can be understood thatelectrons near the CBM in the bulk Si are Confined within a cylindrical geometry.
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Si12822H1544(14,366 atoms)・10nm diameter、3.3nm height、(100)・Grid spacing:0.45Å (~14Ry)・# of grid points:4,718,592・# of bands:29,024・Memory:1,022GB~2,044GB
Si12822H1544
Top View Side View
Si nano wire with surface roughness
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SiNW Band compact model
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Landauer Formalism for Ballistic FET
From xmax to xmin
[ ][ ]∑
⎭⎬⎫
⎩⎨⎧
−+−+
⎟⎟⎠
⎞⎜⎜⎝
⎛=
i BiD
BiSi
BD TkE
TkEgqTkGI
/)(exp1/)(exp1ln
0
00 µ
µ
µS
µD
xO xmax xmin
Qf
Qb
k
Energy
µSµD
E0
E1
E2min
E2max
qVD
E2min
Qf
Qb
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0
5
10
15
20
25
30
35
40
0 0.1 0.2 0.3 0.4 0.5
Drain Bias (V)
Current (uA)
IV Characteristics of Ballistic SiNW FET
T=1KT=300K
Vg-Vt=1.0 V
0.7 V
0.3 V
0.05 V
Small temperature dependency35µA/wire for 4 quantum channels
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Model of Carrier Scattering
ChannelOpticalPhonon
Initial ElasticZone
Optical PhononEmission Zone
ε~kBT
ε*
Source
TransmissionProbability : Ti
Elastic Backscatt.Elastic Backscatt.+(Optical Phonon Emission)
x00x
V(x)
F(0)
G(0)
Linear Potential Approx. : Electric Field E
TransmissionProbability to Drain
To Drain
0Drain fromInjection )0()0()0()(
=⎟⎟⎠
⎞−=
FGFT ε
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Résumé of the Compact Model
.)( 0
G
bfStG C
qVV
+=
−−−
µµα
.
22
ln
2
⎪⎭
⎪⎬⎫
⎪⎩
⎪⎨⎧
−+
++=
oxox
oxox
oxG
ttrttr
Cεπ
0 1 1 ( ( ))( ) ( ) ( )1 exp 1 exp 1 exp
f b i i ii i S i S i D
B B B
q dkQ Q g T k dkk k kk T k T k T
επ ε µ ε µ ε µ
∞
−∞ −∞
⎤⎡ ⎧ ⎫⎥⎢ ⎪ ⎪
⎪ ⎪ ⎥⎢+ = − −⎨ ⎬ ⎥⎢ ⎧ ⎫ ⎧ ⎫ ⎧ ⎫− − −⎪ ⎪+ + + ⎥⎢ ⎨ ⎬ ⎨ ⎬ ⎨ ⎬⎪ ⎪⎢ ⎥⎩ ⎭ ⎩ ⎭ ⎩ ⎭⎣ ⎩ ⎭ ⎦
∑ ∫ ∫
.ln
2
⎟⎠⎞
⎜⎝⎛ +
=
rtr
Cox
oxG
επDDS qV=− µµ
Unknowns are ID, (µS-µ0), (µD-µ0), (Qf+Qb)
[ ]( , ) ( , )i s D ii
qI g f f T dε µ ε µ επ
= −∑ ∫h
( )0
00 0 0 0 0
2( )
2 ln
D qET
qExB D D qE mD Bε
εε
=+⎛ ⎞+ + + ⎜ ⎟
⎝ ⎠
PlanarGate
GAA
(Electrostatics requirement)
(Carrier distributionin Subbands)
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I-VD Characteritics (RT)
Electric current 20~25 µANo satruration at Large VD
0
5
10
15
20
25
30
35
40
45
0 0.1 0.2 0.3 0.4 0.5 0.6
Drain Bias [V]
Current [uA]
VG-Vt=0.1V,Bal.
VG-Vt=0.1V,Qbal
VG-Vt=0.4V,Bal.
VG-Vt=0.4V,Qbal.
VG-Vt=0.7V,Bal.
VG-Vt=0.7V,Qbal.
VG-Vt=1.0V,Bal.
VG-Vt=1.0V,Qbal.
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SiNW FET Fabrication
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SiNW FET Fabrication
Sacrificial Oxidation
SiN sidewall support formation
Ni SALISIDE Process (Ni 9nm / TiN 10nm)
S/D & Fin Patterning
Gate Oxidation & Poly-Si DepositionGate Lithography & RIE EtchingGate Sidewall Formation
30nm
30nm
30nm
Oixde etch back
Standard recipe for gate stack formationBackend
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(a) SEM image of Si NW FET (Lg = 200nm) (b) high magnification observation of gate and its sidewall.
64
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Fabricated SiNW FET
30nm
Poly-Si
SiN
Nanow
ire
SiN support
SiNW
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Lg=65nm, Tox=3nm
1.E-12
1.E-11
1.E-10
1.E-09
1.E-08
1.E-07
1.E-06
1.E-05
1.E-04
1.E-03
-1.5 -1.0 -0.5 0.0 0.5 1.0
0.E+00
1.E-05
2.E-05
3.E-05
4.E-05
5.E-05
6.E-05
7.E-05
-1.0 -0.5 0.0 0.5 1.00
10 20 30 40 50 60 70
Dra
in C
urre
nt (µ
A)
Drain Voltage (V)
Vg-Vth=1.0 V
Vg-Vth= -1.0 V
0.8 V
0.6 V
0.4 V
0.2 V
(a)
10-12
Gate Voltage (V)
pFET nFET
(b)
10-11
10-10
10-9
10-8
10-7
10-6
10-5
10-4
10-3
Dra
in C
urre
nt (A
)
Vd=-50mV
Vd=-1V
Vd=50mV
Vd=1V
1.E-12
1.E-11
1.E-10
1.E-09
1.E-08
1.E-07
1.E-06
1.E-05
1.E-04
1.E-03
-1.5 -1.0 -0.5 0.0 0.5 1.0
0.E+00
1.E-05
2.E-05
3.E-05
4.E-05
5.E-05
6.E-05
7.E-05
-1.0 -0.5 0.0 0.5 1.00
10 20 30 40 50 60 70
Dra
in C
urre
nt (µ
A)
Drain Voltage (V)
Vg-Vth=1.0 V
Vg-Vth= -1.0 V
0.8 V
0.6 V
0.4 V
0.2 V
(a)
10-12
Gate Voltage (V)
pFET nFET
(b)
10-11
10-10
10-9
10-8
10-7
10-6
10-5
10-4
10-3
Dra
in C
urre
nt (A
)
Vd=-50mV
Vd=-1V
Vd=50mV
Vd=1V
On/Off>106、60uA/wire
Recent results to be presented by ESSDERC 2010 next week in Sevile
Wire cross-section: 20 nm X 10 nm
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010203040506070
1 10 100 1000Gate Length (nm)
I ON
(µA
/ w
ire)
nMOSpMOS
(5)
(5)
(10)
(10)(12)
(12x19)
(12)
(12x19)
(13x20)
(9x14)(10)
(10)
(10)
(8)
(8)
(16)
(13)
(34)
(3)(3)
(30)
(19)
VDD: 1.0~1.5 V
括弧内は寸法を示す
010203040506070
1 10 100 1000Gate Length (nm)
I ON
(µA
/ w
ire)
nMOSpMOS
010203040506070
1 10 100 1000Gate Length (nm)
I ON
(µA
/ w
ire)
nMOSpMOS
(5)
(5)
(10)
(10)(12)
(12x19)
(12)
(12x19)
(13x20)
(9x14)(10)
(10)
(10)
(8)
(8)
(16)
(13)
(34)
(3)(3)
(30)
(19)
VDD: 1.0~1.5 V
括弧内は寸法を示す
(12)
010203040506070
1 10 100 1000Gate Length (nm)
I ON
(µA
/ w
ire)
nMOSpMOS
(5)
(5)
(10)
(10)(12)
(12x19)
(12)
(12x19)
(13x20)
(9x14)(10)
(10)
(10)
(8)
(8)
(16)
(13)
(34)
(3)(3)
(30)
(19)
VDD: 1.0~1.5 V
括弧内は寸法を示す
010203040506070
1 10 100 1000Gate Length (nm)
I ON
(µA
/ w
ire)
nMOSpMOS
010203040506070
1 10 100 1000Gate Length (nm)
I ON
(µA
/ w
ire)
nMOSpMOS
(5)
(5)
(10)
(10)(12)
(12x19)
(12)
(12x19)
(13x20)
(9x14)(10)
(10)
(10)
(8)
(8)
(16)
(13)
(34)
(3)(3)
(30)
(19)
VDD: 1.0~1.5 V
括弧内は寸法を示す
010203040506070
1 10 100 1000Gate Length (nm)
I ON
(µA
/ w
ire)
nMOSpMOS
(5)
(5)
(10)
(10)(12)
(12x19)
(12)
(12x19)
(13x20)
(9x14)(10)
(10)
(10)
(8)
(8)
(16)
(13)
(34)
(3)(3)
(30)
(19)
VDD: 1.0~1.5 V
括弧内は寸法を示す
010203040506070
1 10 100 1000Gate Length (nm)
I ON
(µA
/ w
ire)
nMOSpMOS
010203040506070
1 10 100 1000Gate Length (nm)
I ON
(µA
/ w
ire)
nMOSpMOS
(5)
(5)
(10)
(10)(12)
(12x19)
(12)
(12x19)
(13x20)
(9x14)(10)
(10)
(10)
(8)
(8)
(16)
(13)
(34)
(3)(3)
(30)
(19)
VDD: 1.0~1.5 V
括弧内は寸法を示す
(12)
本研究で得られたオン電流
(10x20)102µA
Our Work
Bench Mark
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Bench MarkBench MarkThis work Ref[11] Ref[12] Ref[13] Ref[14] Ref[15] Ref[4]
NW Cross-section (nm) Rect. Rect. Rect. Cir. Cir. Elliptical Elliptical NW Size (nm) 10x20 10x20 14 10 10 12 13x20
Lg (nm) 65 25 100 30 8 65 35EOT or Tox (nm) 3 1.8 1.8 2 4 3 1.5
Vdd (V) 1.0 1.1 1.2 1.0 1.2 1.2 1.0Ion(uA) per wire 60.1 102 30.3 26.4 37.4 48.4 43.8
Ion(uA/um) by dia. 3117 5010 2170 2640 3740 4030 2592Ion(uA/um) by cir. 1609 2054 430 841 1191 1283 825
SS (mV/dec.) 70 79 68 71 75 ~75 85DIBL (mV/V) 62 56 15 13 22 40-82 65
Ion/Ioff ~1E6 >1E6 >1E5 ~1E6 >1E7 >1E7 ~2E5
Ref[11] by Stmicro Lg=25nm,Tox=1.8nmThis work Lg=65nm,Tox=3nm
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Y. Jiang, VLSI 2008, p.34H.-S. Wong, VLSI 2009, p.92S. Bangsaruntip, IEDM 2009, p.297C. Dupre, IEDM 2008, p. 749S.D.Suk, IEDM 2005, p.735G.Bidel, VLSI 2009, p.240
SiナノワイヤFET
Planer FETS. Kamiyama, IEDM 2009, p. 431P. Packan, IEDM 2009, p.659
1.2~1.3V
1.0~1.1V
Lg=500~65nm
IIONON/I/IOFF OFF Bench markBench mark
This work
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0 .E + 0 0
1 .E + 1 9
2 .E + 1 9
3 .E + 1 9
4 .E + 1 9
5 .E + 1 9
6 .E + 1 9
0 2 4 6 8Distance from SiNW Surface (nm)
6543210
角の部分
平らな部分
電子濃度(x1019cm-3)Electron Density
Edge portion
Flat portion
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0
2000
4000
6000
8000
10000
12000
2008 2010 2012 2014 2016 2018 2020 2022 2024 2026
Year
I ON
(µA/
µm)
SiNW (12nm×19nm)
MGFDbulk
ION∝Lg-0.5×Tox
-1(20)
(11)
(33)
(15)
(26)
今回用いたIONの仮定
1µm当たりの本数
コンパクトモデルの完成
S/D寄生抵抗低減技術
pMOSの高性能化
低EOT実現技術
Compact model
Small EOT for high-k
P-MOS improvement
Low S/D resistance
# of wires /1µm
Assumption
ITRSNan
owire
Primitive estimation !
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Our roadmap for R &D Source: H. Iwai, IWJT 2008
Current Issues
III-V & Ge NanowireHigh-k gate insulatorWire formation technique
CNT:
Width and Chirality control Growth and integration of CNT
Graphene:Graphene formation technique Suppression of off-current
Very small bandgap or no bandgap (semi-metal)
Control of ribbon edge structure which affects bandgap
Chirality determines conduction types: metal or semiconductor
73
Si NanowireControl of wire surface property
Compact I-V model
Source Drain contactOptimization of wire diameter
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Thank you for your attention