Download - Phillip Allen short course notes
Lecture 010 – Introduction (3/24/10) Page 010-1
CMOS Analog Circuit Design © P.E. Allen - 2010
LECTURE 010 - INTRODUCTION TO CMOS ANALOG CIRCUITDESIGN
LECTURE ORGANIZATIONOutline• Introduction• What is Analog Design?• Skillset for Analog IC Circuit Design• Trends in Analog IC Design• Notation, Terminology and Symbols• SummaryCMOS Analog Circuit Design, 2nd Edition ReferencePages 1-16
Lecture 010 – Introduction (3/24/10) Page 010-2
CMOS Analog Circuit Design © P.E. Allen - 2010
INTRODUCTIONCourse ObjectiveThis course teaches analog integrated circuit design using CMOS technology.
070209-01
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SPECIFICATIONS
Lecture 010 – Introduction (3/24/10) Page 010-3
CMOS Analog Circuit Design © P.E. Allen - 2010
Course Prerequisites• Basic understanding of electronics
- Active and passive components- Large and small signal models- Frequency response
• Circuit analysis techniques- Mesh and loop equations- Superposition, Thevenin and Norton’s equivalent circuits
• Integrated circuit technology- Basics process steps- PN junctions
Lecture 010 – Introduction (3/24/10) Page 010-4
CMOS Analog Circuit Design © P.E. Allen - 2010
Course Organization – Based on 2nd Ed. of CMOS Analog Circuit Design
070209-02
Chapter 9Switched Capaci-
tor Circuits
Chapter 6Simple CMOS &BiCMOS OTA's
Chapter 7High Performance
OTA's
Chapter 10D/A and A/DConverters
Chapter 11AnalogSystems
Chapter 2CMOS/BiCMOS
Technology
Chapter 3CMOS/BiCMOS
Modeling
Chapter 4CMOS
Subcircuits
Chapter 5CMOS
Amplifiers
Systems
Complex
Circuits
Devices
Simple
Introduction
Chapter 8CMOS/BiCMOS
Comparators
Chapter 10D/A and A/DConverters
Lecture 010 – Introduction (3/24/10) Page 010-5
CMOS Analog Circuit Design © P.E. Allen - 2010
References 1.) P.E. Allen and D.R. Holberg, CMOS Analog Circuit Design – 2nd Ed., Oxford
University Press, 2002. 2.) P.R. Gray, P.J. Hurst, S.H. Lewis and R.G. Meyer, Analysis and Design of Analog
Integrated Circuits – 4th Ed., John Wiley and Sons, Inc., 2001. 3.) B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, Inc., 2001. 4.) R.J. Baker, H.W. Li and D.E. Boyce, CMOS Circuit Design, Layout, and
Simulation, IEEE Press, 1998. 5.) D. Johns and K. Martin, Analog Integrated Circuit Design, John Wiley and Sons,
Inc., 1997. 6.) K.R. Laker and W.M.C. Sansen, Design of Analog Integrated Circuits and Systems,
McGraw-Hill, Inc., 1994. 7.) R.L. Geiger, P.E. Allen and N.R. Strader, VLSI Techniques for Analog and Digital
Circuits, McGraw-Hill, Inc., 1990. 8.) A. Hastings, The Art of Analog Layout – 2nd Ed., Prentice-Hall, Inc., 2005. 9.) J. Williams, Ed., Analog Circuit Design - Art, Science, and Personalities,
Butterworth-Heinemann, 1991.10.) R.A. Pease, Troubleshooting Analog Circuits, Butterworth-Heinemann, 1991.
Lecture 010 – Introduction (3/24/10) Page 010-6
CMOS Analog Circuit Design © P.E. Allen - 2010
Course PhilosophyThis course emphasizes understanding of analog integrated circuit design.Although simulators are very powerful, the designer must understand the circuit beforeusing the computer to simulate a circuit.
Lecture 010 – Introduction (3/24/10) Page 010-7
CMOS Analog Circuit Design © P.E. Allen - 2010
WHAT IS ANALOG DESIGN?Analysis versus synthesis (design)
ANALYSISSystem Properties DESIGN
System 1
Properties
System 2
System 3
System 4
031028-01
• Analysis: Given a system, find its properties. The solution is unique.• Design: Given a set of properties, find a system possessing them. The solution is rarely
unique.
Lecture 010 – Introduction (3/24/10) Page 010-8
CMOS Analog Circuit Design © P.E. Allen - 2010
The Analog IC Design Process
Conception of the idea
Definition of the design
Implementation
Simulation
Physical Verification
Parasitic Extraction
Fabrication
Testing and Verification
Product
Comparisonwith design
specifications
Comparisonwith design
specifications
Physical Definition
ElectricalDesign
PhysicalDesign
Fabrication
Testing andProduct
DevelopmentFig. 1.1-2
Lecture 010 – Introduction (3/24/10) Page 010-9
CMOS Analog Circuit Design © P.E. Allen - 2010
What is Electrical Design?Electrical design is the process of going from the specifications to a circuit solution. Theinputs and outputs of electrical design are:
-
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M1 M2
M3 M4
M5
M6
M7
vout
VDD
VSS
VBias
CL
+
-
CcAnalogIntegrated
Circuit Design
W/L ratios
Topology
DC Currents
��L
W
Circuit orsystems
specifications
Fig. 1.1-3
The electrical design requires active and passive device electrical models for- Creating the design- Verifying the design- Determining the robustness of the design
Lecture 010 – Introduction (3/24/10) Page 010-10
CMOS Analog Circuit Design © P.E. Allen - 2010
Steps in Electrical Design1.) Selection of a solution
- Examine previous designs- Select a solution that is simple
2.) Investigate the solution- Analyze the performance (without a computer)- Determine the strengths and weaknesses of the solution
3.) Modification of the solution- Use the key principles, concepts and techniques to implement- Evaluate the modifications through analysis (still no computers)
4.) Verification of the solution- Use a simulator with precise models and verify the
solution- Large disagreements with the hand analysis and
computer verification should be carefully examined.
0601216-02
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Lecture 010 – Introduction (3/24/10) Page 010-11
CMOS Analog Circuit Design © P.E. Allen - 2010
What is Physical Design?Physical design is the process of representing the electrical design in a layout consistingof many distinct geometrical rectangles at various levels. The layout is then used tocreate the actual, three-dimensional integrated circuit through a process calledfabrication.
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Lecture 010 – Introduction (3/24/10) Page 010-12
CMOS Analog Circuit Design © P.E. Allen - 2010
What is the Layout Process?1.) The inputs are the W/L values and the schematic (generally from schematic entry
used for simulation).2.) A CAD tool is used to enter the various geometries. The designer must enter the
location, shape, and level of the particular geometry.3.) During the layout, the designer must obey a set of rules called design rules. These
rules are for the purpose of ensuring the robustness and reliability of the technology.4.) Once the layout is complete, then a process called layout versus schematic (LVS) is
applied to determine if the physical layout represents the electrical schematic.5.) The next step is now that the physical dimensions of the design are known, the
parasitics can be extracted. These parasitics primarily include:a.) Capacitance from a conductor to groundb.) Capacitance between conductorsc.) Bulk resistance
6.) The extracted parasitics are entered into the simulated database and the design is re-simulated to insure that the parasitics will not cause the design to fail.
Lecture 010 – Introduction (3/24/10) Page 010-13
CMOS Analog Circuit Design © P.E. Allen - 2010
Packaging†
Packaging of the integrated circuit is an important part of the physical design process.The function of packaging is:1.) Protect the integrated circuit2.) Power the integrated circuit3.) Cool the integrated circuit4.) Provide the electrical and mechanical connection between the integrated circuit and
the outside world.Packaging steps:
Dicingthe wafer
Attachment of the chip to a lead frame
Connectingthe chip to
a lead frame
Encapsulating the chip and lead
frame in a package031115-01
Other considerations of packaging:• Speed• Parasitics (capacitive and inductive)
† Rao Tummala, “Fundamentals of Microsystems Packaging,” McGraw-Hill, NY, 2001.
Lecture 010 – Introduction (3/24/10) Page 010-14
CMOS Analog Circuit Design © P.E. Allen - 2010
What is Test Design?Test design is the process of coordinating, planning and implementing the
measurement of the analog integrated circuit performance.
Objective: To compare the experimental performance with the specifications and/orsimulation results.
Types of tests:• Functional – verification of the nominal specifications• Parametric – verification of the characteristics to within a specified tolerance• Static – verification of the static (AC and DC) characteristics of a circuit or system• Dynamic – verification of the dynamic (transient) characteristics of a circuit or system
Additional Considerations:Should the testing be done at the wafer level or package level?How do you remove the influence (de-embed) of the measurement system from themeasurement?
Lecture 010 – Introduction (3/24/10) Page 010-15
CMOS Analog Circuit Design © P.E. Allen - 2010
ANALOG INTEGRATED CIRCUIT DESIGN SKILLSETCharacteristics of Analog Integrated Circuit Design• Done at the circuits level• Complexity is high• Continues to provide challenges as technology evolves• Demands a strong understanding of the principles, concepts and techniques• Good designers generally have a good physics background• Must be able to make appropriate simplifications and assumptions• Requires a good grasp of both modeling and technology• Have a wide range of skills - breadth (analog only is rare)• Be able to learn from failure• Be able to use simulation correctly
Lecture 010 – Introduction (3/24/10) Page 010-16
CMOS Analog Circuit Design © P.E. Allen - 2010
Understanding TechnologyUnderstanding technology helps the analog IC designer to know the limits of thetechnology and the influence of the technology on the design.Device Parasitics:
Connection Parasitics:
Drain
RD
RG RB
RS
CGD CBD
CGS CBS
Gate Bulk
Source
Collector
RC
RB
RSub
RE
Cμ CJS
Cπ
Base
Substrate
Emitter
CGB
050319-05
vin vout
+5V
M2
M1
vin
+5V
M2
M1
050304-01
vout
Lecture 010 – Introduction (3/24/10) Page 010-17
CMOS Analog Circuit Design © P.E. Allen - 2010
Implications of Smaller Technology on IC DesignThe good:• Smaller geometries• Smaller parasitics• Higher transconductance• Higher bandwidthsThe bad:• Reduced voltages• Smaller channel resistances (lower gain)• More nonlinearity• Deviation from square-law behaviorThe challenging:• Increased substrate noise in mixed signal applications• Threshold voltages are not scaling with power supply• Reduced dynamic range• Poor matching at minimum channel length
Lecture 010 – Introduction (3/24/10) Page 010-18
CMOS Analog Circuit Design © P.E. Allen - 2010
Understanding ModelingModeling:
Modeling is the process by which the electrical properties of an electronic circuit orsystem are represented by means of mathematical equations, circuit representations,graphs or tables.Models permit the predicting or verification of the performance of an electroniccircuit or system.
ElectronicCircuits
and Systems
Equations,Circuit
representations,graphs, tables
Prediction orverification of
circuit or systemperformance
Electronic Modeling Process030130-02
Examples:Ohm’s law, the large signal model of a MOSFET, the I-V curves of a diode, etc.
Goal:Models that are simple and allow the designer to understand the circuit performance.
Lecture 010 – Introduction (3/24/10) Page 010-19
CMOS Analog Circuit Design © P.E. Allen - 2010
Key Principles, Concepts and Techniques of Analog IC Design• Principles mean fundamental laws that
are precise and never change.(Webster – A comprehensive andfundamental law, doctrine, orassumption. The laws or facts of natureunderlying the working of an artificialdevice.)
• Concepts will include relationships,“soft-laws” (ones that are generallytrue), analytical tools, things worthremembering.(Webster – An abstract idea generalizedfrom particular instances.)
• Techniques will include the assumptions,“tricks”, tools, methods that one uses to simplify and understand.
(Webster – The manner in which technical details are treated, a method ofaccomplishing a desired aim or goal.)
AnalogIC Design
Process
Techniques"Tricks"
Principles (laws)used in design
Concepts - Information
that enhancesdesign
040511-01
AnalogDesign
Lecture 010 – Introduction (3/24/10) Page 010-20
CMOS Analog Circuit Design © P.E. Allen - 2010
Complexity in Analog DesignAnalog design is normally done in a non-hierarchical manner and makes little use of
repeated blocks. As a consequence, analog design can become quite complex andchallenging.How do you handle the complexity?
1.) Use as much hierarchy as possible.2.) Use appropriate organization
techniques.3.) Document the design in an efficient
manner.4.) Make use of assumptions and
simplifications.5.) Use simulators appropriately.
Systems Level (ADC)
Circuits Level (op amps)
Block Level (amplifier)
Sub-block Level (current sink)
Components (transistor)
Systems
Circuits
Components
031030-03
Lecture 010 – Introduction (3/24/10) Page 010-21
CMOS Analog Circuit Design © P.E. Allen - 2010
AssumptionsAssumptions:
An assumption is taking something to be true without formal proof. Assumptions inanalog circuit design are used for simplifying the analysis or design. The goal of anassumption is to separate the essential information from the nonessential informationof a problem.The elements of an assumption are:
1.) Formulating the assumption to simplify the problem without eliminating theessential information.
2.) Application of the assumption to get a solution or result.3.) Verification that the assumption was in fact appropriate.
Examples:Neglecting a large resistance in parallel with a small resistanceMiller effect to find a dominant poleFinding the roots of a second-order polynomial assuming the roots are real andseparated
Lecture 010 – Introduction (3/24/10) Page 010-22
CMOS Analog Circuit Design © P.E. Allen - 2010
WHERE IS ANALOG IC DESIGN TODAY?Analog IC Design has Reached Maturity
There are established fields of application:• Digital-analog and analog-digital conversion• Disk drive controllers• Modems - filters• Bandgap reference• Analog phase lock loops• DC-DC conversion• Buffers• Codecs• Etc.
Existing philosophy regarding analog circuits:“If it can be done economically by digital, don’t use analog.”
Consequently:Analog finds applications where speed, area, or power have advantages over a digitalapproach.
Lecture 010 – Introduction (3/24/10) Page 010-23
CMOS Analog Circuit Design © P.E. Allen - 2010
Analog IC Design ChallengesTechnology:• Digital circuits have scaled well with technology• Analog does not benefit as much from smaller features
- Speed increases- Gain decreases- Matching decreases- Nonlinearity increases- New issues appear such as gate current leakage
Analog Circuit Challenges:• Trade offs are necessary between linearity, speed, precision and power
• As analog is combined with more digital, substrate interference will become worse
Lecture 010 – Introduction (3/24/10) Page 010-24
CMOS Analog Circuit Design © P.E. Allen - 2010
Digitally Assisted Analog CircuitsUse digital circuits which work better atscaled technologies to improve analogcircuits that do not necessarily improvewith technology scaling.Principles and Techniques:
• Open-loop vs. closed loop - Open loop is less accurate but smaller Faster, less power - Closed-loop is more accurate but larger Slower, more power
• Averaging - Increase of accuracy Smaller devices, more speed
• Calibration - Accuracy increases Increased resolution with same area
• Dynamic Element Matching - Enhancement of component precision
• Doubly correlated sampling - Reduction of dc influences (noise, offset) Smaller devices, more speed
• Etc.
Lecture 010 – Introduction (3/24/10) Page 010-25
CMOS Analog Circuit Design © P.E. Allen - 2010
What is the Future of Analog IC Design?• More creative circuit solutions are required to achieve the desired performance.• Analog circuits will continue to be a part of large VLSI digital systems• Interference and noise will become even more serious as the chip complexity increases• Packaging will be an important issue and offers some interesting solutions• Analog circuits will always be at the cutting edge of performance• Analog designer must also be both a circuit and systems designer and must know:
Technology and modelingAnalog circuit designVLSI digital designSystem application concepts
• There will be no significantly new and different technologies - innovation will combinenew applications with existing or improved technologies
• Semicustom methodology will eventually evolve with CAD tools that will allow:- Design capture and reuse- Quick extraction of model parameters from new technology- Test design- Automated design and layout of simple analog circuits
Lecture 010 – Introduction (3/24/10) Page 010-26
CMOS Analog Circuit Design © P.E. Allen - 2010
NOTATION, TERMINOLOGY AND SYMBOLOGYDefinition of Symbols for Various Signals
Signal Definition Quantity Subscript ExampleTotal instantaneous value of the signal Lowercase Uppercase qA
DC value of the signal Uppercase Uppercase QA
AC value of the signal Lowercase Lowercase qa
Complex variable, phasor, or rms valueof the signal
Uppercase Lowercase Qa
Example:
t
ID iD
id
Idm
Fig. 1.4-1
Dra
in C
urre
nt
Lecture 010 – Introduction (3/24/10) Page 010-27
CMOS Analog Circuit Design © P.E. Allen - 2010
MOS Transistor Symbols
G
S
D
G
S
D
G
S
D
G
S
D
B G
S
D
B
G
S
D
EnhancementNMOS withVBS = 0V.
EnhancementPMOS withVBS = 0V.
EnhancementNMOS withVBS 0V.
EnhancementPMOS withVBS 0V.
SimpleNMOSsymbol
SimplePMOSsymbol
Lecture 010 – Introduction (3/24/10) Page 010-28
CMOS Analog Circuit Design © P.E. Allen - 2010
Other Schematic Symbols
Differential amplifier,op amp, or comparator
+
-
+
-
V1 GmV1
I2
+-
+
-
V1 V2AvV1
+
-
+-
+
-
V2
I1
RmI1
I2I1
AiI1
Voltage-controlled,voltage source
Voltage-controlled, current source
Current-controlled, voltage source
Current-controlled, current source
Independent current source
Independentvoltage sources
+
-V
+
-V
+
-
V
Lecture 010 – Introduction (3/24/10) Page 010-29
CMOS Analog Circuit Design © P.E. Allen - 2010
Three-Terminal NotationQABC
A = Terminal with the larger magnitude of potentialB = Terminal with the smaller magnitude of potentialC = Condition of the remaining terminal with respect to terminal B
C = 0 There is an infinite resistance between terminal B and the 3rd terminalC = S There is a zero resistance between terminal B and the 3rd terminalC = R There is a finite resistance between terminal B and the 3rd terminalC = X There is a voltage source in series with a resistor between terminal B
and the 3rd terminal in such a manner as to reverse bias a PNjunction.
Examples
(a.) Capacitance from drain to gate with the source shorted to the gate.(b.) Drain-source current when gate is shorted to source (depletion device)(c.) Breakdown voltage from drain to gate with the source is open- circuited to the gate.
+
-VGS
S D
G
CDGS
S
DG
IDSS
+
-
S D
G
IDS BVDGO
(a.) (b.) (c.)
Lecture 010 – Introduction (3/24/10) Page 010-30
CMOS Analog Circuit Design © P.E. Allen - 2010
SUMMARY• Successful analog IC design proceeds with understanding the circuit before simulation.• Analog IC design consists of three major steps:
1.) Electrical design Topology, W/L values, and dc currents2.) Physical design (Layout)3.) Test design (Testing)
• Analog designers must be flexible and have a skill set that allows one to simplify andunderstand a complex problem
• Analog IC design has reached maturity and is here to stay.• The appropriate philosophy is “If it can be done economically by digital, don’t use
analog”.• As a result of the above, analog finds applications where speed, area, or power result in
advantages over a digital approach.• Deep-submicron technologies will offer exciting challenges to the creativity of the
analog designer.
Lecture 020 – Submicron CMOS Technology (3/24/10) Page 020-1
CMOS Analog Circuit Design © P.E. Allen - 2010
LECTURE 020 - SUBMICRON CMOS TECHNOLOGYLECTURE ORGANIZATION
Outline• CMOS Technology• Fundamental IC Process Steps• Typical Submicron CMOS Fabrication Process• SummaryCMOS Analog Circuit Design, 2nd Edition ReferencePages 18-29
Lecture 020 – Submicron CMOS Technology (3/24/10) Page 020-2
CMOS Analog Circuit Design © P.E. Allen - 2010
CMOS TECHNOLOGYClassification of Silicon Technology
Silicon IC Technologies
gate gate gate gate060112-02
JunctionIsolated
Dielectric Isolated
Oxideisolated
CMOSPMOS
(Aluminum Gate)
NMOS
Bipolar Bipolar/CMOS MOS
Aluminum Silicon Aluminum Silicon Silicon-Germanium
Silicon
Lecture 020 – Submicron CMOS Technology (3/24/10) Page 020-3
CMOS Analog Circuit Design © P.E. Allen - 2010
Categorization of CMOS Technology• Minimum feature size as a function of time:
1
0.1
0.01
Min
imum
Fea
ture
Siz
e (µ
m)
1985 1990 1995 2000 2005 2010070215-01Year
Deep Submicron Technology
Ultra Deep Submicron Technology
Submicron Technology
• Categories of CMOS technology:1.) Submicron technology – Lmin 0.35 microns2.) Deep Submicron technology (DSM) – 0.1 microns Lmin 0.35 microns3.) Ultra-Deep Submicron technology (UDSM) – Lmin 0.1 microns
Lecture 020 – Submicron CMOS Technology (3/24/10) Page 020-4
CMOS Analog Circuit Design © P.E. Allen - 2010
Why CMOS Technology?Comparison of BJT and MOSFET technology from an analog viewpoint:
Comparison Feature BJT MOSFETCutoff Frequency(fT) 100 GHz 50 GHz (0.25μm)
Noise (thermal about the same) Less 1/f More 1/fDC Range of Operation 9 decades of exponential
current versus vBE
2-3 decades of square lawbehavior
Transconductance (Same current) Larger by 10X Smaller by 10XSmall Signal Output Resistance Slightly larger Smaller for short channelSwitch Implementation Poor GoodCapacitor Voltage dependent More optionsPerformance/Power Ratio High LowTechnology Improvement Slower Faster
Therefore,• Almost every comparison favors the BJT, however a similar comparison made from a
digital viewpoint would come up on the side of CMOS.• Therefore, since large-volume mixed-mode technology will be driven by digital
demands, CMOS is an obvious result as the technology of availability.
Lecture 020 – Submicron CMOS Technology (3/24/10) Page 020-5
CMOS Analog Circuit Design © P.E. Allen - 2010
How Does IC Technology Influence Analog IC Design?
Characteristics of analog IC design:• Continuous in signal amplitude• Discrete or continuous in time• Signal processing primarily depends on ratios of values and time constants
- Ratios are generally resistance, conductance, or capacitance- Time constants are generally products of resistance and capacitance
• Dynamic range is determined by the largest and smallest signals
Influence of IC Technology:• Accuracy of signal processing depends on the accuracy of the ratios of values• The dynamic range depends upon the linearity of the circuit elements and the noise• The value of components is limited by area considerations• IC technology introduces resistive, capacitive and inductive parasitics that cause
deviation from desired behavior• The analog circuit is subject to the influence of other circuits fabricated in the same
substrate
Lecture 020 – Submicron CMOS Technology (3/24/10) Page 020-6
CMOS Analog Circuit Design © P.E. Allen - 2010
FUNDAMENTAL IC PROCESS STEPSBasic Steps• Oxide growth• Thermal diffusion• Ion implantation• Deposition• Etching• Shallow trench isolation• EpitaxyPhotolithographyPhotolithography is the means by which the above steps are applied to selected areas ofthe silicon wafer.Silicon Wafer
0.5-0.8mm
n-type: 3-5 Ω-cmp-type: 14-16 Ω-cm Fig. 2.1-1r
125-200 mm(5"-8")
Lecture 020 – Submicron CMOS Technology (3/24/10) Page 020-7
CMOS Analog Circuit Design © P.E. Allen - 2010
OxidationDescription:Oxidation is the process by which a layer of silicon dioxide is grown on the surface of asilicon wafer.
Original silicon surface
0.44 tox
tox
Silicon substrate
Silicon dioxide
Fig. 2.1-2
Uses:• Protect the underlying material from contamination• Provide isolation between two layers.Very thin oxides (100Å to 1000Å) are grown using dry oxidation techniques. Thickeroxides (>1000Å) are grown using wet oxidation techniques.
Lecture 020 – Submicron CMOS Technology (3/24/10) Page 020-8
CMOS Analog Circuit Design © P.E. Allen - 2010
DiffusionDiffusion is the movement of impurity atoms at the surface of the silicon into the bulk ofthe silicon. Always in the direction from higher concentration to lower concentration.
HighConcentration
LowConcentration
Fig. 150-04
Diffusion is typically done at high temperatures: 800 to 1400°C
Depth (x)
t1 < t2 < t3
t1t2
t3
N(x)
NB
Depth (x)
t1 < t2 < t3
Infinite source of impurities at the surface. Finite source of impurities at the surface.
N0
Fig. 150-05
ERFC Gaussian
t1 t2t3
N(x)
NB
N0
Lecture 020 – Submicron CMOS Technology (3/24/10) Page 020-9
CMOS Analog Circuit Design © P.E. Allen - 2010
Ion ImplantationIon implantation is the process by whichimpurity ions are accelerated to a highvelocity and physically lodged into thetarget material.
• Annealing is required to activate theimpurity atoms and repair the physicaldamage to the crystal lattice. This stepis done at 500 to 800°C.
• Ion implantation is a lower temperatureprocess compared to diffusion.
• Can implant through surface layers, thus it isuseful for field-threshold adjustment.
• Can achieve unique doping profile such asburied concentration peak.
Path of impurity
atom
Fixed Atom
Fixed Atom
Fixed AtomImpurity Atomfinal resting place
Fig. 150-06
N(x)
NB
0 Depth (x)
Concentration peak
Fig. 150-07
Lecture 020 – Submicron CMOS Technology (3/24/10) Page 020-10
CMOS Analog Circuit Design © P.E. Allen - 2010
DepositionDeposition is the means by which various materials are deposited on the silicon wafer.Examples: • Silicon nitride (Si3N4)
• Silicon dioxide (SiO2)
• Aluminum • PolysiliconThere are various ways to deposit a material on a substrate: • Chemical-vapor deposition (CVD) • Low-pressure chemical-vapor deposition (LPCVD) • Plasma-assisted chemical-vapor deposition (PECVD) • Sputter depositionMaterial that is being deposited using these techniques covers the entire wafer andrequires no mask.
Lecture 020 – Submicron CMOS Technology (3/24/10) Page 020-11
CMOS Analog Circuit Design © P.E. Allen - 2010
Etching
Etching is the process of selectivelyremoving a layer of material.When etching is performed, the etchant mayremove portions or all of: • The desired material • The underlying layer • The masking layerImportant considerations: • Anisotropy of the etch is defined as,
A = 1-(lateral etch rate/vertical etch rate) • Selectivity of the etch (film to mask and film to substrate) is defined as,
Sfilm-mask = film etch rate
mask etch rate A = 1 and Sfilm-mask = are desired.
There are basically two types of etches: • Wet etch which uses chemicals • Dry etch which uses chemically active ionized gases.
MaskFilm
bUnderlying layer
a
c
MaskFilm
Underlying layer
(a) Portion of the top layer ready for etching.
(b) Horizontal etching and etching of underlying layer.Fig. 150-08
Selectivity
AnisotropySelectivity
Lecture 020 – Submicron CMOS Technology (3/24/10) Page 020-12
CMOS Analog Circuit Design © P.E. Allen - 2010
EpitaxyEpitaxial growth consists of the formation of a layer of single-crystal silicon on thesurface of the silicon material so that the crystal structure of the silicon is continuousacross the interfaces.• It is done externally to the material as opposed to diffusion which is internal• The epitaxial layer (epi) can be doped differently, even opposite to the material on
which it is grown• It is accomplished at high temperatures using a chemical reaction at the surface• The epi layer can be any thickness, typically 1-20 microns
Si Si Si Si Si Si Si Si Si Si Si Si
Si Si Si Si Si Si Si Si Si Si Si Si
Si Si Si Si Si Si Si Si Si Si Si Si
Si Si Si Si Si Si Si Si Si Si Si Si
Si Si Si Si Si Si Si Si Si Si Si Si
Si Si Si Si Si Si Si Si Si Si Si Si
+
-
-
-
- -
-
+
+
+
Gaseous cloud containing SiCL4 or SiH4
Si Si Si Si+
Fig. 150-09
Lecture 020 – Submicron CMOS Technology (3/24/10) Page 020-13
CMOS Analog Circuit Design © P.E. Allen - 2010
PhotolithographyComponents
• Photoresist material• Mask• Material to be patterned (e.g., oxide)
Positive photoresistAreas exposed to UV light are soluble in the developerNegative photoresistAreas not exposed to UV light are soluble in the developerSteps1. Apply photoresist2. Soft bake (drives off solvents in the photoresist)3. Expose the photoresist to UV light through a mask4. Develop (remove unwanted photoresist using solvents)5. Hard bake ( 100°C)6. Remove photoresist (solvents)
Lecture 020 – Submicron CMOS Technology (3/24/10) Page 020-14
CMOS Analog Circuit Design © P.E. Allen - 2010
Illustration of Photolithography - ExposureThe process of exposingselective areas to lightthrough a photo-mask iscalled printing.Types of printing include:• Contact printing• Proximity printing• Projection printing
Photoresist
Photomask
UV Light
Photomask
Polysilicon
Fig. 150-10
Lecture 020 – Submicron CMOS Technology (3/24/10) Page 020-15
CMOS Analog Circuit Design © P.E. Allen - 2010
Illustration of Photolithography - Positive Photoresist
Photoresist
Photoresist
Polysilicon
Polysilicon
Polysilicon
Etch
Removephotoresist
Develop
Fig. 150-11
Lecture 020 – Submicron CMOS Technology (3/24/10) Page 020-16
CMOS Analog Circuit Design © P.E. Allen - 2010
TYPICAL SUBMICRON CMOS FABRICATION PROCESSN-Well CMOS Fabrication Major Steps 1.) Implant and diffuse the n-well 2.) Deposition of silicon nitride 3.) n-type field (channel stop) implant 4.) p-type field (channel stop) implant 5.) Grow a thick field oxide (FOX) 6.) Grow a thin oxide and deposit polysilicon 7.) Remove poly and form LDD spacers 8.) Implantation of NMOS S/D and n-material contacts 9.) Remove spacers and implant NMOS LDDs10.) Repeat steps 8.) and 9.) for PMOS11.) Anneal to activate the implanted ions12.) Deposit a thick oxide layer (BPSG - borophosphosilicate glass)13.) Open contacts, deposit first level metal and etch unwanted metal14.) Deposit another interlayer dielectric (CVD SiO2), open vias, deposit 2nd level metal
15.) Etch unwanted metal, deposit a passivation layer and open over bonding pads
Lecture 020 – Submicron CMOS Technology (3/24/10) Page 020-17
CMOS Analog Circuit Design © P.E. Allen - 2010
Major CMOS Process Steps
n-well implant
Photoresist Photoresist
Si3N4
n-well
p- substrate
p- substrate
SiO2
SiO2
Step 1 - Implantation and diffusion of the n-wells
Step 2 - Growth of thin oxide and deposition of silicon nitride
070523-01
Lecture 020 – Submicron CMOS Technology (3/24/10) Page 020-18
CMOS Analog Circuit Design © P.E. Allen - 2010
Major CMOS Process Steps – Continued
Photoresist
p- field implant
Si3N4
n-well
PhotoresistPhotoresist
n- field implant
Pad oxide (SiO2)
n-well
Si3N4
p- substrate
p- substrate
Step 3.) Implantation of the n-type field channel stop
Step 4.) Implantation of the p-type field channel stop
070523-02
Lecture 020 – Submicron CMOS Technology (3/24/10) Page 020-19
CMOS Analog Circuit Design © P.E. Allen - 2010
Major CMOS Process Steps – Continued
FOX
Polysilicon
n-well
FOX
n-well
Si3N4
p- substrate
p- substrate
FOX
FOX
Step 5.) Growth of the thick field oxide (LOCOS - localized oxidation of silicon)
Step 6.) Growth of the gate thin oxide and deposition of polysilicon. The thresholds can be shifted by an implantation before the deposition of polysilicon.
070523-03
Lecture 020 – Submicron CMOS Technology (3/24/10) Page 020-20
CMOS Analog Circuit Design © P.E. Allen - 2010
Major CMOS Process Steps – Continued
Step 7.) Removal of polysilicon and formation of the sidewall spacers
Step 8.) Implantation of NMOS source and drain and contact to n-well (not shown)
070523-04
Photoresist
SiO2 spacerPolysilicon
FOX
n-wellp- substrate
FOX
Photoresist
n+ S/D implant
Polysilicon
FOX
n-wellp- substrate
FOX
FOXFOX
FOXFOX
Lecture 020 – Submicron CMOS Technology (3/24/10) Page 020-21
CMOS Analog Circuit Design © P.E. Allen - 2010
Major CMOS Process Steps - Continued
070209-03
Photoresist
n- S/D LDD implant
Polysilicon
FOX
n-wellp- substrate
FOX
Polysilicon
FOX
n-wellp- substrate
FOX
LDD Diffusion
FOX FOX
FOX FOX
Step 9.) Remove sidewall spacers and implant the NMOS lightly doped source/drains
Step 10.) Implant the PMOS source/drains and contacts to the p- substrate (not shown), remove the sidewall spacers and implant the PMOS lightly doped source/drains
Lecture 020 – Submicron CMOS Technology (3/24/10) Page 020-22
CMOS Analog Circuit Design © P.E. Allen - 2010
Major CMOS Process Steps – Continued
Step 11.) Anneal to activate the implanted ions
Step 12.) Deposit a thick oxide layer (BPSG - borophosphosilicate glass)
070523-05
BPSG
Polysiliconn+ Diffusion p+ Diffusion
FOX FOXn-well
Polysilicon
n-well
n+ Diffusion p+ Diffusion
FOX FOX
p- substrate
p- substrate
FOX
FOX
Lecture 020 – Submicron CMOS Technology (3/24/10) Page 020-23
CMOS Analog Circuit Design © P.E. Allen - 2010
Major CMOS Process Steps - Continued
BPSG
n-wellFOXFOX
p- substrate
BPSG
n-well
Metal 1
FOXFOX
p- substrate
Metal 2
Metal 1CVD oxide, Spin-on glass (SOG)
FOX
FOX
Step 13.) Open contacts, deposit first level metal and etch unwanted metal
Step 14.) Deposit another interlayer dielectric (CVD SiO2), open contacts, deposit second level metal
070523-06
Lecture 020 – Submicron CMOS Technology (3/24/10) Page 020-24
CMOS Analog Circuit Design © P.E. Allen - 2010
Major CMOS Process Steps – Continued
070523-07
BPSG
n-well
Metal 1
FOXFOX
p- substrate
Metal 2Passivation protection layer
FOX
Step 15.) Etch unwanted metal and deposit a passivation layer and open over bonding pads
p-well process is similar but starts with a p-well implant rather than an n-well implant.
Lecture 020 – Submicron CMOS Technology (3/24/10) Page 020-25
CMOS Analog Circuit Design © P.E. Allen - 2010
Approximate Side View of CMOS Fabrication
Metal 4
Metal 3
Metal 2
Metal 1
Passivation
Polysilicon
Diffusion
2 microns
070523-08
Lecture 020 – Submicron CMOS Technology (3/24/10) Page 020-26
CMOS Analog Circuit Design © P.E. Allen - 2010
PlanarizationPlanarization attempts to minimize the variation in surface height of the wafer.Planarization techniques
• Repeated applications of SOG• Resist etch-back – highest areas of
oxide are exposed longest to theetchant and therefore erode away themost.
Influence of planarization on analog design:+ Number of levels of metal and the metal integrity depends on planarization+ Thin film components at the surface require good planarization+ Without planarization, resistance of conductors increases+ Planarization at the top level leads to less package induced stress (trimming?)+ Planarized passivation helps printing when the depth of field is small.- With planarization, the capacitance of the interdielectric isolation can vary (a good
reason to extract capacitance!)- Significant difference in contact aspect ratio (deep versus shallow contacts)
TungstenPlug
Lecture 020 – Submicron CMOS Technology (3/24/10) Page 020-27
CMOS Analog Circuit Design © P.E. Allen - 2010
Chemical Mechanical PolishingCMP produces the required degree of planarization for modern submicron technology.
• Both chemical effect (slurry) and mechanical (pad pressure) take place.• Although CMP is superior to SOG and resist etchback, large areas devoid of underlying
metal or poly produce low regions in the final surface.• Challenge: Achieve a highly planarized surface over a wide range of pattern density.
Lecture 020 – Submicron CMOS Technology (3/24/10) Page 020-28
CMOS Analog Circuit Design © P.E. Allen - 2010
Horizontal Stripe Fill Vertical Stripe FillLayout with white space
070810-02
CMP Planarization
Pattern Fill
CMP Planarization
070810-01
Chemical Mechanical Polishing – ContinuedImpact on analog design: + Makes the surface flatter
- Vias and plugs can become longer adding resistance+ More uniform surface giving better metal coverage and foundation for thin film
components- Thickness varies with pattern density
Examples of pattern fill:
Pattern density design rules are both local and global.
Lecture 020 – Submicron CMOS Technology (3/24/10) Page 020-29
CMOS Analog Circuit Design © P.E. Allen - 2010
Silicide/Salicide TechnologyUsed to reduce interconnect resistivity by placing a low-resistance silicide such as TiSi2,WSi2, TaSi2, etc. on top of polysiliconSalicide technology (self-aligned silicide) provides low resistance source/drainconnections as well as low-resistance polysilicon.
Metal
FOX
Polysilicide
Polycide structure Salicide structure
FOX
070523-09
FOX
Polysilicide
FOX
Salicide
Metal
Lecture 020 – Submicron CMOS Technology (3/24/10) Page 020-30
CMOS Analog Circuit Design © P.E. Allen - 2010
SUMMARY• Fabrication is the means by which the circuit components, both active and passive, are
built as an integrated circuit.• Basic process steps include:
1.) Oxide growth 2.) Thermal diffusion 3.) Ion implantation4.) Deposition 5.) Etching 6.) Epitaxy
• The complexity of a process can be measured in the terms of the number of maskingsteps or masks required to implement the process.
• Major CMOS Processing Steps: 1.) Well definition 2.) Definition of active areas and substrate/well contacts (SiNi3) 3.) Thick field oxide (FOX) 4.) Thin field oxide and polysilicon 5.) Diffusion of the source and drains (includes the LDD) 6.) Dielectric layer/Contacts (planarization) 7.) Metallization 8.) Dielectric layer/Vias
Lecture 030 – DSM CMOS Technology (3/24/10) Page 030-1
CMOS Analog Circuit Design © P.E. Allen - 2010
LECTURE 030 - DEEP SUBMICRON (DSM) CMOS TECHNOLOGYLECTURE ORGANIZATION
Outline• Characteristics of a deep submicron CMOS technology• Typical deep submicron CMOS technology• SummaryCMOS Analog Circuit Design, 2nd Edition ReferenceNew material
Lecture 030 – DSM CMOS Technology (3/24/10) Page 030-2
CMOS Analog Circuit Design © P.E. Allen - 2010
CHARACTERISTICS OF A DEEP SUBMICRON CMOS TECHNOLOGYIsolation of TransistorsThe use of reverse bias pn junctions to isolate transistors becomes impractical as thetransistor sizes decrease.
Lecture 030 – DSM CMOS Technology (3/24/10) Page 030-3
CMOS Analog Circuit Design © P.E. Allen - 2010
Use of Shallow Trench Isolation TechnologyShallow trench isolation (STI) allows closer spacing of transistors by eliminating thedepletion region at the surface.
p+ p p- MetalSaliciden- n n+Oxide Poly
070330-03
PolycideGate Ox
n+
n-well
n+
p-well
n+
Substrate
n+
ShallowTrench
Isolation
n+
ShallowTrench
Isolation
ShallowTrench
Isolation
p+p+ n+n+
Substrate Salicide
Well Salicide Decreasedspacing
Substrate Salicide
Shal
low
Trench Isolation
Isol
atio
n
Shal
low
Tre
nch
Lecture 030 – DSM CMOS Technology (3/24/10) Page 030-4
CMOS Analog Circuit Design © P.E. Allen - 2010
Comparison of STI and LOCOSWhat are the differences between a LOCOS and STI technology?
Comments:
• If the n+ to p+ spacing is large, the Bird’s beak can be compensated using techniquessuch as poly buffered LOCOS
• At some point as the n+ to p+ spacing gets smaller, the restricted bird’s beak leads toundesirable stress effects in the transistor.
• An important advantage of STI is that it minimizes the heat cycle needed for n+ or p+isolation compared to LOCOS. This is a significant advantage for any process wherethere are implants before STI.
Lecture 030 – DSM CMOS Technology (3/24/10) Page 030-5
CMOS Analog Circuit Design © P.E. Allen - 2010
Shallow Trench Isolation (STI)
060203-01
Nitride
Silicon(1)
(2)
(3)
(4)
(5)
(6)
1.) Cover the wafer with pad oxide and silicon nitride.
2.) First etch nitride and pad oxide. Next, an anisotropicetch is made in the silicon to a depth of 0.4 to 0.5 microns.
3.) Grow a thin thermal oxide layer on the trench walls.
4.) A CVD dielectric film is used to fill the trench.
5.) A chemical mechanical polishing (CMP) step is used topolish back the dielectric layer until the nitride is reached.The nitride acts like a CMP stop layer.
6.) Densify the dielectric material at 900°C and strip thenitride and pad oxide.
Lecture 030 – DSM CMOS Technology (3/24/10) Page 030-6
CMOS Analog Circuit Design © P.E. Allen - 2010
Illustration of a Deep Submicron (DSM) CMOS Technology
n+
p-substrate
Metal Layers
NMOSTransistor
PMOSTransistor
031211-02
M1M2M3M4M5M6M7M80.8μm
0.3μm 7μm
Deep n-wellDeep p-well
n+
STI�p+ p+
STI STI
Salicide
Polycide
Salicide
PolycideSidewall Spacers
Salicide
Source/drainextensions
Source/drainextensions
��
In addition to NMOS and PMOS transistors, the technology provides:1.) A deep n-well that can be utilized to reduce substrate noise coupling.2.) A MOS varactor that can serve in VCOs3.) At least 6 levels of metal that can form many useful structures such as inductors,
capacitors, and transmission lines.
Lecture 030 – DSM CMOS Technology (3/24/10) Page 030-7
CMOS Analog Circuit Design © P.E. Allen - 2010
TransistorsfT as a function of gate-source overdrive, VGS-VT (0.13μm):
100 200 300 400 500
20
30
40
50
60
70
10
00
Typical, 25°C
Slow, 70°CPMOS
Typical, 25°C
Slow, 70°CNMOS
f T (
GH
z)
|VGS-VT| (mV) 030901-07
The upper frequency limit is probably around 40 GHz for NMOS with an fT in thevicinity of 60GHz with an overdrive of 0.5V and at the slow-high temperature corner.
Lecture 030 – DSM CMOS Technology (3/24/10) Page 030-8
CMOS Analog Circuit Design © P.E. Allen - 2010
Resistors1.) Diffused and/or implanted resistors.2.) Well resistors.3.) Polysilicon resistors.4.) Metal resistors.
Lecture 030 – DSM CMOS Technology (3/24/10) Page 030-9
CMOS Analog Circuit Design © P.E. Allen - 2010
CapacitorsPolysilicon-polysiliconcapacitors:
Metal-metal capacitors:
060530-01
Third levelfrom top metal
Second level from top metalInter-
mediateOxideLayers
Top Metal
Protective Insulator Layer
Metal Via
Capacitor Top Metal
Capacitor bottom plate
Capacitordielectric
Fourth levelfrom top metal
Vias connecting bottom plate to lower metal
Vias connecting top plate to top metal
Vias connecting bottom plate to lower metal
Lecture 030 – DSM CMOS Technology (3/24/10) Page 030-10
CMOS Analog Circuit Design © P.E. Allen - 2010
InductorsTop view and cross-section of a planar inductor:
W
S
D
D
Top Metal
Next LevelMetal
Top Metal
Next LevelMetal
Vias
Oxide
Oxide
Silicon Substrate
N turns
030828-01
Lecture 030 – DSM CMOS Technology (3/24/10) Page 030-11
CMOS Analog Circuit Design © P.E. Allen - 2010
TYPICAL DEEP SUBMICRON (DSM) CMOS FABRICATION PROCESSMajor Fabrication Steps for a DSM CMOS Process 1.) p and n wells 2.) Shallow trench isolation 3.) Threshold shift and anti-punch through implants 4.) Thin oxide and gate polysilicon 5.) Lightly doped drains and sources 6.) Sidewall spacer 7.) Heavily doped drains and sources 8.) Siliciding (Salicide and Polycide) 9.) Bottom metal, tungsten plugs, and oxide10.) Higher level metals, tungsten plugs/vias, and oxide11.) Top level metal, vias and protective oxide
Lecture 030 – DSM CMOS Technology (3/24/10) Page 030-12
CMOS Analog Circuit Design © P.E. Allen - 2010
Starting MaterialThe substrate should be highly doped to act like a good conductor.
p+ p p- MetalSaliciden- n n+Oxide Poly 060118-02PolycideGate Ox
Substrate
Lecture 030 – DSM CMOS Technology (3/24/10) Page 030-13
CMOS Analog Circuit Design © P.E. Allen - 2010
Step 1 - n and p wellsThese are the areas where the transistors will be fabricated - NMOS in the p-well andPMOS in the n-well.Done by implantation followed by a deep diffusion.
p+ p p- MetalSaliciden- n n+Oxide Poly 060118-03PolycideGate Ox
p+ n+
n-well p-well
Substrate
n well implant and diffusion p well implant and diffusion
Lecture 030 – DSM CMOS Technology (3/24/10) Page 030-14
CMOS Analog Circuit Design © P.E. Allen - 2010
Step 2 – Shallow Trench IsolationThe shallow trench isolation (STI) electrically isolates one region/transistor fromanother.
p+ p p- MetalSaliciden- n n+Oxide Poly 060118-04PolycideGate Ox
p+ n+
n-well
ShallowTrench
Isolation
p-well
ShallowTrench
Isolation
ShallowTrench
Isolation
Substrate
Lecture 030 – DSM CMOS Technology (3/24/10) Page 030-15
CMOS Analog Circuit Design © P.E. Allen - 2010
Step 3 – Threshold Shift and Anti-Punch Through ImplantsThe natural thresholds of the NMOS is about 0V and of the PMOS is about –1.2V. An p-implant is used to make the NMOS harder to invert and the PMOS easier resulting inthreshold voltages balanced around zero volts.
p+ p p- MetalSaliciden- n n+Oxide Poly 060118-05PolycideGate Ox
n+
n-well p-well
ShallowTrench
Isolation
Substrate
p threshold implant p threshold implant
n+ anti-punch through implant p+ anti-punch through implant
ShallowTrench
Isolation
ShallowTrench
Isolation
Also an implant can be applied to create a higher-doped region beneath the channels toprevent punch-through from the drain depletion region extending to source depletionregion.
Lecture 030 – DSM CMOS Technology (3/24/10) Page 030-16
CMOS Analog Circuit Design © P.E. Allen - 2010
Step 4 – Thin Oxide and Polysilicon GatesA thin oxide is deposited followed by polysilicon. These layers are removed where theyare not wanted.
p+ p p- MetalSaliciden- n n+Oxide Poly 060118-06PolycideGate Ox
p+ n+
n-well p-well
Substrate
ShallowTrench
Isolation
ShallowTrench
Isolation
ShallowTrench
Isolation
Lecture 030 – DSM CMOS Technology (3/24/10) Page 030-17
CMOS Analog Circuit Design © P.E. Allen - 2010
Step 5 – Lightly Doped Drains and SourcesA lightly-doped implant is used to create a lightly-doped source and drain next to thechannel of the MOSFETs.
p+ p p- MetalSaliciden- n n+Oxide Poly 070321-01PolycideGate Ox
p+ n+
n-well
ShallowTrench
Isolationp-well
ShallowTrench
Isolation
ShallowTrench
Isolation
Substrate
Shallow n-
ImplantShallow n-
ImplantShallow p-
ImplantShallow p-
Implant
Lecture 030 – DSM CMOS Technology (3/24/10) Page 030-18
CMOS Analog Circuit Design © P.E. Allen - 2010
Step 6 – Sidewall Spacers
p+ p p- MetalSaliciden- n n+Oxide Poly 070321-02PolycideGate Ox
p+ n+
n-well
ShallowTrench
Isolationp-well
ShallowTrench
Isolation
ShallowTrench
Isolation
Substrate
SidewallSpacers
SidewallSpacers
A layer of dielectric is deposited on the surface and removed in such a way as to leave“sidewall spacers” next to the thin-oxide-polysilicon-polycide sandwich. Thesesidewall spacers will prevent the part of the source and drain next to the channel frombecoming heavily doped.
Lecture 030 – DSM CMOS Technology (3/24/10) Page 030-19
CMOS Analog Circuit Design © P.E. Allen - 2010
Step 7 – Implantation of the Heavily Doped Sources and DrainsNote that not only does this step provide the completed sources and drains but allows forohmic contact into the wells and substrate.
p+ p p- MetalSaliciden- n n+Oxide Poly 070321-03PolycideGate Ox
n+
n-well
n+
ShallowTrench
Isolationp-well
p+
ShallowTrench
Isolation
Substrate
p+
implantn+
implantn+
implantn+
implantp+
implantp+
implant
ShallowTrench
Isolation
p+p+ n+ n+
Lecture 030 – DSM CMOS Technology (3/24/10) Page 030-20
CMOS Analog Circuit Design © P.E. Allen - 2010
Step 8 – Siliciding (Salicide and Polycide)This step reduces the resistance of the bulk diffusions and polysilicon and forms an ohmiccontact with material on which it is deposited.Salicide = Self-aligned silicide
p+ p p- MetalSaliciden- n n+Oxide Poly 070321-04PolycideGate Ox
SalicideSalicideSalicide
Polycide
p+ n+
n-well
n+
ShallowTrench
Isolationp-well
p+
Salicide
ShallowTrench
Isolation
Substrate
Polycide
ShallowTrench
Isolation
n+ n+p+ p+
Lecture 030 – DSM CMOS Technology (3/24/10) Page 030-21
CMOS Analog Circuit Design © P.E. Allen - 2010
Step 9 – Intermediate Oxide LayerAn oxide layer is used to cover the transistors and to planarize the surface.
Lecture 030 – DSM CMOS Technology (3/24/10) Page 030-22
CMOS Analog Circuit Design © P.E. Allen - 2010
Step 10- First-Level MetalTungsten plugs are built through the lower intermediate oxide layer to provide contactbetween the devices, wells and substrate to the first-level metal.
Lecture 030 – DSM CMOS Technology (3/24/10) Page 030-23
CMOS Analog Circuit Design © P.E. Allen - 2010
Step 11 – Second-Level MetalThe previous step is repeated for the second-level metal.
Lecture 030 – DSM CMOS Technology (3/24/10) Page 030-24
CMOS Analog Circuit Design © P.E. Allen - 2010
Completed FabricationAfter multiple levels of metal are applied, the fabrication is completed with a thicker top-level metal and a protective layer to hermetically seal the circuit from the environment.Note that metal is used for the upper level metal vias. The chip is electrically connectedby removing the protective layer over large bonding pads.
Lecture 030 – DSM CMOS Technology (3/24/10) Page 030-25
CMOS Analog Circuit Design © P.E. Allen - 2010
Scanning Electron Microscope of a MOSFET Cross-section
Fig. 2.8-20
TEOS
TEOS/BPSG
Tungsten Plug
SOG
Polycide
PolyGate
SidewallSpacer
Lecture 030 – DSM CMOS Technology (3/24/10) Page 030-26
CMOS Analog Circuit Design © P.E. Allen - 2010
Scanning Electron Microscope Showing Metal Levels and Interconnect
Fig.180-11
Metal 1
Metal 2
Metal 3
TungstenPlugs
AluminumVias
Transistors
Lecture 030 – DSM CMOS Technology (3/24/10) Page 030-27
CMOS Analog Circuit Design © P.E. Allen - 2010
SUMMARY• DSM technology typically has a minimum channel length between 0.35μm and 0.1μm• DSM technology addresses the problem of excessive depletion region widths in
junction isolation techniques by using shallow trench isolation• DSM technology may have from 4 to 8 levels of metal• Lightly doped drains and sources are a key aspect of DSM technology
Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-1
CMOS Analog Circuit Design © P.E. Allen - 2010
LECTURE 040 - ULTRA-DEEP SUBMICRON AND BiCMOSTECHNOLOGIES
LECTURE ORGANIZATIONOutline• Ultra-deep submicron CMOS technology
- Features- Advantages- Problems
• BiCMOS technology process flow- CMOS is typical submicron (0.5 μm)
• SummaryCMOS Analog Circuit Design, 2nd Edition ReferenceNew material
Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-2
CMOS Analog Circuit Design © P.E. Allen - 2010
ULTRA-DEEP SUBMICRON (UDSM) CMOS TECHNOLOGYUSDM Technology• Lmin 0.1 microns
• Minimum feature size less than 100 nanometers• Today’s state of the art:
- 65 nm drawn length- 15 nm lateral diffusion (35 nm gate length)- 1.2 nm transistor gate oxide- 8 layers of copper interconnect
• Specialized processing is used to increase drive capability and maintain low offcurrents
Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-3
CMOS Analog Circuit Design © P.E. Allen - 2010
65 Nanometer CMOS TechnologyTEM cross-section of a 35 nm NMOS and PMOS transistors.†
NMOS: PMOS:
These transistors utilize enhanced channel strains to increase drive capability and toreduce off currents.
† P. Bai, et. Al., “A 65nm Lobic Technology Featuring 35nm Gate Lengths, Enhanced Channel Strain, 8 Cu Interconnect Layers, Low-k ILD and 0.57
μm2 SRAM Cell, IEEE Inter. Electron Device Meeting, Dec. 12-15, 2005.
NMOS
220 nm pitch
Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-4
CMOS Analog Circuit Design © P.E. Allen - 2010
UDSM Metal and InterconnectsPhysical aspects:
Layer Pitch(nm)
Thickness(nm)
AspectRatio
Isolation 220 230 -Polysilicon 220 90 -Contacted Gate Pitch 220 - -Metal 1 210 170 1.6Metal 2 210 190 1.8Metal 3 220 200 1.8Metal 4 280 250 1.8Metal 5 330 300 1.8Metal 6 480 430 1.8Metal 7 720 650 1.8Metal 8 1080 975 1.8
Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-5
CMOS Analog Circuit Design © P.E. Allen - 2010
What are the Advantages of UDSM CMOS Technology?Digital Viewpoint:• Improved Ion/Ioff 70 Mbit SRAM chip:
• Reduced gate capacitance• Higher drive current capability• Reduced interconnect density• Reduction of active powerAnalog Viewpoint:• More levels of metal• Higher fT• Higher capacitance density• Reduced junction capacitance per gm
Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-6
CMOS Analog Circuit Design © P.E. Allen - 2010
What are the Disadvantages of UDSM CMOS Technology (for Analog)?• Reduction in power supply resulting in reduced headroom• Gate leakage currents• Reduced small-signal intrinsic gains• Increased nonlinearity (IIP3)• Noise and matching??Intrinsic gain and IP3 as a function of the gate overdrive for decreasing VDS:†
† Anne-Johan Annema, et. Al., “Analog Circuits in Ultra-Deep-Submicron CMOS,” IEEE J. of Solid-State Circuits, Vol. 40, No. 1, Jan. 2005, pp. 132-
143.
Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-7
CMOS Analog Circuit Design © P.E. Allen - 2010
What is the Gate Leakage Problem?Gate current occurs in thin oxide devices due to direct tunneling through the thin oxide.Gate current depends on:1.) The gate-source voltage (and the drain-gate voltage)
iGS = K1vGS exp(K2vGS) and iGD = K3vGD exp(K4vGD)
2.) Gate area – NMOS leakage 6nA/μm2 and PMOS leakage 3nA/μm2
Unfortunately, the gate leakage current is nonlinear with respect to the gate-source andgate-drain voltages. A possible model is:
051205-03
f(vGS)
f(vGD)+
−vGD
+
−vGS f(vDG)
f(vSG)+
−vSG
+
−vDG
NMOS PMOS
Large Signal Models
ggd
ggs
NMOS
gsg
gdg
PMOS
Small Signal Models
Base current cancellation schemes used for BJTs are difficult to apply to the MOSFET.
Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-8
CMOS Analog Circuit Design © P.E. Allen - 2010
Gate Leakage and fgateThe gate leakage can be represented by a conductance, ggate, in parallel with the
gate capacitance, Cgate. Since these two elements have identical area dependence, theyresult in a frequency, fgate, that is fairly independent of the drain-source voltage, vds.
fgate = ggate
2 Cgate
1.5·1016 vGS2etox(vGS-13.6) (NMOS)
0.5·1016 vGS2etox(vGS-13.6) (PMOS)
where tox is in nm and vGS is in V.
For frequencies above fgate theMOSFET looks capacitive and belowfgate, the MOSFET looks resistive (gateleakage).
Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-9
CMOS Analog Circuit Design © P.E. Allen - 2010
UDSM CMOS Technology Summary• Increased transconductance and frequency capability• Low power supply voltages• Reduced parasitics• Gate leakage causes challenges for analog applications of UDSM technology
- Can no longer use the MOSFET for capacitance- Conflict between matching and gate leakage
• Other issues- Noise- Zero temperature coefficient behavior- Etc.
Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-10
CMOS Analog Circuit Design © P.E. Allen - 2010
BiCMOS TECHNOLOGYTypical 0.5μm BiCMOS TechnologyMasking Sequence: 1. Buried n+ layer 9. Base oxide/implant 17. Contacts
2. Buried p+ layer 10. Emitter implant 18. Metal 1 3. Collector tub 11. Poly 1 19. Via 1 4. Active area 12. NMOS lightly doped drain 20. Metal 2 5. Collector sinker 13. PMOS lightly doped drain 21. Via 2 6. n-well 14. n+ source/drain 22. Metal 3 7. p-well 15. p+ source/drain 23. Nitride passivation 8. Emitter window 16. Silicide protectionNotation used in the following slides:
BSPG = Boron and Phosphorus doped Silicate Glass (oxide)Kooi Nitride = A thin layer of silicon nitride on the silicon surface as a result of thereaction of silicon with the HN3 generated, during the field oxidation.TEOS = Tetro-Ethyl-Ortho-Silicate. A chemical compound used to deposit conformaloxide films.
Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-11
CMOS Analog Circuit Design © P.E. Allen - 2010
n+ and p+ Buried Layers
Starting Substrate:
p-substrate 1μm
5μmBiCMOS-01
n+ and p+ Buried Layers:
p-substrate
n+ buried layer p+ buriedlayer
n+ buried layer p+ buried layer
1μm
5μm
NMOS TransistorPMOS TransistorNPN Transistor
BiCMOS-02
Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-12
CMOS Analog Circuit Design © P.E. Allen - 2010
Epitaxial Growth
p-substrate
n+ buried layer p+ buriedlayer
n+ buried layerp+ buried layer
p-typeEpitaxialSilicon
p-well n-well p-well
1μm
5μm
NMOS TransistorPMOS TransistorNPN Transistor
n-well
BiCMOS-03
Comment:• As the epi layer grows vertically, it assumes the doping level of the substrate beneathit.• In addition, the high temperature of the epitaxial process causes the buried layers to
diffuse upward and downward.
Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-13
CMOS Analog Circuit Design © P.E. Allen - 2010
Collector Tub
p-substrate
n+ buried layer p+ buriedlayer
n+ buried layer p+ buried layer
p-typeEpitaxialSilicon
p-welln-well
p-well
1μm
5μm
Collector Tub
NMOS TransistorPMOS TransistorNPN Transistor
BiCMOS-04
Original Area of CollectorTub Implant
Comment:• The collector area is developed by an initial implant followed by a drive-in diffusion to
form the collector tub.
Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-14
CMOS Analog Circuit Design © P.E. Allen - 2010
Active Area Definition
p-substrate
n+ buried layer p+ buriedlayer
n+ buried layer p+ buried layer
p-typeEpitaxialSilicon
p-welln-well
p-well
1μm
5μm
Collector Tub
NMOS TransistorPMOS TransistorNPN Transistor
BiCMOS-05
Nitrideα-Silicon
Comment:• The silicon nitride is use to impede the growth of the thick oxide which allows contact
to the substrate• -silicon is used for stress relief and to minimize the bird’s beak encroachment
Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-15
CMOS Analog Circuit Design © P.E. Allen - 2010
Field Oxide
p-substrate
n+ buried layer p+ buriedlayer
n+ buried layer p+ buried layer
p-typeEpitaxialSilicon
FOX
p-welln-well
p-well
1μm
5μm
Collector Tub
Field Oxide Field Oxide
NMOS TransistorPMOS TransistorNPN Transistor
BiCMOS-06
FOX Field Oxide
Comments:• The field oxide is used to isolate surface structures (i.e. metal) from the substrate
Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-16
CMOS Analog Circuit Design © P.E. Allen - 2010
Collector Sink and n-Well and p-Well Definitions
p-substrate
n+ buried layer p+ buriedlayer
n+ buried layer p+ buried layer
p-typeEpitaxialSilicon
p-well p-well
1μm
5μm
Collector Tub
Field Oxide
NMOS TransistorPMOS TransistorNPN Transistor
BiCMOS-07
FOX
Field Oxide
Collector Sink Anti-Punch ThroughThreshold Adjust
Anti-Punch ThroughThreshold Adjust
n-well
FOX Field Oxide
Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-17
CMOS Analog Circuit Design © P.E. Allen - 2010
Base Definition
p-substrate
n+ buried layer p+ buriedlayer
n+ buried layer p+ buried layer
p-typeEpitaxialSilicon
FOX
p-well p-well
1μm
5μm
Collector Tub
NMOS TransistorPMOS TransistorNPN Transistor
BiCMOS-08
Field Oxide Field Oxide
n-well
FOX Field Oxide
Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-18
CMOS Analog Circuit Design © P.E. Allen - 2010
Definition of the Emitter Window and Sub-Collector Implant
p-substrate
n+ buried layer p+ buriedlayer
n+ buried layer p+ buried layer
p-typeEpitaxialSilicon
p-well p-well
1μm
5μm
NMOS TransistorPMOS TransistorNPN Transistor
BiCMOS-09
Field Oxide
n-well
Sub-Collector
FOX
Field Oxide
Sacrifical Oxide
FOX Field Oxide
Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-19
CMOS Analog Circuit Design © P.E. Allen - 2010
Emitter Implant
p-substrate
n+ buried layer p+ buriedlayer
n+ buried layer p+ buried layer
p-typeEpitaxialSilicon
p-well p-well
1μm
5μm
Collector Tub
NMOS TransistorPMOS TransistorNPN Transistor
BiCMOS-10
Field Oxide
n-well
Sub-CollectorFO
X
Field Oxide
Emitter Implant
FOX Field Oxide
Comments:• The polysilicon above the base is implanted with n-type carriers
Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-20
CMOS Analog Circuit Design © P.E. Allen - 2010
Emitter Diffusion
p-substrate
n+ buried layer p+ buriedlayer
n+ buried layer p+ buried layer
p-typeEpitaxialSilicon
p-well p-well
1μm
5μm
NMOS TransistorPMOS TransistorNPN Transistor
BiCMOS-11
Field Oxide
n-well
FOX
Field Oxide
Emitter
FOX Field Oxide
Comments:• The polysilicon not over the emitter window is removed and the n-type carriers diffuse
toward the base forming the emitter
Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-21
CMOS Analog Circuit Design © P.E. Allen - 2010
Formation of the MOS Gates and LD Drains/Sources
p-substrate
n+ buried layer p+ buriedlayer
n+ buried layer p+ buried layer
p-typeEpitaxialSilicon
p-well p-well
1μm
5μm
NMOS TransistorPMOS TransistorNPN Transistor
BiCMOS-12
Field Oxide
n-well
FOX
Field OxideFOX Field Oxide
Comments:• The surface of the region where the MOSFETs are to be built is cleared and a thin gate
oxide is deposited with a polysilicon layer on top of the thin oxide• The polysilicon is removed over the source and drain areas• A light source/drain diffusion is done for the NMOS and PMOS (separately)
Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-22
CMOS Analog Circuit Design © P.E. Allen - 2010
Heavily Doped Source/Drain
p-substrate
n+ buried layer p+ buriedlayer
n+ buried layer p+ buried layer
p-typeEpitaxialSilicon
p-well p-well
1μm
5μm
NMOS TransistorPMOS TransistorNPN Transistor
BiCMOS-13
Field Oxide
n-well
FOX
Field OxideFOX Field Oxide
Comments:• The sidewall spacers prevent the heavy source/drain doping from being near the
channel of the MOSFET
Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-23
CMOS Analog Circuit Design © P.E. Allen - 2010
Siliciding
p-substrate
n+ buried layer p+ buriedlayer
n+ buried layer p+ buried layer
p-typeEpitaxialSilicon
p-well p-well
1μm
5μm
NMOS TransistorPMOS TransistorNPN Transistor
BiCMOS-14
Field Oxide
n-wellFO
X
Field Oxide
Silicide TiSi2 Silicide TiSi2 Silicide TiSi2
FOX Field Oxide
Comments:• Siliciding is used to reduce the resistance of the polysilicon and to provide ohmic
contacts to the base, emitter, collector, sources and drains
Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-24
CMOS Analog Circuit Design © P.E. Allen - 2010
Contacts
p-substrate
n+ buried layer p+ buriedlayer
n+ buried layer p+ buried layer
p-typeEpitaxialSilicon
p-well p-well
1μm
5μmBiCMOS-15
Field Oxide Field Oxide
n-well
FOX
Field Oxide Field Oxide
Tungsten Plugs Tungsten PlugsTungsten PlugsTEOS/BPSG/SOG TEOS/BPSG/SOG TEOS/BPSG/SOG
FOX
Comments:• A dielectric is deposited over the entire wafer• One of the purposes of the dielectric is to smooth out the surface• Tungsten plugs are used to make electrical contact between the transistors and metal1
Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-25
CMOS Analog Circuit Design © P.E. Allen - 2010
Metal1
p-substrate
n+ buried layer p+ buriedlayer
n+ buried layer p+ buried layer
p-typeEpitaxialSilicon
p-well p-well
1μm
5μmBiCMOS-16
Field Oxide Field Oxide
n-wellFO
X
Field Oxide Field Oxide
TEOS/BPSG/SOG TEOS/BPSG/SOG TEOS/BPSG/SOG
Metal1 Metal1Metal1
FOX
Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-26
CMOS Analog Circuit Design © P.E. Allen - 2010
Metal1-Metal2 Vias
p-substrate
n+ buried layer p+ buriedlayer
n+ buried layer p+ buried layer
p-typeEpitaxialSilicon
p-well p-well
1μm
5μmBiCMOS-17
Field Oxide Field Oxide
n-well
FOX
Field Oxide Field Oxide
TEOS/BPSG/SOG TEOS/BPSG/SOG TEOS/BPSG/SOG
Tungsten Plugs Oxide/SOG/Oxide
FOX
Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-27
CMOS Analog Circuit Design © P.E. Allen - 2010
Metal2
p-substrate
n+ buried layer p+ buriedlayer
n+ buried layer p+ buried layer
p-typeEpitaxialSilicon
p-well p-well
1μm
5μmBiCMOS-18
Field Oxide Field Oxide
n-well
FOX
Field Oxide Field Oxide
TEOS/BPSG/SOG TEOS/BPSG/SOG TEOS/BPSG/SOG
Metal 2
FOX
Oxide/SOG/Oxide
Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-28
CMOS Analog Circuit Design © P.E. Allen - 2010
Metal2-Metal3 Vias
p-substrate
n+ buried layer p+ buriedlayer
n+ buried layer p+ buried layer
p-typeEpitaxialSilicon
p-well p-well
1μm
5μmBiCMOS-19
Field Oxide Field Oxide
n-well
FOX
Field Oxide Field Oxide
TEOS/BPSG/SOG TEOS/BPSG/SOG TEOS/BPSG/SOG
FOX
TEOS/BPSG/SOG
Oxide/SOG/Oxide
Comments:• The metal2-metal3 vias will be filled with metal3 as opposed to tungsten plugs
Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-29
CMOS Analog Circuit Design © P.E. Allen - 2010
Completed Wafer
p-substrate
n+ buried layer p+ buriedlayer
n+ buried layer p+ buried layer
p-typeEpitaxialSilicon
p-well p-well
1μm
5μmBiCMOS-20
Field Oxide Field Oxide
n-well
FOX
Field Oxide Field Oxide
TEOS/BPSG/SOG TEOS/BPSG/SOG TEOS/BPSG/SOG
Nitride (Hermetically seals the wafer)
FOX
TEOS/BPSG/SOG
Metal3
Oxide/SOG/Oxide
Oxide/SOG/Oxide
Metal3Vias
Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-30
CMOS Analog Circuit Design © P.E. Allen - 2010
SUMMARY• UDSM technology typically has a minimum channel length less than 0.1μm• UDSM transistors utilize enhanced channel strains to increase drive capability and
reduce off currents• Advantages of UDSM technology include:
- Smaller devices- Higher speeds and transconductances- Improved Ion/Ioff
• Disadvantages of UDSM technology include:- Gate leakage currents- Reduced small signal gains- Increased nonlinearity
• BiCMOS technology- Offers both CMOS transistors and a high performance vertical BJT- CMOS is typically a generation behind- Silicon germanium can be used to enhance the BJT performance
Lecture 050 – PN Junction and CMOS Transistors (4/30/10) Page 050-1
CMOS Analog Circuit Design © P.E. Allen - 2010
LECTURE 050 - PN JUNCTIONS AND CMOS TRANSISTORSLECTURE ORGANIZATION
Outline• pn junctions• MOS transistors• Layout of MOS transistors• Parasitic bipolar transistors in CMOS technology• High voltage CMOS transistors• SummaryCMOS Analog Circuit Design, 2nd Edition ReferencePages 29-43
Lecture 050 – PN Junction and CMOS Transistors (4/30/10) Page 050-2
CMOS Analog Circuit Design © P.E. Allen - 2010
PN JUNCTIONSHow are PN Junctions used in CMOS?• PN junctions are used to electrically isolate one semiconductor region from another• PN diodes• ESD protection• Creation of the thermal voltage for bandgap purposes• Depletion capacitors – voltage variable capacitors (varactors)
Components of a pn junction:1.) p-doped semiconductor – a semiconductor having atoms containing a lack ofelectrons (acceptors). The concentration of acceptors is NA in atoms per cubiccentimeter.2.) n-doped semiconductor – a semiconductor having atoms containing an excess ofelectrons (donors). The concentration of these atoms is ND in atoms per cubiccentimeter.
Lecture 050 – PN Junction and CMOS Transistors (4/30/10) Page 050-3
CMOS Analog Circuit Design © P.E. Allen - 2010
Abrupt PN Junction
060121-02
p+ semiconductor n semiconductor
Metal-semiconductor junction pn junction Metal-semiconductor junction
p+ semiconductor n semiconductor
Depletion RegionW
xW1 0 W2
W1 = Depletion width on p side W2 = Depletion width on n side
1. Doped atoms near the metallurgical junction lose their free carriers by diffusion.2. As these fixed atoms lose their free carriers, they build up an electric field, which
opposes the diffusion mechanism.3. Equilibrium conditions are reached when:
Current due to diffusion = Current due to electric field
Lecture 050 – PN Junction and CMOS Transistors (4/30/10) Page 050-4
CMOS Analog Circuit Design © P.E. Allen - 2010
Influence of Doping Level on the Depletion RegionsIntuitively, one can see that the depletion regions are inversely proportional to the dopinglevel. To achieve equilibrium, equal and opposite fixed charge on both sides of thejunction are required. Therefore, the larger the doping the smaller the depletion regionon that side of the junction.The equations that result are:
W1 = 2 ( o -vD)
qNA 1 +NAND
1
NA
and
W2 = 2 ( o -vD)
qND 1 +NDNA
1
ND
Assume that vD = 0, o = 0.637V and ND = 1017 atoms/cm3. Find the p-side depletionregion width if NA = 1015 atoms/cm3 and if NA = 1019 atoms/cm3:
For NA = 1015 atoms/cm3 the p-side depletion width is 0.90 μm.
For NA = 1019 atoms/cm3 the p-side depletion width is 0.9 nm.
Lecture 050 – PN Junction and CMOS Transistors (4/30/10) Page 050-5
CMOS Analog Circuit Design © P.E. Allen - 2010
Graphical Characterization of the Abrupt PN JunctionAssume the pn junction is open-circuited.
Cross-section of an ideal pn junction:
060121-03
p+ semiconductor n semiconductor
xpxn
xd
+ −vDiD
Symbol for the pn junction:Built-in potential, o:
o = Vt lnNAND
ni2 ,
where
Vt = kTq
ni is the intrinsic concentration of silicon.060121-04
0
Impurity Concentration (cm-3)
ND
NA
x
0
Impurity Concentration (cm-3)
qND
x-W1
-qNA
W2
x
Electric Field (V/cm)
E0
x
Potential (V)
ψο
xd
iD
vD+ -
vD+ -
iD
Fig. 06-03
Lecture 050 – PN Junction and CMOS Transistors (4/30/10) Page 050-6
CMOS Analog Circuit Design © P.E. Allen - 2010
Reverse-Biased PN JunctionsDepletion region:
xd = xp + xn = W1 + W2
xp = W1 vR
and
xn = W2 vR
Breakdown voltage (BV):If vR > BV, avalanche multiplication will
occur resulting in a high conduction state asillustrated.
vR
iD
vD
060121-05
+− vR = 0V
+− vR > 0V
xd
xd
Influenceof vR ondepletion
region width
vD
iD
BV
060121-06
ReverseBias
ForwardBias
Lecture 050 – PN Junction and CMOS Transistors (4/30/10) Page 050-7
CMOS Analog Circuit Design © P.E. Allen - 2010
Breakdown Voltage as a Function of DopingIt can be shown that†:
BV si(NA + ND)2qNAND E
2max
where Emax = 3x105 V/cm for silicon.
An example:Assume that ND = 1017 atoms/cm3.
Find BV if NA = 1015 atoms/cm3 and if NA = 1019 atoms/cm3:
NA = 1015 atoms/cm3:
If NA << ND, then BV si
2qNA E2
max = 1.04x10-12·9x1010
2·1.6x10-19·1015 = 291V
NA = 1019 atoms/cm3:
If NA >> ND, then BV si
2qND E2
max = 1.04x10-12·9x1010
2·1.6x10-19·1017 = 2.91V
† P. Allen and D. Holberg, CMOS Analog Circuit Design, 2nd ed., Oxford University Press, 2002
Lecture 050 – PN Junction and CMOS Transistors (4/30/10) Page 050-8
CMOS Analog Circuit Design © P.E. Allen - 2010
Depletion CapacitancePhysical viewpoint of the depletion capacitance:
Cj = siAd =
siAW 1+W2
= siA
2 si( o-vD)q(ND+NA)
NDNA
+NAND
= AsiqNAND
2(NA+ND) 1o-vD
= Cj0
1 -vD
o
060204-01 + −vD
xd
W2W1
+− +− +−+− +− +−
d
060204-02
Cj0
Cj
vD0 ψo
Reverse Bias
Ideal
Gummel-Poon Effect
Lecture 050 – PN Junction and CMOS Transistors (4/30/10) Page 050-9
CMOS Analog Circuit Design © P.E. Allen - 2010
Forward-Biased PN JunctionsWhen the pn junction is forward-biased, the potential barrier is reduced and significantcurrent begins to flow across the junction. This current is given by:
iD = Is expvDVt
- 1 where Is = qADppno
Lp +Dnnpo
Ln qAD
L ni
2
N = KT 3exp-VGO
Vt
Graphically, the iD versus vD characteristics are given as:
-40 -30 -20 -10 0 10 20 30 40vD/Vt
iDIs
10
8
6
4
2
0
x1016
x1016
x1016
x1016
x1016
-5
0
5
10
15
20
25
-4 -3 -2 -1 0 1 2 3 4
iDIs
vD/Vt
060204-03
ln(iD/Is)
vD
Decade currentchange/60mV or Octave currentchange/18mV
0V
Lecture 050 – PN Junction and CMOS Transistors (4/30/10) Page 050-10
CMOS Analog Circuit Design © P.E. Allen - 2010
Graded PN JunctionsIn practice, the pn junction is graded rather than abrupt.
060204-04
p+n+
xx
ImpurityConcentration
0Surface Junction
Impurity profileapproximates aconstant slope
p+
IntrinsicConcentration
The previous expressions become:Depletion region widths-
W1 =2 si( o-vD)NDqNA(NA+ND)
m
W2 =2 si( o-vD)NAqND(NA+ND)
m W 1N
m
Depletion capacitance-
Cj = AsiqNAND
2(NA+ND)m
1
o-vD m
= Cj0
1 -vD
om
where 0.33 m 0.5.
Lecture 050 – PN Junction and CMOS Transistors (4/30/10) Page 050-11
CMOS Analog Circuit Design © P.E. Allen - 2010
Metal-Semiconductor JunctionsOhmic Junctions: A pn junction formed by a highly doped semiconductor and metal.
Energy band diagram IV Characteristics
ContactResistance
1
I
V
������������
Vacuum Level
qφm qφsqφB EC
EF
EV
Thermionic or tunneling
n-type metal n-type semiconductor Fig. 2.3-4
Schottky Junctions: A pn junction formed by a lightly doped semiconductor and metal.Energy band diagram IV Characteristics
I
V
����������������
qφBECEF
EV
n-type metal
Forward Bias
Reverse Bias
Reverse Bias
Forward Bias
n-type semiconductor Fig. 2.3-5
Lecture 050 – PN Junction and CMOS Transistors (4/30/10) Page 050-12
CMOS Analog Circuit Design © P.E. Allen - 2010
MOS TRANSISTORPHYSICAL ASPECTS OF MOS TRANSISTORS
Physical Structure of MOS Transistors in an n-well Technology
p+ p p- Metal Salicide n- n n+ Oxide Poly
070322-02
Polycide Gate Ox
n+
n-well
n+
p-well
n+
Substrate
n+
Substrate Salicide Substrate Salicide
Shallow Trench
Isolation
Well Salicide
p+ p+
Shallow Trench
Isolation
n+ n+
W
L
W
L
Width (W) of the MOSFET = Width of the source/drain diffusionLength (L) of the MOSFET = Width of the polysilicon gate between the S/D diffusionsNote that the MOSFET is isolated from the well/substrate by reverse biasing theresulting pn junction
Lecture 050 – PN Junction and CMOS Transistors (4/30/10) Page 050-13
CMOS Analog Circuit Design © P.E. Allen - 2010
Enhancement MOSFETsThe channel of an enhancement MOSFET is formed when the proper potential is appliedto the gate of the MOSFET. This potential inverts the material immediately below thegate to the same type of impurity as the source and drain forming the channel.
060205-06
VDS<VDS(sat)VGS=0V
S G DVDS
VDS<VDS(sat)0V<VGS<VT
S G DVDS
VDS<VDS(sat)
S G DVDS
VGS>VT
Cutoff Weak Inversion Strong Inversion
VT = Gate-bulk work function ( MS) + voltage to change the surface potential (-2 F)+ voltage to offset the channel-bulk depletion charge (-Qb/Cox)+ voltage to compensate the undesired interface charge (-Qss/Cox)
VT = MS -2 F - Qb0
Cox -
QSS
Cox -
Qb - Qb0
Cox = VT0 + |-2 F + vSB| - |-2 F|
where VT0 = MS - 2 F -
Qb0
Cox -
QSS
Cox , =
2q siNA
Cox and Qb 2qNA si(|-2 F+vSB|)
Lecture 050 – PN Junction and CMOS Transistors (4/30/10) Page 050-14
CMOS Analog Circuit Design © P.E. Allen - 2010
Depletion Mode MOSFETThe channel is diffused into the substrate so that a channel exists between the source anddrain with no external gate potential.
Fig. 4.3-4n+ n+
p substrate (bulk)
Channel Length, L
n-channel
Polysilicon
Bulk Source Gate Drain
p+
Chann
el W
idth,
W
The threshold voltage for a depletion mode NMOS transistor will be negative (a negativegate potential is necessary to attract enough holes underneath the gate to cause thisregion to invert to p-type material).
Lecture 050 – PN Junction and CMOS Transistors (4/30/10) Page 050-15
CMOS Analog Circuit Design © P.E. Allen - 2010
Weak Inversion Operation
Weak inversion operation occurs when the appliedgate voltage is below VT and occurs when the surfaceof the substrate beneath the gate is weakly inverted.
Regions of operation according to the surfacepotential, S.
S < F : Substrate not inverted
F < S < 2 F : Channel is weakly inverted(diffusion current)
2 F < S : Strong inversion (drift current)
060205-07
VDS<VDS(sat)0V<VGS<VT
S G DVDS
Weak Inversion
DiffusionCurrent
log iD
10-6
10-120 VT
VGS
Drift CurrentDiffusion Current
Drift current versusdiffusion current in aMOSFET:
Lecture 050 – PN Junction and CMOS Transistors (4/30/10) Page 050-16
CMOS Analog Circuit Design © P.E. Allen - 2010
LAYOUT OF MOS TRANSISTORSLayout of a Single MOS transistor:
060223-01
STI
n-well
W
L
Drain
Gate Source
Well/Bulk
p-well
DrainWell/Bulk
W
L
Gate Source
Comments:• Make sure to contact the source and drain with multiple contacts to evenly distribute
the current flow under the gate.• Minimize the area of the source and drain to reduce bulk-source/drain capacitance.
Lecture 050 – PN Junction and CMOS Transistors (4/30/10) Page 050-17
CMOS Analog Circuit Design © P.E. Allen - 2010
Geometric EffectsOrientation:Devices oriented in the same direction match more precisely than those oriented in otherdirections.
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����
������
��������
Good Matching041027-02
Poorer Matching
Lecture 050 – PN Junction and CMOS Transistors (4/30/10) Page 050-18
CMOS Analog Circuit Design © P.E. Allen - 2010
Diffusion and Etch Effects• Poly etch rate variation – use dummy elements to prevent etch rate differences.
��������
������������
��������
041027-03
��������Dummy
Gate
��������Dummy
Gate
• Do not put contacts on top of the gate for matched transistors.• Be careful of diffusion interactions for diffusions near the channel of the MOSFET
Lecture 050 – PN Junction and CMOS Transistors (4/30/10) Page 050-19
CMOS Analog Circuit Design © P.E. Allen - 2010
Thermal and Stress Effects• Oxide gradients – use common centroid geometry layout• Stress gradients – use proper location and common centroid geometry layout• Thermal gradients – keep transistors well away from power devices and use common
centroid geometry layout with interdigitated transistorsExamples of Common Centroid Interdigitated transistor layout:
A B B A
Dum
my
Gat
e
Dum
my
Gat
e
DA SA/SB DB SA/SB DA
GA GAGB GBInterdigitated, common centroid layout
041027-04
Dum
my
Gat
e
Dum
my
Gat
e
BA
AB
SA/SBDA DB
GA GBGB GA
SB/SADB DACross-Coupled Transistors
Lecture 050 – PN Junction and CMOS Transistors (4/30/10) Page 050-20
CMOS Analog Circuit Design © P.E. Allen - 2010
MOS Transistor LayoutPhotolithographic invariance (PLI) are transistors that exhibit identical orientation. PLIcomes from optical interactions between the UV light and the masks.Examples of the layout of matched MOS transistors:1.) Examples of mirror symmetry and photolithographic invariance.
Mirror Symmetry��������
����
Photolithographic Invariance����
��������
Fig. 2.6-05
Lecture 050 – PN Junction and CMOS Transistors (4/30/10) Page 050-21
CMOS Analog Circuit Design © P.E. Allen - 2010
MOS Transistor Layout - Continued2.) Two transistors sharing a common source and laid out to achieve both
photolithographic invariance and common centroid.
����
��������
��������
����
����
��������
��������
����
Metal 2
Via 1
Metal 1
Fig. 2.6-06
Lecture 050 – PN Junction and CMOS Transistors (4/30/10) Page 050-22
CMOS Analog Circuit Design © P.E. Allen - 2010
MOS Transistor Layout - Continued3.) Compact layout of the previous example.
������������
��������
��������
Fig. 2.6-07
Metal 2
Metal 2
Via 1
Metal 1
Lecture 050 – PN Junction and CMOS Transistors (4/30/10) Page 050-23
CMOS Analog Circuit Design © P.E. Allen - 2010
PARASITIC BIPOLAR TRANSISTORS IN CMOS TECHNOLOGYA Lateral Bipolar Transistorn-well CMOS technology:• It is desirable to have the lateral
collector current much larger than thevertical collector current.
• Lateral BJT generally has goodmatching.
• The lateral BJT can be used as aphotodetector with reasonably goodefficiency.
• Triple well technology allows thecurrent of the vertical collector toavoid the substrate.
060221-01
p+
n-well
n+
Substrate
E LCBVC
STI STI
LC
STI Lateral Collector
Emitter
Base
VerticalCollector
p+ p+
Lecture 050 – PN Junction and CMOS Transistors (4/30/10) Page 050-24
CMOS Analog Circuit Design © P.E. Allen - 2010
060221-02
p+
n-well
n+
Substrate
BVC
STI STI
LC
STI Lateral Collector Emitter
Base
VerticalCollector
p+ p+p+
E LC
Keeps carriers fromflowing at the surfaceand reduces 1/f noise
A Field-Aided Lateral BJT
Use minimum channel length toenhance beta:ßF 50 to 100 depending onthe process
Lecture 050 – PN Junction and CMOS Transistors (4/30/10) Page 050-25
CMOS Analog Circuit Design © P.E. Allen - 2010
HIGH VOLTAGE CMOS TRANSISTORSExtended Voltage MOSFETSThe electric field from the source to drain in the channel is shown below.
��������������������������������������������������Source n+
������Drain n+
������������Channel
p - substrate
xp xdDistance, x
ElectricField
Emax
0
Draindepletion
region
Substrate depletion region
Sourcedepletion
region
Area = Vp Area = Vd
040920-01
Pinch-off region
The voltage drop from drain to source is,VDS = Vp + Vd = 0.5(Emaxxp + Emaxxd) = 0.5Emax(xp + xd)
Emax and xp are limited by hot carrier generation and channel length modulationrequirements whereas these limitations do not exist for xd.Therefore, to get extended voltage transistors, make xd larger.
Lecture 050 – PN Junction and CMOS Transistors (4/30/10) Page 050-26
CMOS Analog Circuit Design © P.E. Allen - 2010
High Voltage ArchitecturesThe objective is to create a lightly doped, extended drain region where the high voltageof the drain can drop down to a level that will not cause the gate oxide to breakdown.LOCOS Architecture:
DSM Architecture:
Lecture 050 – PN Junction and CMOS Transistors (4/30/10) Page 050-27
CMOS Analog Circuit Design © P.E. Allen - 2010
Lateral DMOS (LDMOS) Using LOCOS CMOS TechnologyThe LDMOS structure is designed to provide sufficient lateral dimension and to preventoxide breakdown by the higher drain voltages.One possible implementation using LOCOS technology:
n well
p substrate
p epi p epi
n+ n+
071025-01
xd xdp-bodyp-body
Drain DrainGate Source/Bulk Gate
n+ n+ p+
• Structure is symmetrical about the source/bulk contact• Channel is formed in the p region under the gates• The lightly doped n region between the drain side of the channel and the n+ drain
contact (xd) increases the depletion region width on the drain side of the channel/drainpn junction resulting in larger values of vDS.
• Drain voltage can be 20-30V
Lecture 050 – PN Junction and CMOS Transistors (4/30/10) Page 050-28
CMOS Analog Circuit Design © P.E. Allen - 2010
Lateral DMOS (LDMOS) Using DSM CMOS TechnologyCross-section of anNLDMOS using DSMtechnology:
Differences between an NLDMOS and NMOS:• Asymmetry• Non-uniform channel• Current flow (not all at the surface)• No self-alignment (larger drain-gate overlap
capacitance)• Note the extended drift region on the drain side of the
channel
Lecture 050 – PN Junction and CMOS Transistors (4/30/10) Page 050-29
CMOS Analog Circuit Design © P.E. Allen - 2010
SUMMARY• pn junction usage in CMOS include:
- Electrical isolation, pn diodes, ESD protection, depletion capacitors• Depletion region widths are inversely proportional to the doping• Depletion region widths are proportional to the reverse bias voltage• Ohmic metal-semiconductor junctions require a highly doped semiconductor• MOSFETs can be:
- Enhancement – the applied gate voltage forms the channel- Depletion – the channel is physically constructed in fabrication
• The threshold voltage of MOSFETs consists of the following components:- Gate bulk work function ( MS)- Voltage to change the surface potential (-2 F)- Voltage to offset the channel-bulk depletion charge (-Qb/Cox)- Voltage to compensate the undesired interface charge (-Qss/Cox)
• Weak inversion is MOSFET operation with the gate-source voltage less than thethreshold voltage
• Layout of the MOSFET is important to its performance and matching capabilities• Extended drain regions lead to higher voltage capability MOSFETs
Lecture 060 – Capacitors (3/24/10) Page 060-1
CMOS Analog Circuit Design © P.E. Allen - 2010
LECTURE 060 - CAPACITORSLECTURE ORGANIZATION
Outline• Introduction• pn junction capacitors• MOSFET gate capacitors• Conductor-insulator-conductor capacitors• Deviation from ideal behavior in capacitors• SummaryCMOS Analog Circuit Design, 2nd Edition ReferencePages 43-47, 58-59 and 63-64
Lecture 060 – Capacitors (3/24/10) Page 060-2
CMOS Analog Circuit Design © P.E. Allen - 2010
INTRODUCTIONTypes of Capacitors for CMOS Technology1.) PN junction (depletion)
capacitors
2.) MOSFET gate capacitors
3.) Conductor-insulator-conductor capacitors
060204-01 + −vD
xd
W2W1
+− +− +−+− +− +−
d
060207-01
p-well
p+
G D,S,B
n+n+
Cox
Cjunction
Top ConductorBottomConductorDielectric
Insulating layer
060206-02
Lecture 060 – Capacitors (3/24/10) Page 060-3
CMOS Analog Circuit Design © P.E. Allen - 2010
Characterization of CapacitorsWhat characterizes a capacitor?1.) Dissipation (quality factor) of a capacitor is
Q = CRp = C
Rs
where Rp is the equivalent resistance in parallel with the capacitor, C, and Rs is the electrical series resistance (ESR) of the capacitor, C.
2.) Parasitic capacitors to ground from each node of the capacitor.3.) The density of the capacitor in Farads/area.4.) The absolute and relative accuracies of the capacitor.5.) The Cmax/Cmin ratio which is the largest value of capacitance to the smallest when
the capacitor is used as a variable capacitor (varactor).6.) The variation of a variable capacitance with the control voltage.7.) Linearity, q = Cv.
Lecture 060 – Capacitors (3/24/10) Page 060-4
CMOS Analog Circuit Design © P.E. Allen - 2010
PN JUNCTION CAPACITORSPN Junction Capacitors in a WellGenerally made by diffusion into the well.
Anode
n-well
p+
Substrate
Fig. 2.5-011
n+n+
������p+
DepletionRegion
Cathode
p- substrate
CjCj
RwjRwj Rw
Cw
Rs
Anode Cathode
VA VBC
Rwj
rD
Layout:
Minimize the distance between the p+ and n+ diffusions.Two different versions have been tested.
1.) Large islands – 9μm on a side2.) Small islands – 1.2μm on a side n-well
n+ diffusion
p+ dif-fusion
Fig. 2.5-1A
Lecture 060 – Capacitors (3/24/10) Page 060-5
CMOS Analog Circuit Design © P.E. Allen - 2010
PN-Junction Capacitors – ContinuedThe anode should be the floating node and the cathode must be connected to ac ground.Experimental data (Q at 2GHz, 0.5μm CMOS)†:
060206-03
00.5
1
1.52
2.5
3
3.54
0 0.5 1 1.5 2 2.5 3 3.5
CA
node
(pF
)
Cathode Voltage (V)
Large Islands
Small Islands
Cmax Cmin
0
20
40
60
80
100
120
0 0.5 1 1.5 2 2.5 3 3.5
QA
node
Qmin Qmax
Large Islands
Small Islands
Cathode Voltage (V)
R-XBridge
Anode Cathode
CathodeVoltage
C
R-XBridge
Anode Cathode
CathodeVoltage
C
Small Islands (598 1.2μm x1.2μm) Large Islands (42 9μm x 9μm)TerminalUnder Test Cmax/Cmin Qmin Qmax Cmax/Cmin Qmin Qmax
Anode 1.23 94.5 109 1.32 19 22.6Cathode 1.21 8.4 9.2 1.29 8.6 9.5
† E. Pedersen, “RF CMOS Varactors for 2GHz Applications,” Analog Integrated Circuits and Signal Processing, vol. 26, pp. 27-36, Jan. 2001.
Electrons as majority carriers lead to higher Q because of their higher mobility.The resistance, Rwj, is reduced in small islands compared with large islands higher Q
Lecture 060 – Capacitors (3/24/10) Page 060-6
CMOS Analog Circuit Design © P.E. Allen - 2010
MOSFET GATE CAPACITORSMOSFET Gate Capacitor StructureThe MOSFET gate capacitors have the gate as one terminal of the capacitor and somecombination of the source, drain, and bulk as the other terminal.In the model of the MOSFET gate capacitor shown below, the gate capacitance is reallytwo capacitors in series depending on the condition of the channel.
Cgate = 1
1Cox
+1Cj
060207-02
p-well
p+
G D
n+n+
Cox
Cjunction
G
S D
B
Cox
Cjunction
Channel Resistance
Bulk Resistance
S B
Lecture 060 – Capacitors (3/24/10) Page 060-7
CMOS Analog Circuit Design © P.E. Allen - 2010
060207-03
p-well
p+
G D,S,B
n+n+
Cox
Cjunction
VG-VD,S,B
Capacitance
StrongInversion
Accumulation
ModerateInversion
WeakInv.
Depletion
CoxCox
MOSFET Gate Capacitor as a function of VGS with D=S=B
Operation:In this configuration, the MOSFET gate capacitor has 5 regions of operation as VGS isvaried. They are:
1.) Accumulation2.) Depletion3.) Weak inversion4.) Moderate inversion5.) Strong inversion
For the first four regions, the gate capacitance is the series combination of Cox and Cjgiven as,
Cgate = 1
1Cox
+1Cj
Lecture 060 – Capacitors (3/24/10) Page 060-8
CMOS Analog Circuit Design © P.E. Allen - 2010
Use of a 3 Segment Model to Explain the Gate Capacitor Variation
Region Channel R Cox and Cj Cgate 3-Segment Model
Accumulation Large In series andCj > Cox
Cgate Cox
Depletion Large In series andCj Cox
Cgate 0.5Cox 0.5Cj
WeakInversion
Large In series andCj < Cox
Cgate Cj
ModerateInversion
Moderate In series andCj < Cox
Cj < Cgate < Cox
StrongInversion
Small In parallel andCj < Cox
Cgate Cox
Lecture 060 – Capacitors (3/24/10) Page 060-9
CMOS Analog Circuit Design © P.E. Allen - 2010
MOSFET Gate Capacitor as a function of VGS with Bulk Fixed (Inversion Mode)
060207-04
p-well
p+
G D,S
n+n+
Cox
Cjunction
VG-VD,S
CoxCox
B Capacitance
0
VT shift if VBS ≠ 0
B=D= S
InversionMode MOS
Conditions:• D = S, B = VSS
• Accumulation region removed by connecting bulk to VDD
• Nonlinear• Channel resistance:
Ron = L
12KP'(VBG-|VT|)
• LDD transistors will give lower Q because of the increased series resistance
Lecture 060 – Capacitors (3/24/10) Page 060-10
CMOS Analog Circuit Design © P.E. Allen - 2010
Inversion Mode NMOS CapacitorBest results are obtainedwhen the drain-source areconnected to ac ground.
Experimental Results (Q at2GHz, 0.5μm CMOS)†:
1.5
2
2.5
3
3.5
4
4.5
0 0.5 1 1.5 2 2.5 3 3.5
CG
ate
(pF)
VG = 2.1V
VG = 1.8V
VG = 1.5V
Cmax Cmin
Drain/Source Voltage (V)
2224
26
2830
32
34
3638
0 0.5 1 1.5 2 2.5 3 3.5
VG = 1.8V
VG = 1.5V
Qmax Qmin
Drain/Source Voltage (V) 070617-06
QG
ate
VG = 2.1VRX
MeterVG VD,S
RXMeter
VG VD,S
VG =1.8V: Cmax/Cmin ratio = 2.15 (1.91), Qmax = 34.3 (5.4), and Qmin = 25.8(4.9)
† E. Pedersen, “RF CMOS Varactors for 2GHz Applications,” Analog Integrated Circuits and Signal Processing, vol. 26, pp. 27-36, Jan. 2001.
���������Cox
p+
Bulk
G D,S
G
D,S
p- substrate/bulk����������������n+n+
n- LDD
Rd RdCd CdCsi
CjRsj
Rsi
Cov Cov B
Fig. 2.5-2
Shown in inversion mode
Lecture 060 – Capacitors (3/24/10) Page 060-11
CMOS Analog Circuit Design © P.E. Allen - 2010
Accumulation Mode NMOS Gate CapacitorG B
n+n+
Cox
060207-05
VG-VD,S,B
Capacitance
Depletion
Cox
Inversion Accumulation
Conditions:• Remove p+ drain and source and put n+ bulk contacts instead.• Implements a variable capacitor with a larger transition region between the maximum
and minimum values.• Reasonably linear capacitor for values of VGB > 0
Lecture 060 – Capacitors (3/24/10) Page 060-12
CMOS Analog Circuit Design © P.E. Allen - 2010
Accumulation Mode Capacitor – ContinuedBest results areobtained when thedrain-source are onac ground.
ExperimentalResults (Q at 2GHz, 0.5μm CMOS)†:
2
2.4
2.8
3.2
3.6
4
0 0.5 1 1.5 2 2.5 3 3.5
CG
ate
(pF)
VG = 0.9V
VG = 0.6V
VG = 0.3V
Cmax Cmin
Drain/Source Voltage (V)
25
30
35
40
45
0 0.5 1 1.5 2 2.5 3 3.5
Qmax Qmin
Drain/Source Voltage (V)
QG
ate
VG = 0.9V
VG = 0.6V
070617-07
VG = 0.3VRXMeter
VG VD,S
RXMeter
VG VD,S
† E. Pedersen, “RF CMOS Varactors for 2GHz Applications,” Analog Integrated Circuits and Signal Processing, vol. 26, pp. 27-36, Jan. 2001.
����
������
Cox
p+Bulk
G D,S
G
D,S
p- substrate/bulk
n+n+
n- LDD
Rd RdCd Cd
Cw
Rs
Cov Cov B
Fig. 2.5-5
n- well
Rw
Shown in depletion mode.
VG = 0.6V: Cmax/Cmin ratio = 1.69 (1.61), Qmax = 38.3 (15.0), and Qmin = 33.2(13.6)
Lecture 060 – Capacitors (3/24/10) Page 060-13
CMOS Analog Circuit Design © P.E. Allen - 2010
CONDUCTOR-INSULATOR-CONDUCTOR CAPACITORSPolysilicon-Oxide-Polysilicon (Poly-Poly) CapacitorsLOCOS Technology:A very linear capacitorwith minimum bottomplate parasitic.
DSM Technology:A very linear capacitor withsmall bottom plate parasitic.
Lecture 060 – Capacitors (3/24/10) Page 060-14
CMOS Analog Circuit Design © P.E. Allen - 2010
Metal-Insulator-Metal (MiM) CapacitorsIn some processes, there is a thin dielectric between a metal layer and a special metallayer called “capacitor top metal”. Typically the capacitance is around 1fF/μm2 and isat the level below top metal.
060530-01
Third levelfrom top metal
Second level from top metalInter-
mediateOxideLayers
Top Metal
Protective Insulator Layer
Metal Via
Capacitor Top Metal
Capacitor bottom plate
Capacitordielectric
Fourth levelfrom top metal
Vias connecting bottom plate to lower metal
Vias connecting top plate to top metal
Vias connecting bottom plate to lower metal
Good matching is possible with low parasitics.
Lecture 060 – Capacitors (3/24/10) Page 060-15
CMOS Analog Circuit Design © P.E. Allen - 2010
Metal-Insulator-Metal Capacitors – Lateral and Vertical FluxCapacitance between conductors on the same level and use lateral flux.
These capacitors are sometimes called fractal capacitors because the fractal patterns arestructures that enclose a finite area with a near-infinite perimeter.The capacitor/area can be increased by a factor of 10 over vertical flux capacitors.
+ - + -
+ - +-
Fringing field
Metal
Fig2.5-9
+ - + -Metal 3
Metal 2
Metal 1
Metal
Top view:
Side view:
Lecture 060 – Capacitors (3/24/10) Page 060-16
CMOS Analog Circuit Design © P.E. Allen - 2010
More Detail on Horizontal Metal Capacitors†
Some of the possible metal capacitor structures include:1.) Horizontal parallel plate (HPP).
2.) Parallel wires (PW):
† R. Aparicio and A. Hajimiri, “Capacity Limits and Matching Properties of Integrated Capacitors, IEEE J. of Solid-State Circuits, vol. 37, no. 3, March
2002, pp. 384-393.
030909-01
030909-02 Top ViewLateral View
Lecture 060 – Capacitors (3/24/10) Page 060-17
CMOS Analog Circuit Design © P.E. Allen - 2010
Horizontal Metal Capacitors - Continued3.) Vertical parallel plates (VPP):
Vias
030909-03
4.) Vertical bars (VB):
Vias
030909-04
Top ViewLateral View
Lecture 060 – Capacitors (3/24/10) Page 060-18
CMOS Analog Circuit Design © P.E. Allen - 2010
Horizontal Metal Capacitors - ContinuedExperimental results for a CMOS process with 3 layers of metal, Lmin =0.5μm, tox =0.95μm and tmetal = 0.63μm for the bottom 2 layers of metal.
Structure Cap. Density(aF/μm2)
Caver.(pF)
Std. Dev.(fF) Caver.
fres.
(GHz)Q @
1 GHzRs ( ) Break-
down (V)
VPP 158.3 18.99 103 0.0054 3.65 14.5 0.57 355PW 101.5 33.5 315 0.0094 1.1 8.6 0.55 380HPP 35.8 6.94 427 0.0615 6.0 21 1.1 690
Experimental results for a digital CMOS process with 7 layers of metal, Lmin =0.24μm,tox = 0.7μm and tmetal = 0.53μm for the bottom 5 layers of metal. All capacitors = 1pF.
Structure(1 pF)
Cap. Density(aF/μm2)
Caver.(pF)
Area(μm2)
Cap.Enhancement
Std.Dev.(fF)
Caver.
fres.(GHz)
Q @1 GHz
Break-down
(V)VPP 1512.2 1.01 670 7.4 5.06 0.0050 > 40 83.2 128VB 1281.3 1.07 839.7 6.3 14.19 0.0132 37.1 48.7 124
HPP 203.6 1.09 5378 1.0 26.11 0.0239 21 63.8 500MIM 1100 1.05 960.9 5.4 - - 11 95 -
Lecture 060 – Capacitors (3/24/10) Page 060-19
CMOS Analog Circuit Design © P.E. Allen - 2010
Horizontal Metal Capacitors - ContinuedHistogram of the capacitance distribution forthe above case (1 pF):
Experimental results for a digital CMOSprocess with 7 layers of metal, Lmin =0.24μm, tox = 0.7μm and tmetal = 0.53μm forthe bottom 5 layers of metal (all capacitors =10pF):
Structure(10 pF)
Cap. Density(aF/μm2)
Caver.(pF)
Area(μm2)
Cap.Enhancement
Std.Dev.(fF)
Caver.
fres.(GHz)
Q @1 GHz
Break-down
(V)
VPP 1480.0 11.46 7749 8.0 73.43 0.0064 11.3 26.6 125VB 1223.2 10.60 8666 6.6 73.21 0.0069 11.1 17.8 121
HPP 183.6 10.21 55615 1.0 182.1 0.0178 6.17 23.5 495MIM 1100 10.13 9216 6.0 - - 4.05 25.6 -
0
2
4
6
8
10
12
94 96 98 100 102 104 106
HPPVPPPW
Num
ber
of d
ice
σcCaver
030909-05
Lecture 060 – Capacitors (3/24/10) Page 060-20
CMOS Analog Circuit Design © P.E. Allen - 2010
DEVIATION FROM IDEAL BEHAVIOR IN CAPACITORSCapacitor Errors1.) Dielectric gradients2.) Edge effects3.) Process biases4.) Parasitics5.) Voltage dependence6.) Temperature dependence
Lecture 060 – Capacitors (3/24/10) Page 060-21
CMOS Analog Circuit Design © P.E. Allen - 2010
Capacitor Errors - Oxide GradientsError due to a variation in dielectric thickness across the wafer.Common centroid layout - only good for one-dimensional errors:
060207-07
2C C 2C CNo common centroid layout Common centroid layout
An alternate approach is to layout numerous repetitions and connect them randomly toachieve a statistical error balanced over the entire area of interest.Improved matching of three components, A, B, and C:
A B C A B C A B C
A BC A B C A B C
AB C A B C A B C
A
B
C 070625-01
Lecture 060 – Capacitors (3/24/10) Page 060-22
CMOS Analog Circuit Design © P.E. Allen - 2010
Capacitor Errors - Edge EffectsThere will always be a randomness on the definition of the edge.However, etching can be influenced by the presence of adjacent structures.For example,
AC
A BC
B
Matching of A and B are disturbed by the presence of C.
Improved matching achieve by matching the surroundings of A and B.
Lecture 060 – Capacitors (3/24/10) Page 060-23
CMOS Analog Circuit Design © P.E. Allen - 2010
Process Bias on CapacitorsConsider the following two capacitors:
If L1 = L2 = 2μm, W2 = 2W1 = 4μm andx = 0.1μm, the ratio of C2 to C1 can
be written as,C2C1
= (2-.2)(4-.2)(2-.2)(2-.2) =
3.81.8 = 2.11 5.6% error in matching
How can this matching error be reduced?The capacitor ratios in general can be expressed as,
C2C1
= (L2-2 x)(W2-2 x)(L1-2 x)(W1-2 x) =
W 2W 1
1 -2 xW 2
1 -2 xW 1
W 2W 1
1 -2 xW 2
1 +2 xW 1
W 2W 1
1 -2 xW 2
+2 xW 1
Therefore, if W2 = W1, the matching error should be minimized. The best matchingresults between two components are achieved when their geometries are identical.
L1
W1
C1 L2 C2
W2041022-03
ΔxΔx
ΔxΔx
Lecture 060 – Capacitors (3/24/10) Page 060-24
CMOS Analog Circuit Design © P.E. Allen - 2010
Replication PrincipleBased on the previous result, a way to minimize the matching error between two or moregeometries is to insure that the matched components have the same area to peripheryratio. Therefore, the replication principle requires that all geometries have the same area-periphery ratio.Correct way to match the previous capacitors (the two C2 capacitors are connectedtogether):
If L1 = L2 = 2μm, W2 = 2W1 = 2μm and x = 0.1μm, the ratio of C2 to C1 can be writtenas,
C2C1
= 2(2-.2)(2-.2)(2-.2)(2-.2) =
2·1.81.8 = 2 0% error in matching
The replication principle works for any geometry and includes transistors, resistors aswell as capacitors.
L1
W1
C1
041022-04
Δx
ΔxL2
W2
C2
Δx
ΔxL2
W2
C2
Δx
Δx
Lecture 060 – Capacitors (3/24/10) Page 060-25
CMOS Analog Circuit Design © P.E. Allen - 2010
Capacitor Errors - Relative AccuracyCapacitor relative accuracy is proportional to the area of the capacitors and inverselyproportional to the difference in values between the two capacitors.For example,
0.04
0.03
0.02
0.01
0.001 2 4 8 16 32 64
Unit Capacitance = 0.5pF
Unit Capacitance = 1pF
Unit Capacitance = 4pF
Rel
ativ
e A
ccur
acy
Ratio of Capacitors
Lecture 060 – Capacitors (3/24/10) Page 060-26
CMOS Analog Circuit Design © P.E. Allen - 2010
Capacitor Errors - ParasiticsParasitics are normally from the top and bottom plate to ac ground which is typically thesubstrate.
060702-08
Top Plate
Bottom Plate
DesiredCapacitor
Bottomplate
parasitic
Topplate
parasitic
Top plate parasitic is 0.01 to 0.001 of Cdesired
Bottom plate parasitic is 0.05 to 0.2 Cdesired
Lecture 060 – Capacitors (3/24/10) Page 060-27
CMOS Analog Circuit Design © P.E. Allen - 2010
Layout Considerations on Capacitor AccuracyDecreasing Sensitivity to Edge Variation:
060207-09
FringingField
FringingField
Sensitive to alignment errors in the upper and lower plates and loss ofcapacitance flux (smaller capacitance).
? ?Insensitive to alignment errors and the flux reaching the bottom plate is largerresulting in large capacitance.
A structure that minimizes the ratio of perimeter to area (circle is best).
060207-10
Bottom Plate
TopPlate
Reduced bottom plate parasitic.
Lecture 060 – Capacitors (3/24/10) Page 060-28
CMOS Analog Circuit Design © P.E. Allen - 2010
Accurate Matching of Capacitors†
Accurate matching of capacitors depends on the following influence:1.) Mismatched perimeter ratios2.) Proximity effects in unit capacitor photolithography3.) Mismatched long-range fringe capacitance4.) Mismatched interconnect capacitance5.) Parasitic interconnect capacitanceLong-range fringe capacitance:
061216-04
Shield to collect long-range fringe fields? ? ? ?
Obviously there will be a tradeoff between matching and speed.
† M.J. McNutt, S. LeMarquis and J.L.Dunkley, “Systematic Capacitance Matching Errors and Corrective Layout Procedures,” IEEE J. of Solid-StateCircuit, vo. 29, No. 5, May 1994, pp. 611-616.
Lecture 060 – Capacitors (3/24/10) Page 060-29
CMOS Analog Circuit Design © P.E. Allen - 2010
ShieldingThe key to shielding is to determine and control the electric fields.Consider the following noisy conductor and its influence on the substrate:
060118-10
Substrate
Noisy Conductor
SubstrateShield
SeparateGround
Noisy Conductor
Increased Parasitic Capacitance
Use of bootstrapping to reduce capacitor bottom plate parasitic:
060316-02
Substrate
Top Plate
Bottom Plate
ShieldSubstrate
Cpar
2Cpar
2Cpar
+1
Lecture 060 – Capacitors (3/24/10) Page 060-30
CMOS Analog Circuit Design © P.E. Allen - 2010
Definition of Temperature and Voltage CoefficientsIn general a variable y which is a function of x, y = f(x), can be expressed as a Taylorseries,
y(x) y(x0) + a1(x- x0) + a2(x- x0)2+ a3(x- x0)3 + ···where the coefficients, ai, are defined as,
a1 = df(x)dx
|x=x0 , a2 =
12
d2f(x)dx2
|x=x0 , ….
The coefficients, ai, are called the first-order, second-order, …. temperature or voltagecoefficients depending on whether x is temperature or voltage.Generally, only the first-order coefficients are of interest.
In the characterization of temperature dependence, it is common practice to use a termcalled fractional temperature coefficient, TCF, which is defined as,
TCF(T=T0) = 1
f(T=T0) df(T)dT
|T=T0 parts per million/°C (ppm/°C)
or more simply,
TCF = 1
f(T) df(T)dT parts per million/°C (ppm/°C)
A similar definition holds for fractional voltage coefficient.
Lecture 060 – Capacitors (3/24/10) Page 060-31
CMOS Analog Circuit Design © P.E. Allen - 2010
Capacitor Errors - Temperature and Voltage DependenceMOSFET Gate Capacitors:
Absolute accuracy ±10%Relative accuracy ±0.2%Temperature coefficient +25 ppm/C°Voltage coefficient -50ppm/V
Polysilicon-Oxide-Polysilicon Capacitors:Absolute accuracy ±10%Relative accuracy ±0.2%Temperature coefficient +25 ppm/C°Voltage coefficient -20ppm/V
Metal-Dielectric-Metal Capacitors:Absolute accuracy ±10%Relative accuracy ±0.6%Temperature coefficient +40 ppm/C°
Voltage coefficient -20ppm/V, 5ppm/V2
Accuracies depend upon the size of the capacitors.
Lecture 060 – Capacitors (3/24/10) Page 060-32
CMOS Analog Circuit Design © P.E. Allen - 2010
Future Technology Impact on CapacitorsWhat will be the impact of scaling down in CMOS technology?• The capacitance can be divided into gate capacitance and overlap capacitance.
Gate capacitance varies with external voltage changesOverlap capacitances are constant with respect to external voltage changes
As the channel length decreases, the gate capacitance becomes less of the totalcapacitance and consequently the Cmax/Cmin will decrease. However, the Q of thecapacitor will increase because the physical dimensions are getting smaller.
• For UDSM, the gate leakage current will eliminate gate capacitors from being useful.Best capacitor for future scaled CMOS?
Polysilicon-polysilicon or metal-metal (too much leakage current in gatecapacitors)Best varactor for future scaled CMOS?
The standard mode CMOS depletion capacitor because Cmax/Cmin is larger thanthat for the accumulation mode and Q should be sufficient. The pn junction will bemore useful for UDSM.
Lecture 060 – Capacitors (3/24/10) Page 060-33
CMOS Analog Circuit Design © P.E. Allen - 2010
SUMMARY• Capacitors are made from:
- pn junctions (depletion capacitors)- MOSFET gate capacitors- Conductor-insulator-conductor capacitors
• Capacitors are characterized by:- Q, a measure of the loss- Density- Parasitics- Absolute and relative accuracies
• Deviations from ideal capacitor behavior include;- Dielectric gradients- Edge effects (etching)- Process biases- Parasitics- Voltage and temperature dependence
Lecture 070 – Resistors and Inductors (4/19/10) Page 070-1
CMOS Analog Circuit Design © P.E. Allen - 2010
LECTURE 070 – RESISTORS AND INDUCTORSLECTURE ORGANIZATION
Outline• Resistors• Inductors• SummaryCMOS Analog Circuit Design, 2nd Edition ReferencePages 47-48, 60-63 and new material
Lecture 070 – Resistors and Inductors (4/19/10) Page 070-2
CMOS Analog Circuit Design © P.E. Allen - 2010
RESISTORSTypes of Resistors Compatible with CMOS Technology1.) Diffused and/or implanted resistors.2.) Well resistors.3.) Polysilicon resistors.4.) Metal resistors.
Lecture 070 – Resistors and Inductors (4/19/10) Page 070-3
CMOS Analog Circuit Design © P.E. Allen - 2010
Characterization of Resistors1.) Value
R = L
AAC and DC resistance
2.) LinearityDoes V = IR?Velocity saturation of carriers
3.) Power
P = VI = I2R4.) Current
Electromigration5.) Parasitics
060210-01
R
Cp
R
Cp2
Cp2
R
L
Area = A
Current
050217-02
L
Area = A
Current
060211-01
i
v
Linear Resistor
Velocity saturation
BreakdownVoltage
Metal050304-04
Lecture 070 – Resistors and Inductors (4/19/10) Page 070-4
CMOS Analog Circuit Design © P.E. Allen - 2010
MOS Resistors - Source/Drain Resistor
060214-02
p- substrate
FOX FOX
SiO2Metal
n- well
p+
Older LOCOS Technology
p+
n-well
p+
STIL
TungstenPlug
IntermediateOxide Layer
TungstenPlug
First Level Metal
STI
Diffusion:10-100 ohms/squareAbsolute accuracy = ±35%Relative accuracy=2% (5μm), 0.2% (50μm)Temperature coefficient = +1500 ppm/°CVoltage coefficient 200 ppm/V
Ion Implanted:500-2000 ohms/squareAbsolute accuracy = ±15%Relative accuracy=2% (5μm), 0.15% (50μm)Temperature coefficient = +400 ppm/°CVoltage coefficient 800 ppm/V
Comments:• Parasitic capacitance to substrate is voltage dependent.• Piezoresistance effects occur due to chip strain from mounting.
Lecture 070 – Resistors and Inductors (4/19/10) Page 070-5
CMOS Analog Circuit Design © P.E. Allen - 2010
Polysilicon Resistor
30-100 ohms/square (unshielded)100-500 ohms/square (shielded)Absolute accuracy = ±3 0%Relative accuracy = 2% (5 μm)Temperature coefficient = 500-1000 ppm/°CVoltage coefficient 100 ppm/VComments:• Used for fuzzes and laser trimming• Good general resistor with low parasitics
Lecture 070 – Resistors and Inductors (4/19/10) Page 070-6
CMOS Analog Circuit Design © P.E. Allen - 2010
N-well Resistor
p- substrate
FOX FOX
Metal
n- well
n+
FOX
n-well
n+ n+
L
TungstenPlug
IntermediateOxide Layer
TungstenPlug
First Level Metal
STI STI
p-substrate
L
060214-04 LOCOS Technology
1000-5000 ohms/squareAbsolute accuracy = ±40%Relative accuracy 5%Temperature coefficient = 4000 ppm/°CVoltage coefficient is large 8000 ppm/VComments:• Good when large values of resistance are needed.• Parasitics are large and resistance is voltage dependent• Could put a p+ diffusion into the well to form a pinched resistor
Lecture 070 – Resistors and Inductors (4/19/10) Page 070-7
CMOS Analog Circuit Design © P.E. Allen - 2010
Metal as a ResistorIllustration:
Resistance from A to B = Resistance of segments L1, L2, L3, L4, and L5 with somecorrection subtracted because of corners.Sheet resistance:
50-70 m / ± 30% for lower or middle levels of metal30-40 m / ± 15% for top level metal
Watch out for the current limit for metal resistors.Contact resistance varies from 5 to 10 .Tempco +4000 ppm/°CNeed to derate the current at higher temperatures:
IDC(Tj) = Dt·IDC(Tr)
Salicide
FirstLevelMetal
SecondLevel Metal
Inter-mediateOxideLayers
Tungsten Plug
Substrate
Tungsten Plug
A BL1
L2
L3
L4
L5
060214-05
Tj(°C) Tr(°C) Dt<85 85 1100 85 0.63110 85 0.48125 85 0.32150 85 0.18
Lecture 070 – Resistors and Inductors (4/19/10) Page 070-8
CMOS Analog Circuit Design © P.E. Allen - 2010
Thin Film ResistorsA high-quality resistor fabricated from a thin nickel-chromium alloy or a silicon-chromium mixture.Uppermost metal layer:
060612-01
Secondlevel fromtop metal
Inter-mediateOxideLayers
Top Metal
Protective Insulator Layer
Thin Film Resistor
L
W
Performance:Sheet resistivity is approximately 5-10 ohms/squareTemperature coefficients of less than 100 ppm/°CAbsolute tolerance of better than ±0.1% using laser trimmingSelectivity of the metal etch must be sufficient to ensure the integrity of the thin-filmresistor beneath the areas where metal is etched away.
Lecture 070 – Resistors and Inductors (4/19/10) Page 070-9
CMOS Analog Circuit Design © P.E. Allen - 2010
Resistor Layout Techniques
060219-01
Metal 1
Active area or PolysiliconContact
Diffusion or polysilicon resistor
L
W
Metal 1
Well diffusionContact
Well resistorL
WActive area
FOX FOXFOX
Metal
Active area (diffusion)
FOX FOX
Metal
Active area (diffusion) Well diffusion
Cut
Cut
Substrate Substrate
Metal
Active area (diffusion)
Substrate
TungstenPlug
LOCOSTechnology
DSMTechnology
Metal
Active area (diffusion)
Substrate
Tungsten Plug
Well diffusionSubstrate
Intermediate Oxide Intermediate Oxide
End structure calculations:
R1 = RcontNcont
+ Rsh(sil) Xc-r + 0.75·Lcon
W - 2·DWsil Rtotal =
1R1
+1R2
+ ···-1
(Lcon = width of the contact)
R2 = RcontNcont
+ Rsh(sil) Xc-r + Xcon +1.75·Lcon
W - 2· Wsil
Lecture 070 – Resistors and Inductors (4/19/10) Page 070-10
CMOS Analog Circuit Design © P.E. Allen - 2010
Extending the Length of ResistorsSnaked Resistors:
060220-01
L1 L2 L2L4 L4
L3
L4 L4 L4
Corner corrections:
0.51.45 1.25
Fig. 2.6-16B
Lecture 070 – Resistors and Inductors (4/19/10) Page 070-11
CMOS Analog Circuit Design © P.E. Allen - 2010
Extending the Length of ResistorsSeries Resistors:
Resistor Ending Influence:
050416-02
0.5 0.3 0.1
060220-02
L1W
Lecture 070 – Resistors and Inductors (4/19/10) Page 070-12
CMOS Analog Circuit Design © P.E. Allen - 2010
Process Bias Influence on ResistorsProcess bias is where the dimensions of the fabricated geometries are not the same as thelayout data base dimensions.Process biases introduce systematic errors.Consider the effect of over-etching-
Assume that etching introduces a process bias of 0.1μm. Two resistors designed tohave a ratio of 2:1 have equal lengths but the widths are different by a factor of two.
4μm
2μm
3.8μm
1.8μm
10μm 041020-01
The actual matching ratio due to the etching bias is,R2R1
= W 1W 2
= 4-0.22-0.2 =
3.81.8 = 2.11 5.6% error in matching
Use the replication principle to eliminate this error.
Lecture 070 – Resistors and Inductors (4/19/10) Page 070-13
CMOS Analog Circuit Design © P.E. Allen - 2010
Etch Rate Variations – Polysilicon ResistorsThe size of the area to be etched determines the etch rate. Smaller areas allow less
access to the etchant while larger areas allow more access to the etchant. This isillustrated below:
A B C A B C
Dum
my
Dum
my
SlowerEtch Rate
SlowerEtch Rate
SlowerEtch Rate
041025-04
The objective is to make A = B = C. In the left-hand case, B is larger due to the sloweretch rates on both sides of B. In the right-hand case, the dummy strips have caused theetch rates on both sides of A, B and C to be identical leading to better matching.It may be advisable to connect the dummy strips to ground or some other low impedancenode to avoid static electrical charge buildup.
Lecture 070 – Resistors and Inductors (4/19/10) Page 070-14
CMOS Analog Circuit Design © P.E. Allen - 2010
Diffusion Interaction – Diffused ResistorsProblem:
Consider three adjacent p+ diffusions into a n epitaxial region,
n-epi
p+ p+ p+A B C
041025-05
Contours ofconstant doping
Areas of diffusion interaction
If A, B, and C are resistors that are to be matched, we see that the effective concentrationof B is larger than A or C because of diffusion interaction. This would cause the Bresistor to be smaller even though the geometry is identical.
Solution: Place identical dummy resistors to the left of A and right of C. Connect thedummy resistors to a low impedance to prevent the formation of floating diffusions thatmight increase the sensitivity to latchup.
Lecture 070 – Resistors and Inductors (4/19/10) Page 070-15
CMOS Analog Circuit Design © P.E. Allen - 2010
Thermoelectric EffectsThe thermoelectric effect, also called the Seebeck effect, is a potential difference that isdeveloped between two dissimilar materials that are at different temperatures. Thepotential developed is given as,
V = S· Twhere,
S = Seebeck coefficient ( 0.4mV/°C)T = temperature difference between the two metals
Thus, a temperature difference between the contacts to a resistor and the resistor of 1°Ccan generate a voltage of 0.4mV causing problems in certain circuits (bandgap).
Two possible resistorlayouts with regardto the thermoelectriceffect:
+ +
- -
Cold
Hot
Thermoelectric potentials add Thermoelectric potentials cancel
+
-
+
-
Res
isto
r Se
gmen
t
Res
isto
r Se
gmen
t
Res
isto
r Se
gmen
t
Res
isto
r Se
gmen
t
+ + + +
Res
isto
r Se
gmen
t
Res
isto
r Se
gmen
t
Res
isto
r Se
gmen
t
Res
isto
r Se
gmen
t
041026-07- - - -
Lecture 070 – Resistors and Inductors (4/19/10) Page 070-16
CMOS Analog Circuit Design © P.E. Allen - 2010
High Sheet Resistivity Resistor LayoutHigh sheet resistivity resistors must use p+ or n+ in order to make contacts to metal.Thus, there is plenty of opportunity for the thermoelectric effect to cause problems if careis not taken. Below are three high sheet resistor layouts with differing thermoelectricperformance.
n diffusedresistor
n+ resistorhead
n+ resistorhead
Cold
Hot
Vertical misalignmentcauses resistor errors
Resistor layout thatminimizes thermoelectric effect and misalignment
041027-01Sensitive tothermoelectric
effects.
Sensitive tomisalignment.
Lecture 070 – Resistors and Inductors (4/19/10) Page 070-17
CMOS Analog Circuit Design © P.E. Allen - 2010
Future Technology Impact on ResistorsWhat will be the impact of scaling down in CMOS technology?• If the size of the resistor remains the same, there will be little impact.• If the size scales with the technology, the contacts and connections to the resistors will
have more influence on the resistor.
Lecture 070 – Resistors and Inductors (4/19/10) Page 070-18
CMOS Analog Circuit Design © P.E. Allen - 2010
MOS Passive RC Component Performance Summary
Component Type Range ofValues
AbsoluteAccuracy
RelativeAccuracy
TemperatureCoefficient
VoltageCoefficient
MOSFET gate Cap. 6-7 fF/μm2 10% 0.1% 20ppm/°C ±20ppm/V
Poly-Poly Capacitor 0.3-0.4 fF/μm2 20% 0.1% 25ppm/°C ±50ppm/V
Metal-Metal Capacitor 0.1-1fF/μm2 10% 0.6% ?? ??
Diffused Resistor 10-100 /sq. 35% 2% 1500ppm/°C 200ppm/V
Ion Implanted Resistor 0.5-2 k /sq. 15% 2% 400ppm/°C 800ppm/V
Poly Resistor 30-200 /sq. 30% 2% 1500ppm/°C 100ppm/V
n-well Resistor 1-10 k /sq. 40% 5% 8000ppm/°C 10kppm/V
Top Metal Resistor 30 m /sq. 15% 2% 4000ppm/°C ??
Lower Metal Resistor 70 m /sq. 28% 3% 4000ppm/°C ??
Lecture 070 – Resistors and Inductors (4/19/10) Page 070-19
CMOS Analog Circuit Design © P.E. Allen - 2010
INDUCTORSCharacterization of Inductors1.) Value of the inductor
Spiral inductor†:
L μ0n2r = 4 x10-7n2r 1.2x10-6n2r
2.) Quality factor, Q = L
R
3.) Self-resonant frequency: fself = 1LC
† H.M Greenhouse, “Design of Planar Rectangular Microelectronic Inductors,” IEEE Trans. Parts, Hybrids, and Packaging, vol. 10, no. 2, June 1974,
pp. 101-109.
060216-02
2r
n = 3
Lecture 070 – Resistors and Inductors (4/19/10) Page 070-20
CMOS Analog Circuit Design © P.E. Allen - 2010
IC InductorsWhat is the range of values for on-chip inductors?
������
������
0 10 20 30 40 50
12
10
8
6
4
2
0Frequency (GHz)
Indu
ctan
ce (
nH)
ωL = 50Ω
Inductor area is too large
Interconnect parasiticsare too large
Fig. 6-5
Consider an inductor used to resonate with 5pF at 1000MHz.
L = 1
4 2fo2C =
1(2 ·109)2·5x10-12
= 5nH
Note: Off-chip connections will result in inductance as well.
Lecture 070 – Resistors and Inductors (4/19/10) Page 070-21
CMOS Analog Circuit Design © P.E. Allen - 2010
Candidates for inductors in CMOS technology are:1.) Bond wires2.) Spiral inductors3.) Multi-level spiral4.) SolenoidBond wire Inductors:
β β
d Fig.6-6
• Function of the pad distance d and the bond angle • Typical value is 1nH/mm which gives 2nH to 5nH in typical packages• Series loss is 0.2 /mm for 1 mil diameter aluminum wire• Q 60 at 2 GHz
Lecture 070 – Resistors and Inductors (4/19/10) Page 070-22
CMOS Analog Circuit Design © P.E. Allen - 2010
Planar Spiral Inductors in CMOS TechnologyI
I
I
I
W
S
ID
Nturns = 2.5
�����SiO2
Silicon
Fig. 6-9
Typically: 3 < Nturns < 5 and S = Smin for the given currentSelect the OD, Nturns, and W so that ID allows sufficient magnetic flux to flowthrough the center.Loss Mechanisms:• Skin effect• Capacitive substrate losses• Eddy currents in the silicon
Lecture 070 – Resistors and Inductors (4/19/10) Page 070-23
CMOS Analog Circuit Design © P.E. Allen - 2010
Planar Spiral Inductors on a Lossy Substrate
W
S
D
D
Top Metal
Next LevelMetal
Top Metal
Next LevelMetal
Vias
Oxide
Oxide
Silicon Substrate
N turns
030828-01
• Spiral inductor is implemented using metal layers in CMOS technology• Topmost metal is preferred because of its lower resistivity• More than one metal layer can be connected together to reduce resistance or area• Accurate analysis of a spiral inductor requires complex electromagnetic simulation• Optimize the values of W, S, and N to get the desired L, a high Q, and a high self-
resonant frequency• Typical values are L = 1-8nH and Q = 3-6 at 2GHz
Lecture 070 – Resistors and Inductors (4/19/10) Page 070-24
CMOS Analog Circuit Design © P.E. Allen - 2010
Inductor ModelingModel:
L 37.5μ0N2a2
11D-14a Cox = W·L·ox
tox
Rs L
W (1-e-t/ ) R1 WLCsub
2
Cp = NW2L·ox
tox C1
2WLCsub
where
μ0 = 4 x10-7 H/m (vacuum permeability) = conductivity of the metal
a = distance from the center of the inductor to the middle of the windingsL = total length of the spiralt = thickness of the metal = skin depth given by = 2/Wμ0
Gsub(Csub) is a process-dependent parameter
Cp
L Rs
Cox2
Cox2
C1 C1R1 R1
030828-02
Lecture 070 – Resistors and Inductors (4/19/10) Page 070-25
CMOS Analog Circuit Design © P.E. Allen - 2010
Inductor Modeling – ContinuedDefinition of the previous components:
Rs is the low frequency resistive loss of a metal and the skin effectCp arises from the overlap of the cross-under with the rest of the spiral. The lateralcapacitance from turn-to-turn is also included.Cox is the capacitance between the spiral and the substrateR1 is the substrate loss due to eddy currentsC1 is capacitance of the substrate
Design specifications:L = desired inductance valueQ = quality factorfSR = self-resonant frequency. The resonant frequency of the LC tank represents theupper useful frequency limit of the inductor. Inductor operation frequency should belower than fSR, f < fSR.
ASITIC: A software tool for analysis and simulation of CMOS spiral inductors andtransformers.
http://formosa.eecs.berkeley.edu/~niknejad/asitic.html
Lecture 070 – Resistors and Inductors (4/19/10) Page 070-26
CMOS Analog Circuit Design © P.E. Allen - 2010
Guidelines for Designing CMOS Sprial Inductors†
D – Outer diameter:• As D increases, Q increases but the self-resonant frequency decreases• A good design generally has D < 200μm
W – Metal width:• Metal width should be as wide as possible• As W increases, Q increases and Rs decreases• However, as W becomes large, the skin effects are more significant, increasing Rs• A good value of W is 10μm < W < 20μm
S – Spacing between turns:• The spacing should be as small as possible• As S and L increase, the mutual inductance, M, decreases• Use minimum metal spacing allowed in the technology but make sure the inter-winding capacitance between turns is not significant
N – Number of turns:
† Jaime Aguilera, et. al., “A Guide for On-Chip Inductor Design in a Conventional CMOS Process for RF Applications,” Applied Microwave &
Wireless, pp. 56-65, Oct. 2001.
• Use a value that gives a layout convenient to work with other parts of the circuit
Lecture 070 – Resistors and Inductors (4/19/10) Page 070-27
CMOS Analog Circuit Design © P.E. Allen - 2010
Design ExampleA 2GHz LC tank is to be designed as a part of LC oscillator. The C value is given as 3pF.(a) Find value of L. (b) Design a spiral inductor with L value (± 5% range) from (a) usingASITIC. Optimize design parameters, W, S, D and N to get a high Q (Qmin = 5). Show L,Q, fSR value obtained from simulation. (c) Show the layout. (d) Give a lumped circuitmodel.Solution(a) LC tank oscillation frequency is given as 2GHz.
osc =1
LC , L =1
osc2 C
=1
(2 2 109 )2 (3 10-12)= 2.11 10-9
L = 2.11nH is desired.(b) L = 2.11nH(± 5%) is used as input parameter. Several design parameters are triedto get high Q and fSR values. Final design has
• Parameters: W = 19um, S = 1um, D = 200um, N = 3.5• Resulting inductor: L = 2.06nH, Q = 7.11, fSR = 9.99GHz @ 2GHz
This design is acceptable as Q > Qmin and f < fSR .
Lecture 070 – Resistors and Inductors (4/19/10) Page 070-28
CMOS Analog Circuit Design © P.E. Allen - 2010
Design Example-Continued(c.) ASITIC generates a layout automatically. It can besaved and imported to use in other tools such as Cadence,ADS and Sonnet.
(d) Analysis in ASITIC gives the following model.2.06nH 3.5
123fF 128fF
4.51-3
The model is usually not symmetrical and this can be used for differential configurationwhere none of the two ports are ac-grounded.
Lecture 070 – Resistors and Inductors (4/19/10) Page 070-29
CMOS Analog Circuit Design © P.E. Allen - 2010
Reduction of Capacitance to GroundComments concerning implementation:1.) Put a metal ground shield between the inductor and the silicon to reduce the
capacitance.• Should be patterned so flux goes through but electric field is grounded• Metal strips should be orthogonal to the spiral to avoid induced loop current• The resistance of the shield should be low to terminate the electric field
2.) Avoid contact resistance wherever possibleto keep the series resistance low.
3.) Use the metal with the lowest resistanceand farthest away from the substrate.
4.) Parallel metal strips if other metal levelsare available to reduce the resistance.
Example
Fig. 2.5-12
Lecture 070 – Resistors and Inductors (4/19/10) Page 070-30
CMOS Analog Circuit Design © P.E. Allen - 2010
Multi-Level Spiral InductorsUse of more than one level of metal to make the inductor.• Can get more inductance per area• Can increase the interwire capacitance so the different levels are often offset to get
minimum overlap.• Multi-level spiral inductors suffer from contact resistance (must have many parallel
contacts to reduce the contact resistance).• Metal especially designed for inductors is top level approximately 4μm thick.
Q = 5-6, fSR = 30-40GHz. Q = 10-11, fSR = 15-30GHz1. Good for high L in small area.
1 The skin effect and substrate loss appear to be the limiting factor at higher frequencies of self-resonance.
Lecture 070 – Resistors and Inductors (4/19/10) Page 070-31
CMOS Analog Circuit Design © P.E. Allen - 2010
Inductors - ContinuedSelf-resonance as a function of inductance. Outer dimension of inductors.
Lecture 070 – Resistors and Inductors (4/19/10) Page 070-32
CMOS Analog Circuit Design © P.E. Allen - 2010
TransformersTransformer structures are easily obtained using stacked inductors as shown below for a1:2 transformer.
Method of reducing theinter-winding capacitances.
4 turns 8 turns 3 turns
Measured 1:2 transformer voltage gains:
Lecture 070 – Resistors and Inductors (4/19/10) Page 070-33
CMOS Analog Circuit Design © P.E. Allen - 2010
Transformers – ContinuedA 1:4 transformer:Structure- Measured voltage gain-
(CL = 0, 50fF, 100fF, 500fF and 1pF.CL is the capacitive loading on thesecondary.)
Secondary
Lecture 070 – Resistors and Inductors (4/19/10) Page 070-34
CMOS Analog Circuit Design © P.E. Allen - 2010
Summary of InductorsScaling? To reduce the size of the inductor would require increasing the flux densitywhich is determined by the material the flux flows through. Since this material will notchange much with scaling, the inductor size will remain constant.Increase in the number of metal layers will offer more flexibility for inductor andtransformer implementation.Performance:• Inductors
Limited to nanohenrysVery low Q (3-5)Not variable
• TransformersReasonably easy to build and work well using stacked inductors
• MatchingNot much data exists publicly – probably not good
Lecture 070 – Resistors and Inductors (4/19/10) Page 070-35
CMOS Analog Circuit Design © P.E. Allen - 2010
SUMMARY• Types of resistors include diffused, well, polysilicon and metal• Resistors are characterized by:
- Value- Linearity- Power- Parasitics
• Technology effects on resistors includes:- Process bias- Diffusion interaction- Thermoelectric effects- Piezoresistive effects
• Inductors are made by horizontal metal spirals, typically in top metal• Inductors are characterized by:
- Value- Losses- Self-resonant frequency- Parasitics
• RF transformers are reasonably easy to build and work well using stacked inductors
Lecture 080 – Latchup and ESD (3/24/10) Page 080-1
CMOS Analog Circuit Design © P.E. Allen - 2010
LECTURE 080 – LATCHUP AND ESDLECTURE ORGANIZATION
Outline• Latchup• ESD• SummaryCMOS Analog Circuit Design, 2nd Edition ReferencePages 48-52 and new material
Lecture 080 – Latchup and ESD (3/24/10) Page 080-2
CMOS Analog Circuit Design © P.E. Allen - 2010
LATCHUPWhat is Latchup?• Latchup is the creation of a low impedance path
between the power supply rails.• Latchup is caused by the triggering of parasitic
bipolar structures within an integrated circuitwhen applying a current or voltage stimulus onan input, output, or I/O pin or by an over-voltageon the power supply pin.
• Temporary versus true latchup:A temporary or transient latchup occurs only while the pulse stimulus is connectedto the integrated circuit and returns to normal levels once the stimulus is removed.A true latchup remains after the stimulus has been removed and requires a powersupply shut down to remove the low impedance path between the power supply rails
070221-01
VDD
Excessive Current
Lecture 080 – Latchup and ESD (3/24/10) Page 080-3
CMOS Analog Circuit Design © P.E. Allen - 2010
Latchup TestingThe test for latchup defines how the designer must think about latchup.• For latchup prevention, you must consider where a current limited ( 100mA), 10ms
pulse is going to go when applied to a pad when the voltage compliance of the pad isconstrained to 50% above maximum power supply and to 2V below ground. (Highertemperatures, 85C°and 125°C, are more demanding, since VBE is lower.)
050727-06
VDD
100mA
10ms
• Latchup is sensitive to layout and is most often solved at the physical layout level.
Lecture 080 – Latchup and ESD (3/24/10) Page 080-4
CMOS Analog Circuit Design © P.E. Allen - 2010
How Does Latchup Occur?Latchup is the regenerative process that can occur in a pnpn structure (SCR-siliconcontrolled rectifier) formed by a parasitic npn and a parasitic pnp transistor.
p
p
n
n
Anode
Cathode
Anode
CathodevPNPN
iPNPN 1/Slope = LimitingResistance
Hold Current, IH
AvalancheBreakdown
VDD
Triggering by increasing V
DD
Sustainingvoltage, VS
050414-01
HoldVoltage, VH
To avoid latchupvPNPN < VS
vPNPN
iPNPN
Body diode(CMOS)
Important concepts:• To avoid latchup, vPNPN VS
• Once the pnpn structure has latched up, the large current required by the above i-vcharacteristics must be provided externally to sustain latchup
• To remove latchup, the current must be reduced below the holding current
Lecture 080 – Latchup and ESD (3/24/10) Page 080-5
CMOS Analog Circuit Design © P.E. Allen - 2010
Latchup TriggeringLatchup of the SCR can be triggered by two different mechanisms.1.) Allowing vPNPN to exceed the sustaining voltage, VS.
2.) Injection of current by a triggering device (gate triggered)
Injector
SCR
050414-03
SCR
Anode
Cathode
pnpGate
npnGate
VDDPad
GateCurrent
Injector
Pad
GateCurrent
Note: The gates mentioned above are SCR junction gates, not MOSFET gates.From the above considerations, latchup requires the following components:
1.) A four-layer structure (SCR) connected between VDD and ground.2.) An injector.3.) A stimulus.
Lecture 080 – Latchup and ESD (3/24/10) Page 080-6
CMOS Analog Circuit Design © P.E. Allen - 2010
Necessary Conditions for Latchup1.) The loop gain of the relevant BJT configuration must exceed unity.
+fbloop VDD ii βn βp io
050414-04
Loop gain:ioii p n
2.) A bias condition must exist such that both bipolars are turned on long enough forcurrent through the “SCR” to exceed its switching current.3.) The bias supply and associated circuits must be capable of supplying the current atleast equal to the switching current and at least equal to the holding current to maintainthe latched state.
Lecture 080 – Latchup and ESD (3/24/10) Page 080-7
CMOS Analog Circuit Design © P.E. Allen - 2010
Latchup Trigger ModesCurrent mode (Positive Injection Example):
When a current is applied to a pad, it can flow throughan injector and trigger latchup of an SCR formed fromparasitic bipolar transistors.
SCR gate current injection parasitic can occur in p-well or n-well technology.
Voltage mode:When the power supply is increased
above the nominal value, the SCR formed fromparasitic bipolar transistors can be triggered.
050414-05SCR
Pad
GateCurrent
Injector
VDD
SCR
VAnode
VDD < VAnode <Vabs,max
050414-06
VDD
Lecture 080 – Latchup and ESD (3/24/10) Page 080-8
CMOS Analog Circuit Design © P.E. Allen - 2010
How does Latchup Occur in an IC?Consider an output driver in CMOS technology:
050416-02p+ p p- n n+ Poly 1Oxide Poly 2 Nitride Salicide Metal
VDD
vOUTvIN
vOUTvIN VDD
n-
Assume that the output is connected to a pad.
Lecture 080 – Latchup and ESD (3/24/10) Page 080-9
CMOS Analog Circuit Design © P.E. Allen - 2010
Parasitic Bipolar Transistors for the n-well CMOS Inverter
050416-03p+ p p- n n+ Poly 1Oxide Poly 2 Nitride Salicide Metal
vOUTvIN VDD
n-
LT1
LT2
VT1VT2Rs1
Rs3 Rs4
Rw1Rw2
Rw3
Rw4Rs2
Parasitic components:Lateral BJTs LT1 and LT2Vertical BJTs VT1 and VT2Bulk substrate resistances Rs1, Rs2, Rs3, and Rs4
Bulk well resistances Rw1, Rw2, Rw3, and Rw4
Lecture 080 – Latchup and ESD (3/24/10) Page 080-10
CMOS Analog Circuit Design © P.E. Allen - 2010
Current Source InjectionApply a voltage compliant current source to the output pad (vOUT > VDD).
050416-04p+ p p- n n+ Poly 1Oxide Poly 2 Nitride Salicide Metal
vOUTvIN VDD
n-
LT1
LT2
VT1VT2Rs Rw
Voltage CompliantCurrent Source
Loop gain:ioutiin
= P1Rw
Rw+r P1 N1Rs
Rs+r N1
= P1 N1Rw
Rw+P1VtIP1
Rs
Rs+N1VtIP2
Lecture 080 – Latchup and ESD (3/24/10) Page 080-11
CMOS Analog Circuit Design © P.E. Allen - 2010
Current Sink InjectionApply a voltage compliant current sink to the output pad (vOUT < 0).
050416-07p+ p p- n n+ Poly 1Oxide Poly 2 Nitride Salicide Metal
vOUTvIN VDD
n-
LT1
LT2
VT1VT2Rs Rw
Rw3
Voltage CompliantCurrent Sink
Loop gain:ioutiin
= P1Rw
Rw+r P1 N1Rs
Rs+r N1
= P1 N1Rw
Rw+P1VtIP1
Rs
Rs+N1VtIP2
Lecture 080 – Latchup and ESD (3/24/10) Page 080-12
CMOS Analog Circuit Design © P.E. Allen - 2010
Latchup from a Transmission GateThe classical push-pull output stage is only one of the many configurations that can leadto latchup. Here is another configuration:
VDD
VDD
Pad
InternalCore
Circuits
Clk
Driver
TransmissionGate
Internal CoreCircuitry
VDDClk
Transmission Gate Clock Driver050416-09 p+ p p- n n+ Poly 1Oxide Poly 2 Nitride Salicide Metaln-
Pad
Injectors Receiver
The two bold solid bipolar transistors in the transmission gate act as injectors to the npn-pnp parasitic bipolars of the clock driver and cause these transistors to latchup. Theinjector sites are the diffusions connected to the pad.
Lecture 080 – Latchup and ESD (3/24/10) Page 080-13
CMOS Analog Circuit Design © P.E. Allen - 2010
The Influence of Shallow Trench Isolation on LatchupAs seen below, the STI causes the parasitic betas to be smaller.
p+ p p- MetalSaliciden- n n+Oxide
n-well p-well
Poly
ShallowTrench
Isolation
SidewallSpacers Polycide
Top Metal
SecondLevel Metal
FirstLevelMetal
Tungsten Plugs
Protective Insulator Layer
Substrate
Inter-mediateOxideLayers
060406-01
Metal Vias Metal Via
p+
Polycide
TungstenPlugs
Gate Ox
Salicide Salicide SalicideSalicide
TungstenPlugs
TungstenPlug
n+ n+p+ p+
ShallowTrench
Isolation
ShallowTrench
Isolation
p+n+
VDD GRD
GRD
OUTPUT
Lecture 080 – Latchup and ESD (3/24/10) Page 080-14
CMOS Analog Circuit Design © P.E. Allen - 2010
Preventing Latch-Up1.) Keep the source/drain of the MOS device not in the well as far away from the well as
possible. This will lower the value of the BJT betas.2.) Reduce the values of RN- and RP-. This requires more current before latch-up can
occur.3.) Surround the transistors with guard rings. Guard rings reduce transistor betas and
divert collector current from the base of SCR transistors.
Figure 190-10
p-welln- substrate
FOX
n+ guard barsn-channel transistor
p+ guard barsp-channel transistor
VDD VSS
FOX FOX FOXFOXFOXFOX
Lecture 080 – Latchup and ESD (3/24/10) Page 080-15
CMOS Analog Circuit Design © P.E. Allen - 2010
What are Guard Rings?Guard rings are used to collect carriers flowing in the silicon. They can be designed tocollect either majority or minority carriers.
Guard rings in n-material: Guard rings in p-material:
Also, the increased doping level of the n+ (p+)guard ring in n (p) material decreases theresistance in the area of the guard ring.
051201-01p+ p p- n n+n-
p+ guard ringCollects majority carriers VDD
n+ guard ringCollects minority carriers
Decreased bulkresistance
051201-02p p- n n+n-
VDD
p+ guard ringCollects minority carriers
n+ guard ringCollects majority carriers
p+
Decreased bulkresistance
Lecture 080 – Latchup and ESD (3/24/10) Page 080-16
CMOS Analog Circuit Design © P.E. Allen - 2010
Example of Reducing the Sensitivity to LatchupStart with an inverter with no attempt to minimize latchup and minimum spacing betweenthe NMOS and PMOS transistors.
050427-03p+ p p- n n+ Poly 1Oxide Poly 2 Nitride Salicide Metal
vOUT
vIN
VDD
n-
Rs
Rw
Note minimum separation
Lecture 080 – Latchup and ESD (3/24/10) Page 080-17
CMOS Analog Circuit Design © P.E. Allen - 2010
Example of Reducing the Sensitivity to Latchup by using Guard RingsNext, place guard rings around the NMOS and PMOS transistors (both I/O and logic) tocollect most of the parasitic NPN and PNP currents locally and prevent turn-on ofadjacent devices.
050427-04p+ p p- n n+ Poly 1Oxide Poly 2 Nitride Salicide Metal
vOUT
vIN
VDD
n-
Rs
Rw
Note increased separation
VDDp+ guardring
n+ guardring
• The guard rings also help to reduce the effective well and substrate resistance.• The guard rings reduce the lateral betaKey: The guard rings should act like collectors
Lecture 080 – Latchup and ESD (3/24/10) Page 080-18
CMOS Analog Circuit Design © P.E. Allen - 2010
Example of Reducing the Sensitivity to Latchup by using Butted ContactsFinally, use butted source contacts to further reduce the well resistance and reduce thesubstrate resistance.
050427-05p+ p p- n n+ Poly 1Oxide Poly 2 Nitride Salicide Metal
vOUT
vIN
VDD
n-
Rs
VDDp+ guardring
n+ guardring
Rw
Lecture 080 – Latchup and ESD (3/24/10) Page 080-19
CMOS Analog Circuit Design © P.E. Allen - 2010
Guidelines for Guard Rings• Guard rings should be low resistance paths.• Guard rings should utilize continuous diffusion areas.• More than one transistor of the same type can be placed inside the same well inside the
same guard ring as long as the design rules for spacing are followed.• Only 2 guard rings are required between adjacent PMOS and NMOS transistors• The well taps and/or the guard ring should be laid out as close to the MOSFET source
as possible.• I/O output NMOSFET should use butted composite for source to bulk connections
when the source is electrically connected to the p-well tap. If separate well tap andsource connections are required due to substrate noise injection problems, minimize thesource-well tap spacing. This will minimize latch up and early snapback of the outputMOSFETs with the drain diffusion tied directly (in metal) to the bond pad.
Lecture 080 – Latchup and ESD (3/24/10) Page 080-20
CMOS Analog Circuit Design © P.E. Allen - 2010
ESD IN CMOS TECHNOLOGYWhat is Electrostatic Discharge?Triboelectric charging happens when 2 materials come in contact and then are separated.
An ESD event occurs when the stored charge is discharged.
Lecture 080 – Latchup and ESD (3/24/10) Page 080-21
CMOS Analog Circuit Design © P.E. Allen - 2010
ESD and Integrated Circuits• ICs consist of components that are very sensitive to excess current and voltage above
the nominal power supply.• Any path to the outside world is susceptible to ESD• ESD damage can occur at any point in the IC assembly and packaging, the packaged
part handling or the system assembly process.• Note that power is normally not on during an ESD event
050727-01
Lecture 080 – Latchup and ESD (3/24/10) Page 080-22
CMOS Analog Circuit Design © P.E. Allen - 2010
ESD Models and Standards• Standard tests give an indication of the ICs robustness to withstand ESD stress.• Increased robustness:
- Reduces field failures due to ESD- Demanded by customers
• Simple ESD model:- VSE = Charging Voltage
- Key parameters of the model:o Maximum current flowo Time constant or how fast the ESD event
dischargeso Risetime of the pulse
070210-01
Risetime
00 t
Imax
Time constant (τ)≈ RLimC
VSEi(t)+
− C
RLimt=0
Current
IC
Lecture 080 – Latchup and ESD (3/24/10) Page 080-23
CMOS Analog Circuit Design © P.E. Allen - 2010
ESD Models• Human body model (HBM): Representative of an ESD
event between a human and an electronic component.
• Machine model (MM): Simulates the ESD event when acharged “machine” discharges through a component.
050423-02
040929-03• Charge device model (CDM): Simulates the
ESD event when the component is chargedand then discharges through a pin. Thesubstrate of the chip becomes charged anddischarges through a pin.
Lecture 080 – Latchup and ESD (3/24/10) Page 080-24
CMOS Analog Circuit Design © P.E. Allen - 2010
ESD Influence on ComponentsAn ESD event typically creates very high values of current (1-10A) for very short periodsof time (150 ns) with very rapid rise times (1ns).Therefore, components experience extremely high values of current with very little powerdissipation or thermal effects.Resistors – become nonlinear at high currents and will breakdownCapacitors – become shorts and can breakdown from overvoltage (pad to substrate)Diodes – current no longer flows uniformly (the connections to the diodes represent theohmic resistance limit)Transistors – ESD event is only a two terminal event, the third terminal is influenced byparasitics and many of the transistor parameters are poorly controlled.
• MOSFETs – the parasitic bipolar experiences snapback under an ESD event• BJTs – will experience snapback under ESD event
Lecture 080 – Latchup and ESD (3/24/10) Page 080-25
CMOS Analog Circuit Design © P.E. Allen - 2010
Objective of ESD Protection• There must be a safe low impedance path between every combination of pins to sink the
ESD current (i.e. 1.5A for 2kV HBM)• The ESD device should clamp the voltage below the breakdown voltage of the internal
circuitry• The metal busses must be designed to survive 1.5A (fast transient) without building up
excessive voltage drop• ESD current must be steered away from sensitive
circuits
• ESD protection will require area on the chip (bussesand timing components)
VDD
VSS
ESDPowerRail
Clamp
SensitiveCircuits
LimitingResistor
041008-01
Lecture 080 – Latchup and ESD (3/24/10) Page 080-26
CMOS Analog Circuit Design © P.E. Allen - 2010
ESD Protection Architecture
InternalCircuits
InputPad
OutputPad
LocalClamp
LocalClamp
LocalClamp
LocalClamp
VDD
VSS
ESDPowerRail
Clamp
040929-06
Rail based protection
Local clamp based protection
Local clamps – Conducts ESD current without loading the internal (core) circuitsESD power rail clamps – Conducts a large amount of current with a small voltage dropESD Events:
Pad-to-rail (uses local clamps only)Pad-to-pad (uses either local or local and ESD power rail clamps)
Lecture 080 – Latchup and ESD (3/24/10) Page 080-27
CMOS Analog Circuit Design © P.E. Allen - 2010
Example of an ESD Breakdown ClampA normal MOSFET that uses the parasitic lateral BJT to achieve a snapback clamp.Normally, the MOSFET has the gate shorted to the source so that drain current is zero.
G
n+ n+
ShallowTrench
Isolation
ShallowTrench
Isolation
p-substrate
S D
Rsub
B
vDS
iDS+-iDS
vDS
Second Breakdown
Snapback Region
AvalancheRegion
Saturation Region
Linear Region
First Breakdown
Device destruction
Vt1Vt2
Negative TC
Positive TC
041217-04
B
p+iC
iSub
Issues:• If the drain voltage becomes too large, the gate oxide may breakdown• If the transistor has multiple fingers, the layout should ensure that the current is
distributed evenly.
Lecture 080 – Latchup and ESD (3/24/10) Page 080-28
CMOS Analog Circuit Design © P.E. Allen - 2010
Example of a Non-Breakdown ClampNMOS Clamp:
Operation: • Normally, the input to the driver is
high, the output low and the NMOS clamp off • For a positive ESD event, the voltage increases across R causing the inverter to turn on
the NMOS clamp providing a low impedance path between the rails • Cannot be used for pads that go above power supply or are active when powered up • For power supply turn-on, the circuit should not trigger (C holds the clamp off during
turn-on)Also, forward biased diodes serve as non-breakdown clamps.
R
C
VDD
VSS
NMOSClamp
Speed-upCapacitor
TriggerCircuit
InverterDriver
041001-03
Lecture 080 – Latchup and ESD (3/24/10) Page 080-29
CMOS Analog Circuit Design © P.E. Allen - 2010
IV Characteristics of Good ESD ProtectionGoal: Sink the ESD current and clamp the voltage.
070221-02
ITarget
ITarget
Case 1 - Okay
ITargetESD Clamp
ProtectedDevice
Case 2 - Protected Device Fails
Case 3 - Okay
ITarget
Case 4 - Protected Device Fails
ESD Clamp
ProtectedDevice
ESD Clamp
ProtectedDevice
ESD Clamp
ProtectedDevice
Voltage
Cur
rent
Voltage
Cur
rent
Voltage
Cur
rent
Voltage
Cur
rent
ESDClamp
ProtectedDevice
Lecture 080 – Latchup and ESD (3/24/10) Page 080-30
CMOS Analog Circuit Design © P.E. Allen - 2010
Comparison Between the NMOS Clamp and the Snapback ClampIncreasing the width of theNMOS clamp will reduce the clamp voltage.
Note that the NMOS clamp does not normally exceed the absolute maximum voltage.NMOS clamps should be used with EPROMs to avoid reprogramming during an ESDevent.
Voltage
Curr
ent
Target
Iesd
Holding
voltage
Trigger
voltage
Increasing
snapback W
Vc Vc Vc
NMOS Vt
IncreasingNMOS W
Ma
x o
pe
ra
tin
g v
olt
ag
e
Lecture 080 – Latchup and ESD (3/24/10) Page 080-31
CMOS Analog Circuit Design © P.E. Allen - 2010
ESD PracticeGeneral Guidelines: • Understand the current flow requirements for an ESD event • Make sure the current flows where desired and is uniformly distributed • Series resistance is used to limit the current in the protected devices • Minimize the resistance in protecting devices • Use distributed (smaller) active clamps to minimize the effect of bus resistance • Understand the influence of packaging on ESD • Use guard rings to prevent latchupCheck list: • Check the ESD path between every pair of pads • Check for ESD protection between the pad and internal circuitry • Check for low bus resistance
- Current: Minimum metal for ESD 40 x Electromigration limit- Voltage: 1.5A in a metal bus of 0.03 /square of 1000μm long and 30μm wide gives
a voltage drop of 1.5V • Check for sufficient contacts and vias in the ESD path (uniform current distribution)
Lecture 080 – Latchup and ESD (3/24/10) Page 080-32
CMOS Analog Circuit Design © P.E. Allen - 2010
SUMMARY• Latchup is the creation of a low impedance path between the power supply rails
resulting in excessive current.• The conditions for latchup are:
- A four-layer, pnpn structure connected between power supply rails- An injector (any diffusion connected to a pad)- A stimulus
• Latchup is prevented by:- Keeping the NMOS and PMOS transistors separated- Reducing the well resistance with appropriate well ties- Surrounding the transistors with guard rings
• ESD is caused by triobelectric charging which discharges through the IC when thepower is off
• The current produced by an ESD event must be controlled – uniform current flow,minimum voltage drop, and must not flow through sensitive circuitry
• An ESD event turns on very quickly (<1ns), has a high peak current (1A), and lasts forapproximately 100 ns.
• ESD clamps consist of breakdown clamps (snapback) and non-breakdown clamps.
Lecture 090 – Large Signal MOSFET Model (3/24/10) Page 090-1
CMOS Analog Circuit Design © P.E. Allen - 2010
LECTURE 090 – LARGE SIGNAL MOSFET MODELLECTURE ORGANIZATION
Outline• Introduction to modeling• Operation of the MOS transistor• Simple large signal model (SAH model)• Subthreshold model• Short channel, strong inversion model• SummaryCMOS Analog Circuit Design, 2nd Edition ReferencePages 73-78 and 97-99
Lecture 090 – Large Signal MOSFET Model (3/24/10) Page 090-2
CMOS Analog Circuit Design © P.E. Allen - 2010
INTRODUCTION TO MODELINGModels Suitable for Understanding Analog DesignThe model required for analog design with CMOS technology is one that leads tounderstanding and insight as distinguished from accuracy.
TechnologyUnderstanding
and Usage
Thinking ModelSimple,
±10% to ±50% accuracy
Design Decisions-"What can I change to
accomplish ....?"
Computer Simulation
Expectations"Ballpark"
Extraction of SimpleModel Parameters
from Computer Models
Comparison ofsimulation with
expectations
Refined andoptimized
design
Updating Model Updating Technology
Fig.3.0-02
This lecture is devoted to the simple model suitable for design not using simulation.
Lecture 090 – Large Signal MOSFET Model (3/24/10) Page 090-3
CMOS Analog Circuit Design © P.E. Allen - 2010
Categorization of Electrical Models
Time Dependence
Time Independent Time Dependent
Linearity
Linear Small-signal, midband Rin, Av, Rout
(.TF)
Small-signal frequencyresponse-poles and zeros(.AC)
Nonlinear DC operating pointiD = f(vD,vG,vS,vB)
(.OP)
Large-signal transientresponse - Slew rate
(.TRAN)
Based on the simulation capabilities of SPICE.
Lecture 090 – Large Signal MOSFET Model (3/24/10) Page 090-4
CMOS Analog Circuit Design © P.E. Allen - 2010
OPERATION OF THE MOS TRANSISTORFormation of the Channel for an Enhancement MOS Transistor
���Polysilicon
p+
p- substrate
Fig.3.1-02
VB = 0 VG =VTVS = 0 VD = 0
p+
p- substrate
VB = 0 VG < VTVS = 0 VD = 0
������Polysilicon
p+
p- substrate
VB = 0 VG >VTVS = 0 VD = 0
Subthreshold (VG<VT)
Threshold (VG=VT)
Strong Threshold (VG>VT)
Inverted Region
Inverted Region
���Polysilicon
����n+
����
������n+ n+��������
�� �������n+ n+
������n+
Depletion Region
Lecture 090 – Large Signal MOSFET Model (3/24/10) Page 090-5
CMOS Analog Circuit Design © P.E. Allen - 2010
Transconductance Characteristics of an Enhancement NMOSFET when VDS = 0.1V
���Polysilicon
p+
p- substrate
Fig.3.1-03
VB = 0 VG = 2VTVS = 0 VD = 0.1V
p+
p- substrate
VB = 0 vG =VTVS = 0 VD = 0.1V
������Polysilicon
p+
p- substrate
VB = 0 VG = 3VTVS = 0 VD = 0.1V
VGS≤VT:
Inverted Region
Inverted Region
���PolysiliconiD
iD
vGSVT 2VT 3VT0
0
iD
iD
vGSVT 2VT 3VT0
0
iD
vGSVT 2VT 3VT0
0
VGS=2VT:
VGS=3VT:
����
������n+ n+
����
��������������
�� �������n+ n+
Depletion Region
n+ n+
Lecture 090 – Large Signal MOSFET Model (3/24/10) Page 090-6
CMOS Analog Circuit Design © P.E. Allen - 2010
Output Characteristics of the Enhancement NMOS Transistor for VGS = 2VT
Fig.3.1-04
VB = 0 VG = 2VTVS = 0 VD = 0.5VT
vG =2VT VD = 0V
VB = 0 VS = 0 VD =VT
VDS=0:iD
vDSVT0.5VT0
0
VDS=0.5VT:
VDS=VT:VG = 2VT
���Polysilicon
p+
p- substrate
VB = 0 VS = 0
Inverted Region
iD
����
��������������
iD
vDSVT0.5VT0
0
iD
vDSVT0.5VT0
0
���Polysilicon
p+
p- substrate Channel current
iD
����
������
����������������
������Polysilicon
p+
p- substrateA depletion region
forms between the drain and channel
iD
�� �����������n+
n+ n+
n+
n+ n+
VGS = 2VT
VGS = 2VT
VGS = 2VT
Lecture 090 – Large Signal MOSFET Model (3/24/10) Page 090-7
CMOS Analog Circuit Design © P.E. Allen - 2010
Output Characteristics of the Enhanced NMOS when vDS = 2VT
Fig.3.1-05
VB = 0 VG = 2VTVS = 0 VD = 2VT
vG =VT
VB = 0 VS = 0
VGS=VT:iD
vDSVT 2VT0
0
VGS=2VT:
VGS=3VT:VG = 3VT
���Polysilicon
p+
p- substrate
VB = 0 VS = 0iD
����
������
������Polysilicon
p+
p- substrate
iD
�� �����������n+n+
n+ n+
VD = 2VT
VD = 2VT
iD
vDS0
0
iD
vDS0
0
3VT
VT 2VT 3VT
VT 2VT 3VT
���Polysilicon
p+
p- substrate
iD
����
������
���������������� n+n+
Further increase in VG will cause the FET to become active
VGS =2VT
VGS =3VT
VGS =VT
Lecture 090 – Large Signal MOSFET Model (3/24/10) Page 090-8
CMOS Analog Circuit Design © P.E. Allen - 2010
Output Characteristics of an Enhancement NMOS Transistor
SPICE Input File:
Output Characteristics for NMOSM1 6 1 0 0 MOS1 w=5u l=1.0uVGS1 1 0 1.0M2 6 2 0 0 MOS1 w=5u l=1.0uVGS2 2 0 1.5M3 6 3 0 0 MOS1 w=5u l=1.0uVGS3 3 0 2.0M4 6 4 0 0 MOS1 w=5u l=1.0uVGS4 4 0 2.5
M5 6 5 0 0 MOS1 w=5u l=1.0uVGS5 5 0 3.0VDS 6 0 5.model mos1 nmos (vto=0.7 kp=110u+gamma=0.4 +lambda=.04 phi=.7).dc vds 0 5 .2.print dc ID(M1), ID(M2), ID(M3), ID(M4),ID(M5).end
0 1 2 3 4 5vDS (Volts)
0
500
1000
1500
2000
i D(μ
A)
VGS = 3.0
VGS = 2.5
VGS = 2.0
VGS = 1.5
VGS = 1.0
Fig. 3.1-6
Lecture 090 – Large Signal MOSFET Model (3/24/10) Page 090-9
CMOS Analog Circuit Design © P.E. Allen - 2010
Transconductance Characteristics of an Enhancement NMOS Transistor
SPICE Input File:
Transconductance Characteristics for NMOSM1 1 6 0 0 MOS1 w=5u l=1.0uVDS1 1 0 1.0M2 2 6 0 0 MOS1 w=5u l=1.0uVDS2 2 0 2.0M3 3 6 0 0 MOS1 w=5u l=1.0uVDS3 3 0 3.0M4 4 6 0 0 MOS1 w=5u l=1.0uVDS4 4 0 4.0
M5 5 6 0 0 MOS1 w=5u l=1.0uVDS5 5 0 5.0VGS 6 0 5.model mos1 nmos (vto=0.7 kp=110u+gamma=0.4 lambda=.04 phi=.7).dc vgs 0 5 .2.print dc ID(M1), ID(M2), ID(M3), ID(M4),ID(M5).probe.end
0
1000
2000
3000
4000
5000
6000
0 1 2 3 4 5vGS (Volts)
i D(μ
A)
VDS = 5V
VDS = 1V
VDS = 2V
VDS = 4VVDS = 3V
Fig. 3.1-7
Lecture 090 – Large Signal MOSFET Model (3/24/10) Page 090-10
CMOS Analog Circuit Design © P.E. Allen - 2010
SIMPLE LARGE SIGNAL MODEL (SAH MODEL)Large Signal Model Derivation
1.) Let the charge per unit area in the channelinversion layer be
QI(y) = -Cox[vGS-v(y)-VT] (coul./cm2)
2.) Define sheet conductivity of the inversionlayer per square as
S = μoQI(y) cm2
v·scoulombs
cm2 = ampsvolt =
1/sq.
3.) Ohm's Law for current in a sheet is
JS = iDW = - SEy = - S
dvdy dv =
-iDSW dy =
-iDdyμoQI(y)W iD dy = -WμoQI(y)dv
4.) Integrating along the channel for 0 to L gives
0
L
iDdy = - 0
vDS
WμoQI(y)dv = 0
vDS
WμoCox[vGS-v(y)-VT] dv
5.) Evaluating the limits gives
iD = WμoCox
L (vGS-VT)v(y) -v2(y)
2vDS
0 iD =
WμoCoxL (vGS-VT)vDS -
vDS2
2
������n+ n+
yv(y)
dy
0 Ly y+dyp-Source Drain
+
--
+vGSvDiD
Fig.110-03
Lecture 090 – Large Signal MOSFET Model (3/24/10) Page 090-11
CMOS Analog Circuit Design © P.E. Allen - 2010
Saturation Voltage - VDS(sat)Interpretation of the largesignal model:
The saturation voltage forMOSFETs is the value of drain-source voltage atthe peak of the inverted parabolas.
diDdvDS
= μoCoxW
L [(vGS-VT) - vDS] = 0
vDS(sat) = vGS - VT
Useful definitions:μoCoxW
L = K’W
L =
Increasingvalues of
Saturation RegionActive Region
vDS
iDvDS = vGS-VT
vGS
Fig. 110-04
vDS
vGSVT
v DS = v GS
- VT
Cutoff Saturation Active
00 Fig. 3.2-4
Lecture 090 – Large Signal MOSFET Model (3/24/10) Page 090-12
CMOS Analog Circuit Design © P.E. Allen - 2010
The Simple Large Signal MOSFET ModelRegions of Operation of the MOS Transistor:1.) Cutoff Region:
vGS - VT < 0
iD = 0
(Ignores subthreshold currents) 2.) Active Region
0 < vDS < vGS - VT
iD = μoCoxW
2L 2(vGS - VT) - vDS vDS
3.) Saturation Region0 < vGS - VT < vDS
iD = μoCoxW
2L vGS - VT2
Output Characteristics of the MOSFET:
0.75
1.0
0.5
0.25
00 0.5 1.0 1.5 2.0 2.5
= 0
= 0.5
= 0.70
= 0.86
= 1.0
Channel modulation effects
ActiveRegion Saturation Region
Cutoff Region
iD/ID0vDS = vGS-VT
vDSVGS0-VT
vGS-VTVGS0-VT
vGS-VTVGS0-VTvGS-VT
VGS0-VTvGS-VT
VGS0-VTvGS-VT
VGS0-VT
Fig. 110-05
Lecture 090 – Large Signal MOSFET Model (3/24/10) Page 090-13
CMOS Analog Circuit Design © P.E. Allen - 2010
Illustration of the Need to Account for the Influence of vDS on the Simple Sah ModelCompare the Simple Sah model to SPICE level 2:
0 0.2 0.4 0.6 0.8 1
25μA
20μA
15μA
10μA
5μA
0μA
K' = 44.8μA/Vk = 0, v (sat) = 1.0V
2
DS
K' = 29.6μA/Vk = 0, v (sat) = 1.0V
2
DS
K' = 44.8μA/Vk=0.5, v (sat) = 1.0V
2
DS
SPICE Level 2
vDS (volts)
i D
VGS = 2.0V, W/L = 100μm/100μm, and no mobility effects.
Lecture 090 – Large Signal MOSFET Model (3/24/10) Page 090-14
CMOS Analog Circuit Design © P.E. Allen - 2010
Modification of the Previous Model to Include the Effects of vDS on VTFrom the previous derivation:
0
L
iD dy = - 0
vDS
WμoQI(y)dv = 0
vDS
WμoCox[vGS - v(y) -VT]dv
Assume that the threshold voltage varies across the channel in the following way:VT(y) = VT + kv(y)
where VT is the value of VT the at the source end of the channel and k is a constant.Integrating the above gives,
iD = WμoCox
L (vGS-VT)v(y) - (1+k)v2(y)
2
vDS
0
or
iD = WμoCox
L (vGS-VT)vDS - (1+k)v2DS
2
To find vDS(sat), set the diD/dvDS equal to zero and solve for vDS = vDS(sat),
vDS(sat) = vGS - VT
1 + k
Therefore, in the saturation region, the drain current is
iD = WμoCox
2(1+k)L (vGS - VT)2
For k = 0.5 and K’ = 44.8μA/V2, excellent correlation is achieved with SPICE 2
Lecture 090 – Large Signal MOSFET Model (3/24/10) Page 090-15
CMOS Analog Circuit Design © P.E. Allen - 2010
Influence of vDS on the Output Characteristics
Channel modulation effect:As the value of vDS increases, theeffective L decreases causing thecurrent to increase.
Illustration:
Note that Leff = L - Xd
Therefore the model in saturationbecomes,
iD = K’W2Leff (vGS-VT)2
diDdvDS
= - K’W2Leff2
(vGS - VT)2 dLeffdvDS
= iD
Leff dXddvDS
iD
Therefore, a good approximation to the influence of vDS on iD is
iD iD( = 0) + diD
dvDS vDS = iD( = 0)(1 + vDS) =
K’W2L (vGS-VT)2(1+ vDS)
���Polysilicon
p+
p- substrateFig110-06
VG > VT VD > VDS(sat)
��������������n+n+
DepletionRegion
Xd
B S
Leff
Lecture 090 – Large Signal MOSFET Model (3/24/10) Page 090-16
CMOS Analog Circuit Design © P.E. Allen - 2010
Channel Length Modulation Parameter,
Assume the MOS is transistor is saturated-
iD = μCoxW
2L (vGS - VT)2(1 + vDS)
Define iD(0) = iD when vDS = 0V.
iD(0) = μCoxW
2L (vGS- VT)2
Now, iD = iD(0)[1 + vDS] = iD(0) + iD(0) vDS
Matching with y = mx + b gives the value of
vDS
iD
-1
iD1(0)iD2(0)iD3(0 VGS3
VGS2
VGS1
)
Lecture 090 – Large Signal MOSFET Model (3/24/10) Page 090-17
CMOS Analog Circuit Design © P.E. Allen - 2010
Influence of Channel Length on
Note that the value of varies with channel length, L. The data below is from a 0.25μmCMOS technology.
0
0.1
0.2
0.3
0.4
0.5
0.6
0 0.5 1 1.5 2 2.5Cha
nnel
Len
gth
Mod
ulat
ion
(V-1
)
Channel Length (microns)
PMOS
NMOS
Fig.130-6
Most analog designers stay away from minimum channel length to get better gains andmatching at the sacrifice of speed.
Lecture 090 – Large Signal MOSFET Model (3/24/10) Page 090-18
CMOS Analog Circuit Design © P.E. Allen - 2010
Influence of the Bulk Voltage on the Large Signal MOSFET ModelThe components of the threshold voltageare:VT = Gate-bulk work function ( MS)
+ voltage to change the surface potential (-2 F)
+ voltage to offset the channel-bulk depletion charge (-Qb/Cox)
+ voltage to compensate the undesired interface charge (-Qss/Cox)
We know thatQb = |2 F| + |vBS|
Therefore, as the bulk becomes morereverse biased with respect to thesource, the threshold voltage mustincrease to offset the increased channel-bulk depletion charge.
060613-02
VD > 0
VSB0 = 0:
VSB1 > 0:
VSB2 >VSB1:
Polysilicon
p+
p- substrate
iD = 0
Polysilicon
p+
p- substrate
iD
n+n+
n+ n+
VD > 0
VD > 0
p+
p- substrate
iD
n+n+
VBS0 = 0V VGS
VBS1 > 0V VGS
VGSVSB2 >VSB1:
Polysilicon
Lecture 090 – Large Signal MOSFET Model (3/24/10) Page 090-19
CMOS Analog Circuit Design © P.E. Allen - 2010
Influence of the Bulk Voltage on the Large Signal MOSFET Model - ContinuedBulk-Source (vBS) influence on the transconductance characteristics-
060612-02
VBS = 0
Decreasing valuesof bulk-source voltage
iD
vDS > vGS-VT
VT0 VT1 VT2 VT3vGS
ID
VGS
In general, the simple model incorporates the bulk effect into VT by the previouslydeveloped relationship:
VT(vBS) = VT0 + 2| f| + |vBS| - 2| f|
Lecture 090 – Large Signal MOSFET Model (3/24/10) Page 090-20
CMOS Analog Circuit Design © P.E. Allen - 2010
Summary of the Simple Large Signal MOSFET Model
N-channel reference convention:Non-saturation-
iD = WμoCox
L (vGS - VT)vDS -vDS2
2 (1 + vDS)
Saturation-
iD = WμoCox
L (vGS-VT)vDS(sat)-vDS(sat)2
2 (1+ vDS)= WμoCox
2L (vGS-VT)2(1+ vDS)
where:μo = zero field mobility (cm2/volt·sec)Cox = gate oxide capacitance per unit area (F/cm2)
= channel-length modulation parameter (volts-1)
VT = VT0 + 2| f| + |vBS| - 2| f|
VT0 = zero bias threshold voltage = bulk threshold parameter (volts-0.5)
2| f| = strong inversion surface potential (volts)For p-channel MOSFETs, use n-channel equations with p-channel parameters and invertthe current.
G
D
B
S
vDS
vGS
iD
+
-
+
-
+vBS
Fig. 110-10
Lecture 090 – Large Signal MOSFET Model (3/24/10) Page 090-21
CMOS Analog Circuit Design © P.E. Allen - 2010
Silicon Constants
ConstantSymbol
Constant Description Value Units
VG
kni
o
si
ox
Silicon bandgap (27°C)Boltzmann’s constant
Intrinsic carrier concentration (27°C)
Permittivity of free space
Permittivity of silicon
Permittivity of SiO2
1.205
1.381x10-23
1.45x1010
8.854x10-14
11.7 o
3.9 o
VJ/K
cm-3
F/cm
F/cm
F/cm
Lecture 090 – Large Signal MOSFET Model (3/24/10) Page 090-22
CMOS Analog Circuit Design © P.E. Allen - 2010
MOSFET ParametersModel Parameters for a Typical CMOS Bulk Process (0.25μm CMOS n-well):
Typical Parameter ValueParameter
Symbol
Parameter DescriptionN-Channel P-Channel
Units
VT0 Threshold Voltage(VBS = 0)
0.5± 0.15 -0.5 ± 0.15 V
K' Transconductance Para-meter (in saturation)
120.0 ± 10% 25.0 ± 10% μA/V2
Bulk thresholdparameter
0.4 0.6 (V)1/2
Channel lengthmodulation parameter
0.32 (L=Lmin)0.06 (L 2Lmin)
0.56 (L=Lmin)0.08 (L 2Lmin)
(V)-1
2| F| Surface potential atstrong inversion
0.7 0.8 V
Lecture 090 – Large Signal MOSFET Model (3/24/10) Page 090-23
CMOS Analog Circuit Design © P.E. Allen - 2010
SUBTHRESHOLD MODELLarge-Signal Model for Weak InversionThe electrons in the substrate at the source side can be expressed as,
np(0) = npoexps
Vt
The electrons in the substrate at the drain side can be expressed as,
np(L) = npoexps-vDSVt
Therefore, the drain current due to diffusion is,
iD = qADn np(L)- np(0)
L = WL qXDnnpoexp
sVt
1 - exp -vDSVt
where X is the thickness of the region in which iD flows.In weak inversion, the changes in the surface potential, s are controlled by changes inthe gate-source voltage, vGS, through a voltage divider consisting of Cox and Cjs, thedepletion region capacitance.
d sdvGS
= Cox
Cox+ Cjs =
1n s =
vGSn + k1 =
vGS-VTn + k2
where
060405-04
PolyOxideChannelDep.
Substrate
Cox
Cjs φs
vGS
k2 = k1 + VTn
Lecture 090 – Large Signal MOSFET Model (3/24/10) Page 090-24
CMOS Analog Circuit Design © P.E. Allen - 2010
Large-Signal Model for Weak Inversion – ContinuedSubstituting the above relationships back into the expression for iD gives,
iD = WL qXDnnpo exp
k2Vt
expvGS-VT
nVt1 - exp -
vDSVt
Define It as
It = qXDnnpo expk2Vt
to get,
iD = WL It exp
vGS-VTnVt
1 - exp -vDSVt
where n 1.5 – 3If vDS > 0, then
iD = It WL exp
vGS-VTnVt
1 +vDSVA
The boundary between nonsaturatedand saturated is found as,Vov = VDS(sat) = VON = VGS -VT = 2nVt
VGS=VT
VGS<VT
iD
vDS00 1V
Fig. 140-03
1μA
Lecture 090 – Large Signal MOSFET Model (3/24/10) Page 090-25
CMOS Analog Circuit Design © P.E. Allen - 2010
SHORT CHANNEL, STRONG INVERSION MODELWhat is Velocity Saturation?
The most important short-channeleffect in MOSFETs is the velocitysaturation of carriers in the channel.A plot of electron drift velocityversus electric field is shown below.
An expression for the electron driftvelocity as a function of the electricfield is,
vd μnE
1 + E/Ec
wherevd = electron drift velocity (m/s)μn = low-field mobility ( 0.07m2/V·s)Ec = critical electrical field at which velocity saturation occurs
5x104
105
2x104
104
5x103
105 106 107
Electric Field (V/m)
Ele
ctro
n D
rift
Vel
ocity
(m
/s)
Fig130-1
Lecture 090 – Large Signal MOSFET Model (3/24/10) Page 090-26
CMOS Analog Circuit Design © P.E. Allen - 2010
Short-Channel Model DerivationAs before,
JD = JS = iDW = QI(y)vd(y) iD = WQI(y)vd(y) =
WQI(y)μnE1 + E/Ec
iD 1+EEc
= WQI(y)μnE
Replacing E by dv/dy gives,
iD 1 +1Ec
dvdy = WQI(y)μn
dvdy
Integrating along the channel gives,
0
L
iD 1 +1
Ec
dvdy dy =
0
vDS
WQI(y)μndv
The result of this integration is,
iD = μnCox
2 1 +1
Ec
vDSL
WL [2(vGS-VT)vDS-vDS2] =
μnCox2 1 + vDS
WL [2(vGS-VT)vDS-vDS2]
where = 1/(EcL) with dimensions of V-1.
Lecture 090 – Large Signal MOSFET Model (3/24/10) Page 090-27
CMOS Analog Circuit Design © P.E. Allen - 2010
Saturation VoltageDifferentiating iD with respect to vDS and setting equal to zero gives,
V’DS(sat) = 1
1 + 2 (VGS-VT -1 (VGS-VT) 1 -(VGS-VT)
2 + ···
if (VGS-VT)
2 < 1
Therefore,
V’DS(sat) VDS(sat) 1 -(VGS-VT)
2 + ···
Note that the transistor will enter the saturation region for vDS < vGS - VT in thepresence of velocity saturation.
Lecture 090 – Large Signal MOSFET Model (3/24/10) Page 090-28
CMOS Analog Circuit Design © P.E. Allen - 2010
Large Signal Model for the Saturation RegionAssuming that
(VGS-VT)2 < 1
givesV’DS(sat) (VGS-VT)
Therefore the large signal model in the saturation region becomes,
iD = K’
2[1 + (vGS-VT)] WL [ vGS - VT]2, vDS (VGS-VT) 1 -
(VGS-VT)2 + ···
Lecture 090 – Large Signal MOSFET Model (3/24/10) Page 090-29
CMOS Analog Circuit Design © P.E. Allen - 2010
The Influence of Velocity Saturation on the Transconductance Characteristics
The following plot was made for K’ = 110μA/V2 and W/L = 1:
0
200
400
600
800
1000
0.5 1 1.5 2 2.5 3
i D/W
(μ
A/μ
m)
vGS (V)
θ = 0
θ = 0.2
θ = 0.4
θ = 0.6
θ = 0.8
θ = 1.0
Fig130-2
Note as the velocity saturation effect becomes stronger, that the drain current-gatevoltage relationship becomes linear.
Lecture 090 – Large Signal MOSFET Model (3/24/10) Page 090-30
CMOS Analog Circuit Design © P.E. Allen - 2010
Circuit Model for Velocity SaturationA simple circuit model to include the influence of velocity saturation isis shown:We know that
iD = K’W2L (vGS’ -VT)2 and vGS = vGS’ + iD RSX
orvGS’ = vGS - iDRXS
Substituting vGS’ into the current relationship gives,
iD = K’W2L (vGS - iDRSX -VT)2
Solving for iD results in,
iD = K’
2 1 + K’WL RSX(vGS-VT)
WL (vGS - VT)2
Comparing with the previous result, we see that
= K’ WL RSX RSX =
LK’W =
1EcK’W
Therefore for K’ = 110μA/V2, W = 1μm and Ec = 1.5x106V/m, we get RSX = 6.06k .
Lecture 090 – Large Signal MOSFET Model (3/24/10) Page 090-31
CMOS Analog Circuit Design © P.E. Allen - 2010
SUMMARY• The modeling of this lecture is devoted to understanding how the circuit works• The two primary current-voltage characteristics of the MOSFET are the
transconductance characteristic and the output characteristic• The simple Sah large signal model is good enough for most applications and technology• The Sah model can be improved in the region of the knee and for the weak dependence
of drain current on drain-source voltage in the saturation region• Most designers do not work at minimum channel length because of the channel length
modulation effect and because worse matching occurs for small areas• The threshold voltage is increased as the bulk-source is reverse biased• The subthreshold model accounts for very small currents that flow in the channel when
the gate-source voltage is smaller than the threshold voltage• The subthreshold current is exponentially related to the gate-source voltage• Velocity saturation occurs at minimum channel length and can be modeled by including
a source degeneration resistor with the simple large signal model
Lecture 100 – MOS Capacitor Model and Large Signal Model Dependence (3/24/10) Page 100-1
CMOS Analog Circuit Design © P.E. Allen - 2010
LECTURE 100 – MOS CAPACITOR MODEL AND LARGESIGNAL MODEL DEPENDENCE
LECTURE ORGANIZATIONOutline• MOSFET capacitor model• Dependence of the large signal model on process• Dependence of the large signal model on voltage• Dependence of the large signal model on temperature• SummaryCMOS Analog Circuit Design, 2nd Edition ReferencePages 79-86
Lecture 100 – MOS Capacitor Model and Large Signal Model Dependence (3/24/10) Page 100-2
CMOS Analog Circuit Design © P.E. Allen - 2010
MOSFET CAPACITOR MODELSubmicron TechnologyPhysical perspective:
SiO2
Bulk
Source DrainGate
CBS CBD
C4
C1 C2 C3
Fig120-06
FOX FOX
MOSFET capacitors consist of:• Depletion capacitances• Charge storage or parallel plate capacitances
Lecture 100 – MOS Capacitor Model and Large Signal Model Dependence (3/24/10) Page 100-3
CMOS Analog Circuit Design © P.E. Allen - 2010
Deep Submicron TechnologyPhysical perspective:
MOSFET capacitors consist of:• Depletion capacitances• Charge storage or parallel plate capacitances
Lecture 100 – MOS Capacitor Model and Large Signal Model Dependence (3/24/10) Page 100-4
CMOS Analog Circuit Design © P.E. Allen - 2010
MOSFET Depletion CapacitorsModel:1.) vBS FC·PB
CBS = CJ·AS
1 -vBSPB
MJ + CJSW·PS
1 -vBSPB
MJSW,
and2.) vBS> FC·PB
CBS = CJ·AS
1- FC1+MJ 1 - (1+MJ)FC + MJ
VBSPB
+ CJSW·PS
1 - FC1+MJSW 1 - (1+MJSW)FC + MJSW
VBSPB
SiO2
Polysilicon gate
Bulk
A B
CD
EF
GH
Drain bottom = ABCDDrain sidewall = ABFE + BCGF + DCGH + ADHE
Source Drain
Fig. 120-07
FC·PB
PB
vBS
CBS
vBS ≤ FC·PBvBS ≥ FC·PB
Fig. 120-08
whereAS = area of the sourcePS = perimeter of the sourceCJSW = zero bias, bulk source sidewall capacitanceMJSW = bulk-source sidewall grading coefficient
For the bulk-drain depletion capacitance replace "S" by "D" in the above.
Lecture 100 – MOS Capacitor Model and Large Signal Model Dependence (3/24/10) Page 100-5
CMOS Analog Circuit Design © P.E. Allen - 2010
SM Charge Storage (Parallel Plate) MOSFET Capacitances - C1, C2, C3 and C4
Overlap capacitances:C1 = C3 = LD·Weff·Cox = CGSO or CGDO(LD 0.015 μm for LDD structures)
Channel capacitances:C2 = gate-to-channel = CoxW eff·(L-2LD) =
CoxW eff·LeffC4 = voltage dependent channel-
bulk/substrate capacitanceBulk
LDMask
W
Oxide encroachment
ActualL (Leff)
Gate
Mask L
Source-gate overlapcapacitance CGS (C1)
Drain-gate overlapcapacitance CGD (C3)
ActualW (Weff)
Fig. 120-09
Source
Gate
Drain
Gate-ChannelCapacitance (C2)
Channel-BulkCapacitance (C4)
FOX FOX
Lecture 100 – MOS Capacitor Model and Large Signal Model Dependence (3/24/10) Page 100-6
CMOS Analog Circuit Design © P.E. Allen - 2010
SM Charge Storage (Parallel Plate) MOSFET Capacitances - C5View looking down the channel from source to drain
Bulk
Overlap Overlap
Source/DrainGate
FOX FOXC5 C5
Fig120-10
C5 = CGBOCapacitance values based on an oxide thickness of 140 Å or Cox=24.7 10-4 F/m2:
Type P-Channel N-Channel UnitsCGSO 220 10-12 220 10-12 F/mCGDO 220 10-12 220 10-12 F/mCGBO 700 10-12 700 10-12 F/mCJ 560 10-6 770 10-6 F/m2
CJSW 350 10-12 380 10-12 F/mMJ 0.5 0.5MJSW 0.35 0.38
Lecture 100 – MOS Capacitor Model and Large Signal Model Dependence (3/24/10) Page 100-7
CMOS Analog Circuit Design © P.E. Allen - 2010
DSM Charge Storage MOSFET Capacitances - C1, C2, C3, C4 and C5
ShallowTrench
IsolationShallowTrench
Isolation
ShallowTrench
Isolation
ShallowTrench
Isolation
C1
C5C5
C2
C4
C3
Side View View Down Channel 070330-04
Channel
C1 and C3 are overlap capacitors due to lateral diffusion of the source and drain
C2 is the gate to channel capacitance
C4 is the depletion capacitance between the channel and the bulk
C5 is the fringing capacitance between the gate and the bulk around the edges of thechannel
Lecture 100 – MOS Capacitor Model and Large Signal Model Dependence (3/24/10) Page 100-8
CMOS Analog Circuit Design © P.E. Allen - 2010
MOSFET Capacitors for the Cutoff RegionSide view:
Bulk
Source-gate overlapcapacitance CGS (C1)
Drain-gate overlapcapacitance CGD (C3)
Source
Gate
Drain
Gate-ChannelCapacitance (C2)
Channel-BulkCapacitance (C4)
FOX FOX
ShallowTrench
Isolation
ShallowTrench
Isolation
Source-gate overlapcapacitance CGS (C1)
Drain-gate overlapcapacitance CGD (C3)
Gate-ChannelCapacitance (C2) Channel-Bulk
Capacitance (C4)
070330-05
As the gate-source voltage varies from 0 to VT, the channel-bulk capacitor varies from avery large capacitor (because of a very small depletion region) to a capacitor muchsmaller than C2.Capacitors in Cutoff:
CGS C1 = Cox·LD·W = CGSO·W
CGD C3 = Cox·LD·W = CGDO·W
CGB C2 varies from Cox·L·W to 2C5
CBD CBD = (CJ·AD)/[1 – (vBD/PB)]MJ + (CJSW·PD)/[1 – (vBD/PB)]MJSW
CBS CBS = (CJ·AS)/[1 – (vBS/PB)]MJ + (CJSW·PS)/[1 – (vBS/PB)]MJSW
Lecture 100 – MOS Capacitor Model and Large Signal Model Dependence (3/24/10) Page 100-9
CMOS Analog Circuit Design © P.E. Allen - 2010
MOSFET Capacitors for the Saturation RegionSide view:
Bulk
Source-gate overlapcapacitance CGS (C1)
Drain-gate overlapcapacitance CGD (C3)
Source
Gate
DrainGate-ChannelCapacitance (C2)
FOX FOXShallowTrench
Isolation
ShallowTrench
Isolation
070330-06
Source-gate overlapcapacitance CGS (C1)
Drain-gate overlapcapacitance CGD (C3)
Gate-ChannelCapacitance (C2)
In the saturation region, C4, becomes small and is not shown above.
Capacitors in Saturation:
CGS C1 = Cox·LD·W + (2/3)Cox·L·W = [CGSO + (2/3)Cox·L]W
CGD C3 = Cox·LD·W = CGDO·W
CGB 2C5 = 2·CGBO·W
CBD CBD = (CJ·AD)/[1 – (vBD/PB)]MJ + (CJSW·PD)/[1 – (vBD/PB)]MJSW
CBS CBS = (CJ·AS)/[1 – (vBS/PB)]MJ + (CJSW·PS)/[1 – (vBS/PB)]MJSW
Lecture 100 – MOS Capacitor Model and Large Signal Model Dependence (3/24/10) Page 100-10
CMOS Analog Circuit Design © P.E. Allen - 2010
MOSFET Capacitors for the Active RegionSide view:
Bulk
Source-gate overlapcapacitance CGS (C1)
Drain-gate overlapcapacitance CGD (C3)
Source
Gate
Drain
Gate-ChannelCapacitance (C2)
FOX FOXShallowTrench
Isolation
ShallowTrench
Isolation
070330-07
Source-gate overlapcapacitance CGS (C1)
Drain-gate overlapcapacitance CGD (C3)
Gate-ChannelCapacitance (C2)
In the saturation region, C4, becomes small and is not shown above.
Capacitors in Active:
CGS C1 = Cox·LD·W + (1/2)Cox·L·W = [CGSO + (1/2)Cox·L]W
CGD C3 = Cox·LD·W + (1/2)Cox·L·W = [CGSO + (1/2)Cox·L]W
CGB 2C5 = 2·CGBO·W
CBD CBD = (CJ·AD)/[1 – (vBD/PB)]MJ + (CJSW·PD)/[1 – (vBD/PB)]MJSW
CBS CBS = (CJ·AS)/[1 – (vBS/PB)]MJ + (CJSW·PS)/[1 – (vBS/PB)]MJSW
Lecture 100 – MOS Capacitor Model and Large Signal Model Dependence (3/24/10) Page 100-11
CMOS Analog Circuit Design © P.E. Allen - 2010
Illustration of CGD, CGS and CGB
Comments on the variation of CBG in the cutoff region:
CBG = 1
1C2 +
1C4
+ 2C5
1.) For vGS 0, CGB C2 + 2C5
(C4 is large because of the thin
inversion layer in weak inversion
where VGS is slightly less than VT))
2.) For 0 < vGS VT, CGB 2C5(C4 is small because of the thickerinversion layer in strong inversion)
0 vGS
CGS
CGS, CGD
CGDCGB
CGS, CGD
C2 + 2C5
C1+ 0.67C2
C1, C32C5
VT vDS +VT
Off Saturation Non-Saturation
vDS = constant vBS = 0
Capacitance
C1+ 0.5C2
Fig120-12
C4 Large
C4 Small
Lecture 100 – MOS Capacitor Model and Large Signal Model Dependence (3/24/10) Page 100-12
CMOS Analog Circuit Design © P.E. Allen - 2010
DEPENDENCE OF THE LARGE SIGNAL MODEL ON PROCESSHow Does Technology Vary?1.) Thickness variations in layers (dielectrics and metal)
060225-01
tox(min) tox(max)
2.) Doping variations
3.) Process biases – differences betweenthe drawn and actual dimensions due to process (etching, lateral diffusion, etc.)
060225-03
Drawn Dimension
Actual Dimension
060225-02
n-well
p+n+ p+
Diffusion Differences
Lecture 100 – MOS Capacitor Model and Large Signal Model Dependence (3/24/10) Page 100-13
CMOS Analog Circuit Design © P.E. Allen - 2010
Large Signal Model Dependence on Process Variations1.) Threshold voltage
VT = VT0 + |-2 F + vSB| - |-2 F|
where
VT0 = MS - 2 F - Qb0
Cox -
QSS
Cox and =
2q siNA
Cox
If VBS = 0, then VT is dependent on doping and oxide thickness because
F = kTq ln
NSUBni
and Cox 1
tox
(Recall that the threshold is also determined by the threshold implant during processing)
2.) Transconductance parameter
K’ = μoCox 1
tox
For short channel devices, the mobility is degraded as given by
μeff = μo
1 + (VGS - VT) and 2x10-9m/V
tox
Lecture 100 – MOS Capacitor Model and Large Signal Model Dependence (3/24/10) Page 100-14
CMOS Analog Circuit Design © P.E. Allen - 2010
Process Variation “Corners”For strong inversion operation, the primary influence is the oxide thickness, tox. We seethat K’ will tend to increase with decreasing oxide thickness whereas VT tends todecrease.If the “speed” of a transistor is increasedby increasing K’ and decreasing VT, thenthe variation of technology can beexpressed on a two-dimensional graphresulting in a rectangular area of“acceptable” process limitation.
Three corner versus five corner models060118-10
PMOSSpeed
NMOS Speed
Fast PMOS
SlowPMOS
SlowNMOS
FastNMOS
AcceptableTechnologyParameters
Large KʼSmall VT
Small KʼLarge VT
Lecture 100 – MOS Capacitor Model and Large Signal Model Dependence (3/24/10) Page 100-15
CMOS Analog Circuit Design © P.E. Allen - 2010
DEPENDENCE OF THE LARGE SIGNAL MODEL ON VOLTAGEWhat is Voltage Variation?Voltage variation is the influence of power supply voltage on the component.(There is also power supply influence on the circuit called power supply rejection ratio,PSRR. We will deal with this much later.)Power supply variation comes from:1.) Influence of depletion region widths on components.2.) Nonlinearity3.) Breakdown voltage
Note: Because the large-signal model for the MOSFET includes all the influences ofvoltage on the transistor, we will focus on passive components except for breakdown.
Lecture 100 – MOS Capacitor Model and Large Signal Model Dependence (3/24/10) Page 100-16
CMOS Analog Circuit Design © P.E. Allen - 2010
Models for Voltage Dependence of a Component1.) ith-order Voltage Coefficients
In general a variable y = f(v) which is a function of voltage, v, can be expressed as aTaylor series,
y(v = V0) y(V0) + a1(v- V0) + a2(v- V0)2+ a3(v- V0)3 + ···where the coefficients, ai, are defined as,
a1 = df(v)dv
|v=V0 , a2 =
12
d2f(v)dv2
|v=V0 , ….
The coefficients, ai, are called the first-order, second-order, …. voltage coefficients.
2.) Fractional Voltage Coefficient or Voltage CoefficientGenerally, only the first-order coefficients are of interest.In the characterization of temperature dependence, it is common practice to use a termcalled fractional voltage coefficient, VCF, which is defined as,
VCF(v=V0) = 1
f(v=V0) df(v)dv
|v=V0 parts per million/V (ppm/V)
or more simply,
VCF = 1
f(v) df(v)dv parts per million/V (ppm/V)
Lecture 100 – MOS Capacitor Model and Large Signal Model Dependence (3/24/10) Page 100-17
CMOS Analog Circuit Design © P.E. Allen - 2010
Influence of Voltage on a Diffused Resistor – Depletion Region
Influence of the depletion region on the p+ resistor:
060305-01
p- substrate
p+
Older LOCOS Technology
p+
n-well
STI STI
p+
Depletion region
Thickness ofp+ Resistor
n- well
FOX FOX
Thickness ofp+ Resistor
As the voltage at the terminals of the resistor become smaller than the n-well potential,the depletion region will widen causing the thickness of the resistor to decrease.
R = L
t W VR
where VR is the reverse bias voltage from the resistor to the well.
This effect is worse for well resistors because the doping concentration of the resistor issmaller.Voltage coefficient for diffused resistors 200-800 ppm/VVoltage coefficient for well resistors 8000 ppm/V
Lecture 100 – MOS Capacitor Model and Large Signal Model Dependence (3/24/10) Page 100-18
CMOS Analog Circuit Design © P.E. Allen - 2010
Voltage Coefficient of Polysilicon ResistorsWhy should polysilicon resistors be sensitive to voltage?There is a small depletion region between the polysilicon and its surrounding materialthat has a very small dependence on the voltage between the polysilicon and thesurrounding material.
Lecture 100 – MOS Capacitor Model and Large Signal Model Dependence (3/24/10) Page 100-19
CMOS Analog Circuit Design © P.E. Allen - 2010
Voltage Nonlinearity and Breakdown VoltageConductivity modulation:As the current in a resistor increases, the conductivity becomes modulated and theresistance increases.Example of a n-well resistor:
As the reverse bias voltage across a pn junctionbecomes large, at some point, called the breakdownvoltage, the current will rapidly increase. Bothtransistors, diodes and depletion capacitors experiencethis breakdown.Model for current multiplication factor:
M = 1
1 +vRBV
n
060311-01
i
v
i = vR
Conductivitymodulation
0.1A
060311-02
iR
vR
Breakdownvoltage
BV
Lecture 100 – MOS Capacitor Model and Large Signal Model Dependence (3/24/10) Page 100-20
CMOS Analog Circuit Design © P.E. Allen - 2010
DEPENDENCE OF THE LARGE SIGNAL MODEL ON TEMPERATURETemperature Dependence of the MOSFETTransconductance parameter:
K’(T) = K’(T0) (T/T0)-1.5 (Exponent becomes +1.5 below 77°K)
Threshold Voltage:VT(T) = VT(T0) + (T-T0) + ···
Typically NMOS = -2mV/°C to –3mV/°C from 200°K to 400°K (PMOS has a + sign)
ExampleFind the value of ID for a NMOS transistor at 27°C and 100°C if VGS = 2V and W/L =
5μm/1μm if K’(T0) = 110μA/V2 and VT(T0) = 0.7V and T0 = 27°C and NMOS = -2mV/°C.
SolutionAt room temperature, the value of drain current is,
ID(27°C) = 110μA/V2·5μm
2·1μm (2-0.7)2 = 465μA
At T = 100°C (373°K), K’(100°C)=K’(27°C) (373/300)-1.5=110μA/V2·0.72=79.3μA/V2
and VT(100°C) = 0.7 – (.002)(73°C) = 0.554V
ID(100°C) = 79.3μA/V2·5μm
2·1μm (2-0.554)2 = 415μA (Repeat with VGS = 2.0855V)
Lecture 100 – MOS Capacitor Model and Large Signal Model Dependence (3/24/10) Page 100-21
CMOS Analog Circuit Design © P.E. Allen - 2010
Zero Temperature Coefficient (ZTC) Point for MOSFETsFor a given value of gate-source voltage, the drain current of the MOSFET will beindependent of temperature. Consider the following circuit:
Assume that the transistor is saturated and that:
μ = μo
TTo
-1.5 and VT(T) = VT(To) + (T-To)
where = -0.0023V/°C and To = 27°C
ID(T) = μoCoxW
2L TTo
-1.5[VGS – VT0 - (T-To)]2
dIDdT =
-1.5μoCox
2To
TTo
-2.5[VGS-VT0- (T-To)]2+ μoCox
TTo
-1.5[VGS-VT0- (T-To)] = 0
VGS – VT0 - (T-To) = -4T
3 VGS(ZTC) = VT0 - To - 3
Let K’ = 10μA/V2, W/L = 5 and VT0 = 0.71V.At T=27°C(300°K), VGS(ZTC)=0.71-(-0.0023)(300°K)-(0.333)(-0.0023)(300°K)=1.63V
At T = 27°C (300°K), ID = (10μA/V2)(5/2)(1.63-0.71)2 = 21.2μAAt T=200°C(473°K),VGS(ZTC)=0.71-(-0.0023)(300°K)-(0.333)(-0.0023)(473°K)=1.76V
ID
VGS
Fig. 4.5-12
Lecture 100 – MOS Capacitor Model and Large Signal Model Dependence (3/24/10) Page 100-22
CMOS Analog Circuit Design © P.E. Allen - 2010
Experimental Verification of the ZTC PointThe data below is for a 5μm n-channel MOSFET with W/L=50μm/10μm,NA=1016 cm-3, tox = 650Å, uoCox = 10μA/V2, and VT0 = 0.71V.
0600613-01
0
20
40
60
80
100
0 0.6 1.2 1.8 2.4 3
25°C100°C
150°C200°C250°C275°C
300°C
VDS = 6V
Zero TC Point
25°C100°C
150°C200°C
250°C
275°C
VGS (V)
I D (
A)
A similar result holds for the p-channel MOSFET.
Lecture 100 – MOS Capacitor Model and Large Signal Model Dependence (3/24/10) Page 100-23
CMOS Analog Circuit Design © P.E. Allen - 2010
ZTC Point for UDSM Technology50 nm CMOS:
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
Nor
mal
ized
Dra
in C
urre
nt
Gate Source Voltage
25°C
50°C
100°C
140°CNMOS
L=500nm
Zero TemperatureCoefficient
071108-02
0.8
0.9
1.0
Note that the ZTC point is close to VDD.
PMOS will have similar characteristics.
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.00
0.1
0.2
0.3
0.4
0.5
0.6
0.7
Nor
mal
ized
Dra
in C
urre
nt
Gate Source Voltage
25°C50°C100°C140°C
NMOSL=50nm
Zero TemperatureCoefficient
071108-01
Lecture 100 – MOS Capacitor Model and Large Signal Model Dependence (3/24/10) Page 100-24
CMOS Analog Circuit Design © P.E. Allen - 2010
Bulk-Drain (Bulk-Source) Leakage Currents
Cross-section of a NMOS in a p-well:VGS>VT:
VGS<VT:
���Polysilicon
p+
n- substrate
Fig.3.6-5
VG > VT VD > VDS(sat)
��������������n+n+
DepletionRegion
B S
p-well
����
���������Polysilicon
p+
n- substrate
Fig.3.6-6
VG <VT VD > VDS(sat)
n+n+
DepletionRegion
B S
p-well
Lecture 100 – MOS Capacitor Model and Large Signal Model Dependence (3/24/10) Page 100-25
CMOS Analog Circuit Design © P.E. Allen - 2010
Temperature Modeling of the PN JunctionPN Junctions (Reverse-biased only):
iD Is = qA Dppno
Lp+
DnnpoLn
qAD
L n
2i
N = KT 3exp VGo
Vt
Differentiating with respect to temperature gives,dIs
dT = 3KT 3
T exp VGo
Vt +
qKT 3VGo
KT 2 exp VGo
Vt =
3Is
T + Is
T VGo
Vt
TCF = dIs
IsdT = 3T +
1T
VGoVt
ExampleAssume that the temperature is 300° (room temperature) and calculate the reversediode current change and the TCF for a 5° increase.SolutionThe TCF can be calculated from the above expression as TCF = 0.01 + 0.155 = 0.165.Since the TCF is change per degree, the reverse current will increase by a factor of 1.165for every degree (or °C) change in temperature. Multiplying by 1.165 five times givesan increase of approximately 2. Thus, the reverse saturation current approximatelydoubles for every 5°C temperature increase.Experimentally, the reverse current doubles for every 8°C increase in temperaturebecause the reverse current is in part leakage current.
Lecture 100 – MOS Capacitor Model and Large Signal Model Dependence (3/24/10) Page 100-26
CMOS Analog Circuit Design © P.E. Allen - 2010
Experimental Verification of the PN Junction Temperature Dependence
Theory:
Is(T) T 3 expVG(T)
kT
Lecture 100 – MOS Capacitor Model and Large Signal Model Dependence (3/24/10) Page 100-27
CMOS Analog Circuit Design © P.E. Allen - 2010
Temperature Modeling of the PN Junction – ContinuedPN Junctions (Forward biased – vD constant):
iD Is exp vDVt
Differentiating this expression with respect to temperature and assuming that the diodevoltage is a constant (vD = VD) gives
diDdT =
iDIs
dIsdT -
1T
VDVt
iD
The fractional temperature coefficient for iD is1iD
diDdT =
1Is
dIsdT -
VDTVt
= 3T +
VGo - VDTVt
If VD is assumed to be 0.6 volts, then the fractional temperature coefficient is equal to0.01+(0.155-0.077) = 0.0879. The forward diode current will approx. double for a 10°C.PN Junctions (Forward biased – iD constant):
VD = Vt ln(ID/Is)Differentiating with respect to temperature gives
dvDdT =
vDT - Vt
1Is
dIsdT =
vDT -
3VtT -
VGoT = -
VGo - vDT -
3VtT
Assuming that vD = VD = 0.6 V the temperature dependence of the forward diode voltageat room temperature is approximately -2.3 mV/°C.
Lecture 100 – MOS Capacitor Model and Large Signal Model Dependence (3/24/10) Page 100-28
CMOS Analog Circuit Design © P.E. Allen - 2010
Resistor Dependence on TemperatureDiffused Resistors:The temperature dependence of resistors depends mostly on the doping level of diffusedand implanted resistors. As the doping level or sheet resistance increases from 100 /to 400 / , the temperature coefficient varies from about +1000 ppm/°C to +4000ppm/°C. Diffused and implanted resistors have good thermal conduction to the substrateor well.Polysilicon Resistors:
Typically has a sheet resistance of 20 / to 80 / and has poor thermal conductionbecause it is electrically isolated by oxide layers.Metal:Metal is often used for resistors and has a positive temperature coefficient.Temperature Coefficients of Resistors:
n-well = 4000 ppm/°C Diffusion = +1500 ppm/°CPolysilicon = 500-2000 ppm/°C Ion implanted = +400 ppm/°CMetal = +3800 ppm/°C (aluminum)
Lecture 100 – MOS Capacitor Model and Large Signal Model Dependence (3/24/10) Page 100-29
CMOS Analog Circuit Design © P.E. Allen - 2010
SUMMARY• The large signal capacitance model includes depletion and parallel plate capacitors• The depletion capacitors CBD and CBS vary with their reverse bias voltage
• The capacitors CGD, CGS, and CGB have different values for the regions of cutoff, activeand saturated
• The large signal model varies with process primarily through μo and tox
• Voltage dependence of resistors and capacitors is primarily due to the influence ofdepletion regions
• The temperature dependent large signal model of the MOSFET yields a gate-sourcevoltage where the derivative of drain current with respect to temperature is zero
• Other MOSFET temperature dependence comes from the leakage currents acrossreverse biased pn junctions
Lecture 110 – Linear Circuit Models (3/24/10) Page 110-1
CMOS Analog Circuit Design © P.E. Allen - 2010
LECTURE 110 – LINEAR CIRCUIT MODELSLECTURE ORGANIZATION
Outline• Frequency independent small signal transistor models• Frequency dependent small signal transistor model• Noise models• Passive component models• Interconnects• Substrate interference• SummaryCMOS Analog Circuit Design, 2nd Edition ReferencePages 86-91 and new material
Lecture 110 – Linear Circuit Models (3/24/10) Page 110-2
CMOS Analog Circuit Design © P.E. Allen - 2010
FREQUENCY INDEPENDENT SMALL SIGNAL TRANSISTOR MODELSWhat is a Small Signal Model?The small signal model is a linear approximation of a nonlinear model.Mathematically:
iD = 2 (vGS - VT)2 id = gmvgs
Graphically:
The large signal curve at point Q has beenapproximated with a small signal model goingthrough the point Q and having a slope of gm.
060311-03
iD = β(vGS-VT)2
id = gmvgs
vGSVGS
iD
IDQ
VT
id
vgs
Large Signal to Small Signal
Lecture 110 – Linear Circuit Models (3/24/10) Page 110-3
CMOS Analog Circuit Design © P.E. Allen - 2010
Why Small Signal Models?The small signal model is a linear approximation to the large signal behavior.1.) The transistor is biased at given DC operating point (Point Q above)2.) Voltage changes are made about the operating point.3.) Current changes result from the voltage changes.If the designer is interested in only the current changes and not the DC value, then thesmall signal model is a fast and simple way to find the current changes given the voltagechanges.
060311-04
id = gmvgs
ΔiDʼ
ΔVGS
Q
id
vgs
Large SignalModel
ΔiD
Lecture 110 – Linear Circuit Models (3/24/10) Page 110-4
CMOS Analog Circuit Design © P.E. Allen - 2010
How Good is the Small Signal Model?It depends on how large are the changes and how nonlinear is the large signal model.• The parameters of the small signal model will depend on the values of the large signal
model.• The model is a tradeoff in complexity versus accuracy (we will choose simplicity and
give up accuracy).• What does a simulator do? Exactly the same thing when it makes an ac analysis (i.e.
frequency response)• Regardless of the approximate nature of the small signal model, it is the primary model
used to predict the signal performance of an analog circuit.
Lecture 110 – Linear Circuit Models (3/24/10) Page 110-5
CMOS Analog Circuit Design © P.E. Allen - 2010
Small-Signal Model for the Saturation RegionThe small-signal model is a linearization of the large signal model about a quiescent oroperating point.Consider the large-signal MOSFET in the saturation region (vDS vGS – VT) :
iD = WμoCox
2L (vGS - VT) 2 (1 + vDS)
The small-signal model is the linear dependence of id on vgs, vbs, and vds. Written as,id gmvgs + gmbsvbs + gds vds
where
gm diD
dvGS |Q = (VGS-VT) = 2 ID
gds diD
dvDS |Q =
ID1 + VDS
IDand
gmbs d DdvBS
|Q =
diDdvGS
dvGSdvBS
|Q = -
diDdVT
dVTdvBS
|Q=
gm
2 2| F| - VBS = gm
Lecture 110 – Linear Circuit Models (3/24/10) Page 110-6
CMOS Analog Circuit Design © P.E. Allen - 2010
Small-Signal Model – ContinuedComplete schematicmodel:
where
gm diD
dvGS |Q =
(VGS-VT) = 2 ID gds diD
dvDS |Q =
iD1 + vDS
iD
and
gmbs = D
vBS |Q =
iDvGS
vGS
vBS
|Q = -
iDvT
vT
vBS
|Q=
gm
2 2| F| - VBS
= gm
Simplified schematic model:
A very useful assumption:gm 10gmbs 100gds
rds
G
S
gmvgsvgs
+
-gmbsvbs
vds
+
-
id
Fig. 120-0
B
vbs
+
-
G
S
B
D
G
S
B
D
S
D
Lecture 110 – Linear Circuit Models (3/24/10) Page 110-7
CMOS Analog Circuit Design © P.E. Allen - 2010
Small-Signal Model for other RegionsActive region:
gm = iDvGS
|Q =
K’WVDSL (1+ VDS)
K’WL VDS gmbs =
iDvBS
|Q =
K’W VDS
2L 2 F - VBS
gds = iD
vDS |Q =
K’WL ( VGS - VT - VDS)(1+ VDS) +
ID1+ VDS
K’WL (VGS - VT - VDS)
Note:While the small-signal model analysis is independent of the region of operation, theevaluation of the small-signal performance is not.
Weak inversion region:If vDS > 0, then
iD = It WL exp
vGS-VTnVt
1 +vDSVA
Small-signal model:
gm = diDdvGS
|Q = It
WL
ItnVt
expvGS-VT
nVt1 +
vDSVA
= IDnVt
= qIDnkT =
IDVt
Cox
Cox+Cjs
gds = diDdvDS
|Q
IDVA
Lecture 110 – Linear Circuit Models (3/24/10) Page 110-8
CMOS Analog Circuit Design © P.E. Allen - 2010
FREQUENCY DEPENDENT SMALL SIGNAL MODELSmall-Signal Frequency Dependent ModelThe depletion capacitors are found by evaluating the large signal capacitors at the DCoperating point.
The charge storage capacitors are constant for a specific region of operation.
Lecture 110 – Linear Circuit Models (3/24/10) Page 110-9
CMOS Analog Circuit Design © P.E. Allen - 2010
Gain-bandwidth of the MOSFET (fT)
The short-circuit current gain is measure of the frequency capability of the MOSFET.Small signal model:
Small signal analysisgives,
iout = gmvgs –
sCgdvgs and vgs = iin
s(Cgs + Cgd)Therefore,
ioutiin =
gm-sCgds(Cgs + Cgd)
gms(Cgs + Cgd)
Assume VSB = 0 and the MOSFET is in saturation,
fT = 12
gmCgs + Cgd
12
gmCgs
Recalling that
Cgs 23 CoxWL and gm = μoCox
WL (VGS-VT) fT =
34
μoL2 (VGS-VT)
For velocity saturation, fT 1/L.
060311-05
iin
iout
VDDiin
iout
+
−vgs
Cgs
gmvgs
Cgd
Cbdrds
Lecture 110 – Linear Circuit Models (3/24/10) Page 110-10
CMOS Analog Circuit Design © P.E. Allen - 2010
NOISE MODELSDerivation of the Thermal Noise ModelThe noise model for the MOSFET is developed for the active region as follows:In the active region, the channel resistance of the MOSFET is given from the simple largesignal model as,
Rchannel = 1
iDvDS
|Q
= 1
K’WL (VGS - VT - VDS)
1
K’WL (VGS - VT)
= 1
gm(sat)
In the saturation region, approximate the channel resistance as 2/3 the value in the activeregion giving,
Rchannel(sat) = 2
3gm(sat) = 2
3gmWe know the current thermal noise spectral density of a resistor of value R is given as
in2 = 4kTR (A2/Hz)
Substituting R by Rchannel(sat) gives the drain current MOSFET thermal noise model as,
in2 = 8kTgm
3 (A2/Hz)
Translating this drain current noise to the gate voltage noise by dividing by gm2 gives
en2 =
8kT3gm
(V2/Hz)
Lecture 110 – Linear Circuit Models (3/24/10) Page 110-11
CMOS Analog Circuit Design © P.E. Allen - 2010
The Influence of the Back Gate on Thermal NoiseUsing the derivation above, we can include the influence of the bulk-source voltage on thethermal noise as follows
Rchannel(sat) = 2
3gm(eff) = 2
3(gm + gmbs) = 2
3gm(1 + )
where
= gmbs
gm
Substituting R with Rchannel(sat) gives the voltage and current noise spectral densities as,
en2 =
8kT3(gm + gmbs) (V
2/Hz) = 8kT
3gm(1 + ) (V2/Hz)
or
in2 = 8kT(gm + gmbs)
3 (A2/Hz) = 8kTgm(1 + )
3 (A2/Hz)
Lecture 110 – Linear Circuit Models (3/24/10) Page 110-12
CMOS Analog Circuit Design © P.E. Allen - 2010
1/f Noise ModelAnother significant noise contribution to MOSFETs is a noise that is typically inverselyproportional to frequency called the 1/f noise.This 1/f noise spectral density is given as,
en2 =
KF2fSCoxWL K’ or in
2 = KF ID
fSCoxL2
whereKF = Flicker noise coefficientS = Slope factor of the 1/f noise
Although we do not have a good explanation for the reason why, the value of KF for aPMOS transistor is smaller than the value of KF for a NMOS transistor with the samecurrent and W/L. The current will also influence the comparative 1/f noise of the NMOSand PMOS.
Lecture 110 – Linear Circuit Models (3/24/10) Page 110-13
CMOS Analog Circuit Design © P.E. Allen - 2010
MOS Device Noise at Low Frequencies
D
B
S
G
D
S
in2
B
G
NoiseFreeMOSFET
D
S
BG
NoiseFreeMOSFET
eN2
*
where
in2 =
8kTgm(1+ )3 +
KF ID
fSCoxL2 (amperes2/Hz)
= gmbs
gm
k = Boltzmann’s constantKF = Flicker noise coefficientS = Slope factor of the 1/f noise
Lecture 110 – Linear Circuit Models (3/24/10) Page 110-14
CMOS Analog Circuit Design © P.E. Allen - 2010
Reflecting the MOSFET Noise to the GateDividing in
2 by gm2 gives the voltage noise spectral density as
en2 =
in2
gm2 =
8kT3gm(1+ ) +
KF2fCoxWL K’ (volts2/Hz)
It will be convenient to use B = KF
2CoxK’ to simplify the notation.
Frequency response of MOSFET noise:
060311-06
Noise SpectralDensity
log10 ffCorner
1/f noise
Thermal noise
The 1/f corner frequency is:
8kT3gm(1+ ) =
KF2fCoxWL K’ fcorner
3gmB8kTWL if gmbs = 0
Lecture 110 – Linear Circuit Models (3/24/10) Page 110-15
CMOS Analog Circuit Design © P.E. Allen - 2010
MOSFET Noise Model at High FrequenciesAt high frequencies, the source resistance can no longer be assumed to be small.
Therefore, a noise current generator at the input results.MOSFET Noise Models:
G D
S S
gmvgs
Cgs
Cgd
rds in2 io2vin
Circuit 1: Frequency Dependent Noise Model
G D
S S
gmvgs
Cgs
Cgd
rdsii2 io2vin
Circuit 2: Input-referenced Noise Model
ei2
vgs
vgs
*
Lecture 110 – Linear Circuit Models (3/24/10) Page 110-16
CMOS Analog Circuit Design © P.E. Allen - 2010
MOSFET Noise Model at High Frequencies – ContinuedTo find ei
2 and ii2, we will perform the following calculations:
ei2:
Short-circuit the input and find io2 of both models and equate to get ei
2 .
Ckt. 1: io2 = in
2
Ckt. 2: io2 = gm
2 ei2+ ( Cgd)2ei
2
ii2:
Open-circuit the input and find io2 of both models and equate to get ii
2 .
Ckt. 1: io2 = in
2
Ckt. 2: io2 =
(1/Cgs)(1/Cds) + (1/Cgs) 2 ii
2 + gm
2ii2
2(Cgs+Cds)2
gm
2
2Cgs2 in
2 if Cgd < Cgs ii2 =
2Cgs2
gm2 in
2
ei2 =
in2
gm2 + ( Cgd)2
Lecture 110 – Linear Circuit Models (3/24/10) Page 110-17
CMOS Analog Circuit Design © P.E. Allen - 2010
PASSIVE COMPONENT MODELSResistor Models
1.) Large signal
2.) Small signalv = Ri
3.) Noise
en2 = 4kTR or in2 = 4kTG
060315-01
R(v)+ −iv
Cp
R(v)+ −iv
Cp1 Cp2
Distributed Model Lumped Model
060311-01
i
v
i = vR
Conductivitymodulation
Lecture 110 – Linear Circuit Models (3/24/10) Page 110-18
CMOS Analog Circuit Design © P.E. Allen - 2010
Capacitor Models
1.) Large signal
2.) Small signal
q = Cv i = C(dv/dt)
3.) Do capacitors have noise? See next page.
060315-03
C(v)
Rp
Cp Cp
+ −v
i
060315-04
C
v
Linear
Nonlinear
One of the parasitic capacitorsis the top plate and the otheris associated with the bottomplate.
Lecture 110 – Linear Circuit Models (3/24/10) Page 110-19
CMOS Analog Circuit Design © P.E. Allen - 2010
Switched Capacitor Circuits - kT/C NoiseCapacitors and switches generate an inherent thermal noise given by kT/C. This noise isverified as follows.An equivalent circuit for a switchedcapacitor:
The noise voltage spectral density of switched capacitor above is given as
e 2Ron = 4kTRon Volts2/Hz =
2kTRon
Volt2/Rad./sec.The rms noise voltage is found by integrating this spectral density from 0 to to give
v 2Ron =
2kTRon
0
12d
12+ 2 =
2kTRon 1
2 = kTC Volts(rms)2
where 1 = 1/(RonC). Note that the switch has an effective noise bandwidth of
fsw = 1
4RonC Hz
which is found by dividing the second relationship by the first.
060315-05
vin voutC vin voutC
Ron
Lecture 110 – Linear Circuit Models (3/24/10) Page 110-20
CMOS Analog Circuit Design © P.E. Allen - 2010
Inductor ModelsR = losses of the inductorCp = parasitic capacitance to ground
Rp = losses due to eddy currents caused by magnetic flux
1.) Large Signal
2.) Small signal
= Liddt = v = L
di
dt3.) Mutual inductance
v1 = L1di1dt + M
di2dt
v2 = Mdi1dt + L2
di2dt
060316-04
L
i
Linear
Nonlinear
060316-05
+
−v1
i1 i2
+
−v2
+
−v1
i1 i2
+
−v2
L1-M
L1 L2
L2-M
M
M
k = ML1L2
Lecture 110 – Linear Circuit Models (3/24/10) Page 110-21
CMOS Analog Circuit Design © P.E. Allen - 2010
INTERCONNECTSTypes of “Wires”1.) Metal
Many layers are available in today’s technologies:- Lower level metals have more resistance (70 m /sq.)- Upper level metal has the less resistance because it is thicker (50 m /sq.)
2.) PolysiliconBetter resistor than conductor (unpolysicided) (135 /sq.)Silicided polysilicon has a lower resistance (5 /sq.)
3.) DiffusionReasonable for connections if silicided (5 /sq.)Unsilicided (55 /sq.)
4.) ViasVias are vertical metal (tungsten plugs or aluminum)
- Connect metal layer to metal layer (3.5 /via)- Connect metal to silicon or polysilicon contact resistance (5 /contact)
Lecture 110 – Linear Circuit Models (3/24/10) Page 110-22
CMOS Analog Circuit Design © P.E. Allen - 2010
Ohmic Contact ResistanceThe metal to silicon contact generates resistance because of the presence of a potentialbarrier between the metal and the silicon.
Contact and Via Resistance:
Contact SystemContact
Resistance( /μm2)
Al-Cu-Si to 160 /sq. base 750
Al-Cu-Si to 5 /sq. emitter 40
Al-Cu/Ti-W/PtSi to160 /sq. base
1250
Al-Cu/Al-Cu (Via) 5Al-Cu/Ti-W/Al-Cu (Via) 5
050319-02
Metal 1
Metal 2
Metal 3
TungstenPlugs
AluminumVias
Transistors
Lecture 110 – Linear Circuit Models (3/24/10) Page 110-23
CMOS Analog Circuit Design © P.E. Allen - 2010
Capacitance of WiresSelf, fringing and coupling capacitances:
CCoupling
CFringeCSelf
CCoupling
CFringeGround plane
Wide Spacing Minimum Spacing
050319-03
Capacitance Typical Value UnitsMetal to diffusion, Self capacitance 33 aF/μm2
Metal to diffusion, Fringe capacitance, minimum spacing 7 aF/μmMetal to diffusion, Fringe capacitance, wide spacing 40 aF/μmMetal to metal, Coupling capacitance, minimum spacing 85 aF/μmMetal to substrate, Self capacitance 28 aF/μm2
Metal to substrate, Fringe capacitance, minimum spacing 4 aF/μmMetal to substrate, Fringe capacitance, wide spacing 39 aF/μm
Lecture 110 – Linear Circuit Models (3/24/10) Page 110-24
CMOS Analog Circuit Design © P.E. Allen - 2010
ElectromigrationElectromigration occurs if the current density is too large and the pressure of carriercollisions on the metal atoms causes a slow displacement of the metal.Black’s law:
MTF = 1
AJ 2 e(Ea/kTj)
WhereA = rate constant (cm4/A2/hr)J = current density (A/cm2)Ea = activation energy in electron volts (0.5eV for Al and 0.7eV for Cu doped Al)
k = Boltzmann’s constant (8.6x10-5 eV/K)Electromigration leads to a maximum current density,Jmax. Jmax for copper dopedaluminum is 5x105 A/cm2 at 85°C.
If t = 10,000 Angstroms and Jmax = 5x105 A/cm2, then a 10μm wide lead can conduct nomore than 50mA at 85°C.
Metal050304-04
Lecture 110 – Linear Circuit Models (3/24/10) Page 110-25
CMOS Analog Circuit Design © P.E. Allen - 2010
Where is AC Ground on the Chip?AC grounds on the chip are any area tied to a fixed potential. This includes the substrateand the wells. All parasitic capacitances are in reference to these points.
p+ p p- MetalSaliciden- n n+Oxide
n-well p-well
Poly
ShallowTrench
Isolation
SidewallSpacers Polycide
Top Metal
SecondLevel Metal
FirstLevelMetal
Tungsten Plugs
Protective Insulator Layer
Substrate
Inter-mediateOxideLayers
060405-05
Metal Vias Metal Via
p+
Polycide
TungstenPlugs
Gate Ox
Salicide Salicide SalicideSalicide
TungstenPlugs
TungstenPlug
n+ n+p+ p+
ShallowTrench
Isolation
ShallowTrench
Isolation
p+n+
DC and AC GroundAC Ground
DC Ground
VDD GRD
GRD
Lecture 110 – Linear Circuit Models (3/24/10) Page 110-26
CMOS Analog Circuit Design © P.E. Allen - 2010
Grounds that are Not GroundsBecause of the resistance of “wires”, current flowing through a wire can cause a voltagedrop.An example of good and badpractice: Circuit
A
Bad:
IA IA+IB IA+IB+IC
R R R
Better:
CircuitB
CircuitC
CircuitA
IAIB
IC
3R2R
R
CircuitB
CircuitC
Best:
CircuitA
R
CircuitB
CircuitC
IA R RIB IC
050305-04
Lecture 110 – Linear Circuit Models (3/24/10) Page 110-27
CMOS Analog Circuit Design © P.E. Allen - 2010
Kelvin ConnectionsAvoid unnecessary ohmic drops.
A B A B
Kelvin ConnectionOhmic Connection 041223-12
X Y
In the left-hand connection, an IR drop is experienced between X and Y causing thepotentials at A and B to be slightly different.For example, let the current be 100μA and the metal be 30m /sq. Suppose that thedistance between X and Y is 100 squares. Therefore, the IR drop is
100μA x 30m /sq. x 100sq. = 0.3mV
Lecture 110 – Linear Circuit Models (3/24/10) Page 110-28
CMOS Analog Circuit Design © P.E. Allen - 2010
SUBSTRATE NOISE INTERFERENCEMethods of Substrate Injection
• Hot carrier
• Leakage
• Minority Carrier
• Displacement Current (large devices)
Lecture 110 – Linear Circuit Models (3/24/10) Page 110-29
CMOS Analog Circuit Design © P.E. Allen - 2010
Other Methods of Substrate Injection
Lecture 110 – Linear Circuit Models (3/24/10) Page 110-30
CMOS Analog Circuit Design © P.E. Allen - 2010
Illustration of Noise Interference Mechanism – No Epi
Lecture 110 – Linear Circuit Models (3/24/10) Page 110-31
CMOS Analog Circuit Design © P.E. Allen - 2010
Illustration of Noise Interference Mechanism – With Epi
Lecture 110 – Linear Circuit Models (3/24/10) Page 110-32
CMOS Analog Circuit Design © P.E. Allen - 2010
How is Noise Injected into Components?MOSFETs:Injection occurs by the bulk effect on thethreshold and across the depletioncapacitance.
BJTs:Injection primarily across the depletioncapacitance.
Passives:
Lecture 110 – Linear Circuit Models (3/24/10) Page 110-33
CMOS Analog Circuit Design © P.E. Allen - 2010
Isolation TechniquesIsolation techniques include both layout and circuit approaches to isolating quiet fromnoisy circuits.
ISOLATION TECHNIQUES
Lecture 110 – Linear Circuit Models (3/24/10) Page 110-34
CMOS Analog Circuit Design © P.E. Allen - 2010
Isolation Techniques – Guard Rings• Collect the majority/minority carriers in the substrate• Connect the guard rings to external potentials through conductors with
- Minimum resistance
- Minimum inductance v = Ldidt
Lecture 110 – Linear Circuit Models (3/24/10) Page 110-35
CMOS Analog Circuit Design © P.E. Allen - 2010
Isolation Techniques - LayoutSeparation:
Physical separation – works well for non-epi, less for epiTrenches:
Good if filled with a dielectric, not good if filled with aconductor.
Layout:Common centroid geometry doesnot help.Keep contact and via resistance to aminimum.Wells help to isolate (deep n-well)
Lecture 110 – Linear Circuit Models (3/24/10) Page 110-36
CMOS Analog Circuit Design © P.E. Allen - 2010
Isolation Techniques - Noise Insensitive Circuit Design• Design for high power supply rejection ratio (PSRR)• Correlated sampling techniques – eliminate low frequency noise• Use “quiet” digital logic (power supply current remains constant)• Use differential signal processing techniques.Example of a 4th order Sigma Delta modulator using differential circuits:
CIRCUIT TECHNIQUES
Lecture 110 – Linear Circuit Models (3/24/10) Page 110-37
CMOS Analog Circuit Design © P.E. Allen - 2010
Noise Isolation Techniques - Reduction of Package Parasitics• Keep the lead
inductance to aminimum (multiplebond wires)
• Package selection
Leadless lead frame: Micro surface mount device:
Still hasbond wires Minimum
inductancepackage
Lecture 110 – Linear Circuit Models (3/24/10) Page 110-38
CMOS Analog Circuit Design © P.E. Allen - 2010
Summary of Substrate Interference• Methods to reduce substrate noise
1.) Physical separation2.) Guard rings placed close to the sensitive circuits with dedicated package pins.3.) Reduce the inductance in power supply and ground leads (best method)4.) Connect regions of constant potential (wells and substrate) to metal with as
many contacts as possible.• Noise Insensitive Circuit Design Techniques
1.) Design for a high power supply rejection ratio (PSRR)2.) Use multiple devices spatially distinct and average the signal and noise.3.) Use “quiet” digital logic (power supply current remains constant)4.) Use differential signal processing techniques.
• Some references1.) D.K. Su, M.J. Loinaz, S. Masui and B.A. Wooley, “Experimental Results and Modeling Techniques forSubstrate Noise in Mixed-Signal IC’s,” J. of Solid-State Circuits, vol. 28, No. 4, April 1993, pp. 420-430.2.) K.M. Fukuda, T. Anbo, T. Tsukada, T. Matsuura and M. Hotta, “Voltage-Comparator-BasedMeasurement of Equivalently Sampled Substrate Noise Waveforms in Mixed-Signal ICs,” J. of Solid-StateCircuits, vol. 31, No. 5, May 1996, pp. 726-731.3.) X. Aragones, J. Gonzalez and A. Rubio, Analysis and Solutions for Switching Noise Coupling in Mixed-Signal ICs, Kluwer Acadmic Publishers, Boston, MA, 1999.
Lecture 110 – Linear Circuit Models (3/24/10) Page 110-39
CMOS Analog Circuit Design © P.E. Allen - 2010
SUMMARY• Small signal models are a linear representation of the transistor electrical behavior• Including the transistor capacitors in the small signal model gives frequency dependence• Noise models include thermal and 1/f noise voltage or current spectral density models• Passive component models include the nonlinearity, small signal and noise models• Interconnects include metal, polysilicon, diffusion and vias• Electromigration occurs if the current density is too large causing a displacement of
metal• Substrate interference is due to interaction between various parts of an integrated circuit
via the substrate• Method to reduce substrate interference include:
- Physical separation- Guard rings- Reduced inductance in the power supply and ground leads- Appropriate contacts to the regions of constant potential- Reduce the source of interfering noise- Use differential signal processing techniques
Lecture 120 – Component Matching (3/25/10) Page 120-1
CMOS Analog Circuit Design © P.E. Allen - 2010
LECTURE 120 – COMPONENT MATCHINGLECTURE ORGANIZATION
Outline• Introduction• Electrical matching• Physical matching• SummaryCMOS Analog Circuit Design, 2nd Edition ReferencePages 56-59 and new material
Lecture 120 – Component Matching (3/25/10) Page 120-2
CMOS Analog Circuit Design © P.E. Allen - 2010
INTRODUCTIONWhat is Accuracy and Matching?
The accuracy of a quantity specifies the difference between the actual value of thequantity and the ideal or true value of the quantity.The mismatch between two quantities is the difference between the actual ratio of thequantities and the desired ratio of the two quantities.
Example:x1 = actual value of one quantityx2 = actual value of a second quantityX1 = desired value of the first quantityX2 = desired value of the second quantityThe accuracy of a quantity can be expressed as,
Accuracy = x - X
X = XX
The mismatch, , can be expressed as,
=
x2x1
-X2X1
X2X1
= X1x2X2x1
- 1
Lecture 120 – Component Matching (3/25/10) Page 120-3
CMOS Analog Circuit Design © P.E. Allen - 2010
Relationship between Accuracy and MatchingLet:
X1 = |x1 - X1| x1 = X1 ± X1
andX2 = |x2 – X2| x2 = X2 ± X2
Therefore, the mismatch can be expressed as,
= X1(X2 ± X2)X2(X1 ± X1) – 1 =
1 ±X2
X2
1 ±X1
X1
– 1 1 ±X2
X2 1 +-
X1X1
– 1
1 ± X2
X2 +-
X1X1
– 1 = ± X2
X2 +-
X1X1
Thus, the mismatch is approximately equal to the difference in the accuracies of x1 and x2assuming the deviations ( X) are small with respect to X.
Lecture 120 – Component Matching (3/25/10) Page 120-4
CMOS Analog Circuit Design © P.E. Allen - 2010
123456789
10
0 X0 1 2 3 4 5 6 7 8 9 10 1211
Num
ber
of S
ampl
es
041005-011314
Characterization of the MismatchMean of the mismatch for N samples-
m = 1N
i=1
N
i
Standard deviation of the mismatch for N samples-
s = = 1
N-1i=1
N( i - m )2
Example:
m = 25340 = 6.325 s = 2.115
Lecture 120 – Component Matching (3/25/10) Page 120-5
CMOS Analog Circuit Design © P.E. Allen - 2010
Motivation for Matching of ComponentsThe accuracy of analog signal processing is determined by the accuracy of gains and timeconstants. These accuracies are dependent upon:
Gain Ratios of components or areasTime constants Products of components or areas
Ratio Accuracy?
Actual Ratio = X1± X1X2± X2 =
X1X2
1±X1
X1
1±X2
X2
X1X2 1±
X1X1 1+-
X2X2
X1X2 1±
X1X1 +-
X2X2
If X1 and X2 match ( X1/X1 X2/X2), then the actual ratio becomes the ideal ratio.
Product Accuracy?
Product accuracy = (X1± X1)(X2± X2) = X1X2 1±X1
X1 1±X2
X2 X1X2 1±X1
X1 ±X2
X2
Unfortunately, the product cannot be accurately maintained in integrated circuits.
Lecture 120 – Component Matching (3/25/10) Page 120-6
CMOS Analog Circuit Design © P.E. Allen - 2010
Switched Capacitor CircuitsSwitched capacitor circuits offer a solution to the product accuracy problem.A switched capacitor replacement of aresistor:
The product of a resistor, R1, and a capacitor,C2, now become,
R1C2 = TcC1 C2 =
1fcC1 C2 =
C2fcC1
The accuracy of the time constant (product) now becomes,C2fcC1 1±
C2C2 +-
C1C1 +-
fcfc
Assuming the clock frequency is accurate and larger than the signal bandwidth, then timeconstants in analog signal processing can be accurately matched by ratios of elements.
060316-06
+
−v1
+
−v2
φ1 φ2
C1+
−v1
+
−v2
R1= C1
Tc
φ1
φ2Tc
Lecture 120 – Component Matching (3/25/10) Page 120-7
CMOS Analog Circuit Design © P.E. Allen - 2010
Types of Mismatches1.) Those controlled or influenced by electrical design
- Transistor operation- Circuit techniques- Correction/calibration techniques
2.) Those controlled or influenced by physical design- Random statistical fluctuations (microscopic fluctuations and irregularities)- Process bias (geometric variations)- Pattern shift (misalignment)- Diffusion interactions- Stress gradients and package shifts- Temperature gradients and thermoelectrics- Electrostatic interactions
Lecture 120 – Component Matching (3/25/10) Page 120-8
CMOS Analog Circuit Design © P.E. Allen - 2010
ELECTRICAL MATCHINGMatching PrincipleAssume that two transistors are matched (large signal model parameters are equal).Then if all terminal voltages of one transistor are equal to the terminal voltages of theother transistor, then the terminal currents will be matched.
Q1 Q2
iC1 iC2iB1 iB2
iE1 iE2
M1 M2
iD1 iD2
041005-02
Note that the terminals may be physically connected together or at the same potential butnot physically connected together.
Lecture 120 – Component Matching (3/25/10) Page 120-9
CMOS Analog Circuit Design © P.E. Allen - 2010
Examples of the Matching Principle
VB
iD1 iD2
M1 M2
M3 M4
+
-Vio
M5M1 M2
M3 M4
VB
iD1 iD2
041005-03
iD1 iD2
M1 M2+
-Vio
M5
Cascode current mirror:The key transistors are M1 and M2. The gates and sources are physically connected
and the drains are equal due to M3 and M4 gate-source drops. As a result, iD1 will bevery close to iD2.
Differential amplifier:When iD1 and iD2 are equal, the fact that the drains of M1 and M2 are equal should
give the smallest value of the input offset voltage, Vio.
Note: Since the drain voltages of M3 and M4 in both circuits are not necessarily equal,the gate-source voltages of M3 and M4 are not exactly equal which cause the drainvoltages of M1 and M2 to not be exactly equal.
Lecture 120 – Component Matching (3/25/10) Page 120-10
CMOS Analog Circuit Design © P.E. Allen - 2010
Gate-Source MatchingNot as precise as the previous principle but useful for biasing applications.A. If the gate-source voltages of two or more FETs areequal and the FETs are matched and operating in thesaturation region, then the currents are related by the W/Lratios of the individual FETs. The gate-source voltagesmay be directly or indirectly connected.
iD1 = K’W1
2L1 (vGS1-VT1)2 (vGS1-VT1)2 =
2K’iD1
(W1/L1)
iD2 = K’W2
2L2 (vGS2-VT2)2 (vGS2-VT2)2 =
2K’iD2
(W2/L2)
If vGS1 = vGS2, then W2
L2iD1 =
W1
L1iD2 or iD1 =
W1/L1
W2/L2iD2
B. If the drain currents of two or more transistors are equal and the trans-istors are matched and operating in the saturation region, then the gate-source voltages are related by the W/L ratios (ignoring bulk effects).
If iD1=iD2, then
vGS1 = VT1+W2/L2
W1/L1(vGS2-VT2) or vGS1 = vGS2 if
W2
L2=
W1
L1
+
-
vGS1
iD1M1
iD2M2
+
-
vGS2
W1L1
W2L2
Fig. 290-02
+
-vGS1
iD1
iD2M2
+
-vGS2
W1L1
W2L2
Fig. 290-0
Lecture 120 – Component Matching (3/25/10) Page 120-11
CMOS Analog Circuit Design © P.E. Allen - 2010
Process Independent Biasing - MOSFETThe sensitivity of the bias points of all transistors depend on both the variation of thetechnological parameters and the accuracy of the biasing circuits.Gate-source voltage decomposition:
The gate-source voltage of the MOSFET can be divided into two parts:1.) The part necessary to form or enhance the channel, VT
2.) The part necessary to cause current toflow, VGS – VT = VON , called theoverdrive.
This overdrive can be expressed,
VON = VDS(sat) = 2ID
K’(W/L)The dependence of the bias point on the technology, VT, can be reduced by making VON= VDS(sat) >> VT.
This implies that small values of W/L are preferable. Unfortunately, this causes thetransconductance to become small if the current remains the same.
Lecture 120 – Component Matching (3/25/10) Page 120-12
CMOS Analog Circuit Design © P.E. Allen - 2010
Doubly Correlated SamplingIllustration of the use of chopper stabilization to remove the undesired signal, vu, from thedesired signal, vin. In this case, the undesired signal is the gate leakage current.
+1
-1t
T fc = 1
vin
vu
voutvB vC
Vin(f)
Vu(f)
VB(f)
ffc0 2fc
f
f
3fcVC(f)
ffc0 2fc 3fc
A1 A2
Clock
VA(f)
ffc0 2fc 3fc
vA
Fig. 7.5-8
Lecture 120 – Component Matching (3/25/10) Page 120-13
CMOS Analog Circuit Design © P.E. Allen - 2010
An Op Amp Using Doubly Correlated Sampling to Remove DC Offsets
051207-01
clkb
clk
clk
clkb
Inn
Inn
Inp
InpVDD
clk clkb
clkclkb
clkb
clkclk
clkb
Inn
Inn
Inp
InpVDD
VDD
M1 M2
M3 M4
Cc
M5
R1
R2
• Chopping with 50% duty cycle• All switches use thick oxide devices to reduce gate leakage• Gain gm1(rds2||rds4)gm5R2Will examine further in low noise op amps.
Lecture 120 – Component Matching (3/25/10) Page 120-14
CMOS Analog Circuit Design © P.E. Allen - 2010
Self-Calibration TechniquesThe objective of self-calibration is to increase the matching between two or morecomponents (generally passive).The requirements for self-calibration:1.) A time interval in which to perform the calibration2.) A means of adjusting the value of one or more of the components.
Fixed Component
AdjustableComponent
Comparisonof values
041007-05
Self-calibration can typically improve the matching by a factor of 2-3 bits (4-8).
Lecture 120 – Component Matching (3/25/10) Page 120-15
CMOS Analog Circuit Design © P.E. Allen - 2010
Example of Capacitor Self-CalibrationConsider the charge amplifier below that should have a gainof unity.
Assume the amplifier has a DC input offset voltage of Vio. The following shows how tocalibrate one (or both) of the capacitors.
+-
VRef
vOUT
C1
C2Vio
VRef -Vio+ -
Vio+-
Autozero Phase
+-
VRef
vOUT
C2
C1
Vio
Vio+-
+
-
Calibration Phase
VRef -Vio
vx
041007-07
In the calibration phase, vx, is:
vx = (VREF-Vio)C2
C1+C2 - (VREF-Vio)
C1C1+C2
= (VREF-Vio)C2-C1C1+C2
The correction circuitry varies C1 or C2 until vx = 0 as observed by vOUT.
+-
vIN vOUT
C1 C2
041007-06
Lecture 120 – Component Matching (3/25/10) Page 120-16
CMOS Analog Circuit Design © P.E. Allen - 2010
Variable ComponentsThe correction circuitry should be controlled by logic circuits so that the correction canbe placed into memory to maintain the calibration of the circuit during application.Implementation for C1 and C2 of the previous example:
C1
S1
C1
S2 S3
C1
2N
SN
C1 1-2K1 2K 2K+1
C1
2K+2
Capacitor C1
C2
S1
C2
S2 S3
C2
2N
SN
C2 1-2K1 2K 2K+1
C2
2K+2
Capacitor C2041007-08
K is selected to achieve the desired tolerance or variationN is selected to achieve the desired resolution (N > K)
Additional circuitry:Every self-calibration system will need additional logic circuits to sense when the valueof vx changes from positive to negative (or vice versa) and to store the switch settings inmemory to maintain the calibration.
Lecture 120 – Component Matching (3/25/10) Page 120-17
CMOS Analog Circuit Design © P.E. Allen - 2010
Basics of Dynamic Element Matching†
Dynamic element matching chooses different, approximately equal-valued elements torepresent a more precise value of a component as a function of time.Goal of dynamic element matching:Convert the error due to element mismatch from a dc offset into an ac signal of equivalentpower which can be removed by the appropriate means (doubly-correlated sampling,highpass filtering of a sigma-delta modulator, etc.)
† L. R. Carley, “A Noise-Shaping Coder Topology for 15+ Bit Converters, IEEE J. of Solid-State Circuits, vol. 24, no. 2, April 1989, pp. 267-273.
R0
S0VRef
i
All resistor are approximately equalvalued to within some tolerance
R1
S1
R2
S2
R3
S3
R4
S4
R5
S5
R6
S6
R7
S7
R8
S8
R9
S9 R0
S0
R1
S1
R2
S2
R3
S3
R4
S4
R5
S5
R6
S6
R7
S7
R8
S8
R9
S9
R0
S0
R1
S1
R2
S2
R3
S3
R4
S4
R5
S5
R6
S6
R7
S7
R8
S8
R9
S9Time t2
Time t1
041010-01
Lecture 120 – Component Matching (3/25/10) Page 120-18
CMOS Analog Circuit Design © P.E. Allen - 2010
How Dynamic Element Matching WorksAssume that we have three approximately equal elements with the following currents:
Element 1 = 0.99mA Element 2 = 1.03mA Element 3 = 0.98mA
Ideal current output level
Error when dynamicelement matching is not used
Error when dynamicelement matching is used
t0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
0
1
2
3
t0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
-1
0
+1
+2
Nor
mal
Err
or (
%)
Elements → 1 1 1 1 1 1 1,2 1,2 1,2 1,2 1,2 1,2 1,2,3
t0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
-1
0
+1
+2
Dyn
amic
Ele
men
tM
atch
ing
Err
or (
%)
Elements → 1 3 2 3 1 2 1,2 2,3 1,3 1,2 1,3 2,3 1,2,3+3
-2
-3 060405-06
Ide
al C
urre
nt (
mA
)
Lecture 120 – Component Matching (3/25/10) Page 120-19
CMOS Analog Circuit Design © P.E. Allen - 2010
Issues of Dynamic Element Matching• The selection of the elements must be truly random for the maximum benefit to occur.• If the number of elements is large this can be an overwhelming task to implement. An
approximation to random selection is the butterfly-type randomizer below:S1
S1
S2
S2
S3
S3
S4
S5
S5
S5
S6
S6
S7
S7
S8
S8
S9
S9
S10
S10
S11
S11
S12
S12
Three-stage, eight-linebutterfly randomizer.Each pair of switchesmarked with the samelabel is controlled toeither exchange the two signal lines or pass them directly to the next stage.
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7041010-03
• When using the dynamic element technique, one needs to be careful that the averagingactivity of the dynamic element matching process does not interfere with otheraveraging processes that might be occurring simultaneously (i.e. modulators).
• Other references:1.) B.H. Leung and s. Sutarja, “Multibit - A/D Converter Incorporating A Novel Class of Dynamic Element Matching
Techniques,” IEEE Trans. on Circuits and Systems-II, vol. 39, no. 1, Jan. 1992, pp. 35-51.
2.) R. Baird and T. Fiez, “Linearity Enhancement of Multibit - A/D and D/A Converters Using Data WeightedAveraging,” IEEE Trans. on Circuits and Systems-II, vol. 42, no. 12, Dec. 1995, pp. 753-762.
Lecture 120 – Component Matching (3/25/10) Page 120-20
CMOS Analog Circuit Design © P.E. Allen - 2010
PHYSICAL MATCHINGReview of Physical MatchingWe have examined these topics in previous lectures. To summarize, the sources ofphysical mismatch are:
- Random statistical fluctuations (microscopic fluctuations and irregularities)- Process bias (geometric variations)- Pattern shift (misalignment)- Diffusion interactions- Stress gradients and package shifts- Temperature gradients and thermoelectrics- Electrostatic interactions
Lecture 120 – Component Matching (3/25/10) Page 120-21
CMOS Analog Circuit Design © P.E. Allen - 2010
Rules for Resistor Matching†
1.) Construct matched resistors from the same material. 2.) Make matched resistors the same width. 3.) Make matched resistors sufficiently wide. 4.) Where practical, use identical geometries for resistors (replication principle) 5.) Orient resistors in the same direction. 6.) Place matched resistors in close physical proximity. 7.) Interdigitate arrayed resistors. 8.) Place dummy resistors on either end of a resistor array. 9.) Avoid short resistor segments.10.) Connect matched resistors in order to cancel thermoelectrics.11.) If possible place matched resistors in a low stress area (minimize pieozoresistance).12.) Place matched resistors well away from power devices.13.) Place precisely matched resistors on the axes of symmetry of the die.14.) Consider the influence of tank modulation for HSR resistors (the voltage modulation
of the reverse-biased depletion region changes the sheet resistivity).15.) Sectioned resistors are superior to serpentine resistors.
† Alan Hastings, Art of Analog Layout, 2n d ed, 2006, Pearson Prentice Hall, New Jersey
Lecture 120 – Component Matching (3/25/10) Page 120-22
CMOS Analog Circuit Design © P.E. Allen - 2010
Rules for Resistor Matching – Continued16.) Use poly resistors in preference to diffused resistors.17.) Do not allow the buried layer shadow to intersect matched diffused resistors.18.) Use electrostatic shielding where necessary.19.) Do not route unconnected metal over matched resistors.20.) Avoid excessive power dissipation in matched resistors.
Lecture 120 – Component Matching (3/25/10) Page 120-23
CMOS Analog Circuit Design © P.E. Allen - 2010
Rules for Capacitor Matching†
1.) Use identical geometries for matched capacitors (replication principle). 2.) Use square or octogonal geometries for precisely matched capacitors. 3.) Make matched capacitors as large as possible. 4.) Place matched capacitors adjacent to one another. 5.) Place matched capacitors over field oxide. 6.) Connect the upper electrode of a matched capacitor to the higher-impedance node. 7.) Place dummy capacitors around the outer edge of the array. 8.) Electrostatically shield matched capacitors. 9.) Cross-couple arrayed matched capacitors.10.) Account for the influence of the leads connecting to matched capacitors.11.) Do not run leads over matched capacitors unless they are electrostatically shielded.12.) Use thick-oxide dielectrics in preference to thin-oxide or composite dielectrics.13.) If possible, place matched capacitors in areas of low stress gradients.14.) Place matched capacitors well away from power devices.15.) Place precisely matched capacitors on the axes of symmetry for the die.
† Alan Hastings, Art of Analog Layout, 2n d ed, 2006, Pearson Prentice Hall, New Jersey
Lecture 120 – Component Matching (3/25/10) Page 120-24
CMOS Analog Circuit Design © P.E. Allen - 2010
Mismatched TransistorsAssume two transistors have vDS1 = vDS2, K1’ K2’ and VT1 VT2. Therefore we have
iOiI =
K2’(vGS - VT2)2
K1’(vGS - VT1)2
How do you analyze the mismatch? Use plus and minus worst case approach. Define K’ = K’2-K’1 and K’ = 0.5(K2’+K1’) K1’= K’-0.5 K’ and K2’= K’+0.5 K’
VT = VT2-VT1 and VT = 0.5(VT1+VT2) VT1 =VT -0.5 VT and VT2=VT+0.5 VT
Substituting these terms into the above equation gives,
iOiI =
(K’+0.5 K’)(vGS - VT - 0.5 VT )2
(K’-0.5 K’)(vGS - VT + 0.5 VT)2 =
1 +K’
2K’ 1 -VT
2(vGS-VT)2
1 -K’
2K’ 1 +VT
2(vGS-VT)2
Assuming that the terms added to or subtracted from “1” are smaller than unity givesiOiI ≈ 1 +
K’2K’ 1 +
K’2K’ 1 -
VT
2(vGS-VT)2
1 -VT
2(vGS-VT)2
1 + K’
K’ - 2 VT
(vGS-VT)
If K’/K’ = ±5% and VT/(vGS-VT) = ±10%, then iO/iI 1 ± 0.05 ±(-0.20) = 1±(0.25)
Lecture 120 – Component Matching (3/25/10) Page 120-25
CMOS Analog Circuit Design © P.E. Allen - 2010
Geometric EffectsHow does the size and shape of the transistor effect its matching?Gate Area:
Vth = CVth
W effLeffKp = K’
CKp
W effLeffW/W =
C W/W
W effLeff
where CVth, CKp and C W/W are constants determined by measurement.
Values from a 0.35μm CMOS technology:
Vth,NMOS = 10.6mV·μm
W effLeff Vth,PMOS =
8.25mV·μmW effLeff
and
W
W NMOS = 0.0056·μm
W effLeff
WW PMOS =
0.0011·μmW effLeff
The above results suggest that PMOS devices would be better matched than NMOSdevices in this technology.
Lecture 120 – Component Matching (3/25/10) Page 120-26
CMOS Analog Circuit Design © P.E. Allen - 2010
Pelgrom’s LawSpatial Averaging: Local and randomvariations decrease as the device sizeincreases, since the parameters “averageout” over a greater area.Pelgrom’s Law:
s2( P) = Ap
2
WL + Sp2 Dx
2
where,
P = mismatch in a parameter, PWL = width times the length of the device (effective Pelgrom area)Ap = proportionality constant between the standard deviation of DP and the area of
the deviceDx = distance between the matched devices
Sp = proportionality constant between the standard deviation of P and Dx
As Dx becomes large, the standard deviation tends to infinity which is not realistic.
Threshold mismatch for 0.18 m NMOS
Lecture 120 – Component Matching (3/25/10) Page 120-27
CMOS Analog Circuit Design © P.E. Allen - 2010
Rules for Transistor Matching†
1.) Use identical finger geometries. 2.) Use large active areas. 3.) For voltage matching, keep VGS-VT, small ( i.e. 0.1V). 4.) For current matching, keep VGS-VT, large (i.e. 0.5V). 5.) Orient the transistors in the same direction. 6.) Place the transistors in close proximity to each other. 7.) Keep the layout of the matched transistors as compact as possible. 8.) Where practical use common centroid geometry layouts. 9.) Place dummy segments on the ends of arrayed transistors.10.) Avoid using very short or narrow transistors.11.) Place transistors in areas of low stress gradients.12.) Do not place contacts on top of active gate area.13.) Keep junctions of deep diffusions as far away from the active gate area as possible.14.) Do not route metal across the active gate region.15.) Place precisely matched transistors on the axes of symmetry of the die.16.) Do not allow the buried layer shadow to intersect the active gate area.17.) Connect gate fingers using metal connections.
† Alan Hastings, Art of Analog Layout, 2n d ed, 2006, Pearson Prentice Hall, New Jersey
Lecture 120 – Component Matching (3/25/10) Page 120-28
CMOS Analog Circuit Design © P.E. Allen - 2010
SUMMARY• IC technology offers poor absolute values but good relative values or matching• In analog circuits, gains are determined by ratios (good matching) and time constants
are determined by products (poor matching)• Electrical matching is determined in the electrical design phase
- Matching due to equal terminal voltages- Matching due to process independent biasing- Doubly correlated sampling- Self-calibration techniques- Dynamic element matching
• Physical matching is determined in the physical design phase- Random statistical fluctuations (microscopic fluctuations and irregularities)
- Process bias (geometric variations)- Pattern shift (misalignment)- Diffusion interactions - Stress gradients and package shifts- Temperature gradients and thermoelectrics- Electrostatic interactions
Lecture130 – Computer Models and Extraction of Simple Large Signal Model (3/25/10) Page 130-1
CMOS Analog Circuit Design © P.E. Allen - 2010
LECTURE 130 – COMPUTER MODELS AND EXTRACTION OFTHE SIMPLE LARGE SIGNAL MODEL
LECTURE ORGANIZATIONOutline• Computer Models• Extraction of a large signal model for hand calculations• Extraction of the simple model for short channel MOSFETs• SummaryCMOS Analog Circuit Design, 2nd Edition ReferencePages 92-97 and 744-753
Lecture130 – Computer Models and Extraction of Simple Large Signal Model (3/25/10) Page 130-2
CMOS Analog Circuit Design © P.E. Allen - 2010
COMPUTER MODELSFET Model Generations• First Generation – Physically based analytical model including all geometry
dependence.• Second Generation – Model equations became subject to mathematical conditioning for
circuit simulation. Use of empirical relationships and parameter extraction.• Third Generation – A return to simpler model structure with reduced number of
parameters which are physically based rather than empirical. Uses better methods ofmathematical conditioning for simulation including more specialized smoothingfunctions.
Performance Comparison of Models (from Cheng and Hu, MOSFET Modeling & BSIM3Users Guide)
Model MinimumL (μm)
MinimumTox (nm)
ModelContinuity
iD Accuracy inStrong Inversion
iD Accuracy inSubthreshold
Small signalparameter
Scalability
MOS1 5 50 Poor Poor Not Modeled Poor PoorMOS2 2 25 Poor Poor Poor Poor FairMOS3 1 20 Poor Fair Poor Poor PoorBSIM1 0.8 15 Fair Good Fair Poor FairBSIM2 0.35 7.5 Fair Good Good Fair Fair
BSIM3v2 0.25 5 Fair Good Good Good GoodBSIM3v3 0.15 4 Good Good Good Good Good
Lecture130 – Computer Models and Extraction of Simple Large Signal Model (3/25/10) Page 130-3
CMOS Analog Circuit Design © P.E. Allen - 2010
First Generation ModelsLevel 1 (MOS1)• Basic square law model based on the gradual channel approximation and the square law
for saturated drain current.• Good for hand analysis.• Needs improvement for deep-submicron technology (must incorporate the square law to
linear shift)Level 2 (MOS2)• First attempt to include small geometry effects• Inclusion of the channel-bulk depletion charge results in the familiar 3/2 power terms• Introduced a simple subthreshold model which was not continuous with the strong
inversion model.• Model became quite complicated and probably is best known as a “developing ground”
for better modeling techniques.Level 3 (MOS3)• Used to overcome the limitations of Level 2. Made use of a semi-empirical approach. • Added DIBL and the reduction of mobility by the lateral field.• Similar to Level 2 but considerably more efficient.• Used binning but was poorly implemented.
Lecture130 – Computer Models and Extraction of Simple Large Signal Model (3/25/10) Page 130-4
CMOS Analog Circuit Design © P.E. Allen - 2010
Second Generation ModelsBSIM (Berkeley Short-Channel IGFET Model)• Emphasis is on mathematical conditioning for circuit simulation• Short channel models are mostly empirical and shifts the modeling to the parameter
extraction capability• Introduced a more detailed subthreshold current model with good continuity• Poor modeling of channel conductanceHSPICE Level 28• Based on BSIM but has been extensively modified.• More suitable for analog circuit design• Uses model binning• Model parameter set is almost entirely empirical• User is locked into HSPICE• Model is proprietaryBSIM2• Closely based on BSIM• Employs several expressions developed from two dimensional analysis• Makes extensive modifications to the BSIM model for mobility and the drain current• Uses a new subthreshold model• Output conductance model makes the model very suitable for analog circuit design
Lecture130 – Computer Models and Extraction of Simple Large Signal Model (3/25/10) Page 130-5
CMOS Analog Circuit Design © P.E. Allen - 2010
Third Generation ModelsBSIM2 – Continued• The drain current model is more accurate and provides better convergence• Becomes more complex with a large number of parameters• No provisions for variations in the operating temperatureBSIM3• This model has achieved stability and is being widely used in industry for deep
submicron technology.• Initial focus of simplicity was not realized.MOS Model 9• Developed at Philips Laboratory• Has extensive heritage of industrial use• Model equations are clean and simple – should be efficientOther Candidates• EKV (Enz-Krummenacher-Vittoz) – fresh approach well suited to the needs of analog
circuit design
Lecture130 – Computer Models and Extraction of Simple Large Signal Model (3/25/10) Page 130-6
CMOS Analog Circuit Design © P.E. Allen - 2010
BSIM2 ModelGeneric composite expression for the model parameters:
X = Xo + LXLeff
+ WXWeff
whereXo = parameter for a given W and LLX (WX) = first-order dependence of X on L (W)
Modeling features of BSIM2:Mobility• Mobility reduction by the vertical and the lateral fieldDrain Current• Velocity saturation• Linear region drain current• Saturation region drain current• Subthreshold current
iDS = μoCoxWeff
Leff·
kTq
evGS-Vt-Voff
n · 1 - eqVDS/kT
whereVoff = VOF + VOFB ·vBS + VOFD ·vDS and n = NO +
NBPHI - vBS
+ ND ·vDS
Lecture130 – Computer Models and Extraction of Simple Large Signal Model (3/25/10) Page 130-7
CMOS Analog Circuit Design © P.E. Allen - 2010
BSIM2 Output Conductance Model
050829-01
Rout
vDSvDS(sat)00
LinearRegion(Triode)
Channellength
modulation(CLM)
Saturation(DIBL) Substrate
currentinduced
bodyeffect
(SCBE)
Draincurrent
5V
• Drain-Induced Barrier Lowering (DIBL) – Lowering of the potential barrier at thesource-bulk junction allowing carriers to traverse the channel at a lower gate biasthan would otherwise be expected.
• Substrate Current-Induced Body Effect (SCBE) – The high field near the drainaccelerates carriers to high energies resulting in impact ionization which generates ahole-electron pair (hot carrier generation). The opposite carriers are swept into thesubstrate and have the effect of slightly forward-biasing the source-substrate junctionThis reduces the threshold voltage and increases the drain current.
Charge Model• Eliminates the partitioning choice (50%/50% is used)• BSIM charge model better documented with more options
Lecture130 – Computer Models and Extraction of Simple Large Signal Model (3/25/10) Page 130-8
CMOS Analog Circuit Design © P.E. Allen - 2010
BSIM2 Basic Parameter Extraction• A number of devices with different W/L are fabricated and measured
Weff,3
Weff,2
Weff,1
Weff
Leff,2Leff,1 Leff,3 Leff,4Leff
3 4
8
1211
7
109
5 6
1 2
• A long, wide device is used as the base to add geometry effects as corrections.• Procedure:
1.) Oxide thickness and the differences between the drawn and effective channeldimensions are provided as process input.2.) A long, wide device is used to determine some base parameters which are used asthe starting point for each individual device extraction in the second phase.3.) In the second phase, a set of parameters is extracted independently for each deviceThis phase represents the fitting of the data for each independent device to the intrinsicequation structure of the model4.) In the third phase, the compiled parameters from the second phase are used todetermine the geometry parameters. This represents the imposition of the extrinsicstructure onto the model.
Lecture130 – Computer Models and Extraction of Simple Large Signal Model (3/25/10) Page 130-9
CMOS Analog Circuit Design © P.E. Allen - 2010
BSIM3 ModelThe background for the BSIM3 model and the equations are given in detail in the textMOSFET Modeling & BSIM3 User’s Guide, by Y. Cheng and C. Hu, Kluwer AcademicPublishers, 1999.The short channel effects included in the BSIM3 model are:• Normal and reverse short-channel and narrow-width effects on the threshold.• Channel length modulation (CLM).• Drain induced barrier lowering (DIBL).• Velocity saturation.• Mobility degradation due to the vertical electric field.• Impact ionization.• Band-to-band tunneling.• Velocity overshoot.• Self-heating.1.) Channel quantization.2.) Polysilicon depletion.
Lecture130 – Computer Models and Extraction of Simple Large Signal Model (3/25/10) Page 130-10
CMOS Analog Circuit Design © P.E. Allen - 2010
BSIM3v3 Model Equations for Hand CalculationsIn strong inversion, approximate hand equations are:
iDS = μeffCox W eff
Leff
1
1+vDS
EsatLeff
vGS -Vth -AbulkvDS
2 vDS , vDS < VDS(sat)
iDS = WeffvsatCox[vGS – Vth – AbulkVDS(sat)] 1+vDS - VDS(sat)
VA , vDS > VDS(sat)
where
VDS(sat) = EsatLeff(vGS-Vth)
AbulkEsatLeff + (vGS-Vth)
Leff = Ldrawn – 2dL
W eff = Wdrawn – 2dW
Esat = Electric field where the drift velocity (v) saturates
vsat = saturation velocity of carriers in the channel
μ = μeff
1+(Ey/Esat) μeff = 2vsat
Esat
Note: Assume Abulk 1 and extract Vth and VA.
Lecture130 – Computer Models and Extraction of Simple Large Signal Model (3/25/10) Page 130-11
CMOS Analog Circuit Design © P.E. Allen - 2010
MOSIS Parametric Test Results
http://www.mosis.org/ RUN: T02D VENDOR: TSMC TECHNOLOGY: SCN025 FEATURE SIZE: 0.25 microns
INTRODUCTION: This report contains the lot average results obtained by MOSIS from measurements of MOSIStest structures on each wafer of this fabrication lot. SPICE parameters obtained from similar measurements on aselected wafer are also attached.COMMENTS: TSMC 0251P5M.TRANSISTOR PARAMETERS W/L N-CHANNEL P-CHANNEL UNITSMINIMUM 0.36/0.24 Vth 0.54 -0.50 voltsSHORT 20.0/0.24 Idss 557 -256 uA/um Vth 0.56 -0.56 volts Vpt 7.6 -7.2 voltsWIDE 20.0/0.24 Ids0 6.6 -1.5 pA/umLARGE 50.0/50.0 Vth 0.47 -0.60 volts Vjbkd 5.8 -7.0 volts Ijlk -25.0 -1.1 pA Gamma 0.44 0.61 V0.5
K’ (Uo*Cox/2) 112.0 -23.0 uA/V2
Lecture130 – Computer Models and Extraction of Simple Large Signal Model (3/25/10) Page 130-12
CMOS Analog Circuit Design © P.E. Allen - 2010
0.25μm BSIM3v3.1 NMOS Parameters.MODEL CMOSN NMOS ( LEVEL = 49+VERSION = 3.1 TNOM = 27 TOX = 5.7E-9+XJ = 1E-7 NCH = 2.3549E17 VTH0 = 0.4273342+K1 = 0.3922983 K2 = 0.0185825 K3 = 1E-3+K3B = 2.0947677 W0 = 2.171779E-7 NLX = 1.919758E-7+DVT0W = 0 DVT1W = 0 DVT2W = 0+DVT0 = 7.137212E-3 DVT1 = 6.066487E-3 DVT2 = -0.3025397+U0 = 403.1776038 UA = -3.60743E-12 UB = 1.323051E-18+UC = 2.575123E-11 VSAT = 1.616298E5 A0 = 1.4626549+AGS = 0.3136349 B0 = 3.080869E-8 B1 = -1E-7+KETA = 5.462411E-3 A1 = 4.653219E-4 A2 = 0.6191129+RDSW = 345.624986 PRWG = 0.3183394 PRWB = -0.1441065+WR = 1 WINT = 8.107812E-9 LINT = 3.375523E-9+XL = 3E-8 XW = 0 DWG = 6.420502E-10+DWB = 1.042094E-8 VOFF = -0.1083577 NFACTOR = 1.1884386+CIT = 0 CDSC = 2.4E-4 CDSCD = 0+CDSCB = 0 ETA0 = 4.914545E-3 ETAB = 4.215338E-4+DSUB = 0.0313287 PCLM = 1.2088426 PDIBLC1 = 0.7240447+PDIBLC2 = 5.120303E-3 PDIBLCB = -0.0443076 DROUT = 0.7752992+PSCBE1 = 4.451333E8 PSCBE2 = 5E-10 PVAG = 0.2068286+DELTA = 0.01 MOBMOD = 1 PRT = 0+UTE = -1.5 KT1 = -0.11 KT1L = 0+KT2 = 0.022 UA1 = 4.31E-9 UB1 = -7.61E-18+UC1 = -5.6E-11 AT = 3.3E4 WL = 0+WLN = 1 WW = -1.22182E-16 WWN = 1.2127+WWL = 0 LL = 0 LLN = 1+LW = 0 LWN = 1 LWL = 0+CAPMOD = 2 XPART = 0.4 CGDO = 6.33E-10+CGSO = 6.33E-10 CGBO = 1E-11 CJ = 1.766171E-3+PB = 0.9577677 MJ = 0.4579102 CJSW = 3.931544E-10+PBSW = 0.99 MJSW = 0.2722644 CF = 0+PVTH0 = -2.126483E-3 PRDSW = -24.2435379 PK2 = -4.788094E-4+WKETA = 1.430792E-3 LKETA = -6.548592E-3 )
Lecture130 – Computer Models and Extraction of Simple Large Signal Model (3/25/10) Page 130-13
CMOS Analog Circuit Design © P.E. Allen - 2010
0.25μm BSIM3v3.1 PMOS ParametersMODEL CMOSP PMOS ( LEVEL = 49+VERSION = 3.1 TNOM = 27 TOX = 5.7E-9+XJ = 1E-7 NCH = 4.1589E17 VTH0 = -0.6193382+K1 = 0.5275326 K2 = 0.0281819 K3 = 0+K3B = 11.249555 W0 = 1E-6 NLX = 1E-9+DVT0W = 0 DVT1W = 0 DVT2W = 0+DVT0 = 3.1920483 DVT1 = 0.4901788 DVT2 = -0.0295257+U0 = 185.1288894 UA = 3.40616E-9 UB = 3.640498E-20+UC = -6.35238E-11 VSAT = 1.975064E5 A0 = 0.4156696+AGS = 0.0702036 B0 = 3.111154E-6 B1 = 5E-6+KETA = 0.0253118 A1 = 2.421043E-4 A2 = 0.6754231+RDSW = 866.896668 PRWG = 0.0362726 PRWB = -0.293946+WR = 1 WINT = 6.519911E-9 LINT = 2.210804E-8+XL = 3E-8 XW = 0 DWG = -2.423118E-8+DWB = 3.052612E-8 VOFF = -0.1161062 NFACTOR = 1.2546896+CIT = 0 CDSC = 2.4E-4 CDSCD = 0+CDSCB = 0 ETA0 = 0.7241245 ETAB = -0.3675267+DSUB = 1.1734643 PCLM = 1.0837457 PDIBLC1 = 9.608442E-4+PDIBLC2 = 0.0176785 PDIBLCB = -9.605935E-4 DROUT = 0.0735541+PSCBE1 = 1.579442E10 PSCBE2 = 6.707105E-9 PVAG = 0.0409261+DELTA = 0.01 MOBMOD = 1 PRT = 0+UTE = -1.5 KT1 = -0.11 KT1L = 0+KT2 = 0.022 UA1 = 4.31E-9 UB1 = -7.61E-18+UC1 = -5.6E-11 AT = 3.3E4 WL = 0+WLN = 1 WW = 0 WWN = 1+WWL = 0 LL = 0 LLN = 1+LW = 0 LWN = 1 LWL = 0+CAPMOD = 2 XPART = 0.4 CGDO = 5.11E-10+CGSO = 5.11E-10 CGBO = 1E-11 CJ = 1.882953E-3+PB = 0.99 MJ = 0.4690946 CJSW = 3.018356E-10+PBSW = 0.8137064 MJSW = 0.3299497 CF = 0+PVTH0 = 5.268963E-3 PRDSW = -2.2622317 PK2 = 3.952008E-3
+WKETA = -7.69819E-3 LKETA = -0.0119828 )
Lecture130 – Computer Models and Extraction of Simple Large Signal Model (3/25/10) Page 130-14
CMOS Analog Circuit Design © P.E. Allen - 2010
EXTRACTION OF A LARGE SIGNAL MODEL FOR HAND CALCULATIONS
ObjectiveExtract a simple model that is useful for design from the computer models such asBSIM3.
Extraction for Short Channel Models
Procedure for extracting short channel models:
1.) Extract the square-law model parameters for a transistor with length at least 10times Lmin.
1.) Using the values of K’, VT , , and extract the model parameters for the followingmodel:
iD = K’
2[1 + (vGS-VT)] WL [ vGS – VT]2(1+ vDS)
Adjust the values of K’, VT , and as needed.
Lecture130 – Computer Models and Extraction of Simple Large Signal Model (3/25/10) Page 130-15
CMOS Analog Circuit Design © P.E. Allen - 2010
Illustration of the Extraction Procedure
Choose L
Extract VT0, K', λ, γ and φ using thesimulator for the simple model
Use the appropriate optimization routine to find θand the new values for VT0, K', λ, γ and for the model
iD = K'2[1 + θ(vGS - VT)]
WL
(vGS - VT)2(1 + λvDS)
Computer Model foryour technology
Initial guesses for VT0, K', λ, γ and φ
VBSVGS
ID
04629-02
Lecture130 – Computer Models and Extraction of Simple Large Signal Model (3/25/10) Page 130-16
CMOS Analog Circuit Design © P.E. Allen - 2010
EXTRACTION OF THE SIMPLE, SQUARE-LAW MODEL
Characterization of the Simple Square-Law ModelEquations for the MOSFET in strong inversion:
iD = K’Weff
2Leff
(vGS - VT) 2(1 + vDS) (1)
iD = K’Weff
Leff
(vGS - VT)vDS -v
2DS2 (1 + vDS) (2)
where
VT = VT0 + [ 2| F| + vSB 2| F| ] (3)
Lecture130 – Computer Models and Extraction of Simple Large Signal Model (3/25/10) Page 130-17
CMOS Analog Circuit Design © P.E. Allen - 2010
Extraction of Model Parameters:
First assume that vDS is chosen such that the vDS term in Eq. (1) is much less than oneand vSB is zero, so that VT = VT0.Therefore, Eq. (1) simplifies to
iD = K’W eff2Leff
(vGS - VT0) 2 (4)
This equation can be manipulated algebraically to obtain the following
i1/2D =
K' Weff2Leff
1/2 vGS =
K' Weff2Leff
1/2 VT0 (5)
which has the formy = mx + b (6)
This equation is easily recognized as the equation for a straight line with m as the slopeand b as the y-intercept. Comparing Eq. (5) to Eq. (6) gives
y = i1/2D (7)
x = vGS (8)
m = K' Weff2Leff
1/2
and
b = -K' Weff
2Leff1/2
VT0
Lecture130 – Computer Models and Extraction of Simple Large Signal Model (3/25/10) Page 130-18
CMOS Analog Circuit Design © P.E. Allen - 2010
Illustration of K’ and VT Extraction
iD( )1/2
vDS>VDSAT
m=′ K Weff
2Leff
⎛ ⎝ ⎜
⎞ ⎠ ⎟ 1/2
vGS′ b =VT0
Weak inversionregion
Mobility degradationregion
00 AppB-01
Comments:• Stay away from the extreme regions of mobility degradation and weak inversion• Use channel lengths greater than Lmin
Lecture130 – Computer Models and Extraction of Simple Large Signal Model (3/25/10) Page 130-19
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 130-1 – Extraction of K’ and VT Using Linear RegressionGiven the following transistor data shown in Table 1 and linear regression formulas basedon the form,
y = mx + b (11)
and
m =
xi yi - ( xi yi)/n
x2i - ( xi)2/n
(12)
determine VT0 and K’W/2L. The data in Table 1 also give I1/2
D as a function of VGS.
Table 1 Data for Example 130-1
VGS (V) ID (μA) ID (μA)1/2 VSB (V)
1.000 0.700 0.837 0.0001.200 2.00 1.414 0.0001.500 8.00 2.828 0.0001.700 13.95 3.735 0.0001.900 22.1 4.701 0.000
Lecture130 – Computer Models and Extraction of Simple Large Signal Model (3/25/10) Page 130-20
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 130-1 – ContinuedSolutionThe data must be checked for linearity before linear regression is applied. Checkingslopes between data points is a simple numerical technique for determining linearity.Using the formula that
Slope = m = y
x =
ID2 - ID1
VGS2 - VGS1
Gives
m1 = 1.414 - 0.837
0.2 = 2.885 m2 = 2.828 - 1.414
0.3 = 4.713
m3 = 3.735 - 2.828
0.2 = 4.535 m4 = 4.701 - 3.735
0.2 = 4.830
These results indicate that the first (lowest value of VGS) data point is either bad, or at apoint where the transistor is in weak inversion. This data point will not be included insubsequent analysis. Performing the linear regression yields the following results.
VT0 = 0.898 V and K'Weff2Leff
= 21.92 μA/V2
Lecture130 – Computer Models and Extraction of Simple Large Signal Model (3/25/10) Page 130-21
CMOS Analog Circuit Design © P.E. Allen - 2010
Extraction of the Bulk-Threshold Parameter Using the same techniques as before, the following equation
VT = VT0 + [ 2| F| + vSB 2| F| ] is written in the linear form where
y = VT
x = 2| F| + vSB 2| F| (13)
m =
b = VT0
The term 2| F| is unknown but is normally in the range of 0.6 to 0.7 volts.
Procedure:
1.) Pick a value for 2| F|.
2.) Extract a value for .
3.) Calculate NSUB using the relationship, = 2 s i q NSUB
Cox
4.) Calculate F using the relationship, F = kTq ln
NSUB
ni
5.) Iterative procedures can be used to achieve the desired accuracy of and 2| F|.Generally, an approximate value for 2| F| gives adequate results.
Lecture130 – Computer Models and Extraction of Simple Large Signal Model (3/25/10) Page 130-22
CMOS Analog Circuit Design © P.E. Allen - 2010
Illustration of the Procedure for Extracting
A plot of iD versus vGS for different values of vSB used to determine is shown below.
iD( )1/2
vGSVT0 VT1 VT2 VT3 FigAppB-02
By plotting VT versus x of Eq. (13) one can measure the slope of the best fit line fromwhich the parameter can be extracted. In order to do this, VT must be determined atvarious values of vSB using the technique previously described.
Lecture130 – Computer Models and Extraction of Simple Large Signal Model (3/25/10) Page 130-23
CMOS Analog Circuit Design © P.E. Allen - 2010
Illustration of the Procedure for Extracting - ContinuedEach VT determined above must be plotted against the vSB term. The result is shownbelow. The slope m, measured from the best fit line, is the parameter .
VT VSB=1V m= γ
VSB =2VVSB =3V
VSB =0V
vSB +2 φF( )0.5− 2 φF( )
0.5FigAppB-03
Lecture130 – Computer Models and Extraction of Simple Large Signal Model (3/25/10) Page 130-24
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 130-2 – Extraction of the Bulk Threshold ParameterUsing the results from Ex. 130-1 and the following transistor data, determine the value of using linear regression techniques. Assume that 2| F| is 0.6 volts.
Table 2 Data for Example 130-2.
VSB (V) VGS (V) ID (μA)
1.000 1.400 1.431
1.000 1.600 4.55
1.000 1.800 9.44
1.000 2.000 15.95
2.000 1.700 3.15
2.000 1.900 7.43
2.000 2.10 13.41
2.000 2.30 21.2
Solution
Table 2 shows data for VSB = 1 volt and VSB = 2 volts. A quick check of the data in thistable reveals that ID versus VGS is linear and thus may be used in the linear regressionanalysis. Using the same procedure as in Ex. 1, the following thresholds are determined:VT0 = 0.898 volts (from Ex. 1), VT = 1.143 volts (@VSB = 1 V), and VT = 1.322 V (@VSB = 2V). Table 3 gives the value of VT as a function of [(2| F| + VSB)1/2 (2| F|)1/2 ] for the threevalues of VSB.
Lecture130 – Computer Models and Extraction of Simple Large Signal Model (3/25/10) Page 130-25
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 130-2 - ContinuedTable 3 Data for Example 130-2.
VSB (V) VT (V) [ 2| F| + VSB - 2| F| ] (V1/2)
0.000 0.898 0.0001.000 1.143 0.4902.000 1.322 0.838
With these data, linear regression must be performed on the data of VT versus [(2| F| +VSB)0.5 (2| F |)0.5]. The regression parameters of Eq. (12) are
xiyi = 1.668
xi yi = 4.466
x2i = 0.9423
( xi)2 = 1.764
These values give m = 0.506 = .
Lecture130 – Computer Models and Extraction of Simple Large Signal Model (3/25/10) Page 130-26
CMOS Analog Circuit Design © P.E. Allen - 2010
Extraction of the Channel Length Modulation Parameter, The channel length modulation parameter should be determined for all device lengthsthat might be used. For the sake of simplicity, Eq. (1) is rewritten as
iD = i'D= ' vDS + i'D
which is in the familiar linear form wherey = iD (Eq. (1))
x = vDS
m = i'Db = i'D (Eq. (1) with = 0)
i'Dm= λ
vDS
iD
i'D
Nonsaturationregion
Saturation region
AppB-03
By plotting iD versus vDS, measuring theslope of the data in the saturation region,and dividing that value by the y-intercept,
can be determined. The procedure isillustrated in the figure shown.
Lecture130 – Computer Models and Extraction of Simple Large Signal Model (3/25/10) Page 130-27
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 130-3 – Extraction of the Channel Length Modulation ParameterGiven the data of ID versus VDS in Table 4, determine the parameter .
Table 4 Data for Example 130-3.
ID (μA) 39.2 68.2 86.8 94.2 95.7 97.2 98.8 100.3VDS (V) 0.500 1.000 1.500 2.000 2.50 3.00 3.50 4.00
SolutionWe note that the data of Table 4 covers both the saturation and nonsaturation regions ofoperation. A quick check shows that saturation is reached near VDS = 2.0 V. To calculate
, we shall use the data for VDS greater than or equal to 2.5 V. The parameters of thelinear regression are
xiyi = 1277.85 xi yi = 5096.00
x2i = 43.5 ( xi)2 = 169These values result in m = I'D = 3.08 and b = I'D = 88, giving = 0.035 V-1.
The slope in the saturation region is typically very small, making it necessary to be carefuthat two data points taken with low resolution are not subtracted (to obtain the slope)resulting in a number that is of the same order of magnitude as the resolution of the datapoint measured. If this occurs, then the value obtained will have significant andunacceptable error.
Lecture130 – Computer Models and Extraction of Simple Large Signal Model (3/25/10) Page 130-28
CMOS Analog Circuit Design © P.E. Allen - 2010
EXTRACTION OF THE SIMPLE MODEL FOR SHORT CHANNEL MOSFETSExtraction for Short Channel MOSFETS
The model proposed is the following one which is the square-law model modified bythe velocity saturation influence.
iD = K’
2[1 + (vGS-VT)] WL [ vGS - VT]2(1+ vDS)
Using the values of K’, VT , , and extracted previously, use an appropriate extractionprocedure to find the value of adjusting the values of K’, VT , and as needed.
Comments:
• We will assume that the bulk will be connected to the source or the standardrelationship between VT and VBS can be used.
• The saturation voltage is still given by
VDS( sat) = VGS - VT
Lecture130 – Computer Models and Extraction of Simple Large Signal Model (3/25/10) Page 130-29
CMOS Analog Circuit Design © P.E. Allen - 2010
Example of a Genetic Algorithm†
1.) To use this algorithm or any other, use the simulator and an appropriate short-channel model (BSIM3) to generate a set of data for the transconductance (iD vs. vGS)and output characteristics (iD vs. vDS) of the transistor with the desired W and Lvalues.
2.) The best fit to the data is found using a genetic algorithm. The constraints on theparameters are obtained from experience with prior transistor parameters and are:
10E-6 < < 610E-6, 1 < < 5, 0 < VT < 1, and 0 < < 0.53,) The details of the genetic algorithm are:
Gene structure is A = [ , , VT, fitness]. A mutation was done by varying all fourparameters. A weighted sum of the least square errors of the data curves was used asthe error function. The fitness of a gene was chosen as 1/error.
4.) The results for an extraction run of 8000 iterations for an NMOS transistor is shownbelow.
(A/V2) VT(V) (V-1)294.1x10-6 1.4564 0.4190 0.1437
5.) The results for a NMOS and PMOS transistor are shown on the following pages.
† Anurag Kaplish, “Parameter Optimization of Deep Submicron MOSFETS Using a Genetic Algorithm,” May 4, 2000, Special Project Report, School
of ECE, Georgia Tech.
Lecture130 – Computer Models and Extraction of Simple Large Signal Model (3/25/10) Page 130-30
CMOS Analog Circuit Design © P.E. Allen - 2010
Extraction Results for an NMOS Transistor with W = 0.32μm and L = 0.18μmTransconductance:
Lecture130 – Computer Models and Extraction of Simple Large Signal Model (3/25/10) Page 130-31
CMOS Analog Circuit Design © P.E. Allen - 2010
Extraction Results for an NMOS Transistor with W = 0.32μm and L = 0.18μmOutput:
Lecture130 – Computer Models and Extraction of Simple Large Signal Model (3/25/10) Page 130-32
CMOS Analog Circuit Design © P.E. Allen - 2010
Extraction Results for an PMOS Transistor with W = 0.32μm and L = 0.18μmTransconductance:
Lecture130 – Computer Models and Extraction of Simple Large Signal Model (3/25/10) Page 130-33
CMOS Analog Circuit Design © P.E. Allen - 2010
Extraction Results for an PMOS Transistor with W = 0.32μm and L = 0.18μmOutput:
Lecture130 – Computer Models and Extraction of Simple Large Signal Model (3/25/10) Page 130-34
CMOS Analog Circuit Design © P.E. Allen - 2010
SUMMARY• Models are much improved for efficient computer simulation• Output conductance model is greatly improved• Narrow channel transistors have difficulty with modeling• Can have discontinuities at bin boundaries• The BSIM model is a complex model, difficult to understand in detail• The simple large signal model can be extracted from any computer model• Extract the model at the desired channel length for the design• Short channel technology can be modeled by finding the by any optimization routine
Lecture 140 – The MOS Switch and Diode (3/25/10) Page 140-1
CMOS Analog Circuit Design © P.E. Allen - 201
LECTURE 140 – THE MOS SWITCH AND MOS DIODELECTURE ORGANIZATION
Outline• MOSFET as a switch• Influence of the switch resistance• Influence of the switch capacitors
- Channel injection- Clock feedthrough
• Using switches at reduced values of VDD
• MOS Diode• SummaryCMOS Analog Circuit Design, 2nd Edition ReferencePages 113-124
Lecture 140 – The MOS Switch and Diode (3/25/10) Page 140-2
CMOS Analog Circuit Design © P.E. Allen - 201
Switch Model• An ideal switch is a short-circuit when ON
and an open-circuit when OFF. VC =controlling terminal for the switch (VC high switch ON, VC low switch OFF)
• Actual switch: ron = resistance of the switch when ON roff = resistance of the switch when OFF VOS = offset voltage when the switch is ON Ioff = offset current when the switch is OFF IA and IB are leakage currents to ground CA and CB are capacitances to ground CAC and CBC = parasitic capacitorsbetween the control terminal and switchterminals
+
−VC
A B
IAB
VAB
RAB = 0Ω(VC= high)
RAB = ∞Ω(VC= low)
060526−03
060526-04
CAC CBC
CA CBVC
IA
rOFF
IOFF
rON
CAB
VOS
A B
C IB
Lecture 140 – The MOS Switch and Diode (3/25/10) Page 140-3
CMOS Analog Circuit Design © P.E. Allen - 201
MOS Transistor as a Switch
060526-05
Bulk
A B
(S/D) (D/S)
C (G)
A B
On Characteristics of a MOS SwitchAssume operation in active region (vDS < vGS - VT) and vDS small.
iD = μCoxW
L (vGS - VT) -vDS
2 vDS μCoxW
L (vGS - VT)vDS
Thus, RON
vDS
iD
=1
μCox
WL (v
GS- V
T)
OFF Characteristics of a MOS SwitchIf vGS < VT, then iD = IOFF = 0 when vDS 0V.If vDS > 0, then
ROFF
1iD =
1IOFF
Lecture 140 – The MOS Switch and Diode (3/25/10) Page 140-4
CMOS Analog Circuit Design © P.E. Allen - 201
MOS Switch Voltage RangesIf a MOS switch is used to connect two circuits that can have analog signal that
vary from 0 to 1V, what must be the value of the bulk and gate voltages for the switch towork properly?
Circuit1
Circuit2
(0 to 1V)
(S/D)
(0 to 1V)
(D/S)
Bulk
GateFig.4.1-3
• To insure that the bulk-source and bulk-drain pn junctions are reverse biased, the bulkvoltage must be less than the minimum analog signal for a NMOS switch.
• To insure that the switch is on, the gate voltage must be greater than the maximumanalog signal plus the threshold for a NMOS switch.
Therefore:VBulk 0VVGate(on) > 1V + VT
VGate(off) 0V
Unfortunately, the large value of reverse bias bulk voltage causes the threshold voltageto increase.
Lecture 140 – The MOS Switch and Diode (3/25/10) Page 140-5
CMOS Analog Circuit Design © P.E. Allen - 201
Current-Voltage Characteristics of a NMOS SwitchThe following simulated output characteristics correspond to triode operation of theMOSFET.
SPICE Input File:MOS Switch On CharacteristicsM1 1 2 0 3 MNMOS W=1U L=1U.MODEL MNMOS NMOS VTO=0.7, KP=110U,+LAMBDA=0.04, GAMMA=0.4 PHI=0.7VDS 1 0 DC 0.0
VGS 2 0 DC 0.0VBS 3 0 DC -5.0.DC VDS -1 1 0.1 VGS 1 5 0.5.PRINT DC ID(M1).PROBE.END
-1V -0.5V 0V 0.5V 1V
100μA
50μA
0μA
-50μA
-100μA
VGS=1.0V
VGS=1.5V
VGS=2.0VVGS=5.0V
VGS=2.5VVGS=3.0VVGS=3.5VVGS=4.0VVGS=4.5V
Fig. 4.1-4vDS
iD
Lecture 140 – The MOS Switch and Diode (3/25/10) Page 140-6
CMOS Analog Circuit Design © P.E. Allen - 201
MOS Switch ON Resistance as a Function of Gate-Source Voltage
1V 1.5V 2V 2.5V 3V 3.5V 4V 4.5V 5V
100kΩ
10kΩ
1kΩ
100Ω
10Ω
W/L = 1μm/1μm
W/L = 5μm/1μm
W/L = 10μm/1μm
W/L = 50μm/1μm
MO
SFE
ET
On
Res
ista
nce
VGS Fig. 4.1-5
SPICE Input File:MOS Switch On Resistance as a f(W/L)M1 1 2 0 0 MNMOS W=1U L=1UM2 1 2 0 0 MNMOS W=5U L=1UM3 1 2 0 0 MNMOS W=10U L=1UM4 1 2 0 0 MNMOS W=50U L=1U.MODEL MNMOS NMOS VTO=0.7, KP=110U,
+LAMBDA=0.04, GAMMA=0.4, PHI=0.7VDS 1 0 DC 0.001VVGS 2 0 DC 0.0.DC VGS 1 5 0.1.PRINT DC ID(M1) ID(M2) ID(M3) ID(M4).PROBE.END
Lecture 140 – The MOS Switch and Diode (3/25/10) Page 140-7
CMOS Analog Circuit Design © P.E. Allen - 201
Influence of the ON Resistance on MOS SwitchesFinite ON Resistance:
ExampleInitially assume the capacitor is uncharged. If VGate(ON) is 5V and is high for 0.1μs,find the W/L of the MOSFET switch that will charge a capacitance of 10pF in fivetime constants.
SolutionThe time constant must be 100ns/5 = 20ns. Therefore RON must be less than20ns/10pF = 2k . The ON resistance of the MOSFET (for small vDS) is
RON = 1
KN’(W/L)(VGS-VT) WL =
1RON·KN’(VGS-VT) =
12k ·110μA/V2·4.3
=1.06Comments:• It is relatively easy to charge on-chip capacitors with minimum size switches.• Switch resistance is really not constant during switching and the problem is more
complex than above.
Lecture 140 – The MOS Switch and Diode (3/25/10) Page 140-8
CMOS Analog Circuit Design © P.E. Allen - 201
Including the Influence of the Varying On ResistanceGate-source Constant
gON(t) = K’W
L (vGS(t)-VT) -0.5vDS(t)
gON(aver.) = 1
rON(aver.)
gON(0) + gON( )2
= K’W2L (VGS-VT) -
K’WVDS(0)4L +
K’W2L (VGS-VT)
= K’W
L (VGS-VT) - K’WVDS(0)
4LGate-source Varying
gON = K’W2L [VGS(0)-VT] -
K’WVDS(0)4L +
K’W2L [VGS( )-vIN-VT]
VGS=5V
VDS
ID t=0
t=∞
gON(0)
gON(∞)
Fig. 4.1-7vDS(0)vDS(∞)
VGS=5V
VGS=5V-vIN
VDS
ID t=0
t=∞
gON(0)
gON(∞)
Fig. 4.1-8vDS(0)vDS(∞)
VGate
C vC(0) = 0-
+
+
-vGS(t)
vIN
Lecture 140 – The MOS Switch and Diode (3/25/10) Page 140-9
CMOS Analog Circuit Design © P.E. Allen - 201
Example 1 - Switch ON ResistanceAssume that at t = 0, the gate of the switch shown
is taken to 5V. Design the W/L value of the switch todischarge the C1 capacitor to within 1% of its initialcharge in 10ns. Use the MOSFET parameters of Table3.1-2.Solution
Note that the source of the NMOS is on the rightand is always at ground potential so there is no bulk effect as long as the voltage acrossC1 is positive. The voltage across C1 can be expressed as
vC1(t) = 5exp-t
RONC1
At 10ns, vC1 is 5/100 or 0.05V. Therefore,
0.05=5exp-10-8
RON10-11 = 5exp
-103
RON exp(GON103)=100 GON =
ln(100)103
=0.0046S
0.0046 = K’W
L (VGS-VT) - K’WVDS(0)
4L = 110x10-6·4.3-110x10-6·5
4WL = 356x10-6
WL
Thus, WL =
0.0046
356x10-6 = 13.71 14
+-+
5V-
0V
5V
C1 =10pF
C2 = 10pF
+ -0V
Fig.4.1-9
vout(t)
Lecture 140 – The MOS Switch and Diode (3/25/10) Page 140-10
CMOS Analog Circuit Design © P.E. Allen - 201
Influence of the OFF State on MOS SwitchesThe OFF state influence is primarily in any current that flows from the terminals of theswitch to ground.An example might be:
vin vout
CH
+-RBulk
+
-vCH
Fig. 4.1-10
Typically, no problems occur unless capacitance voltages are held for a long time. Forexample,
vout(t) = vCH e-t/(RBulkCH)
If RBulk 109 and CH = 10pF, the time constant is 109·10-11 = 0.01seconds
Lecture 140 – The MOS Switch and Diode (3/25/10) Page 140-11
CMOS Analog Circuit Design © P.E. Allen - 201
Influence of Parasitic CapacitancesThe parasitic capacitors have two influences:• Parasitics to ground at the switch terminals (CBD and CBS) add to the value of the
desired capacitors.This problem is solved by the use of stray-insensitive switched capacitor circuits
• Parasitics from gate to source and drain cause charge injection and clockfeedthrough onto or off the desired capacitors.This problem can be minimized but not eliminated.
Model for studying gate capacitance:
Lecture 140 – The MOS Switch and Diode (3/25/10) Page 140-12
CMOS Analog Circuit Design © P.E. Allen - 201
Channel Charge InjectionConsider the simple switch configuration shown:
When the switch is ON, a charge is stored in thechannel which is equal to,
Qch = -WLCox(VH-vin-VT)
where VH is the value of the clock waveform when the switch is on (VH VDD)
When the switch turns OFF, this charge is injectedinto the source and drain terminals as shown.Assuming the charge splits evenly, then the change ofvoltage across the capacitor, CL, is
V = Qch2CL
= -WLCox(VH-vin-VT)
2CL
The charge injection does not influence vin because itis a voltage source.
060613-03
vin CL
ClkON
OFF OFF
060613-04
vin CL
ClkON
OFF
e-e-
vin ΔV
Lecture 140 – The MOS Switch and Diode (3/25/10) Page 140-13
CMOS Analog Circuit Design © P.E. Allen - 201
Clock FeedthroughIn addition to the charge injection, the overlap capacitors of the MOSFET couple theturning off part of the clock to the load capacitor. This is called clock feedthrough.The model for this case is given as:
Fig. 4.1-16
VS +VTSwitch OFF
A
B
C
CLvin ≈VS ≈VD
Chargeinjection
COLCOL
VS +VT
COL
CL
+
-
vCL
VL
VS
VT
VLCircuit at theinstant gate
reaches VS +VT
The gate decrease from B to C is modeled as a negative step of magnitude VS +VT - VL.The output voltage on the capacitor after opening the switch is,
vCL = CL
COL+CLVS-
COL
COL+CLVT -(VS+VT -VL)
COL
COL+CL VS-(VS+2VT -VL)
COL
CL
if COL < CL.
Therefore the error voltage is,
Verror -(VS + 2VT – VL)COLCL
= -(vin + 2VT – VL) COLCL
Lecture 140 – The MOS Switch and Diode (3/25/10) Page 140-14
CMOS Analog Circuit Design © P.E. Allen - 201
Modeling the Influence of Charge Injection and Clock FeedthroughThe influence of change injection and clock feedthrough on a switch is a complexanalysis which is better suited for computer analysis. Here we will attempt to developan understanding sufficient to show ways of reducing these effects.
To begin the model development, there are two cases of charge injection dependingupon the transition rate when the switch turns off.
1.) Slow transition time – the charge in the channel can react instantaneously tochanges in the turning-off, gate-source voltage.2.) Fast transition time – the charge in the channel cannot react fast enough to respondto the changes in the turning-off, gate-source voltage.
Lecture 140 – The MOS Switch and Diode (3/25/10) Page 140-15
CMOS Analog Circuit Design © P.E. Allen - 201
Slow Transition TimeConsider the following switch circuit:
vin+VT
Switch ONA
B
C
CLvin
Fig. 4.1-13
vin+VTSwitch OFF
A
B
C
CLvin
Chargeinjection
1.) During the on-to-off transition time from A to B, the charge injection is absorbed bythe low impedance source, vin.
2.) The switch turns off when the gate voltage is vin+VT (point B).
3.) From B to C the switch is off but the gate voltage is changing. As a result chargeinjection occurs to CL.
Lecture 140 – The MOS Switch and Diode (3/25/10) Page 140-16
CMOS Analog Circuit Design © P.E. Allen - 201
Fast Transition TimeFor the fast transition time, the rate of transition is faster than the channel time constantso that some of the charge during the region from point A to point B is injected onto CL
even though the transistor switch has not yet turned off.
vin+VT
Switch ONA
B
C
CLvin
Fig. 4.1-14
vin+VTSwitch OFF
A
B
C
CLvin
Chargeinjection
Chargeinjection
Lecture 140 – The MOS Switch and Diode (3/25/10) Page 140-17
CMOS Analog Circuit Design © P.E. Allen - 201
A Quantized Model of Charge Injection/Clock Feedthrough†
Approximate the gate transition as a staircase and discretized in voltage as follows:Voltage
vin+VT
vCL
vGATE
Discretized Gate Voltage
tSlow Transition
Voltage
vin+VT
vCL
vGATE
Discretized Gate Voltage
tFast Transition
Chargeinjectiondue to fasttransition
Fig 4.1-15
vin vin
The time constant of the channel, Rchannel·Cchannel, determines whether or not thecapacitance, CL, fully charges during each voltage step.
† B.J. Sheu and C. Hu, “Switched-Induced Error Voltage on A Switched Capacitor,” IEEE J. Solid-State Circuits, Vol. SC-19, No. 4, pp. 519-525,
August 1984.
Lecture 140 – The MOS Switch and Diode (3/25/10) Page 140-18
CMOS Analog Circuit Design © P.E. Allen - 201
Analytical Expressions to Approximate Charge Injection/Clock FeedthroughAssume the gate voltage is making a transition from high, VH, to low, VL.
vGate = vG(t) = VH – Ut where U = magnitude of the slope of vG(t)
Define VHT = VH - VS - VT and = K’W
L .
The error in voltage across CL, Verror, is given below in two terms. The first termcorresponds to the feedthrough that occurs while the switch is still on and the secondterm corresponds to feedthrough when the switch is off.
1.) Slow transition occurs when V
2HT
2CL >> U.
Verror = -W·CGD0 +
Cchannel
2CL
UCL
2 - W·CGD0
CL (VS+2VT -VL)
2.) Fast transition occurs when V
2HT
2CL << U.
Verror = -W·CGD0 +
Cchannel
2CL
VHT -V
3HT
6U·CL -
W·CGD0CL
(VS+2VT -VL)
Lecture 140 – The MOS Switch and Diode (3/25/10) Page 140-19
CMOS Analog Circuit Design © P.E. Allen - 201
Example 2 - Calculation of Charge Feedthrough ErrorCalculate the effect of charge feedthroughon the previous circuit where VS = 1V, CL
= 1pfF, W/L = 0.8μm/0.8μm, and VG isgiven below for the two cases. Usemodel parameters from Tables 3.1-2 and3.2-1. Neglect L and W effects.Solution
Case 1:
The value of U is equal to 5V/0.2nS or 25x109. Next we must test to see if theslow or fast transition time is appropriate. First calculate the value of VT as
VT = VT0 + 2| F| -VBS - 2| F| = 0.7 + 0.4 0.7+1 - 0.4 0.7 = 0.887V
Therefore,
which corresponds to the fast transition case. Using the previous expression gives,Verror =
vG
t0.2ns 50ns
5V
0V
Case 2
Case 1
Fig. 4.1-17
-176x10-18+0.5(1.58x10-15)
1x10-123.113-
3.32x10-3
30x10-3 -
176x10-18
1x10-12(1+1.774-0) = -3.39mV
VHT =VH-VS-VT = 5-1-0.887=3.113V V
2HT
2CL =
110x10-6·3.1132
2·1pF = 5.32x108< 25x109
Lecture 140 – The MOS Switch and Diode (3/25/10) Page 140-20
CMOS Analog Circuit Design © P.E. Allen - 201
Example 2 - ContinuedCase 2:
In this case U is equal to 5V/50ns or 1x108 which means that the slow transitioncase is valid (1x108 < 5.32x108).Using the previous expression gives,
Verror = -176x10-18+0.5(1.58x10-15)
1x10-12
314x10-6
220x10-6-176x10-18
1x10-12(1+1.774-0)
= -1.64mVComment:
These results are not expected to give precise answers regarding the amount ofcharge feedthrough one should expect in an actual circuit. Rather, they are a guide tounderstand the effects of various circuit elements and terminal conditions in order tominimize unwanted behavior by design techniques.
Lecture 140 – The MOS Switch and Diode (3/25/10) Page 140-21
CMOS Analog Circuit Design © P.E. Allen - 201
Solutions to Charge Injection1.) Use minimum size switches to reduce the overlap capacitances and/or increaseCL.
2.) Use a dummy compensating transistor.
φ1 φ1
M1 MD
W1L1
WDLD
= W12L1
Fig. 4.1-19
• Requires complementary clocks• Complete cancellation is difficult and may in fact may make the feedthrough
worse3.) Use complementary switches (transmission gates)4.) Use differential implementation of switched capacitor circuits (probably the best
solution)
Lecture 140 – The MOS Switch and Diode (3/25/10) Page 140-22
CMOS Analog Circuit Design © P.E. Allen - 201
Input-Dependent Charge InjectionExamination of the error voltage reveals that,
Error voltage = Component independent of input + Component dependent on inputThis only occurs for switches that are floating and is due to the fact that the inputinfluences the voltage at which the transistor switches (vin VS VD). Leads tospurious responses and other undesired results.Solution:Use delayed clocks to re-move the input-depend-ence by removing thepath for injection fromthe floating switches.Assume that Cs ischarged to Vin (both 1
and 1d are high):
1.) 1 opens, no input-dependent feedthrough because switch terminals (S3) are at ground potential.
2.) 1d opens, no feedthrough occurs because there is no current path (except throughsmall parasitic capacitors).
Ci
1
21d
2
CsVin
LC
VoutS1S2 S3
S4
1
2
1d
Clock Delay
t
t
t
Fig. 4.1-20
Lecture 140 – The MOS Switch and Diode (3/25/10) Page 140-23
CMOS Analog Circuit Design © P.E. Allen - 201
CMOS Switches (Transmission Gate)
VDD
Clock
Clock
A B
Fig. 4.1-21
BAClock
Clock
Advantages:• Feedthrough somewhat diminished• Larger dynamic range• Lower ON resistanceDisadvantages:• Requires a complementary clock• Requires more area
Lecture 140 – The MOS Switch and Diode (3/25/10) Page 140-24
CMOS Analog Circuit Design © P.E. Allen - 201
Example 3 - Charge Injection for a CMOS SwitchCalculate the effect of charge feedthrough on thecircuit shown below. Assume that U = 5V/50ns =108V/s, vin = 2.5V and ignore the bulk effect. Usethe model parameters from Tables 3.1-2 and 3.2-1.SolutionFirst we must identify the transition behavior. Forthe NMOS transistor we have
NV2
HTN2CL
= 110x10-6·(5-2.5-0.7)2
2·10-12 = 1.78x108
For the PMOS transistor, noting thatVHTP = VS - |VTP| - VL = 2.5-0.7-0 = 1.8
we havePV
2HTP
2CL =
50x10-6·(1.8)2
2·10-12 = 8.10x107 . Thus, the NMOS transistor is in the
slow transition and the PMOS transistor is in the fast transition regimes.
vin
M2
M1
0.8μm0.8μm
0.8μm0.8μm
+
-
vCL
CL =1pF
5V
0Vvin-|VTP|
5V
0Vvin+VTN
Fig. 4.1-18
Lecture 140 – The MOS Switch and Diode (3/25/10) Page 140-25
CMOS Analog Circuit Design © P.E. Allen - 201
Example 3 - ContinuedError due to NMOS (slow transition):
Verror(NMOS) = -176x10-18+0.5(1.58x10-15)
10-12
·108·10-12
2·110x10-6 -
176x10-18
10-12 (2.5+1.4-0)
= -1.840mVError due to PMOS (fast transition):
Verror(PMOS)=176x10-18+0.5(1.58x10-15)
10-121.8-
50x10-6(1.8)3
6·108·10-12+
176x10-18
10-12(5+1.4-2.5)
= 1.956mVNet error voltage due to charge injection is 116μV. This will vary with VS.
Lecture 140 – The MOS Switch and Diode (3/25/10) Page 140-26
CMOS Analog Circuit Design © P.E. Allen - 201
Dynamic Range of the CMOS SwitchThe switch dynamic range is therange of voltages at the switchterminals (VA VB=VA,B) overwhich the ON resistance is small.
VDD
A B
VDD
M1
M21μAVA,B
Fig. 4.1-22
Spice File:
Simulation CMOS transmission switch resistanceM1 1 3 2 0 MNMOS L=1U W=10UM2 1 0 2 3 MPMOS L=1U W=10U.MODEL MNMOS NMOS VTO=0.7, KP=110U,+LAMBDA=0.04, GAMMA=0.4, PHI=0.7.MODEL MPMOS PMOS VTO=-0.7, KP=50U,+ LAMBDA=0.05, GAMMA=0.5, PHI=0.8
VDD 3 0VAB 1 0IA 2 0 DC 1U.DC VAB 0 3 0.02 VDD 1 3 0.5.PRINT DC V(1,2).END
Result: Low ON resistance over a wide voltage range is difficult as the power supplydecreases.
0
10kΩ
0V 0.5V 1V 1.5V 2V 2.5V 3V
8kΩ
6kΩ
4kΩ
2kΩ
VDD=1V
VDD=1.5V
VDD=2V
VDD=2.5VVDD=3V
VDD=1V
VDD=1.5V
VDD=2V
Switc
h O
n R
esis
tanc
e
VA,B (Common mode voltage) Fig. 4.1-22A
Lecture 140 – The MOS Switch and Diode (3/25/10) Page 140-27
CMOS Analog Circuit Design © P.E. Allen - 201
Charge Pumps for Switches with Low Power Supply VoltagesAs power supply voltages decrease below 2V, it becomes difficult to keep the
switch on at a low value of on-resistance over the range of the power supply. The resultis that rON becomes a function of the signal amplitude and produces harmonics.
Consequently, charge pumps are used to provide a gate voltage above power supply.Principle of a charge pump:
vOUT = 2VDD C2
C2 + CL + CNMOSswitch
Lecture 140 – The MOS Switch and Diode (3/25/10) Page 140-28
CMOS Analog Circuit Design © P.E. Allen - 201
Simulation of the Charge Pump Circuit†
Circuit:VDD
C1
VSS
M1 CLK_out
CLK_in
M2M3
M4
Fig. 4.1-23
CLK_outM5
M6
C1
Simulation:
† T.B. Cho and R.R. Gray, “A 10b, 20 Msample/s, 35mW Pipeline A/D Converter,” IEEE J. of Solid-State Circuits, Vol. 30, No. 3m March 1995, pp.166-172.
3.0
2.0
1.0
0.0
-1.00.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0
Vol
ts
Time (μs)
Input
Output
Fig. 4.1-24
Lecture 140 – The MOS Switch and Diode (3/25/10) Page 140-29
CMOS Analog Circuit Design © P.E. Allen - 201
Bootstrapped Switches with High Reliability†
In the previous charge pump switch driver, the amount of gate-source drivedepends upon the input signal and can easily cause reliability problems because itbecomes too large for low values of input signal.
The solution to this problem is a bootstrapped switch as shown.
Actual bootstrap switch:
† A.M. Abo and P.R. Gray, “A 1.5V, 10-bit, 14.3-MS/s CMOS Pipeline Analog-to-Digital Converter, IEEE J. of Solid-State Circuits, Vol. 34, No. 5,May 1999, pp. 599-605.
VDD
OFF ON Fig. 4.1-25VDD
φ
φ
φ
φ
C1 C2C3
M1 M2 M3 M4
M5
M12
M8
M13
M9
M7 M10
M11S D
VDD
vg
vg
t
Input Signal
Boosted Clock
VDD
Fig. 4.1-26
low: M7 and M10 make vg=0 and C3 charges to VDD, high: C3 connected to vGS11.
M7 reduces the vDS and vGS of M10 when = 0. M13 ensures that vGS8 VDD.
The parasitics at the source of M11 require this node to be driven from a low impedance.
Lecture 140 – The MOS Switch and Diode (3/25/10) Page 140-30
CMOS Analog Circuit Design © P.E. Allen - 201
MOSFET DIODEMOS Diode
When the MOSFET has the gate connected to the drain, it acts like a diode withcharacteristics similar to a pn-junction diode.
+
vGS = v
-
i
+
vSG = v
-i
VT
i
vFig. 4-2-1
Note that when the gate is connected to the drain of an enhancement MOSFET, theMOSFET is always in the saturation region.
vDS vGS - VT vD - vS vG - vS - VT vD - vG -VT vDG -VT
Since VT is always greater than zero for an enhancement device, then vDG = 0 satisfiesthe conditions for saturation.• Works for NMOS or PMOS• Note that the drain could be VT less than the gate and still be in saturation
Lecture 140 – The MOS Switch and Diode (3/25/10) Page 140-31
CMOS Analog Circuit Design © P.E. Allen - 201
How Does the MOS Diode Compare with a pn Diode?The comparison is basically the difference between an exponential and a square-lawfunction. However, if the designer is willing to spend W/L, the comparison becomesmore interesting as shown below.
If the threshold voltage is less than 0.4V, the MOS diode is a clear winner over the pnjunction diode even for modest W/L ratios.
Lecture 140 – The MOS Switch and Diode (3/25/10) Page 140-32
CMOS Analog Circuit Design © P.E. Allen - 201
SUMMARY• Symmetrical switching characteristics• High OFF resistance• Moderate ON resistance (OK for most applications)• Clock feedthrough is proportional to size of switch (W) and inversely proportional
to switching capacitors.• Output offset due to clock feedthrough has 2 components:
Input dependentInput independent
• Complementary switches help increase dynamic range.
• Fully differential operation should minimize the clock feedthrough.
• As power supply reduces, floating switches become more difficult to fully turn on.• Switches contribute a kT/C noise which can get folded back into the baseband.• The gate-drain connected MOSFET can make a good diode realization
Lecture 150 – Resistor Implementations and Current Sinks and Sources (3/25/10) Page 150-1
CMOS Analog Circuit Design © P.E. Allen - 201
LECTURE 150 – RESISTOR IMPLEMENTATIONS ANDCURRENT SINKS AND SOURCES
LECTURE ORGANIZATIONOutline• Resistor implementations• Simple current sinks and sources• Improved performance current sinks and sources• SummaryCMOS Analog Circuit Design, 2nd Edition ReferencePages 126-134
Lecture 150 – Resistor Implementations and Current Sinks and Sources (3/25/10) Page 150-2
CMOS Analog Circuit Design © P.E. Allen - 201
RESISTOR IMPLEMENTATION USING MOSFETSReal Resistors versus MOSFET Resistors• Smaller in area than actual resistors• Can pass a large current through a large resistance without a large voltage drop
060526-10
iD
vDS
100μA
1V
MOSFET (rds = 100kΩ)
100kΩ Resistor
10μA10V
AC resistance = vds
id = 1
gds
where
gds 2 (VGS-VT)2 = ID
Lecture 150 – Resistor Implementations and Current Sinks and Sources (3/25/10) Page 150-3
CMOS Analog Circuit Design © P.E. Allen - 201
MOS Diode as a ResistorAC and DC resistance:
DC resistance = VDSID
= VTID
+ 2ID
Small-Signal Load (AC resistance):
060526-11
rds
D = G
S S
G
S
gmvgsvgs
+
-
vds
+
-
idD
S
D = G
AC resistance = vds
id = 1
gm + gds
1gm
wheregm = (VGS-VT) = 2 ID
Lecture 150 – Resistor Implementations and Current Sinks and Sources (3/25/10) Page 150-4
CMOS Analog Circuit Design © P.E. Allen - 201
Use of the MOSFET to Implement a Floating ResistorIn many applications, it is useful to implement a
resistance using a MOSFET. First, consider thesimple, single MOSFET implementation.
RAB = L
K’W(VGS - VT)
VBias
A B A B
Fig. 4.2-9
RAB
100μA
60μA
20μA
-20μA
-60μA
-100μA-1V -0.6V -0.2V 0.2V 0.6V 1V
VGS=2V
VGS=3V
VGS=4V
VGS=5V
VGS=10V
VGS=9V
VGS=8VVGS=7V
VGS=6V
Fig. 4.2-95
Lecture 150 – Resistor Implementations and Current Sinks and Sources (3/25/10) Page 150-5
CMOS Analog Circuit Design © P.E. Allen - 201
Cancellation of Second-Order Voltage Dependence – Parallel MOSFETsCircuit:
Assume both devices are non-saturated
iD1 = ß1 (vAB + VC - VT)vAB -vAB2
2
iD2 = ß2 (VC - VT)vAB -vAB2
2
iAB
= iD1 + iD2 = ß vAB2 + (VC - VT)vAB -vAB2
2 + (VC - VT)vAB -vAB2
2
iAB
= 2ß(VC - VT)vAB RAB
=1
2ß(VC - VT)
060526-12
M1
M2
VCA B A BRAB
+ -
vAB
iAB iAB
+ -vAB
VC
Lecture 150 – Resistor Implementations and Current Sinks and Sources (3/25/10) Page 150-6
CMOS Analog Circuit Design © P.E. Allen - 201
Parallel MOSFET PerformanceVoltage-Current Characteristic:
Vc=7V
VDS
0
I(VSENSE)
-2 -1 0 1 2
2mA
1mA
-1mA
-2mA
W=15u L=3uVBS=-5.0V
6V
5V
4V
3V
Fig. 4.1-11
SPICE Input File:NMOS parallel transistor realizationM1 2 1 0 5 MNMOS W=15U L=3UM2 2 4 0 5 MNMOS W=15U L=3U.MODEL MNMOS NMOS VTO=0.75, KP=25U, +LAMBDA=0.01,GAMMA=0.8 PHI=0.6VC 1 2E1 4 0 1 2 1.0VSENSE 10 2 DC 0
VDS 10 0VSS 5 0 DC -5.DC VDS -2.0 2.0 .2 VC 3 7 1.PRINT DC I(VSENSE).PROBE.END
Lecture 150 – Resistor Implementations and Current Sinks and Sources (3/25/10) Page 150-7
CMOS Analog Circuit Design © P.E. Allen - 201
SIMPLE CURRENT SINKS AND SOURCES
Ideal Current Sinks and SourcesWhat is an ideal current sink or source?
060527-01
Io
v
i
+
−v
i
Io
• Current is fixed at a value of Io• Voltage can be any value from + to -• Be careful when using a current sink or source to replace a MOSFET sink/source in
simulation
Lecture 150 – Resistor Implementations and Current Sinks and Sources (3/25/10) Page 150-8
CMOS Analog Circuit Design © P.E. Allen - 201
Characterization of MOSFET Sinks and SourcesA sink/source is characterized by two quantities:• rout - a measure of the “flatness” of the current sink/source (its independence of
voltage)• VMIN - the min. across the sink or source for which the current is no longer constant
NMOS Current Sink:
0601527-02
VDD
VGG
i
v+
-
VMINVGG
VGG-VT00
0
Slope = 1/rout
iDS= i
vDS = vVDD
VDD
Io
i
v+
-
Io
rout = 1
diD/dvDS =
1+ VDS
D
1ID and VMIN = VDS(sat) = VGS - VT0 = VGG - VT0
Note: The NMOS current sink can only have positive values of v.
Lecture 150 – Resistor Implementations and Current Sinks and Sources (3/25/10) Page 150-9
CMOS Analog Circuit Design © P.E. Allen - 201
PMOS Current Source
0601527-03
VDD
VGG
i
v+
-
VMINVGG
VGG-|VT0|0
0
Slope = 1/rout
iSD= i
vSD = vVDD
VDD
Io
i
v+
- Io
Lecture 150 – Resistor Implementations and Current Sinks and Sources (3/25/10) Page 150-10
CMOS Analog Circuit Design © P.E. Allen - 201
Gate-Source Voltage ComponentsIt is important to note that the gate-source voltage consists of two parts as illustratedbelow:
Fig. 280-03VT
ID
VGSvGS
iD
00
EnhanceChannel
W/L10W/L 0.1W/L
ProvideCurrent
VGS = VT0 + VON = Part to enhance the channel + Part to cause current flowwhere
VON = VDS(sat) = VGS - VT0
VMIN = VON = VDS(sat) =2ID
K’(W/L) for the simple current sink.
Note that VMIN can be reduced by using large values of W/L.
Lecture 150 – Resistor Implementations and Current Sinks and Sources (3/25/10) Page 150-11
CMOS Analog Circuit Design © P.E. Allen - 201
Simulation of a Simple MOS Current Sink
������
0
20
40
60
80
100
120
0 1 2 3 4 5
i OU
T (μ
A)
vOUT (Volts)
Slope = 1/Rout
Vmin
VGS1 =1.126V
iOUT
vOUT
+
-
10μm1μm
Comments:VMIN is too large - desire VMIN to approach zero, at least approach VCE(sat)
Slope too high - desire the characteristic to be flat implying very large outputresistance
(KN’ = 110μA/V2, VT = 0.7Vand = 0.04V-1) rds = 250k
Lecture 150 – Resistor Implementations and Current Sinks and Sources (3/25/10) Page 150-12
CMOS Analog Circuit Design © P.E. Allen - 201
How is VGG Implemented?
The only voltage source assumed available is VDD.
Therefore, VGG, can be implemented in many ways with the example below being oneway.
0601527-04
VDD
VGG
i
v+
- VBias=VGG
VDD
i
v+
-
R
+
-
Better and more stable implementations of VGG will be shown later.
Lecture 150 – Resistor Implementations and Current Sinks and Sources (3/25/10) Page 150-13
CMOS Analog Circuit Design © P.E. Allen - 201
IMPROVED PERFORMANCE CURRENT SINKSImproving the Performance of the Simple NMOS Current SinkThe simple NMOS current sink shown previously had two problems.1.) The value of VMIN may be too large.
2.) The output resistance (250k ) was too small.How can the designer solve these problems?1.) The first problem can be solved by increasing the W/L value of the NMOS transistor.
VMIN = VON = VDS(sat) =2ID
K’(W/L)In the simulation shown previously,
VMIN =2·100μA
110μA/V2·10 = 0.426V
We could decrease this to 0.1V with a W/L = 182.2.) How can the small output resistance be increased? Answer is feedback.
Lecture 150 – Resistor Implementations and Current Sinks and Sources (3/25/10) Page 150-14
CMOS Analog Circuit Design © P.E. Allen - 201
Blackman’s Formula for Finding the Resistance at a Port with Feedback†
Blackman’s formula to find the resistance at a port X, isbased on the following circuit:
The resistance seen looking into port X is given as,
Rx = Rx(k=0)1 + RR(port shorted)1 + RR(port opened)
The return ratio, RR, is found by changing the dependentsource to an independent source as shown:Therefore, the return ratio is defined as,
RR = - vcvc' = -
icic'
The key is to find a feedback circuit that when we calculate the RR, it is non-zero whenport X is shorted and zero when port X is opened. In this case, the resistance at port Xis
Rx = Rx(k=0)[1 + RR(port shorted)]
† R.B. Blackman, “Effect of Feedback on Impedance,” Bell Sys. Tech.J., Vol. 23, pp. 269-277, October 1943.
Lecture 150 – Resistor Implementations and Current Sinks and Sources (3/25/10) Page 150-15
CMOS Analog Circuit Design © P.E. Allen - 201
Identification of the Proper Type of FeedbackFor the port X, the circuit variables associated with the input port should be able to beexpressed as, Input Variable to Port X = Signal variable to the circuit – Feedback variablewhere the variables can be voltage or current.1.) Series feedback (variables
are voltage):
RR(Vx = 0) 0RR(Ix = 0) = 0 (Vin is disconnected
from Vfb)
2.) Shunt feedback (variablesare current):
RR(Vx = 0) = 0(Iin is disconnected from Ifb)
RR(Ix = 0) 0
We see that for series feedback RR(port opened) will be zero and for shunt feedbackthat RR(port shorted) will be zero.
Lecture 150 – Resistor Implementations and Current Sinks and Sources (3/25/10) Page 150-16
CMOS Analog Circuit Design © P.E. Allen - 201
Increasing the Output Resistance of the Simple Current SinkChoosing series feedback, we select the following circuit to boostthe output resistance of the simple current sink:Assume that we can neglect the bulk effect and find the inputresistance by 1.) small-signal analysis and 2.) return ratio method.1.) Small-signal Analysis:
vx = (ix + gmvs)rds + ixR
vx = (ix + gmixR)rds + ixR = ix(1 + R + gmrdsR)
Rx = vx
ix = 1 + R + gmrdsR gmrdsR
2.) Return Ratio: Rx(k=0) = Rx(gm=0) = rds + R
RR(vx = 0) = -vc
vc' = gm rdsRrds+R
RR(ix = 0) = 0
Rx = (rds + R) 1 + gm
rdsRrds+R
= 1 + R + gmrdsR gmrdsR
Lecture 150 – Resistor Implementations and Current Sinks and Sources (3/25/10) Page 150-17
CMOS Analog Circuit Design © P.E. Allen - 201
Cascode Current SinkReplacing R with the simplecurrent sink leads to a practicalimplementation shown as:
Small signal output resistance:Noting that vgs1 = vg2 = vb2 = 0 and writing a loop equation we get,
vout = (iout - gm2vgs2 - gmbs2vbs2)rds2 + rds1iout
However,vgs2 = 0 - vs2 = -ioutrds1 and vbs2 = 0 - vs2 = -ioutrds1
Therefore,vout = iout[rds1 + rds2 + gm2rds1rds2 + gmbs2rds1rds2]
or
rout = vout
iout = rds1 + rds2 + gm2rds1rds2 + gmbs2rds1rds2 gm2rds1rds2
A general principle is beginning to emerge:The output resistance of a cascode circuit R x (Common source voltage gain of thecascoding transistor)
+
vOUT
-
iOUT
M2
M1VGG2
VGG1
rds2
iout
+
vout
-
gm2vgs2 gmbs2vbs2
+
-
vs2
Fig. 280-11vgs1 =vg2 = vb2 = 0
gm1vgs1 rds1
Lecture 150 – Resistor Implementations and Current Sinks and Sources (3/25/10) Page 150-18
CMOS Analog Circuit Design © P.E. Allen - 201
Design of VGG1 and VGG2
060527-06
VGG2
VGG1
M2
+
−VGS2
+
−VDS1= VDS1(sat)
+
−VDS2 ≥VDS2(sat)
vOUT(min) = VDS1(sat)+VDS2(sat)
1.) VGG1 is selected to provide the desired current. M1 is assumed to be in saturation.
2.) VGG2 is selected to keep VDS1 as small as possible and still be in saturation.
VGG2 = VDS1(sat) + VGS2 = VDS1(sat) + VT + VDS2(sat)
If W1/L1 = W2/L2, then VGG2 = 2VDS(sat) + VT = 2VON + VT
Thus, for the previous NMOS current sink, VGG2 would be equal to,
VGG2 = 2(0.426) + 0.7 = 1.552V
Lecture 150 – Resistor Implementations and Current Sinks and Sources (3/25/10) Page 150-19
CMOS Analog Circuit Design © P.E. Allen - 201
Simulation of the Cascode CMOS Current SinkExample
Use the model parametersKN’=110μA/V2, VT = 0.7 and N =0.04V-1 to calculate (a) the small-signal output resistance for the simplecurrent sink if IOUT = 100μA and (b)the small-signal output resistance forthe cascode current sink with IOUT =100μA. Assume that all W/L valuesare 1.
Solution
(a) Using = 0.04 V-1 and IOUT =100μA gives rds1 = 250k = rds2. (b) Ignoring the bulk effect, we find that gm1 = gm2
= 469μS which gives rout = (250k )(469μS)(250k ) = 29.32M .
������������
0
20
40
60
80
100
120
0 1 2 3 4 5
i OU
T (μ
A)
vOUT (Volts)
Slope = 1/Rout
Vmin
VGG1 =1.126V
iOUT
vOUT
+
-
VGG2 =1.552V
All W/Ls are10μm/1μm
Fig. 280-12
Lecture 150 – Resistor Implementations and Current Sinks and Sources (3/25/10) Page 150-20
CMOS Analog Circuit Design © P.E. Allen - 201
High-Swing Cascode Current SinkThis current sink achieves the smallest possible VMIN.
Since
VON = 2ID
K’(W/L),then if L/W of M4is quadrupled, thenVON is doubled.
VMIN = 2VON.
ExampleUse the cascode current sink configuration above to design a current sink of 100μA
and a VMIN = 1V. Assume the device parameters of Table 3.1-2.
SolutionWith VMIN = 1V, choose VON = 0.5V. Assuming M1 and M2 are identical gives
WL =
2·IOUT
K’·VON2 =
2·100x10-6
110x10-6x0.25 = 7.27
W1
L1 =
W2
L2 =
W3
L3 = 7.27 and
W4
L4 = 1.82
060527-07
+
-
M2
M1
1/1
1/1
M31/1
1/4
M4
VDD VDD
iOUT
vOUT
+
-VON
+
-VON
+
-
VT+2VON
VT+VON+
-
VT+VON+
-
2VON0 vOUT
iOUT
VMIN
Lecture 150 – Resistor Implementations and Current Sinks and Sources (3/25/10) Page 150-21
CMOS Analog Circuit Design © P.E. Allen - 201
Improved High-Swing Cascode Current SinkBecause the drain-source voltages of thematching transistors, M1 and M3 are notequal, iOUT IREF.
To circumvent this problem the cascodecurrent sink shown is utilized:
Note that the drain-source voltage of M1 andM3 are identical causing iOUT to be areplication of IREF.
Design Procedure1.) Since VMIN = 2VON = 2VDS(sat), let VON = 0.5VMIN.
2.) VON = 2IREF
K’(W/L) W1
L1 =
W2
L2 =
W3
L3 =
W5
L5 =
2IREF
K’VON2 =
8IREF
K’VMIN2
3.) W4
L4 =
2IREF
K’(VGS4-VT)2 =
2IREF
K’(2VON)2 =
IREF
2K’VON2
060527-08
+
-
M2
M1
1/1
1/1
M3
1/1
1/4
M4
VDD VDD
iOUT
vOUT
+
-
VON
+
-
VON
+
-
VT+2VON
VT+VON+
-
VT+VON+
-+
-
VON
M5
1/1
-
+
-
VT
R1 R2
Lecture 150 – Resistor Implementations and Current Sinks and Sources (3/25/10) Page 150-22
CMOS Analog Circuit Design © P.E. Allen - 201
Signal Flow in TransistorsThe last example brings up an interesting and important point. This point is
illustrated by the following question, “How does IREF flow into the M3-M5combination of transistors since there is no path to the gate of M5?”Consider how signals flow in transistors:
D
G
S
+-
+
+
++
C
B
E
+-
+
+
++
Fig. 4.3-12B
Output Only
InputOnly
Output Only
InputOnly
Answer to the above question:As VDD increases (i.e. the circuit begins to operate),
IREF cannot flow into the drain of M5, so it flows throughthe path indicated by the arrow to the gate of M3. Itcharges the stray capacitance and causes the gate-sourcevoltage of M3 to increase to the exact value necessary tocause IREF to flow through the M3-M5 combination.
M3
VDD
+
-
IREF
M5
Fig. 4.3-12A
VT +2VON
VGS3
Lecture 150 – Resistor Implementations and Current Sinks and Sources (3/25/10) Page 150-23
CMOS Analog Circuit Design © P.E. Allen - 201
Example 150-1 - Design of a Minimum VMIN Current SinkAssume IREF = 100μA and design a cascode current sink with a VMIN = 0.3V using thefollowing parameters: VTO=0.7, KP=110U, LAMBDA=0.04, GAMMA=0.4, PHI=0.7
SolutionFrom the previous equations, we get
W1
L1 =
W2
L2 =
W3
L3 =
W5
L5 =
8IREF
K’VMIN 2 = 8·100
110·(0.3V)2 = 80.8 and
W4
L4 =
IREF
2K’VON 2 = 100
2·110·0.152 = 20.2
Simulation Results:
0
20
40
60
80
100
120
0 1 2 3 4 5vOUT(V)
i OU
T(μ
A)
VMIN
Fig. 290-06
Low Vmin Cascade Current Sink - Method No. 2M1 5 1 0 0 MNMOS W=81U L=1UM2 2 3 5 5 MNMOS W=81U L=1UM3 4 1 0 0 MNMOS W=81U L=1UM4 3 3 0 0 MNMOS W=20U L=1UM5 1 3 4 4 MNMOS W=81U L=1U.MODEL MNMOS NMOS VTO=0.7 KP=110U+LAMBDA=0.04 GAMMA=0.4 PHI=0.7VDD 6 0 DC 5VIIN1 6 1 DC 100UIIN2 6 3 DC 100UVOUT 2 0 DC 5.0.OP.DC VOUT 5 0 0.05.PRINT DC ID(M2)
.END
Lecture 150 – Resistor Implementations and Current Sinks and Sources (3/25/10) Page 150-24
CMOS Analog Circuit Design © P.E. Allen - 201
Self-Biased Cascode Current Sink†
The VT + 2VON bias voltage is developed through a seriesresistor.
Design procedure:Same as the previous except
R = VON
IREF =
VMIN
2IREF
For the previous example,
R = 0.3V
2·100μA = 1.5k
If the reference current is small, R can become large.
† T.L. Brooks and A.L. Westwick, “A Low-Power Differential CMOS Bandgap Reference,” Proc. of IEEE Inter. Solid-State Circuits Conf., Feb.
1994, pp. 248-249.
IREF
VDD
VT+2VON
R
iOU
M1 M2
M3 M4+
-VT
+
-
VON
+
-
VON
+
-
VONVT+VON
Fig. 290-
Lecture 150 – Resistor Implementations and Current Sinks and Sources (3/25/10) Page 150-25
CMOS Analog Circuit Design © P.E. Allen - 201
MOS Regulated Cascode Sink†
vOUT
VDD
M1 M2
M3
M4
M5M6M7
IREF
iOUT
VO1
+
-
IREF
IREF
Fig. 290-08
A
Increasing vGS3VGS3(max)
VGS3(norm)
VDS3(sat)�vDS3
VDS3(min)�
iD3
Comments:• Achieves very high output resistance by increasing the loop gain (return-ratio) due to
the M4-M5 inverting amplifier.
LG = gm3rds2
gm4
gds4+gds5
gm3rds2gm4rds4
2 If rds4 rds5, then rout
rds3gm3rds2gm4rds4
2
• M3 maintains “constant” current even though it is no longer in the saturation region.
† E. Sackinger and W. Guggenbuhl, “A Versatile Building Block: The CMOS Differential Difference Amplifier,” IEEE J. of Solid-State Circuits,
vol. SC-22, no. 2, pp. 287-294, April 1987.
Lecture 150 – Resistor Implementations and Current Sinks and Sources (3/25/10) Page 150-26
CMOS Analog Circuit Design © P.E. Allen - 201
Regulated Cascode Current Sink - ContinuedSmall signal model:
Solving for the output resistance:iout = gm3vgs3 + gds3(vout-vgs4)
Butvgs4 = ioutrds2
andvgs3 = vg3 - vs3 = -gm4(rds4||rds5)vgs4 - vgs4 = -rds2[1 + gm4(rds4||rds5)]iout
iout = -gm3rds2[1 + gm4(rds4||rds5)]iout + gds3vout - gds3rds2iout
vout = rds3[1 + gm3rds2 + gds3rds2 + gm3rds2gm4(rds4||rds5)]iout
rout = vout
iout = rds3[1 + gm3rds2 + gds3rds2 + gm3rds2gm4(rds4||rds5)]
rds3gm3rds2gm4(rds4||rds5)
If IREF = 100μA, all W/Ls are 10μm/1μm we get rds = 0.25M and gm = 469μS whichgives
rout (0.25M )(469μS)(0.25M )(469μS)(0.125M ) = 1.72G
gm4vgs4
gm3vgs3
rds4rds5 rds2rds3
vgs4
vgs3G3=D4=D5
D2=S3=G4
+
-
+ -D3
S2 = G2= S4
vout
+
-
iout
Fig. 290-09
Lecture 150 – Resistor Implementations and Current Sinks and Sources (3/25/10) Page 150-27
CMOS Analog Circuit Design © P.E. Allen - 201
Can 1G Output Resistance Really be Achieved?No, because of substrate currents. Substrate currents are caused by impact ionizationdue to high electric fields cause an impact which generates a hole-electron pair. Theelectrons flow out the drain and the holes flow into the substrate causing a substratecurrent flow.Illustration:
���Polysilicon
p+
p- substrate
Fig130-7
VG > VT
VD > VDS(sat)
������������������������n+
DepletionRegion
B S
FixedAtom
Freehole
Freeelectron
A n+
Maximum output resistance 500M -1G
Lecture 150 – Resistor Implementations and Current Sinks and Sources (3/25/10) Page 150-28
CMOS Analog Circuit Design © P.E. Allen - 201
Model of Substrate Current FlowSubstrate current:
iDB = K1(vDS - vDS(sat))iDe-[K2/(vDS-vDS(sat))]
where
K1 and K2 are process-dependent parameters (typical values: K1 = 5V-1 and K2 =30V)Schematic model:
D
G
S
B
iDB
Fig130-8Small-signal model:
gdb = iDBvDB
= K2 IDB
VDS - VDS(sat) 1nS
This conductance will prevent the realization of high-output resistance currentsinks/sources such as the regulated cascode current sink.
Lecture 150 – Resistor Implementations and Current Sinks and Sources (3/25/10) Page 150-29
CMOS Analog Circuit Design © P.E. Allen - 201
Minimizing the VMIN of the Regulated Cascode Current Sink
VMIN:
Without the use of the VO1 battery shown, VMIN is pretty bad. It is,
VMIN = VGS4 + VDS3(sat) = VT + 2VON
Minimizing VMIN:
If VO1 = VT , then VMIN = 2VON. This is accomplished by the following circuit:
If VGS4A - VGS4B = VDS2(sat) = VON,
then VMIN = 2VON
A number of solutions exist. For example, let IB = IREF. This gives ID4A = 5.824IREF
assuming all W/L ratios are identical.
VDDVDDVDD
M1 M2
M3
M4A M4B
+
-
vOUT
IBID4AIREF+IB
+ +
- -VGS4AVGS4B
+
-VDS2
+
-VDS2
IB
iOUT
IREF+IB
Fig. 290-10
2ID4
KN’(W4A/L4A) - 2IB
KN’(W4B/L4B) = 2IB+2IREF
KN’(W2/L2
or ID4
W4A/L4A -
IB
W4B/L4B =
IB+IREF
W2/L2
Lecture 150 – Resistor Implementations and Current Sinks and Sources (3/25/10) Page 150-30
CMOS Analog Circuit Design © P.E. Allen - 201
Example 150-2 - Design of a Minimum VMIN Regulated Cascode Current SinkDesign a regulated cascode current sink for 100μA and minimum voltage of VMIN =0.3V.SolutionLet the W/L ratios of M1 through M5 be equal and let IB = 10μA. Therefore,
VMIN = 0.3V = VON3 + VON2 = 2·100μA
110μA/V2(W/L) +2·110μA
110μA/V2(W/L)
= 2·100μA
110μA/V2(W/L) 1 + 1.1
Therefore,
0.3V = 2·100μA
110μA/V2(W/L)(2.049)
WL =
2·100μA·2.0492
110μA/V20.32 = 84.8 85.
With IB = 10μA, then ID4A =
10 + 110 2 = 186μA M1 M2
M3
M4A M4B
+
-
vOUT
iOUT
Fig. 290-11
110μA 186μA 10μA
10μA
110μA
85/1
85/185/1
85/185/1
+5V +5V +5V
Lecture 150 – Resistor Implementations and Current Sinks and Sources (3/25/10) Page 150-31
CMOS Analog Circuit Design © P.E. Allen - 201
Comparison of the MOS Cascode and Regulated Cascode Current SinkClose examination in the knee area reveals interesting differences.Simulation results:
80
85
90
95
100
105
110
0 0.1 0.2 0.3 0.4 0.5vOUT (V)
i OU
T (μ
A)
MOS Cascode
RegulatedMOS Cascode
Fig. 290-12
BJT Cascode
Comments: • The regulated cascode current is smaller than the cascode current because the drain-
source voltages of M1 and M2 are not equal. • The regulated cascode current sink has a smaller VMIN due to the fact that M3 can
have a drain-source voltage smaller than VDS(sat)
Lecture 150 – Resistor Implementations and Current Sinks and Sources (3/25/10) Page 150-32
CMOS Analog Circuit Design © P.E. Allen - 201
SUMMARYSummary of Both BJT and MOS Current Sinks/Sources
Current Sink/Source rOUT VMIN
Simple MOS Current Sinkrds =
1D
VDS(sat) =VON
Simple BJT Current Sinkro =
VAC
VCE(sat)
0.2VCascode MOS gm2rds2rds1 2VON
Cascode BJT Fro 2VCE(sat)Regulated Cascode Current Sink rds3gm3rds2gm4(rds4||rds5) VT +VON
Minimum VMIN RegulatedCascode Current Sink
rds3gm3rds2gm4(rds4||rds5) VON
Resistor Implementations• MOSFET resistors may use less area than actual resistors• Linearity is the primary issue for MOSFET resistor realizations
Lecture 160 – Current Mirrors and Simple References (3/25/10) Page 160-1
CMOS Analog Circuit Design © P.E. Allen - 2010
LECTURE 160 – CURRENT MIRRORS AND SIMPLEREFERENCES
LECTURE ORGANIZATIONOutline• MOSFET current mirrors• Improved current mirrors• Voltage references with power supply independence• Current references with power supply independence• Temperature behavior of voltage and current referencesCMOS Analog Circuit Design, 2nd Edition ReferencePages 134-153
Lecture 160 – Current Mirrors and Simple References (3/25/10) Page 160-2
CMOS Analog Circuit Design © P.E. Allen - 2010
MOSFET CURRENT MIRRORSWhat is a Current Mirror?A current mirror replicates the input current of a current sink or current source as anoutput current. The output current may be identical to the input current or can be ascaled version of it.
060528-01
VDD
CurrentMirror
iIN
VDD
iOUT = KiIN
VDD
CurrentMirror
IIN
VDD
IOUT = KIINiin Kiout
iOUTiIN
The above current mirrors are referenced with respect to ground. Current mirrors canalso be referenced with respect to VDD and current sink inputs and outputs.
Lecture 160 – Current Mirrors and Simple References (3/25/10) Page 160-3
CMOS Analog Circuit Design © P.E. Allen - 2010
Characterization of Current MirrorsA current mirror is basically nothing more than a current amplifier. The idealcharacteristics of a current amplifier are:
• Output current linearly related to the input current, iout = Aiiin• Input resistance is zero• Output resistance is infinity
Also, the characteristic VMIN applies not only to the output but also the input.• VMIN(in) is the range of vin over which the input resistance is not small• VMIN(out) is the range of vout over which the output resistance is not large
Graphically:
Therefore, Rout, Rin, VMIN(out), VMIN(in), and Ai will characterize the current mirror.
CurrentMirror
+
-vin
iin+
-vout
iout
vin
iin
VMIN�(in)
Slope= 1/Rin
iin vout
iout
VMIN�(out)
Slope = 1/Rout
iout
1Ai
Fig. 300-01Input Characteristics Transfer Characteristics Output Characteristics
Lecture 160 – Current Mirrors and Simple References (3/25/10) Page 160-4
CMOS Analog Circuit Design © P.E. Allen - 2010
Simple MOS Current MirrorCircuit:
Assume that vDS2 > vGS - VT2, theniOiI =
L1W2
W1L2
VGS-VT2
VGS-VT1
2 1 + vDS2
1 + vDS1
K2’K1’
If the transistors are matched, then K1’ = K2’ and VT1 = VT2 to give,iOiI =
L1W2
W1L2
1 + vDS2
1 + vDS1
If vDS1 = vDS2, theniOiI =
L1W2
W1L2
Therefore the sources of error are:1.) vDS1 vDS2
2.) M1 and M2 are not matched.
M1 M2
iI iO
+
-
vDS1
+
-
vDS2
Fig. 300-02
+-vGS-
Lecture 160 – Current Mirrors and Simple References (3/25/10) Page 160-5
CMOS Analog Circuit Design © P.E. Allen - 2010
Influence of the Channel Modulation Parameter, If the transistors are matched and the W/L ratios are equal, then
iOiI =
1 + vDS2
1 + vDS1
if the channel modulation parameter is the same for both transistors (L1 = L2).
Ratio error (%) versus drain voltage difference:
Note that one could use this effect tomeasure .
Measure VDS1,VDS2, iI and iO andsolve the above equation for the channelmodulation parameter, . 4.0
8.0
5.0
6.0
7.0
0.0
3.0
2.0
1.0
0.0 5.0 vDS2 - vDS1 (volts)
λ = 0.01
1.0 2.0
λ = 0.015
λ = 0.02
Ratio Error vDS2 - vDS1 (volts)
v DS2
v DS1
1 11
100
+ +−
⎡ ⎣⎢⎤ ⎦⎥
×λ λ
%R
atio
Err
orvDS1 = 2.0 volt
Fig. 300-033.0 4.0
Lecture 160 – Current Mirrors and Simple References (3/25/10) Page 160-6
CMOS Analog Circuit Design © P.E. Allen - 2010
Illustration of the Offset Voltage Error Influence
Assume that VT1 = 0.7V and K’W/L = 110μA/V2.
8.0
16.0
10.0
12.0
14.0
0.0
6.0
4.0
2.0
0.0 10
ΔVT (mV)
1.0 2.0
i O i i
100
⎡ ⎣⎢⎤ ⎦⎥
×%
Rat
io E
rror
1−
iI = 1μA
3.0 4.0 5.0 6.0 7.0 8.0 9.0
iI = 3μA
iI = 5μA
iI = 10μA
iI = 100μA
Fig. 300-4
Key: Make the part of VGS causing the current to flow, VON, more significant than VT.
Lecture 160 – Current Mirrors and Simple References (3/25/10) Page 160-7
CMOS Analog Circuit Design © P.E. Allen - 2010
Influence of Error in Aspect Ratio of the TransistorsExample 160-1 - Aspect Ratio Errors in Current MirrorsA layout is shown for a one-to-four current amplifier. Assume that the lengths areidentical (L1 = L2) and find the ratio error if W1 = 5 ± 0.1 μm. The actual widths of the twotransistors are
W 1 = 5 ± 0.1 μm and W2 = 20 ± 0.1 μm
SolutionWe note thatthe toleranceis not multi-plied by thenominal gainfactor of 4.The ratio ofW 2 to W1 and consequently the gain of the current amplifier is
iOiI =
W 2W 1
= 20 ± 0.15 ± 0.1 = 4
1 ± (0.1/20)1 ± (0.1/5) 4 1 ±
0.120 1 -
±0.15 4 1 ±
0.120 -
±0.420 = 4 - (±0.03)
where we have assumed that the variations would both have the same sign (correlated). Itis seen that this ratio error is 0.75% of the desired current ratio or gain.
iO
M1 M2
+
-
+
-
+
-
VDS1VDS2
iI
VGS����������
M1M2iO iI
GND
Fig. 300-5
Lecture 160 – Current Mirrors and Simple References (3/25/10) Page 160-8
CMOS Analog Circuit Design © P.E. Allen - 2010
Influence of Error in Aspect Ratio of the Transistors-ContinuedExample 160-2 - Reduction of the Aspect Ratio Errors in Current MirrorsUse the layout technique illustrated below and calculate the ratio error of a currentamplifier having the specifications of the previous example.SolutionsThe actual widths of M1 and M2 are
W 1 = 5 ± 0.1 μm and W2 = 4(5 ± 0.1) μm
The ratio of W2 to W1 and consequently the current gain is given below and is for al
practical purposes independent of layout error.
iOiI =
4(5 ± 0.1)5 ± 0.1 = 4
��������
��������
��������
����
����M1M2bM2a M2dM2c iO
M1 M2
iI
iI
GND
GND
iO
Fig. 300-6
Lecture 160 – Current Mirrors and Simple References (3/25/10) Page 160-9
CMOS Analog Circuit Design © P.E. Allen - 2010
Summary of the Simple MOS Current Mirror/Amplifier• Minimum input voltage is VMIN(in) = VT+VON
Okay, but could be reduced to VON.Principle:
M1M2
VTiI iO
VT+VON+-
+
-VON
M1 M2VT
Fig. 300-7
iI iO
VT+VON
+
-
+
-
VON
Ib
IbIb
VDD
Ib
M3 M4
M5 M6 M7
Will deal with later in low voltage op amps.• Minimum output voltage is VMIN(out) = VON
• Output resistance is Rout = 1ID
• Input resistance is Rin 1
gm
• Current gain accuracy is poor because vDS1 vDS2
Lecture 160 – Current Mirrors and Simple References (3/25/10) Page 160-10
CMOS Analog Circuit Design © P.E. Allen - 2010
IMPROVED CURRENT MIRRORSLarge Output Swing Cascode Current Mirror
• Rout gm2rds2rds1
• Rin = ? vin = rds5(iin-gm5vgs5)+vs5 = rds5(iin +gm5vs5)+vs5 = rds5iin+(1+gm5rds5)vs5
But, vs5 = rds3(iin - gm3vin)
vin = rds5iin + (1+gm5rds5)rds3iin - gm3rds3(1+gm5rds5)vin
Rin = vin
iin = rds5 + rds3 + rds3gm5rds5
gm3rds3(1+gm5rds5) 1
gm3
• VMIN(out) = 2VON
• VMIN(in) = VT + VON
• Current gain is excellent because vDS1 = vDS3.
060528-02
M2
M1M3
1/4
M4
VDD
IIN IOUT
M5
iin
1/1
1/1
1/1
1/1
gm5vgs5rds5
gm3vgs3 rds3
+
-
vs5
D5=G3
D3=S5
S3=G5
+
-
viniin
= gm3vin
VDD VDD
ioutR
Lecture 160 – Current Mirrors and Simple References (3/25/10) Page 160-11
CMOS Analog Circuit Design © P.E. Allen - 2010
Self-Biased Cascode Current Mirror
• Rin = ?
vin = iinR + rds3(iin-gm3vgs3)+ rds1(iin-gm1vgs1)
But,vgs1 = vin-iinR
andvgs3 = vin-rds1(iin-gm1vgs1)
= vin-rds1iin+gm1rds1(vin-iinR)vin = iinR+rds3iin-gm3rds3[vin-rds1iin+gm1rds1(vin-iinR)]+rds1[iin-gm1(vin+iinR)]vin[1+gm3rds3+gm1rds1gm3rds3+gm1rds1]
= iin[R+rds1+rds3+gm3rds3rds1+ gm1rds1gm3rds3R]
Rin =
R + rds1 + rds3 + gm3rds3rds1 + gm1rds1gm3rds3R1 + gm3rds3 + gm1rds1gm3rds3 + gm1rds1
1
gm1 + R
• Rout gm4rds4rds2
• VMIN(in) = VT + 2VON •VMIN(out) = 2VON • Current gain matching is excellent
VDD VDD
I1 I2iin iout
R
M1 M2
M3 M4
gm3vgs3
rds3
R
gm1vgs1 rds1
+
-
vin
+
-
v2v1
+
-
+
-
vin
Small-signal model to calculate Rin.Self-biased, cascode current mirrorFig. 310-03
iin
Lecture 160 – Current Mirrors and Simple References (3/25/10) Page 160-12
CMOS Analog Circuit Design © P.E. Allen - 2010
MOS Regulated Cascode Current Mirror
IBiasIO
M3
M2
M1
ii
M4
FIG. 310-11
VDD
io
VDD
II
VDD
• Rout gm2rds3
• Rin 1
gm4
• VMIN(out) = VT+2VON (Can be reduced to 2VON)
• VMIN(in) = VT+VON (Can be reduced to VON)• Current gain matching - good as long as vDS4 = vDS2
Lecture 160 – Current Mirrors and Simple References (3/25/10) Page 160-13
CMOS Analog Circuit Design © P.E. Allen - 2010
Summary of MOS Current Mirrors
CurrentMirror
Accuracy OutputResistance
InputResistance
MinimumOutputVoltage
MinimumInput
VoltageSimple Poor rds 1
gm
VON VT+VON
Wide OutputSwing
Cascode
Excellent gmrds2 1
gm
2VON VT+VON
Self-biasedCascode
Excellent gmrds2
R + 1
gm
2VON VT+2VON
RegulatedCascode
Good-Excellent
gm2rds
3 1gm
VT+2VON
(Can be2VON)
VT+VON
(Can beVON)
Lecture 160 – Current Mirrors and Simple References (3/25/10) Page 160-14
CMOS Analog Circuit Design © P.E. Allen - 2010
VOLTAGE REFERENCES WITH POWER SUPPLY INDEPENDENCEPower Supply IndependenceHow do you characterize power supply independence?Use the concept of:
SVREF
VDD =
VREF/VREF
VDD/VDD =
VDD
VREF
VREF
VDD
Application of sensitivity to determining power supply dependence:
VREF
VREF = S
VREF
VDD
VDD
VDD
Thus, the fractional change in the reference voltage is equal to the sensitivity times thefractional change in the power supply voltage.For example, if the sensitivity is 1, then a 10% change in VDD will cause a 10% change inVREF.
Ideally, we want SVREF
VDD to be zero for power supply independence.
Lecture 160 – Current Mirrors and Simple References (3/25/10) Page 160-15
CMOS Analog Circuit Design © P.E. Allen - 2010
MOSFET-Resistance Voltage References
vout
VDD
+
-
R
VREF
VDD
+
-
R
VREF
R1
R2
Fig. 370-03
VREF = VGS = VT +
2(VDD-VREF)R
or
VREF = VT - 1R +
2(VDD-VT)R +
1( R)2
SVREF
VDD
= 1
1 + 2 (VDD-VT)R
VDD
VREF
Assume that VDD=5V, W/L =100 and R=100k ,
Thus, VREF 0.7875V and SVREF
VDD
= 0.0653
This circuit allows VREF to belarger. If the current in R1 (andR2) is small compared to thecurrent flowing through thetransistor, then
VREF R1 + R2
R2 VGS
Lecture 160 – Current Mirrors and Simple References (3/25/10) Page 160-16
CMOS Analog Circuit Design © P.E. Allen - 2010
Bipolar-Resistance Voltage References
vout
VCC
+
-
R
VREF
VCC
+
-
R
VREF
R1
R2
Fig. 370-04
VREF = VEB = kTq ln
IIs
and I = VCC VEB
R VCCR
give VREF kTq ln
VCCRIs
SVREFVCC =
1ln[VCC/(RIs)] =
1ln(I/Is)
If VCC = 5V, R = 4.3k and Is = 1fA,then VREF = 0.719V.
Also, SVREF
VCC
= 0.0362
If the current in R1 (and R2)is small compared to thecurrent flowing through thetransistor, then
VREF R1 + R2
R1 VEB
Can use diodes in place of the BJTs.
Lecture 160 – Current Mirrors and Simple References (3/25/10) Page 160-17
CMOS Analog Circuit Design © P.E. Allen - 2010
CURRENT REFERENCES WITH POWER SUPPLY INDEPENDENCEPower Supply IndependenceAgain, we want
SIREF
VDD =
IREF/IREF
VDD/VDD =
VDD
IREF
IREF
VDD
to approach zero.
Therefore, as SIREF
VDD approaches zero, the change in IREF as a function of a change in VDD
approaches zero.
Lecture 160 – Current Mirrors and Simple References (3/25/10) Page 160-18
CMOS Analog Circuit Design © P.E. Allen - 2010
Gate-Source Referenced Current ReferenceThe circuit below uses both positive and negative feedback to accomplish a currentreference that is reasonably independent of power supply.Circuit:
i
v
IQ
VQ
RI2 =
WL
I1 = (VGS1 - VT)2
M2
+
-
M1
I5
M8
VGS1
M3M4
R
I6
M5
M6
I1 I2
Startup
VDD
VGS1M7
Fig. 370-06
Desiredoperatingpoint
Undesiredoperatingpoint
0V
K'N2RB
Principle:
If M3 = M4, then I1 I2. However, the M1-R loop gives VGS1=VT1 + 2I1
KN’(W1/L1)
Solving these two equations gives I2 = VGS1
R = VT1
R + 1R
2I1KN’(W1/L1)
The output current, Iout=I1=I2 can be solved as Iout= VT1
R + 1
1R2 +
1R
2VT1
1R +1
( 1R)2
Lecture 160 – Current Mirrors and Simple References (3/25/10) Page 160-19
CMOS Analog Circuit Design © P.E. Allen - 2010
Simulation Results for the Gate-Source Referenced Current Reference
The current ID2 appears to be okay, why isID1 increasing?Apparently, the channel modulation on thecurrent mirror M3-M4 is large.At VDD = 5V, VSD3 = 2.83V and VSD4 =1.09V which gives ID3 = 1.067ID4
107μANeed to cascode the upper current mirror.SPICE Input File:
Simple, Bootstrap Current ReferenceVDD 1 0 DC 5.0VSS 9 0 DC 0.0M1 5 7 9 9 N W=20U L=1UM2 3 5 7 9 N W=20U L=1UM3 5 3 1 1 P W=25U L=1UM4 3 3 1 1 P W=25U L=1UM5 9 3 1 1 P W=25U L=1UR 7 9 10KILOHMM8 6 6 9 9 N W=1U L=1UM7 6 6 5 9 N W=20U L=1U
RB 1 6 100KILOHM.OP.DC VDD 0 5 0.1.MODEL N NMOS VTO=0.7 KP=110UGAMMA=0.4 +PHI=0.7 LAMBDA=0.04.MODEL P PMOS VTO=-0.7 KP=50UGAMMA=0.57 +PHI=0.8 LAMBDA=0.05.PRINT DC ID(M1) ID(M2) ID(M5).PROBE.END
0 1 2 3 4 5VDD
120μA
100μA
80μA
60μA
40μA
20μA
0
ID1
ID2
Fig. 370-07
Lecture 160 – Current Mirrors and Simple References (3/25/10) Page 160-20
CMOS Analog Circuit Design © P.E. Allen - 2010
Cascoded Gate-Source Referenced Current Reference
SPICE Input File:
Cascode, Bootstrap Current ReferenceVDD 1 0 DC 5.0VSS 9 0 DC 0.0M1 5 7 9 9 N W=20U L=1UM2 4 5 7 9 N W=20U L=1UM3 2 3 1 1 P W=25U L=1UM4 8 3 1 1 P W=25U L=1UM3C 5 4 2 1 P W=25U L=1UMC4 3 4 8 1 P W=25U L=1URON 3 4 4KILOHMM5 9 3 1 1 P W=25U L=1UR 7 9 10KILOHMM8 6 6 9 9 N W=1U L=1U
M7 6 6 5 9 N W=20U L=1URB 1 6 100KILOHM.OP.DC VDD 0 5 0.1.MODEL N NMOS VTO=0.7 KP=110UGAMMA=0.4 PHI=0.7 LAMBDA=0.04.MODEL P PMOS VTO=-0.7 KP=50UGAMMA=0.57 PHI=0.8 LAMBDA=0.05.PRINT DC ID(M1) ID(M2) ID(M5).PROBE.END
0 1 2 3 4 5VDD
120μA
100μA
80μA
60μA
40μA
20μA
0
ID1
ID2
Fig. 370-
M2
+
-
M1
I5
M8
VGS1
M3 M4
R
M5
I1 I2
Startup
VDD
M7
0V
RB
M3C MC4
MC5
RON
Lecture 160 – Current Mirrors and Simple References (3/25/10) Page 160-21
CMOS Analog Circuit Design © P.E. Allen - 2010
Base-Emitter Referenced Circuit
M2
+
-
+
-
M1
I5
M7
-
VEB1
VR
M3 M4
R
M5
I1
I2
Startup
Q1
VDD
070621-01
i2
i1
Desiredoperating
point
Undesiredoperating
point
i2=Vtln(i1/Is)/R
i2=i1M6
Iout
= I2 = V
EB1
R
BJT can be a MOSFET in weak inversion.
Lecture 160 – Current Mirrors and Simple References (3/25/10) Page 160-22
CMOS Analog Circuit Design © P.E. Allen - 2010
Low Voltage Gate-Source Referenced MOS Current ReferenceThe previous gate-source referenced circuits required at least 2 volts across the powersupply before operating.A low-voltage gate-source referenced circuit:
VSS
M3 M4
VDD
R
M1 M2
VT
VTI1
I2
VT+VON
VON
VR
VT+VON
VON
Fig. 4.5-8A
Without the batteries, VT, the minimum power supply is VT+2VON+VR.
With the batteries, VT, the minimum power supply is 2VON+VR 0.5V
Lecture 160 – Current Mirrors and Simple References (3/25/10) Page 160-23
CMOS Analog Circuit Design © P.E. Allen - 2010
Summary of Power-Supply Independent References• Reasonably good, simple voltage and current references are possible• Best power supply sensitivity is approximately 0.01
(10% change in power supply causes a 0.1% change in reference)
Type of ReferenceS
VREF
VPP or S
IREF
VPP
Voltage division 1Simple Current Reference 1MOSFET-R <1BJT-R <<1Gate-source Referenced <<1Base-emitter Referenced <<1
Lecture 160 – Current Mirrors and Simple References (3/25/10) Page 160-24
CMOS Analog Circuit Design © P.E. Allen - 2010
TEMPERATURE BEHAVIOR OF VOLTAGE AND CURRENT REFERENCESCharacterization of Temperature DependenceThe objective is to minimize the fractional temperature coefficient defined as,
TCF = 1
VREF
VREF
T = 1T S
VREF
T parts per million per °C or ppm/°C
Temperature dependence of PN junctions:
i IsexpvVt
Is = KT3exp-VGO
Vt
1Is
IsT =
(ln Is)T =
3T +
VGOTVt
VGOTVt
dvBEdT
VBE - VGOT = -2mV/°C at room temperature
(VGO = 1.205 V at room temperature and is called the bandgap voltage)Temperature dependence of MOSFET in strong inversion:
dvGSdT =
dVTdT +
2LWCox
ddT
iDμo
μo = KT-1.5
VT(T) = VT(To) - (T-To)
dvGSdT - -2.3
mV°C
Resistors: (1/R)(dR/dT) ppm/°C
Lecture 160 – Current Mirrors and Simple References (3/25/10) Page 160-25
CMOS Analog Circuit Design © P.E. Allen - 2010
Bipolar-Resistance Voltage ReferencesFrom previous work we know that,
VREF = kTq ln
VDD - VREF
RIs
However, not only is VREF a function of T, but R and Is are also
functions of T.
dV
REF
dT = kq ln
VDD
-VREF
RIs
+ kTq
RIs
VDD
-VREF
-1RI
s
dVREF
dT -V
DD-V
REF
RIs
dRRdT +
dIs
IsdT
= V
REF
T - V
t
VDD
-VREF
dV
REF
dT - Vt
dRRdT +
dIs
IsdT =
VREF
-VGO
T - V
t
VDD
-VREF
dV
REF
dT - 3V
t
T - V
t
R dRdT
dVREF
dT =
VREF
-VGO
T - Vt
dRRdT -
3Vt
T
1 +V
t
VDD
-VREF
V
REF-V
GO
T - Vt
dRRdT -
3Vt
T
TCF =
1V
REF
dV
REF
dT = V
REF-V
GO
VREF
·T - V
t
VREF
dRRdT -
3Vt
VREF
·T
If VREF = 0.6V, Vt = 0.026V, and the R is polysilicon, then at 27°K the TCF is
VDD
+
-
R
VREF
Fig. 380-1
TCF =0.6-1.2050.6·300 -
0.026·0.00150.6 -
3·0.0260.6·300 = 33110-6-65x10-6-433x10-6 =-3859ppm/°C
Lecture 160 – Current Mirrors and Simple References (3/25/10) Page 160-26
CMOS Analog Circuit Design © P.E. Allen - 2010
MOSFET Resistor Voltage ReferenceFrom previous results we know that
VREF = VGS = VT +
2(VDD-VREF)R
or VREF = VT - 1R +
2(VDD-VT)R +
1( R)2
Note that VREF, VT, , and R are all functions of temperature.
It can be shown that the TCF of this reference is
dVREFdT =
+VDD VREF
2 R1.5T
1R
dRdT
1 +1
2 R (VDD VREF)
TCF = +
VDD VREF2 R
1.5T
1R
dRdT
VREF(1 +1
2 R (VDD VREF))
VDD
+
-
R
VREF
Fig. 380-02
Lecture 160 – Current Mirrors and Simple References (3/25/10) Page 160-27
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 160-3 - Calculation of MOSFET-Resistor Voltage Reference TCF
Calculate the temperature coefficient of the MOSFET-Resistor voltage reference whereW/L=2, VDD=5V, R=100k using the parameters of Table 3.1-2. The resistor, R, ispolysilicon and has a temperature coefficient of 1500 ppm/°C.Solution
First, calculate VREF . Note that R = 220x10-6x105 = 22 and dRRdT = 1500ppm/°C
VREF = 0.7 1
22 + 2(5 0.7)
22 +122
2 = 1.281V
Now, dVREF
dT = 2.3x10-3 +
5 1.2812 22
1.5300 1500x10-6
1 +1
2 22 (5 - 1.281)
= -1.189x10-3V/°C
The fractional temperature coefficient is given by
TCF = 1.189x10-3 1
1.281 = 928 ppm/°C
Lecture 160 – Current Mirrors and Simple References (3/25/10) Page 160-28
CMOS Analog Circuit Design © P.E. Allen - 2010
Gate-Source and Base-Emitter Referenced Current Source/SinksGate-source referenced source:
The output current was given as, Iout = VT1
R + 1
1R2 +
1R
2VT1
1R +1
( 1R)2
Although we could grind out the derivative of Iout with respect to T, the temperatureperformance of this circuit is not that good to spend the time to do so. Therefore, let usassume that VGS1 VT1 which gives
Iout VT1
R dIout
dT = 1R
dVT1
dT - 1R2
dRdT
In the resistor is polysilicon, then
TCF = 1
Iout dIout
dT = 1
VT1 dVT1
dT - 1R
dRdT =
-VT1
- 1R
dRdT =
-2.3x10-3
0.7 -1.5x10-3 = -4786ppm/°C
Base-emitter referenced source:
The output current was given as, Iout = I2 = VBE1
R
The TCF = 1
VBE1 dVBE1
dT - 1R
dRdT
If VBE1 = 0.6V and R is poly, then the TCF = 1
0.6 (-2x10-3) - 1.5x10-3 = -4833ppm/°C.
Lecture 160 – Current Mirrors and Simple References (3/25/10) Page 160-29
CMOS Analog Circuit Design © P.E. Allen - 2010
Technique to Make gm Dependent on a ResistorConsider the following circuit with all transistors having aW/L = 10. This is a bootstrapped reference which creates aVbias independent of VDD. The two key equations are:
I3 = I4 I1 = I2and
VGS1 = VGS2 + I2RSolving for I2 gives:
I2 = VGS1-VGS2
R = 1R
2I1ß1
-2I2ß2
= 2I1
R ß1 1 -
12
I2 = 1
R 2ß1 I2 = I1 =
1
2ß1R2 =
1
2·110x10-6·10·25x106 = 18.18μA
Now, Vbias can be written as
Vbias=VGS1=2I2ß1
+VTN = 1
ß1R+VTN = 1
110x10-6·10·5x103 + 0.7 = 0.1818+0.7=0.8818V
Any transistor with VGS = Vbias will have a current flow that is given by 1/2ßR2.
Therefore, gm = 2Iß = 2ß
2ßR2 =
1R gm =
1R
M3 M4
M1M2A
M2B M2C
M2D
R=5kΩ
VDD
+
-VBias
Fig. 4.5-11
Lecture 160 – Current Mirrors and Simple References (3/25/10) Page 160-30
CMOS Analog Circuit Design © P.E. Allen - 2010
Summary of Reference Performance
Type of Reference SVREF
VDD
TCF Comments
MOSFET-R <1 >1000ppm/°CBJT-R <<1 >1000ppm/°CGate-SourceReferenced
Good if currentsare matched
>1000ppm/°C Requires start-up circuit
Base-emitterReferenced
Good if currentsare matched
>1000ppm/°C Requires start-up circuit
• A MOSFET can have zero temperature dependence of iD for a certain vGS
• If one is careful, very good independence of power supply can be achieved• None of the above references have really good temperature independenceConsider the following example:
A 10 bit ADC has a reference voltage of 1V. The LSB is approximately 0.001V.Therefore, the voltage reference must be stable to within 0.1%. If a 100°C change intemperature is experienced, then the TC
F must be 0.001%/C or multiplying by 104
requires a TCF = 10ppm/°C.
Lecture 170 – Temperature Stable References (4/20/10) Page 170-1
CMOS Analog Circuit Design © P.E. Allen - 2010
LECTURE 170 – TEMPERATURE STABLE REFERENCESLECTURE ORGANIZATION
Outline• Principles of temperature stable references• Examples of temperature stable references• Design of bias voltages for a chip• SummaryCMOS Analog Circuit Design, 2nd Edition ReferencePages 153-159
Lecture 170 – Temperature Stable References (4/20/10) Page 170-2
CMOS Analog Circuit Design © P.E. Allen - 2010
PRINCIPLES OF TEMPERATURE STABLE REFERENCESTemperature Stable References• The previous reference circuits failed to provide small values of temperature coefficient
although sufficient power supply independence was achieved.• This section introduces a temperature stable reference that cancels a positive
temperature coefficient with a negative temperature coefficient. The technique issometimes called the bandgap reference although it has nothing to do with thebandgap voltage.
PrincipleVREF(T) = VPTAT(T) + K·VCTAT(T)
whereVPTAT(T) is a voltage that is proportionalto absolute temperature (PTAT)
VCTAT(T) is a voltage that iscomplimentary to absolute temperature(CTAT)
andK is a temperature independent constant that makes VREF(T) independent oftemperature
Lecture 170 – Temperature Stable References (4/20/10) Page 170-3
CMOS Analog Circuit Design © P.E. Allen - 2010
PTAT VoltageThe principle illustrated on the last slide requires perfectly linear positive and negativetemperature coefficients to work properly. We will now show a technique of generatingPTAT voltages that are linear with respect to temperature.Implementation of a PTAT voltage:
VPTAT = VD = VD1 – VD2 = Vt lnI1Is1 - Vt ln
I2Is2
= Vt lnI1I2
Is2Is1 = Vt ln
Is2Is1 = Vt ln
A2A1 =
kTq ln
A2A1
if I1 = I2.
Therefore, if A2 = 10A1, VD at room temperature becomes,
VD = kq ln
A2A1 T =
1.381x10-23J/°K1.6x10-19 Coul ln(10) T = (+ 0.086mV/°C)T
VPTAT = Vt lnA2A1
Lecture 170 – Temperature Stable References (4/20/10) Page 170-4
CMOS Analog Circuit Design © P.E. Allen - 2010
Psuedo-PTAT CurrentsIn developing temperature independent voltages, it is useful to showhow to generate PTAT currents. A straight-forward method is tosuperimpose VPTAT across a resistor as shown:
Because R is always dependent on temperature, this current is called a pseudo-PTATcurrent and is designated by IPTAT’.
When a pseudo-PTAT current flows through a secondresistor with the same temperature characteristics as thefirst, it creates a new VPTAT voltage.
The new VPTAT voltage, VPTAT2 is equal to,
VPTAT2 = R2R1 VPTAT1
Differentiating with respect to temperature givesdVPTAT2
dT = R2R1
dR2R2dT -
dR1R1dT +
dVPTAT1dT
Therefore, if the temperature coefficient of R1 and R2 are equal, then the temperaturedependence of VPTAT2 is the same as VPTAT1.
Lecture 170 – Temperature Stable References (4/20/10) Page 170-5
CMOS Analog Circuit Design © P.E. Allen - 2010
Pseudo-PTAT Currents - ContinuedThis can be done through the circuits below which use only MOSFETs and pn junctionsor MOSFETs, an op amp and pn junctions.
In these circuits, I1 = I2 and the voltage across D1 is made equal to the voltage across theseries combination of R and D2 to create the pseudo-PTAT current,
IPTAT’ = VD1 - VD2
R = kTRq ln
A2A1
where VGS1 = VGS2 for the MOSFET only version.
Psuedo-PTAT current generator using
only MOSFETs and pn junctions.
VDD
I1
VDD
I2
+
−VGS1
D1D2A1 A2
Μ1 Μ2
Μ3Μ4
+
−VGS2
R IPTAT’
VDD
Μ5
IPTAT’
Psuedo-PTAT current generator using
MOSFETs, an op amp and pn junctions.
VDD
I1
VDD
I2
D1D2A1 A2
Μ1 Μ2 Μ3
R IPTAT’
VDD
IPTAT’+ −
100326-04
Lecture 170 – Temperature Stable References (4/20/10) Page 170-6
CMOS Analog Circuit Design © P.E. Allen - 2010
CTAT VoltageThis becomes more challenging because a true CTAT voltage does not exist. The bestapproach is to examine the pn junction (can be a diode or BJT).The current through a pn junction shown can be written as,
JD = qDnni
2
LnNA+
qDppno
Lp
(vD VG0)Vt
= AT exp vD VG0
Vt
Consider the circuit shown. It can be shown, that vD(T) can be given as,
vD(T) = VGO 1 -TT0 + vD0
TT0 +
kTq ln
T0T +
kTq ln
JDJD0
where,VGO = bandgap voltage of silicon (1.205V)T0 = a reference temperature about which T varies
= a temperature coefficient for the pn junction saturation current ( 3)JD = pn junction current density
In the above expression for vD(T) the term kTq ln
T0
T is not linear with T!!
This term will create a problem called “bandgap curvature problem” because a perfectlylinear PTAT function cannot be cancelled by a term that is not truly CTAT.
Lecture 170 – Temperature Stable References (4/20/10) Page 170-7
CMOS Analog Circuit Design © P.E. Allen - 2010
Pseudo CTAT CurrentsThe circuits below show two ways of creating a pseudo CTAT current using negativefeedback:†
The negative feedback loop shown causes the current designated as ICTAT’ to be,
ICTAT’ = VBER =
VDR
† I.M. Gunawan, G.C.M. Jeijer, J. Fonderie, and J.H. Huijsing, “A Curvature-Corrected Low-Voltage Bandgap Reference, IEEE J. Solid-state Circuits, vol. SC-28, No. 6, June1993, pp. 677-670.
Lecture 170 – Temperature Stable References (4/20/10) Page 170-8
CMOS Analog Circuit Design © P.E. Allen - 2010
Temperature Independent Voltage ReferencesBasic structures:
Series form:
VREF = IPTAT’R2 + VD = R2R1
VPTAT + VCTAT
Parallel form:
VREF = (IPTAT’ + ICTAT’)R3 + VD = R3R1
VPTAT + R3R2
VCTAT = R3R2
R2R1
VPTAT + VCTAT
To achieve temperature independence, VREF must be differentiated with respect totemperature and set equal to zero. The resistor ratios and other parameters can be usedto achieve temperature independence.
Lecture 170 – Temperature Stable References (4/20/10) Page 170-9
CMOS Analog Circuit Design © P.E. Allen - 2010
Conditions for Temperature IndependenceDifferentiating either the series or parallel form with respect to temperature and equatingto zero gives,
K = R2R1
= - dVCTAT/dTdVPTAT/dT
The slopes of VCTAT and VPTAT at a given temperature, T0, are:
mCTAT = dVCTAT
dT
|
T=T0 =
VD - VGO
T0
+ ( - )k
q =
VCTAT - VGO
T0
+ ( - )Vt0
T0
where = temperature dependence of JD [JD(T) T , where = 1 for PTATcurrent flowing through the pn junction]
and
mPTAT = dVPTAT
dT
|
T=T0 =
k
q ln
JD2
JD1
= k
q ln
A2
A1
= Vt0
T0
lnA2
A1
= VPTAT
T0
Therefore, the temperature independent constant multiplying VPTAT is
Temp. independent constant = K = R2R1 =
VGO - VCTAT + ( - )Vt0VPTAT
Therefore,VREF = VGO-VCTAT + ( - )Vt0 + VCTAT = VGO + ( - )Vt0 1.205V+0.057 = 1.262V
Lecture 170 – Temperature Stable References (4/20/10) Page 170-10
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 170-1 – Temp. Independent Constant for Series and Parallel References(a.) Design the ratio of R2/R1 for the series configuration if VCTAT = 0.6V and A2/A1 = 10for room temperature (Vt = 0.026V). Assume = 3.2 and = 1. Find the value of VREF.
R2R1 =
VGO - VCTAT + ( - )Vt0VPTAT =
1.205 - 0.6 + 2.2(0.026)0.026(2.3026) = 11.06
VREF = 1.205 + 2.2(0.026) = 1.262V(b.) For the parallel configuration find the values of R2/R1 and R3/R2 if VREF = 0.5V.
From (a.) we know that R2/R1 = 11.05. We also know that,
VREF = R3R1
VPTAT + R3R2
VCTAT = R3R2
R2R1
VPTAT + VCTAT
= (R3/R2)[11.05ln(10)(0.026) + 0.6] = (R3/R2)1.262 = 0.5
(R3/R2) = 0.3963
If R1 = 1k , then R2 = 11.05k and R3 = 4.378k
Lecture 170 – Temperature Stable References (4/20/10) Page 170-11
CMOS Analog Circuit Design © P.E. Allen - 2010
A Series Temperature Independent Voltage ReferenceAn early realization of the series form is shown below†:Assuming VOS = 0, then VR1 is
VR1 = VEB2 - VEB1 = Vt lnJ2Js2
- Vt lnJ1Js1
= Vt lnI2AE1I1AE2
= Vt lnR2AE1R1AE2
The op amp forces the relationship I1R2 = I2R3
VREF = VEB2+I2R3 = VEB2+VR1R2R1
= VEB2+ R2R1
VtlnR2AE1R1AE2
= VCTAT+ R2R1
lnR2AE1R1AE2
Vt
Differentiating the above with respect to temperature and setting the result to zero, givesR2R1
lnR2AE1R1AE2
= VGO - VCTAT + ( - )Vt0
Vt
If VOS 0, then VREF becomes,
VREF = VEB2 - 1 +R2R1
VOS + R2R1
Vt lnR2AE1R1AE2
1 -VOSI1R2
† K.E. Kujik, “A Precision Reference Voltage Source,” IEEE Journal of Solid-State Circuits, Vol. SC-8, No. 3 (June 1973) pp. 222-226.
Lecture 170 – Temperature Stable References (4/20/10) Page 170-12
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 170-2 – Design of the Previous Temperature Independent ReferenceAssume that AE1 = 10 AE2, VEB2 = 0.7 V, R2 = R3, and Vt = 0.026 V at room temperaturefor temperature independent reference on the previous slide. Find R2/R1 to give a zerotemperature coefficient at room temperature. If VOS = 10 mV, find the change in VREF. Notethat I1R2 = VREF VEB2 VOS.
Evaluating the temperature independent constant gives
R2R1
ln R2 AE1R3AE2
= VGO - VCTAT + ( - )Vt0
VPTAT =
1.205 - 0.7 + (2.2)(0.026)0.026 = 21.62
Therefore, R2/R1 = 9.39. In order to use the equation for VREF with VOS 0, we mustknow the approximate value of VREF and iterate if necessary because I1 is a function ofVREF. Assuming VREF to be 1.262, we obtain from
VREF = VEB2 - 1 +R2R1
VOS + R2R1
Vt lnR2AE1R1AE2
1 -VOS
VREF - VEB2 - VOS
a new value VREF = 1.153 V. The second iteration makes little difference on the resultbecause VREF is in the argument of the logarithm
Lecture 170 – Temperature Stable References (4/20/10) Page 170-13
CMOS Analog Circuit Design © P.E. Allen - 2010
Series Temperature Independent Voltage ReferencesThe references shown do not use an op amp and avoid the issues with offset voltage andPSRR.
I1 = IPTAT’ = VBE2 - VBE1
R2
= Vt
R2
lnI2
Is2
- lnI1
Is1
= VtR2
lnIs1Is2
= VtR2
lnAE1AE2
Since I1= I2, VREF = VBE2 + I1R1 = VBE1 + R1R2
lnAE1AE2
Vt
= VCTAT + R1R2
lnAE1AE2
VPTAT
VD1 = I2R1 + VD2
I3 = I2 = IPTAT’ = VtR ln(n)
VREF = VD3 + I3(kR) = VD3 + kVt ln(n) = VCTAT + k ln(n)VPTAT
Lecture 170 – Temperature Stable References (4/20/10) Page 170-14
CMOS Analog Circuit Design © P.E. Allen - 2010
Parallel Temperature Independent Voltage ReferenceA parallel form of the temperature independent voltage reference is shown below:
VREF = R3R1
VPTAT + R3R2
VCTAT
Comments:• The BJT of the ICTAT’ generator can be replaced with an MOSFET-diode equivalent• Any value of VREF can be achieved• Part (b.) of Example 170-1 showed how to design the resistors of this implementation
Lecture 170 – Temperature Stable References (4/20/10) Page 170-15
CMOS Analog Circuit Design © P.E. Allen - 2010
How Can a Bandgap “Current” Reference be Obtained?Use a MOSFET under ZTC operation and design the parallel form of the bandgap voltagereference to give a value of VZTC.
060529-09
VDD
IPTAT
VDD
IVBE
R3+
−VREF =VGS(ZTC)
IREF
Lecture 170 – Temperature Stable References (4/20/10) Page 170-16
CMOS Analog Circuit Design © P.E. Allen - 2010
Bandgap Curvature Problem
Unfortunately, the kTq ln
T0
T term of the pnjunction contributed a nonlinearity to theCTAT realization. This is illustrated by thedashed lines in the plot shown.The result is shown below where the referencevoltage is not constant with temperature.
Comments:• True temperature independence is only achieved over a small range of temperatures• References that do not correct this problem have a temperature dependence of 10
ppm°/C to 50 ppm/°C over 0°C to 70°C.
Lecture 170 – Temperature Stable References (4/20/10) Page 170-17
CMOS Analog Circuit Design © P.E. Allen - 2010
Some Curvature Correction Techniques• Squared PTAT Correction:
Temperature coefficient 1-20 ppm/°C
• VBE loop
M. Gunaway, et. al., “A Curvature-Corrected Low-Voltage BandgapReference,” IEEE Journal of Solid-State Circuits, vol. 28, no. 6, pp. 667-670, June 1993.
• ß compensationI. Lee et. al., “Exponential Curvature-Compensated BiCMOS BandgapReferences,” IEEE Journal of Solid-State Circuits, vol. 29, no. 11, pp. 1396-1403,Nov. 1994.
• Nonlinear cancellationG.M. Meijer et. al., “A New Curvature-Corrected Bandgap Reference,” IEEEJournal of Solid-State Circuits, vol. 17, no. 6, pp. 1139-1143, December 1982.
VBE VPTAT
VRef = VBE + VPTAT + VPTAT2
Temperature
Vol
tage
Fig. 400-01
VPTAT2
Lecture 170 – Temperature Stable References (4/20/10) Page 170-18
CMOS Analog Circuit Design © P.E. Allen - 2010
VBE Loop Curvature Correction Technique
Circuit:Operation:
INL = VBE1-VBE2
R3 =
Vt
R3 ln
Ic1A2
A1Ic2
= Vt
R3 ln
2IPTAT
INL+IConstant
whereIconstant = INL + IPTAT + IVBE
INL + Vt
Rx +
VBE
R2
(a quasi-temperature independent current subject to the TCF of the resistors)where
Vt = kT/qIc1 and Ic2 are the collector currents of Qn1 and Qn2, respectivelyRx = a resistor used to define IPTAT
VREF = VBE
R2+
Vt
R3ln
2IPTAT
INL + Iconstant+ IPTAT R1
VDD VDD VDDIPTAT IPTAT
IPTAT
INL
IVBE+INL
IVBE
IConstantQn1x1
Qn2x2R2
R3 VREF
3-Output Current Mirror (IVBE+INL)
VDD
Fig. 400-02
R1
Temperature coefficient 3 ppm/°C with a total quiescent current of 95μA.
Lecture 170 – Temperature Stable References (4/20/10) Page 170-19
CMOS Analog Circuit Design © P.E. Allen - 2010
ß Compensation Curvature Correction TechniqueCircuit: Operation:
VREF = VBE + AT +BT
(1+ß) R VBE + AT +BTß R
whereA and B are constantT = temperature
The temperature dependence of ß is
ß(T) e-1/T ß(T) = Ce-1/T
VREF = VBE(T) + AT +BTe1/T
C
Not good for small values of Vin.
Vin V
REF + V
sat. = V
GO + V
sat. = 1.4V
I=AT I=BT
RVREF
Vin
BT1+ß
Fig. 400-0
Lecture 170 – Temperature Stable References (4/20/10) Page 170-20
CMOS Analog Circuit Design © P.E. Allen - 2010
Series Temperature Independent Voltage Reference with Curvature CorrectionObjective: Eliminate nonlinear term from VCTAT.
Result: 0.5 ppm/°C from -25°C to 85°C.Operation: VREF = VPTAT + 3VCTAT – 2VConstant
Note that, IPTAT Ic T 1 = 1and IConstant Ic T 0 = 0,Previously we found,
VCTAT(T) VGO - TT0
VGO-VCTAT(T0) -( - )Vt lnTT0
so that
VCTAT(IPTAT) =VGO-TT0
VGO-VBE(T0) -( -1)Vt lnTT0
and
VCTAT(IConstant) =VGO - TT0
VGO -VCTAT(T0) - Vt lnTT0
Combining the above relationships gives, VREF(T) = VPTAT + VGO - (T/T0)[VGO - VCTAT(T0)] - [ - 3] Vt ln (T/T0)
If 3, then VREF(T) VPTAT + VGO 1 - (T/T0) + VCTAT(T0)(T/T0)
Lecture 170 – Temperature Stable References (4/20/10) Page 170-21
CMOS Analog Circuit Design © P.E. Allen - 2010
A Parallel Version of the Nonlinear Curvature Correction TechniqueThe last idea was good in concept but not appropriate for CMOS implementation. Thefollowing is a better implementation.
VREF = R0[IPTAT’ + ICTAT’ – Iconst.] = R0R1
VPTAT + R0R2
VCTAT - R0R3
Vconst.
Use the resistor ratios to eliminate the nonlinear term given and .
Lecture 170 – Temperature Stable References (4/20/10) Page 170-22
CMOS Analog Circuit Design © P.E. Allen - 2010
Parallel Curvature Correction Reference - ContinuedSubstitute for VCTAT and Vconst. in the expression for VREF.
VREF = R0R1
VPTAT + R0R2
VGO-TT0
VGO-VCTAT(T0) -( -1)Vt lnTT0
- R0R3
VGO-TT0
VGO-VCTAT(T0) - Vt lnTT0
To cancel the nonlinear CTAT term, we want the following relationship to hold:R0R2
( -1) = R0R3
R2R3
= ( -1)
(Fortunately is always greater than 1)
With these constraints, we find the voltage reference to be,
VREF = R0R1
VPTAT + R0R2
-R0R3
VGO-TT0
VGO-VCTAT(T0)
= R0R1
VPTAT + 1 R0R2
VGO-TT0
VGO-VCTAT(T0)
= R0R2
R2R1
VPTAT+ VGO-TT0
VGO-VCTAT(T0) = R0R2
R2R1
VPTAT+VCTAT(T0) , (T = T0)
Design R2/R1 to achieve temperature independence and R0/R2 to get VREF.
Lecture 170 – Temperature Stable References (4/20/10) Page 170-23
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 170-3 – Design of a Zero Temperature Coefficient Voltage ReferenceAssume that VCTAT = 0.7 V, R3 = 10k , = 3.2, A2 = 10A1, and Vt = 0.026 V at room
temperature for the parallel curvature correction circuit. Find R2 and R3 to give a zerotemperature coefficient at room temperature and a reference voltage of 1.0V.
To eliminate the nonlinear CTAT term,R2R3
= ( -1)
= (2.2)3.2 = 0.6875 R2 = 6.88k
To cancel the temperature dependence,
Temp. independent constant = K = R2
R1=
VGO - VCTAT + ( - )Vt0VPTAT
orR2R1
= VGO - VCTAT + ( - )Vt0
VPTAT = (1.205 0.7 + (3.2-1)(0.026)
(0.026)(2.3026) = 9.3907 R1=2.34k
The reference voltage can be written as,
VREF = R0R2
R2R1
VPTAT+VCTAT(T0) = R0R2
[9.3907(0.026)(2.3026) + 0.7]
R0R2
= (3.2)1.262 = 2.535 R0 = 2.535R2 = 17.44k
Lecture 170 – Temperature Stable References (4/20/10) Page 170-24
CMOS Analog Circuit Design © P.E. Allen - 2010
Other Characteristics of Bandgap Voltage ReferencesNoise
Voltage references for high-resolution ADCs are particularly sensitive to noise.Noise sources: Op amp, resistors, switches, etc.
PSRRMaximize the PSRR of the op amp.
Offset VoltagesBecomes a problem when op amps are used.VBE2 = VBE1 + VR1 + VOS
VBE = VBE2 - VBE1 = VR1 + VOS = Vt lniC2AE1
iC1AE2
Since iC2R3 = iC1R2 - VOS
then iC2
iC1 =
R2
R3 -
VOS
iC1R3 =
R2
R3 1 +
VOS
iC1R2
Therefore,
VR1 = -VOS + Vt lnR2AE1
R3AE21 +
VOS
iC1R2
VREF = VBE2 - VOS + iC1R2 = VBE2 - VOS + VR1
R1R2 = VBE2 - VOS +
R2
R1
VREF = VBE2 - VOS 1+R2
R1+
R2
R1Vt ln
R2AE1
R3AE21 -
VOS
iC1R2
Fig. 400-05
iC1iC2
VCC
Q1Q2
+-
+
VREF
-
VEE
VOS
R3 R2
R1
+
-VR1
Lecture 170 – Temperature Stable References (4/20/10) Page 170-25
CMOS Analog Circuit Design © P.E. Allen - 2010
Noise Analysis of a Bandgap ReferenceConsider the simple classical BG reference shown(R2 = 10 R1 = 10k ):
The open-circuit output noise voltage squared isfound as,
eno2 = [en12/R12 + en22/R12 + gm52en32
+ gm52en42 + gm52en52 + ind12/(gm12R12)
+ ind22 + ind32 + inr12 + inr22] R22
Assuming the MOSFETs are matched and the dccurrents in D1, D2, and D3 are equal gives,
eno2 [gm52(en32+en42+en52) + ind22+ ind32 + inr12 + inr22] R22
Thermal noise gives (gm5 = 400μS),
eno2 = 8kTgm52R22+4qI1+
4kTR1 +
4kTR2 R22 5.3x10-19+6.4x10-23+1.7x10-15(V2/Hz)
1/f noise gives,
060605-02
VDD
M1 M2
M3M4
x1
+
−
eno2
i2i1
D1D2 D3
xn xn
M5
i3
** *en32 en42 en52
* *en12 en22
ind12
inr12R1 R2
ind22
inr22
ind32
eno2 = 3gm52 KF
2fCoxWL K’
Lecture 170 – Temperature Stable References (4/20/10) Page 170-26
CMOS Analog Circuit Design © P.E. Allen - 2010
DESIGN OF BIAS VOLTAGES FOR A CHIPDistributing Bias Voltages over a DistanceThe major problem is the IR drops in busses. For example,
100µA
100µA
1mm
M1 M2VBias
050716-01
ID1 ID2100µA
If the bus metal is 50m /sq. and is 5μm wide, the resistance of the bus in one direction is(50m /sq.)x(1000μm/5μm) = 10 . The difference in drain currents for an overdrive of0.1V is,
VGS1 = 1mV + VGS2 + 1mV = VGS2 + 2mV
ID1ID2 =
(VGS1-VTN)2
(VGS2-VTN)2 = (VGS2-VTN+2mV)2
(VGS2-VTN)2 = 0.1+0.002
0.12= 1.04
Lecture 170 – Temperature Stable References (4/20/10) Page 170-27
CMOS Analog Circuit Design © P.E. Allen - 2010
Use Current to Avoid IR Drops in Long Metal LinesExample:
Lecture 170 – Temperature Stable References (4/20/10) Page 170-28
CMOS Analog Circuit Design © P.E. Allen - 2010
Practical Aspects of Temperature-Independent and Supply-Independent BiasingA temperature-independent and supply-independent current source and its distribution:
The currents are used to distribute the bias voltages to remote sections of the chip.
Lecture 170 – Temperature Stable References (4/20/10) Page 170-29
CMOS Analog Circuit Design © P.E. Allen - 2010
Practical Aspects of Bias Distribution Circuits - Continued
Distribution of the current avoids change in bias voltage due to IR drop in bias lines.
Slave bias circuit:
From here on out in these notes, VPBias1 = VPB1 = VDD-|VTP|-VSD(sat) VPBias2 = VPB2 = VDD-|VTP|-2VSD(sat)
andVNBias1 = VNB1 = VTN + VDS(sat) VNBias2 = VNB2 = VTN + 2VDS(sat)
From Master Bias
Ib Ib
VDD
VPBias1
VPBias2
VNBias2
VNBias1
Fig. 400-08
Lecture 170 – Temperature Stable References (4/20/10) Page 170-30
CMOS Analog Circuit Design © P.E. Allen - 2010
SUMMARY OF TEMPERATURE STABLE REFERENCES• The classical form of the temperature stable reference has a value of voltage close to the
bandgap voltage and is called the “bandgap voltage reference”.• Bandgap voltage references can achieve temperature dependence less than 50 ppm/°C• Correction of second-order effects in the bandgap voltage reference can achieve very
stable (1 ppm/°C) voltage references.• Watch out for second-order effects such as noise when using the bandgap voltage
reference in sensitive applications.• Distribution of bias voltages over a long distance should be done by current rather than
voltage.
Lecture 180 – Inverting Amplifiers (3/27/10) Page 180-1
CMOS Analog Circuit Design © P.E. Allen - 2010
LECTURE 180 – INVERTING AMPLIFIERSLECTURE ORGANIZATION
Outline• Introduction• Active Load Inverting Amplifier• Current Source Load Inverting Amplifier• Push-Pull Inverting Amplifier• Noise Analysis of Inverting Amplifiers• SummaryCMOS Analog Circuit Design, 2nd Edition ReferencePages 168-180
Lecture 180 – Inverting Amplifiers (3/27/10) Page 180-2
CMOS Analog Circuit Design © P.E. Allen - 2010
INTRODUCTIONTypes of Amplifiers
Type of Amplifier Gain = OutputInput
Ideal InputResistance
Ideal OutputResistance
Voltage Av = Output VoltageInput Voltage Infinite Zero
Current Ai = Output CurrentInput Current Zero Infinite
Transconductance Gm = Output CurrentInput Voltage Infinite Infinite
Transresistance Rm = Output VoltageInput Current Zero Zero
Most CMOS amplifiers fit naturally into the transconductance amplifier category as theyhave large input resistance and fairly large output resistance.If the load resistance is high, the CMOS transconductance amplifier is essentially avoltage amplifier.
Lecture 180 – Inverting Amplifiers (3/27/10) Page 180-3
CMOS Analog Circuit Design © P.E. Allen - 2010
Amplifier Notation
060607-02
VoltageAmplifier
InputVoltage
OutputVoltage
VDD
VSS
Split Power Supplies
VoltageAmplifier
InputVoltage
OutputVoltage
VDD
Single Power Supply
Simpler notation:
060607-03
VoltageAmplifier
InputVoltage
OutputVoltage
VDD
VSS
Split Power Supplies
VoltageAmplifier
InputVoltage
OutputVoltage
VDD
Single Power Supply
Lecture 180 – Inverting Amplifiers (3/27/10) Page 180-4
CMOS Analog Circuit Design © P.E. Allen - 2010
Characterization of an Amplifier1.) Large signal static characterization:
• Plot of output versus input (transfer curve)• Large signal gain• Output and input swing limits
2.) Small signal static characterization:• AC gain• AC input resistance• AC output resistance
3.) Small signal dynamic characterization:• Bandwidth• Noise• Power supply rejection
4.) Large signal dynamic characterization:• Slew rate• Nonlinearity
Lecture 180 – Inverting Amplifiers (3/27/10) Page 180-5
CMOS Analog Circuit Design © P.E. Allen - 2010
Components of a CMOS Voltage/Transconductance Amplifier1.) A transconductance stage that converts the input voltage to current.2.) A transresistance stage (load) that converts the current from the transconductancestage back to voltage.
060607-01
VoltageAmplifier
InputVoltage
OutputVoltage Voltage-to
CurrentConversion
InputVoltage Current-to
VoltageConversion
CurrentOutputVoltage
TransconductanceStage
TransresistanceStage
Voltage Amplifier
Lecture 180 – Inverting Amplifiers (3/27/10) Page 180-6
CMOS Analog Circuit Design © P.E. Allen - 2010
Inverting and Noninverting AmplifiersThe types of amplifiers are based on the various configurations of the actual transistors.If we assume that one terminal of the transistor is grounded, then three possibilitiesresult:
060608-01
Load
VDD
vin
vout+
−
CommonSource
VDD
vin
vout+
CommonGate
Load
+
VDD
vin
Load
vout++
CommonDrain
Note that there are two categories of amplifiers:1.) Noninverting - Those whose input and output are in phase (common gate and
common drain)2.) Inverting - Those whose input and output are out of phase (common source)
Lecture 180 – Inverting Amplifiers (3/27/10) Page 180-7
CMOS Analog Circuit Design © P.E. Allen - 2010
ACTIVE LOAD INVERTING AMPLIFIERVoltage Transfer Characteristic of the Active Load Inverter
0 1 2 3 4 5
I D (
mA
)
0
4
5
0 1 2 3 4 5v O
UT
3
vIN
A B
C
D
E
H I K
F
M2
M1
vIN
vOUT
ID
5V
+
-
+
-
W2L2
=1μm1μm
W1L1
=2μm1μm
Fig. 320-02
vIN=5.0VvIN=4.0V
vIN=4.5V
vIN=1.0V
vIN=1.5V
vIN=2.0V
vIN=2.5V
A,BCD
E
F
M2
2
1J
HI
JK
G
M1 saturat
ed
M1 activ
e
0.0
0.1
0.2
0.3
0.4
0.5vIN=3.5VvIN=3.0V
G
vOUTM2 cutoff
M2 saturated
The boundary between active and saturation operation for M1 isvDS1 vGS1 - VTN vOUT vIN - 0.7V
Lecture 180 – Inverting Amplifiers (3/27/10) Page 180-8
CMOS Analog Circuit Design © P.E. Allen - 2010
Large-Signal Voltage Swing Limits of the Active Load InverterMaximum output voltage, vOUT(max):
vOUT(max) VDD - |VTP| (ignores subthreshold current influence on the MOSFET)
Minimum output voltage, vOUT(min):Assume that M1 is nonsaturated and that VT1 = |VT2| = VT.vDS1 vGS1 - VTN vOUT vIN - 0.7V
The current through M1 is
iD = 1 (vGS1 VT)vDS1
v2
DS12 = 1 (VDD VT)(vOUT )
(vOUT)2
2and the current through M2 is
iD = 2
2 (vSG2 VT)2 = 2
2 (VDD vOUT VT)2 = 2
2 (vOUT + VT VDD)2
Equating these currents gives the minimum vOUT as,
vOUT(min) = VDD VTVDD VT1 + ( 2/ 1)
Lecture 180 – Inverting Amplifiers (3/27/10) Page 180-9
CMOS Analog Circuit Design © P.E. Allen - 2010
Small-Signal Midband Performance of the Active Load InverterThe development of the small-signal model for the active load inverter is shown below:
M2
M1vIN
vOUTID
VDD
gm2vgs2
gm1vgs1
rds2
rds1
+
-
vin
G1D1=D2=G2
S1=B1
S2=B2
+
-
vout gm1vin rds1
+
-
vin
+
-
voutgm2vout rds2
Rout
Fig. 320-03
Sum the currents at the output node to get,gm1vin + gds1vout + gm2vout + gds2vout = 0
Solving for the voltage gain, vout/vin, givesvoutvin
= gm1
gds1 + gds2 + gm2
gm1gm2
= K'NW 1L2K'PL1W 2
1/2
The small-signal output resistance can also be found from the above by letting vin = 0 toget,
Rout = 1
gds1 + gds2 + gm2
1gm2
Lecture 180 – Inverting Amplifiers (3/27/10) Page 180-10
CMOS Analog Circuit Design © P.E. Allen - 2010
Frequency Response of the Active Load InverterIncorporation of the parasiticcapacitors into the small-signalmodel:If we assume the input voltage has asmall source resistance, then we canwrite the following:
sCM(Vout-Vin) + gmVin
+ GoutVout + sCoutVout = 0
Vout(Gout + sCM + sCout) = - (gm – sCM)Vin
VoutVin =
-(gm – sCM)Gout+ sCM + sCout
= -gmRout 1-
sCMgm
1+ sRout(CM + Cout) = gmRout 1 -
sz1
1 -sp1
where gm = gm1, p1 = 1
Rout(Cout+CM) , and z1 = gm1CM
and Rout = [gds1+gds2+gm2]-1 1
gm2 , CM = Cgd1 , and Cout = Cbd1+Cbd2+Cgs2+CL
Fig. 320-04Cgs1
Cgd1
Cgs2
Cbd2
Cbd1
VDD
Vin
Vout
CL
M2
M1
CM
CoutRoutVout
+
-
Vin gmVin
+
-
Lecture 180 – Inverting Amplifiers (3/27/10) Page 180-11
CMOS Analog Circuit Design © P.E. Allen - 2010
Complex Frequency (s) Analysis of Circuits – (Optional)The frequency response of linear circuits can be analyzed using the complex frequencyvariable s which avoids having to solve the circuit in the time domain and then transforminto the frequency domain.Passive components in the s domain are:
ZR(s) = R ZL(s) = sL and ZC(s) = 1sC
s-domain analysis uses the complex impedance of elements as if they were “resistors”.Example:
Sum currents flowing away from node A to get,sC1(V2 – V1) + gmV1 + G2V2 + sC2V2 = 0
Solving for the voltage gain transfer function gives,
T(s) = V2(s)V1(s) =
-sC1 + gms(C1+ C2) + G2 = -gmR2
sC1/gm - 1s(C1+ C2)R2 + 1
+
−V1
+
−V2gmV1
C1
R2 C2
060204-06
+
−V1(s)
+
−V2(s)
gmV1(s)
1/sC1
sC2
1R2
As-domainconversion
Lecture 180 – Inverting Amplifiers (3/27/10) Page 180-12
CMOS Analog Circuit Design © P.E. Allen - 2010
Complex Frequency Plane – (Optional)The complex frequency variable, s, is really a complex number and can be expressed as
s = + j where = Re[s] and = Im[s].Complex frequency plane:
It is useful to plot the rootsof the transfer function onthe complex frequency plane.For the previous T(s), the roots are:
The numerator root (zero) is s = z1 = +(gm/C1)
The denominator root (pole) is s = p1= -[1/R2(C1+ C2)]
Lecture 180 – Inverting Amplifiers (3/27/10) Page 180-13
CMOS Analog Circuit Design © P.E. Allen - 2010
What is the Frequency Response of an Amplifier? – (Optional)Frequency response results when we replace the complex frequency variable s with j inthe transfer function of an amplifier. (This amounts to evaluating T(s) on the imaginaryaxis of the complex frequency plane.)The frequency response is characterized by the magnitude and phase of T(j ).Example:
Assume T(s) = a0 + a1sb0 + b1s
s = j T(j ) =
a0 + a1jb0 + b1j =
a0 + j a1b0 + j b1
Since T(j ) is a complex number, we can express the magnitude and phase as,
|T(j )| = a0
2 + ( a1)2
b02 + ( b1)2 Arg[T(j )] = +tan-1
a1a0
- tan-1b1
b0
For the previous example, the magnitude and phase would be,
|T(j )| = gmR21 + ( C1/gm)2
1 + [ R2(C1+C2)]2
Arg[T(j )] = -tan-1( C1/gm) - tan-1[ R2(C1+C2)]
Note: Because the zero is onthe positive real axis, thephase due to the zero is-tan-1( ) rather than +tan-1( ).More about that later.
Lecture 180 – Inverting Amplifiers (3/27/10) Page 180-14
CMOS Analog Circuit Design © P.E. Allen - 2010
Linear Graphical Illustration of Magnitude and Phase – (Optional)The important concepts of frequency response are communicated through the graphicalportrayal of the magnitude and phase.Consider our example,
T(s) = V2(s)V1(s) = -gmR2
sC1/gm - 1s(C1+ C2)R2 + 1 = -T(0)
s/z1 - 1s/p1- 1
where T(0) = gmR2, z1 = +(gm/C1) and p1= -[1/R2(C1+ C2)].
Replacing s with j gives [remember tan-1(-x) = - tan-1(x)],
|T(j )| = T(0)1 + ( /z1)2
1 + ( /p1)2 and Arg[T(j )] = ±180°-tan-1( /z1) - tan-1[ /p1]
Graphically, we get the following if we assume |p1| = 0.1|z1|,
Lecture 180 – Inverting Amplifiers (3/27/10) Page 180-15
CMOS Analog Circuit Design © P.E. Allen - 2010
Logarithmic Graphical Illustration of Frequency Response – (Optional)If the frequency range is large, it is more useful to use a logarithmic scale for thefrequency. In addition, if one expresses the magnitude as 20 log10(|T(j )|, the plots canbe closely approximated with straight lines which enables quick analysis by hand. Suchplots are called Bode plots.
To construct a Bode asymptotic magnitude plot for a low pass transfer function in theform of products of roots:1.) Start at a low frequency and plot 20 log10(|T(0)| until you reach the smallest root.
2.) At the frequency equal to magnitude of the smallest root, change to a line with a slopeof +20dB/decade if the root is a zero or -20dB/decade if the root is a pole.
3.) Continue increasing in frequency until you have plotted the influence of all roots.
Lecture 180 – Inverting Amplifiers (3/27/10) Page 180-16
CMOS Analog Circuit Design © P.E. Allen - 2010
The Influence of the Complex Frequency Plane on Frequency Response – (Optional)The root locations in the complex frequency plane have a direct influence on thefrequency response as illustrated below. Consider the transfer function:
T(s) = -T(0)s/z1 - 1s/p1- 1 = -
|p1|z1 T(0)
s-z1s-p1 = - 0.1T(0)
s-z1s-p1 where z1 = 10|p1|
070413-03
jω
σ
j10
j8
j6
j4
j2
j0
p1=-1 z1=10
j10-z1
j8-z1
j6-z1
j4-z1
j2-z1j0-z1
j10-p1
j8-p1
j6-p1
j4-p1
j2-p1
j0-p1
2 4 6 8 10
1.0
0.8
0.6
0.4
0.2
0.00 1 3 5 7 9
|T(jω)|/T(0)
ω
Region ofmaximuminfluenceby p1
Region ofmaximuminfluenceby z1
Note: The roots maximally influence the magnitude when is such that the anglebetween the vector and the horizontal axis is 45°. This occurs at j1 for p1 and j10 for z1.
Lecture 180 – Inverting Amplifiers (3/27/10) Page 180-17
CMOS Analog Circuit Design © P.E. Allen - 2010
Bandwidth of a Low-Pass Amplifier – (Optional)One of the most important aspects of frequency analysis is to find the frequency at whichthe amplitude decreases by -3dB or 1/ 2. This can easily be found from the magnitudethe frequency response.
060205-03
+
−V1(jω)
+
−V2(jω)
ΑA(0)
|A(jω)|
00
0.707A(0)
ωA=0.707
Bandwidth
ω
Amplifier with a Dominant Root: Since the amplifier is low-pass, the poles will be smaller in magnitude than the zeros.If one of the poles is approximately 4-5 times smaller than the next smallest pole, thebandwidth of the amplifier is given as
Bandwidth |Smallest pole|Amplifier with no Dominant Root:
If there are several poles with roughly the same magnitude, then one should use thegraphical method above to find the bandwidth.
Lecture 180 – Inverting Amplifiers (3/27/10) Page 180-18
CMOS Analog Circuit Design © P.E. Allen - 2010
Example of Finding the Bandwidth of an Amplifier– (Optional)Suppose an amplifier has a pole at -10 rads/sec and another at -20 rads/sec. and a zero at+50 radians/sec. Find the bandwidth of this amplifier if the low frequency gain is 100.SolutionSince the poles are close together, construct a Bode plot and graphically find thebandwidth.
From the graph, we see that the -3dB bandwidth is close to 11-12 Mrad/sec or 1.75-1.91MHz.
Lecture 180 – Inverting Amplifiers (3/27/10) Page 180-19
CMOS Analog Circuit Design © P.E. Allen - 2010
Frequency Response of the Active Inverter - ContinuedSo, back to the frequency response of the active load inverter, we find that if |p1| < z1,then the -3dB frequency is approximately equal to the magnitude of the pole which is[Rout(Cout+CM)]-1.
0512-06-02.EPS
dB
20log10(gmRout)
0dB |p1| ≈ ω-3dBlog10ωz1
Observation:In general, the poles in a MOSFET circuit can be found by summing the capacitance
connected to a node and multiplying this capacitance times the equivalent resistance fromthis node to ground and inverting the product.
Lecture 180 – Inverting Amplifiers (3/27/10) Page 180-20
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 180 -1 - Performance of an Active Resistor-Load InverterCalculate the output-voltage swing limits for VDD = 5 volts, the small-signal gain, the
output resistance, and the -3 dB frequency of active load inverter if (W1/L1) is 2 μm/1 μmand W2/L2 = 1 μm/1 μm, Cgd1 = 100fF, Cbd1 = 200fF, Cbd2 = 100fF, Cgs2 = 200fF, CL = 1pF, and ID1 = ID2 = 100μA, using the parameters in Table 3.1-2.
SolutionFrom the above results we find that:
vOUT(max) = 4.3 volts
vOUT(min) = 0.418 volts
Small-signal voltage gain = -1.92V/VRout = 9.17 k including gds1 and gds2 and 10 k ignoring gds1 and gds2
z1 = 2.10x109 rads/sec
p1 = -64.1x106 rads/sec.
Thus, the -3 dB frequency is 10.2 MHz.
Lecture 180 – Inverting Amplifiers (3/27/10) Page 180-21
CMOS Analog Circuit Design © P.E. Allen - 2010
CURRENT SOURCE INVERTERVoltage Transfer Characteristic of the Current Source Inverter
0 1 2 3 4 5
I D (
mA
)
vOUT
0 1 2 3 4 5v O
UT
vIN
M2
M1
vIN
vOUT
ID
5V
+
-
+
-
W2L2
=2μm1μm
W1L1
= 2μm1μm
Fig. 5.1-5
C
M2
2.5V
A B C
D
E
G H I KF
J1
0
2
3
4
5
M2 saturated
EHIKJ
G
F
M2 active
M1 activ
eM1 sa
turated
vIN=5.0VvIN=4.0V
vIN=4.5V
vIN=1.0V
vIN=1.5V
vIN=2.0V
vIN=2.5V
0.0
0.1
0.2
0.3
0.4
0.5vIN=3.5VvIN=3.0V
D
A,B
Regions of operation for the transistors: M1: vDS1 vGS1 -VTn vOUT vIN - 0.7V
M2: vSD2 vSG2 - |VTp| VDD-vOUT VDD -VGG2 - |VTp| vOUT 3.2V
Lecture 180 – Inverting Amplifiers (3/27/10) Page 180-22
CMOS Analog Circuit Design © P.E. Allen - 2010
Large-Signal Voltage Swing Limits of the Current Source Load InverterMaximum output voltage, vOUT(max):
vOUT (max) VDD
Minimum output voltage, vOUT(min):Assume that M1 is nonsaturated. The minimum output voltage is,
vOUT(min) = vOUT(min) = (VDD - VT1) 1 - 1 -21
VDD - VGG - |VT2|VDD - VT1
2
This result assumes that vIN is taken to VDD.
Lecture 180 – Inverting Amplifiers (3/27/10) Page 180-23
CMOS Analog Circuit Design © P.E. Allen - 2010
Small-Signal Midband Performance of the Current Source Load InverterSmall-Signal Model:
M2
M1vIN
vOUTID
VDD
gm1vgs1
rds2
rds1
+
-
vin
G1 D1=D2
S1=B1=G2
S2=B2
+
-
vout gm1vin rds1
+
-
vin
+
-
voutrds2
Rout
Fig. 5.1-5B
VGG2
Midband Performance:voutvin
= gm1
gds1 + gds2 =
2K'NW 1L1ID
1/2
11 + 2
1
D!!! and Rout =
1gds1 + gds2
1
ID( 1 + 2)
060614-01
vin
vout
Strong InversionWeakInvers-
ionlog(IBias)≈ 1µA
Lecture 180 – Inverting Amplifiers (3/27/10) Page 180-24
CMOS Analog Circuit Design © P.E. Allen - 2010
Frequency Response of the Current Source Load InverterIncorporation of the parasiticcapacitors into the small-signalmodel (x is connected to VGG2):
If we assume the input voltagehas a small source resistance,then we can write the following:
Vout(s)Vin(s) =
gmRout 1 -sz1
1 -sp1
where gm = gm1, p1 = 1
Rout(Cout+CM) , and z1 = gmCM
and Rout = 1
gds1 + gds2 and Cout = Cgd2 + Cbd1 + Cbd2 + CL CM = Cgd1
Therefore, if |p1|<|z1|, then the 3 dB frequency response can be expressed as
-3dB 1 = gds1 + gds2
Cgd1 + Cgd2 + Cbd1 + Cbd2 + CL
Cgd2
Cgd1
Cgs2
Cbd2
Cbd1
VDD
Vin
Vout
CL
M2
M1
CM
CoutRoutVout
+
-
Vin gmVin
+
-
Fig. 5.1-4
x
Lecture 180 – Inverting Amplifiers (3/27/10) Page 180-25
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 180-2 - Performance of a Current-Sink InverterA current-sink inverter is shown. Assume that W1 = 2 μm, L1 = 1
μm, W2 = 1 μm, L2 = 1μm, VDD = 5 volts, VNB1 = 3 volts, and theparameters of Table 3.1-2 describe M1 and M2. Use the capacitorvalues of Example 180-1 (Cgd1 = C gd2). Calculate the output-swinglimits and the small-signal performance.Solution
To attain the output signal-swing limitations, we treat current sink inverter as acurrent source CMOS inverter with PMOS parameters for the NMOS and NMOSparameters for the PMOS and use NMOS equations. Using a prime notation to designatethe results of the current source CMOS inverter that exchanges the PMOS and NMOSmodel parameters,
vOUT(max)’ = 5V and vOUT(min)’ = (5-0.7) 1 - 1 -110·150·2
3-0.75-0-0.7
2 = 0.74V
In terms of the current sink CMOS inverter, these limits are subtracted from 5V to getvOUT(max) = 4.26V and v OUT (min) = 0V.
To find the small signal performance, first calculate the dc current. The dc current, ID, is
ID = KN’W 1
2L1 (VGG1-VTN)2 =
110·12·1 (3-0.7)2 = 291μA
vout/vin = 9.2V/V, Rout = 38.1 k , and f-3dB = 2.78 MHz.
VDD
vOUT
vIN
VNB1
M1
M2
+−
VSG1
ID
070413-04
Lecture 180 – Inverting Amplifiers (3/27/10) Page 180-26
CMOS Analog Circuit Design © P.E. Allen - 2010
PUSH-PULL INVERTING AMPLIFIERVoltage Transfer Characteristic of the Push-Pull Inverting Amplifier
0 1 2 3 4
I D (
mA
)
vOUT
0 1 2 3 4 5
v OU
T
vIN
M2
M1
vIN
vOUT
ID
5V
+
-
+
-
W2L2
=2μm1μm
W1L1
= 1μm1μm
Fig. 5.1-8
0.0
0.2
0.4
0.6
0.8
1.0
vIN=1.0VvIN=1.5V
vIN=2.0V
vIN=2.5V
vIN=3.0V
A B C DE
GH I K
F
J
vIN=5.0V vIN=4.0VvIN=4.5V vIN=3.5V
E
D
FG
HI
vIN=3.0V
2
3
4
1
0
M2 active
M2 saturat
edM1 act
iveM1 sat
urated
CA,B 5
vIN=4.5VvIN=3.5V
vIN=2.5V
J,K
vIN=2.0V
vIN=0.5VvIN=1.0V
vIN=1.5V
Notethe rail-to-railoutputvoltageswing
Regions of operation for M1 and M2: M1: vDS1 vGS1 - VT1 vOUT vIN - 0.7V
M2: vSD2 vSG2-|VT2| VDD -vOUT VDD -vIN-|VT2| vOUT vIN + 0.7V
Lecture 180 – Inverting Amplifiers (3/27/10) Page 180-27
CMOS Analog Circuit Design © P.E. Allen - 2010
Small-Signal Performance of the Push-Pull Amplifier
gm1vin rds1 gm2vin rds2
+
-
vin
+
-
vout
Fig. 5.1-9
Cout
CM
M2
M1
5V
+
-
+
-
vinvout
Small-signal analysis gives the following results:
voutvin
= (gm1 + gm2)gds1 + gds2
= (2/ID) K'N(W1/L1) + K'P(W2/L2)
1 + 2
Rout = 1
gds1 + gds2
z = gm1+gm2
CM =
gm1+gm2Cgd1+Cgd2
and p1 = (gds1 + gds2)
Cgd1 + Cgd2 + Cbd1 + Cbd2 + CL
If z1 > |p1|, then
-3dB = gds1 + gds2
Cgd1 + Cgd2 + Cbd1 + Cbd2 + CL
Lecture 180 – Inverting Amplifiers (3/27/10) Page 180-28
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 180-3 - Performance of a Push-Pull InverterThe performance of a push-pull CMOS inverter is to be examined. Assume that W 1 =
1 μm, L1 = 1 μm, W2 = 2 μm, L2 = 1μm, VDD = 5 volts, and use the parameters of Table3.1-2 to model M1 and M2. Use the capacitor values of Example 180-1 (Cgd1 = Cgd2).Calculate the output-swing limits and the small-signal performance assuming that ID1 =ID2 = 300μA.
SolutionThe output swing is seen to be from 0V to 5V. In order to find the small signal
performance, we will make the important assumption that both transistors are operatingin the saturation region. Therefore:
voutvin
= -257μS - 245μS
12μS + 15μS = -18.6V/V
Rout = 37 k
f-3dB = 2.86 MHz
andz1 = 399 MHz
Lecture 180 – Inverting Amplifiers (3/27/10) Page 180-29
CMOS Analog Circuit Design © P.E. Allen - 2010
NOISE ANALYSIS OF INVERTING AMPLIFIERSNoise Analysis of Inverting AmplifiersNoise model:
en22
en12
M2
M1
NoiseFree
MOSFETs
eout2
VDD
vin
eeq2
M2
M1
NoiseFree
MOSFETs
eout2
VDD
vin
Fig. 5.1-10
*
*
*
Approach:1.) Assume a mean-square input-voltage-noise spectral density en
2 in series with thegate of each MOSFET.(This step assumes that the MOSFET is the common source configuration.)
2.) Calculate the output-voltage-noise spectral density, eout2 (Assume all sources are
additive).3.) Refer the output-voltage-noise spectral density back to the input to get equivalent
input noise eeq2.
4.) Substitute the type of noise source, 1/f or thermal.
Lecture 180 – Inverting Amplifiers (3/27/10) Page 180-30
CMOS Analog Circuit Design © P.E. Allen - 2010
Noise Analysis of the Active Load Inverter1.) See model to the right.
2.) eout2 = en1
2 gm1gm2
2+ en22
3.) eeq2 = en1
2 1 +gm2gm1
2 en2en1
2
Up to now, the type of noise is not defined.1/f Noise
Substituting en2=
KF2fCoxWLK’ =
BfWL , into the above gives,
eeq(1/f)2 =
B1f W1L1
1 +K'2B2K'1B1
L1L2
2
eeq(1/f) = B1
f W1L1
1/2 1 +
K'2B2K'1B1
L1L2
2 1/2
To minimize 1/f noise, 1.) Make L2>>L1, 2.) increase the value of W1 and 3.) choose M1as a PMOS.Thermal Noise
Substituting en2=
8kT3gm
into the above gives,
eeq(th) =8kT
3[2K'1(W/L)1I1]1/2 1+W 2L1K'2L2W 1K'1
1/2 1/2
To minimize thermal noise, maximize the gain of the inverter.
en22
en12
M2
M1
NoiseFree
MOSFETs
eout2
VDD
vin
eeq2
M2
M1
NoiseFree
MOSFET
eout2
VDD
vin
Fig. 5.1-
*
*
*
Lecture 180 – Inverting Amplifiers (3/27/10) Page 180-31
CMOS Analog Circuit Design © P.E. Allen - 2010
Noise Analysis of the Active Load Inverter - Continued
When calculating the contribution of en22 to eout
2, it was assumed that the gain wasunity. To verify this assumption consider the following model:
en22
gm2vgs2 rds1vgs2
+
-
rds2 eout2
+
_
Fig. 5.1-11
*
We can show that,eout
2
en22 =
gm2(rds1||rds2)1 + gm2(rds1||rds2) 2 1
Lecture 180 – Inverting Amplifiers (3/27/10) Page 180-32
CMOS Analog Circuit Design © P.E. Allen - 2010
Noise Analysis of the Current Source Load Inverting AmplifierModel:
en22
en12
M2
M1
NoiseFree
MOSFETs
eout2
VDD
vin
eeq2
M2
M1
NoiseFree
MOSFETs
eout2
VDD
vin
Fig. 5.1-12.
VGG2*
* *
The output-voltage-noise spectral density of this inverter can be written as,eout
2 = (gm1rout)2en12 + (gm2rout)2en2
2
or
eeq2 = en1
2 + (gm2rout)2
(gm1rout)2en22 = en1
2 1 +gm2
gm1
2en2
2
en12
This result is identical with the active load inverter.Thus the noise performance of the two circuits are equivalent although the small-signalvoltage gain is significantly different.
Lecture 180 – Inverting Amplifiers (3/27/10) Page 180-33
CMOS Analog Circuit Design © P.E. Allen - 2010
Noise Analysis of the Push-Pull AmplifierModel:
The equivalent input-voltage-noise spectral density of the push-pull inverter can be foundas
eeq = gm1en1
gm1 + gm2
2+
gm2en2gm1 + gm2
2
If the two transconductances are balanced (gm1 = gm2), then the noise contribution ofeach device is divided by two.The total noise contribution can only be reduced by reducing the noise contribution ofeach device. (Basically, both M1 and M2 act like the “load” transistor and “input” transistor, sothere is no defined input transistor that can cause the noise of the load transistor to beinsignificant.)
en22
en12
VDD
M2
M1
eout2vin
NoiseFree
MOSFETs
Fig. 5.1-13.
*
*
Lecture 180 – Inverting Amplifiers (3/27/10) Page 180-34
CMOS Analog Circuit Design © P.E. Allen - 2010
SUMMARYTable of Performance
InverterAC Voltage
GainAC OutputResistance Bandwidth (CGB=0)
Equivalent,input-referred,mean-square noise voltage
p-channelactive load inverter
-gm1gm2
1gm2
gm2CBD1+CGS1+CGS2+CBD2
en12 + en2
2gm2
gm1
2
Currentsource loadinverter
-gm1gds1+gds2
1gds1+gds2
gds1+gds2CBD1+CGD1+CDG2+CBD2
en12 + en2
2gm2
gm1
2
Push-Pullinverter
-(gm1+gm2)gds1+gds2
1gds1+gds2
gds1+gds2CBD1+CGD1+CGS2+CBD2 gm1en1
gm1+ gm2
2+gm1en1
gm1+ gm2
2
Lecture 190 – Differential Amplifier (3/27/10) Page 190-1
CMOS Analog Circuit Design © P.E. Allen - 2010
LECTURE 190 – DIFFERENTIAL AMPLIFIERLECTURE ORGANIZATION
Outline• Characterization of a differential amplifier• Differential amplifier with a current mirror load• Differential amplifier with MOS diode loads• An intuitive method of small signal analysis• Large signal performance of differential amplifiers• Differential amplifiers with current source loads• Design of differential amplifiers• SummaryCMOS Analog Circuit Design, 2nd Edition ReferencePages 180-199
Lecture 190 – Differential Amplifier (3/27/10) Page 190-2
CMOS Analog Circuit Design © P.E. Allen - 2010
CHARACTERIZATION OF A DIFFERENTIAL AMPLIFIERWhat is a Differential Amplifier?
A differential amplifier is an amplifier that amplifies the difference between twovoltages and rejects the average or common mode value of the two voltages.Differential and common mode voltages:
v1 and v2 are called single-ended voltages. They are voltages referenced to acground.The differential-mode input voltage, vID, is the voltage difference between v1 and v2.
The common-mode input voltage, vIC, is the average value of v1 and v2 .
vID = v1 - v2 and vIC = v1+v2
2 v1 = vIC + 0.5vID and v2 = vIC - 0.5vID
vOUT = AVDvID ± AVCvIC = AVD(v1 - v2) ± AVC v1 + v2
2
whereAVD = differential-mode voltage gain
AVC = common-mode voltage gain
+- +
vOUT
-
vIC
vID2
vID2
Fig. 5.2-1B
Lecture 190 – Differential Amplifier (3/27/10) Page 190-3
CMOS Analog Circuit Design © P.E. Allen - 2010
Differential Amplifier Definitions• Common mode rejection rato (CMRR)
CMRR = AVD
AVC
CMRR is a measure of how well the differential amplifier rejects the common-modeinput voltage in favor of the differential-input voltage.• Input common-mode range (ICMR)
The input common-mode range is the range of common-mode voltages over whichthe differential amplifier continues to sense and amplify the difference signal with thesame gain.Typically, the ICMR is defined by the common-mode voltage range over which allMOSFETs remain in the saturation region.
• Output offset voltage (VOS(out))
The output offset voltage is the voltage which appears at the output of the differentialamplifier when the input terminals are connected together.• Input offset voltage (VOS(in) = VOS)
The input offset voltage is equal to the output offset voltage divided by the differentialvoltage gain.
VOS = VOS(out)
AVD
Lecture 190 – Differential Amplifier (3/27/10) Page 190-4
CMOS Analog Circuit Design © P.E. Allen - 2010
Transconductance Characteristic of the Differential AmplifierConsider the following n-channel differentialamplifier (called a source-coupled pair). Whereshould bulk be connected? Consider a p-well,CMOS technology:
�yD1 G1 S1 �yS2 G2 D2
n+ n+ n+ n+ n+p+
p-well
n-substrate
VDD
Fig. 5.2-3
1.) Bulks connected to the sources: No modulation of VT but large common modeparasitic capacitance.2.) Bulks connected to ground: Smaller common mode parasitic capacitors, butmodulation of VT.
What are the implications of a large common mode capacitance?
IBias
iD1 iD2
VDD
VBulk
M1 M2
M3M4 ISS
+-
vG1
vGS1+
-vGS2
vG2
Fig. 5.2-2
vID
+
−R R
0V
+
−vINvIN
Littlecharging ofcapacitance
Large charging of capacitance
070416-02
Lecture 190 – Differential Amplifier (3/27/10) Page 190-5
CMOS Analog Circuit Design © P.E. Allen - 2010
Transconductance Characteristic of the Differential Amplifier - ContinuedDefining equations:
vID = vGS1 vGS2 = 2iD1 1/2
2iD2 1/2
and ISS = iD1 + iD2
Solution:
iD1 = ISS2 +
ISS2
v2ID
ISS
2v4ID
4I2SS
1/2and iD2 =
ISS2
ISS2
v2ID
ISS
2v4ID
4I2SS
1/2
which are valid for vID < 2(ISS/ )1/2.Illustration of the result:
Differentiating iD1 (or iD2)with respect to vID andsetting VID =0V gives
gm = diD1dvID(VID = 0) =
bISS4 =
K'1ISSW14L1 (half the gm of an inverting amplifier)
iD/ISS
0.8
0.2
0.0
1.0
0.6
0.4
1.414 2.0-1.414-2.0vID
(ISS/ß)0.5
iD1
iD2
Fig. 5.2-4
Lecture 190 – Differential Amplifier (3/27/10) Page 190-6
CMOS Analog Circuit Design © P.E. Allen - 2010
DIFFERENTIAL AMPLIFIER WITH A CURRENT MIRROR LOADVoltage Transfer Characteristic of the Differential Amplifier
In order to obtain the voltage transfer characteristic, a load for the differential amplifiermust be defined. We will select a current mirror load as illustrated below.
Note that output signal to ground isequivalent to the differential outputsignal due to the current mirror.The short-circuit, transconductance isgiven as
gm = diOUTdvID (VID = 0) = ISS =
K'1ISSW1L1
VBias
ISS
M1 M2
M3 M4
VDD
M5
vGS1+
-vGS2
+-
vG2
-
vOUT
iOUT
vG1
-
iD1 iD2
iD3 iD4
-
+
Fig. 5.2-5
2μm1μm
2μm1μm
2μm1μm
2μm1μm
2μm1μm
VDD2
Lecture 190 – Differential Amplifier (3/27/10) Page 190-7
CMOS Analog Circuit Design © P.E. Allen - 2010
Voltage Transfer Function of the Differential Amplifer with a Current Mirror Load
VBias
ISS
M1 M2
M3 M4
VDD
M5
vGS1+
- vGS2+
-vG2
-
vOUT
iOUT
vG1
-
iD1 iD2
iD3 iD4
-
+2μm1μm
2μm1μm
2μm1μm
2μm1μm
2μm1μm
0
1
2
3
4
5
-1 -0.5 0 0.5 1vID (Volts)
v OU
T (V
olts
)
M2 saturatedM2 active
M4 activeM4 saturated
VIC� = 2V
= 5V
060705-01
Regions of operation of the transistors:M2 is saturated when, vDS2 vGS2-VTN vOUT-VS1 VIC-0.5vID-VS1-VTN vOUT VIC-VTN
where we have assumed that the region of transition for M2 is close to vID = 0V. M4 is saturated when, vSD4 vSG4 - |VTP| VDD-vOUT VSG4-|VTP| vOUT VDD-VSG4+|VTP|
The regions of operations shown on the voltage transfer function assume ISS = 100μA.
Note: VSG4 = 2·5050·2 +|VTP| = 1 + |VTP| vOUT 5 - 1 - 0.7 + 0.7 = 4V
Lecture 190 – Differential Amplifier (3/27/10) Page 190-8
CMOS Analog Circuit Design © P.E. Allen - 2010
Differential Amplifier Using p-channel Input MOSFETs
VBias IDD
M1 M2
M3 M4
VDD
M5
vSG1
+
-vSG2
+
-
vG2
-
vOUT
iOUT
vG1
-
iD1 iD2
iD3 iD4
-
+
Fig. 5.2-7
++
Lecture 190 – Differential Amplifier (3/27/10) Page 190-9
CMOS Analog Circuit Design © P.E. Allen - 2010
Input Common Mode Range (ICMR)ICMR is found by setting vID = 0 and varying vIC
until one of the transistors leaves the saturation.Highest Common Mode VoltagePath from G1 through M1 and M3 to VDD:
VIC(max) =VG1(max) =VG2(max)
=VDD -VSG3 -VDS1(sat) +VGS1or
VIC(max) = VDD - VSG3 + VTN1
Path from G2 through M2 and M4 to VDD:
VIC(max)’ =VDD -VSD4(sat) -VDS2(sat) +VGS2
=VDD -VSD4(sat) + VTN2
VIC(max) = VDD - VSG3 + VTN1
Lowest Common Mode Voltage (Assume a VSS for generality)
VIC(min) = VSS +VDS5(sat) + VGS1 = VSS +VDS5(sat) + VGS2
where we have assumed that VGS1 = VGS2 during changes in the input common modevoltage.
VBias
ISS
M1 M2
M3 M4
VDD
M5
vGS1+
-vGS2
+-
vG2
-
vOUT
iOUT
vG1
-
iD1 iD2
iD3 iD4
-
+
Fig. 330-02
2μm1μm
2μm1μm
2μm1μm
2μm1μm
2μm1μm
VDD2
Lecture 190 – Differential Amplifier (3/27/10) Page 190-10
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 190-1 - Small-Signal Analysis of the Differential-Mode of the Diff. AmpA requirement for differential-mode operation is that the differential amplifier is balanced†
gm3rds3
1
rds1
gm1vgs1
rds2
gm2vgs2
i3i3
+
-
+
-
+G2
vid
vg1 vg2
G1
C1
-
rds5
S1=S2
rds4
C3
C2
+
-
vout
D1=G3=D3=G4
S3 S4
D2=D4
gm3rds31
rds1gm1vgs1 rds2gm2vgs2
i3
i3
+
-
+
-
+G2
vid
vgs1 vgs2
G1
C1
-
S1=S2=S3=S4
rds4
C3C2
+
-
vout
D1=G3=D3=G4 D2=D4iout'
ISS
M1 M2
M3 M4
VDD
M5
vout
iout
iD1 iD2
iD3 iD4
-
+
Fig. 330-03
VBias
vid
Differential Transconductance:Assume that the output of the differential amplifier is an ac short.
iout’ = gm1gm3rp1
1 + gm3rp1 vgs1 gm2vgs2 gm1vgs1 gm2vgs2 = gmdvid
where gm1 = gm2 = gmd, rp1 = rds1 rds3 and i'out designates the output current into a shortcircuit.
† It can be shown that the current mirror causes this requirement to be invalid because the drain loads are not matched. However, we will continue to usethe assumption regardless.
Lecture 190 – Differential Amplifier (3/27/10) Page 190-11
CMOS Analog Circuit Design © P.E. Allen - 2010
Small-Signal Analysis of the Differential-Mode of the Diff. Amplifier - ContinuedOutput Resistance: Differential Voltage Gain:
rout = 1
gds2 + gds4 = rds2||rds4 Av =
voutvid
= gmd
gds2 + gds4
If we assume that all transistors are in saturation and replace the small signa
parameters of gm and rds in terms of their large-signal model equivalents, we achieve
Av = voutvid
= (K'1ISSW 1/L1)1/2
( 2 + 4)(ISS/2) = 2
2 + 4
K'1W 1ISSL1
1/2
1ISS
Note that the small-signal gain is inverselyproportional to the square root of the biascurrent!Example:
If W1/L1 = 2μm/1μm and ISS = 50μA(10μA), then
Av(n-channel) = 46.6V/V (104.23V/V)
Av(p-channel) = 31.4V/V (70.27V/V)
rout = 1
gds2 + gds4 =
125μA·0.09V-1 = 0.444M (2.22M )
060614-01
vin
vout
Strong InversionWeakInvers-
ionlog(IBias≈ 1μA
Lecture 190 – Differential Amplifier (3/27/10) Page 190-12
CMOS Analog Circuit Design © P.E. Allen - 2010
Common Mode Analysis for the Current Mirror Load Differential AmplifierThe current mirror load differential amplifier is not a good example for common modeanalysis because the current mirror rejects the common mode signal.
-
+
vic
M1 M2
M4
M5
vout ≈ 0V
VDD
VBias+
-
M3M1-M3-M4
Fig. 5.2-8A
M2
Total commonmode Output
due to vic
= Common modeoutput due to
M1-M3-M4 path -
Common modeoutput due to
M2 path
Therefore: • The common mode output voltage should ideally be zero. • Any voltage that exists at the output is due to mismatches in the gain between the two
different paths.
Lecture 190 – Differential Amplifier (3/27/10) Page 190-13
CMOS Analog Circuit Design © P.E. Allen - 2010
DIFFERENTIAL AMPLIFIER WITH MOS DIODE LOADSSmall-Signal Analysis of the Common-Mode of the Differential AmplifierThe common-mode gain of the differential amplifier with a current mirror load is ideallyzero.To illustrate the common-mode gain, we need a different type of load so we will considerthe following:
Differential-Mode Analysis:
vo1vid
-gm12gm3
and vo2vid
+ gm22gm4
Note that these voltage gains are half of the active load inverter voltage gain.
vic
vo1
v1
vo2
v2
VBias
ISS
VDD
M1 M2
M3 M4
M5
vo1
vid
VDD
M1 M2
M3 M4vo2 vo1
vic
vo2
VBias
ISS
VDD
M1 M2
M3 M4
2ISS M5x1
22
Differential-mode circuit Common-mode circuitGeneral circuit
2vid
2
Fig. 330-05
Lecture 190 – Differential Amplifier (3/27/10) Page 190-14
CMOS Analog Circuit Design © P.E. Allen - 2010
Small-Signal Analysis of the Common-Mode of the Differential Amplifier – Cont’d
Common-Mode Analysis:
Assume that rds1 is large and can be ignored(greatly simplifies the analysis).
vgs1 = vg1-vs1 = vic - 2gm1rds5vgs1
Solving for vgs1 gives
vgs1 = vic
1 + 2gm1rds5
The single-ended output voltage, vo1, as a function of vic can be written as
vo1vic
= - gm1[rds3||(1/gm3)]
1 + 2gm1rds5 -
(gm1/gm3)1 + 2gm1rds5
- gds52gm3
Common-Mode Rejection Ratio (CMRR):
CMRR = |vo1/vid||vo1/vic| =
gm1/2gm3
gds5/2gm3 = gm1rds5
How could you easily increase the CMRR of this differential amplifier?
+
-vic
vgs1+ -
2rds5 rds1
gm1vgs1
rds3 gm31
+
-vo1
Fig. 330-06
Lecture 190 – Differential Amplifier (3/27/10) Page 190-15
CMOS Analog Circuit Design © P.E. Allen - 2010
Frequency Response of the Differential AmplifierBack to the current mirror load differential amplifier:
gm31gm1vgs1 rds2gm2vgs2
i3
i3
+
-
+
-
+G2
vid
vgs1 vgs2
G1
C1
-
S1=S2=S3=S4
rds4
C3C2
+
-
vout
D1=G3=D3=G4 D2=D4
M1 M2
M3 M4
VDD
M5
vout
-
+
VBias
vidCL
Cbd1
Cbd2
Cbd3 Cbd4
Cgd2Cgd1
Cgs3+Cgs4
Cgd4
gm31gm1vgs1 rds2gm2vgs2
i3
i3
+
-
+
-
+ vid
vgs1 vgs2
-
rds4C2
+
-
vout
070416-03
Ignore the zeros that occur due to Cgd1, Cgd2 and Cgd4.
C1 = Cgd1+Cbd1+Cbd3+Cgs3+Cgs4, C2 = Cbd2 +Cbd4+Cgd2+CL and C3 = Cgd4
If gm3/C1 >> (gds2+gds4)/C2, then we can write
Vout(s) gm1
gds2 + gds4 2
s + 2[Vgs1(s) - Vgs2(s)] where 2
gds2 + gds4C2
then the approximate frequency response of the differential amplifier reduces toVout(s)Vid(s)
gm1gds2 + gds4
2s + 2 (A more detailed analysis will be made in Lecture 220)
Lecture 190 – Differential Amplifier (3/27/10) Page 190-16
CMOS Analog Circuit Design © P.E. Allen - 2010
AN INTUITIVE METHOD OF SMALL SIGNAL ANALYSISSimplification of Small Signal AnalysisSmall signal analysis is used so often in analog circuit design that it becomes desirable tofind faster ways of performing this important analysis.Intuitive Analysis (or Schematic Analysis)Technique:1.) Identify the transistor(s) that convert the input voltage to current (these transistorsare called transconductance transistors).2.) Trace the currents to where they flow into an equivalent resistance to ground.3.) Multiply this resistance by the current to get the voltage at this node to ground.4.) Repeat this process until the output is reached.Simple Example:
vo1 = -(gm1vin) R1 vout = -(gm2vo1)R2 vout = (gm1R1gm2R2)vin
vin
vout
VDD
R1
gm1vin
VDD
vo1 gm2vo1
R2M1
M2
Fig. 5.2-10C
Lecture 190 – Differential Amplifier (3/27/10) Page 190-17
CMOS Analog Circuit Design © P.E. Allen - 2010
Intuitive Analysis of the Current-Mirror Load Differential Amplifier
VBias
M1 M2
M3 M4
VDD
M5
vid+
- +
-vout
gm2vid
-
+
Fig. 5.2-11
2vid2
2gm1vid
2
gm1vid2
gm1vid2
+ -vid
rout
1.) i1 = 0.5gm1vid and i2 = -0.5gm2vid
2.) i3 = i1 = 0.5gm1vid
3.) i4 = i3 = 0.5gm1vid
4.) The resistance at the output node, rout, is rds2||rds4 or 1
gds2 + gds4
5.) vout = (0.5gm1vid+0.5gm2vid )rout =gm1vin
gds2+gds4 =
gm2vin
gds2+gds4
vout
vin =
gm1
gds2+gds4
Lecture 190 – Differential Amplifier (3/27/10) Page 190-18
CMOS Analog Circuit Design © P.E. Allen - 2010
Some Concepts to Help Extend the Intuitive Method of Small-Signal Analysis1.) Approximate the output resistance of any cascode circuit as
Rout (gm2rds2)rds1
where M1 is a transistor cascoded by M2.2.) If there is a resistance, R, in series with the source of the transconductance transistor,let the effective transconductance be
gm(eff) =
gm
1+gmR
Proof:gm2(eff)vin
vin
VBias
M2
M1 vinrds1
M2
gm2(eff)vin gm2vgs2
vgs2
vin
+ -
rds1
iout
Small-signal model
Fig. 5.2-11A
vgs2 = v
g2 - vs2 = vin - (g
m2rds1)vgs2 vgs2 =
vin
1+gm2rds1
Thus, iout
= g
m2vin
1+gm2rds1
= gm2(eff) v
in
Lecture 190 – Differential Amplifier (3/27/10) Page 190-19
CMOS Analog Circuit Design © P.E. Allen - 2010
Noise Analysis of the Differential Amplifier
VBias
M1 M2
M3 M4
VDD
M5
Vout
ito2
Fig. 5.2-11C
en12
en42en32
en22 eeq2
VBias
VDD
M5
M1 M2
M3 M4
M5
vOUT
* *
* *
*
Solve for the total output-noise current to get,ito 2 = gm1
2en12 + gm2
2en22 + gm3
2en32 + gm4
2en42
This output-noise current can be expressed in terms of an equivalent input noise voltageeeq
2, given as ito2 = gm1
2eeq2
Equating the above two expressions for the total output-noise current gives,
eeq2 = en1
2 + en22 +
gm3gm1
2 en32 + en4
2
1/f Noise (en12=en2
2 and en32=en4
2): Thermal Noise (en12=en2
2 and en32=en4
2):
eeq(1/f)=2BP
f W1L1 1 +
K’N BNK’PBP
L1L3
2 eeq(th)=16kT
3[2K'1(W/L)1I1]1/2 1+W 3L1K'3L3W 1K'1
1/2
Lecture 190 – Differential Amplifier (3/27/10) Page 190-20
CMOS Analog Circuit Design © P.E. Allen - 2010
iout
vin
ISS
-ISS
iout
vin
ISS
-ISS
Linearization
060608-03
LARGE SIGNAL PERFORMANCE OF THE DIFFERENTIAL AMPLIFIERLinearization of the Transconductance
Goal:
Method (degeneration):
060118-10
VDD
VDD2
iout
vin
+
−
RS2
RS2
VNBias1
M1 M2
M3 M4
M5
or
VDD
VDD2
iout
vin
+
−
RS
VNBias1
M1 M2
M3 M4
M5M6
Lecture 190 – Differential Amplifier (3/27/10) Page 190-21
CMOS Analog Circuit Design © P.E. Allen - 2010
Linearization with Active Devices
060608-05
VDD
VDD2
iout
vin
+
−VNBias1
M1 M2
M3 M4
M5x1/2M5x1/2
VBias
M6
M6 is in deep triode region
or
VDD
VDD2
iout
vin
+
−VNBias1
M1 M2
M3 M4
M5M6
M6
M6 and M7 are in the triode region
M7
Note that these transconductors on this slide and the last can all have a varyingtransconductance by changing the value of ISS.
Lecture 190 – Differential Amplifier (3/27/10) Page 190-22
CMOS Analog Circuit Design © P.E. Allen - 2010
Slew Rate of the Differential AmplifierSlew Rate (SR) = Maximum output-voltage rate (either positive or negative)
It is caused by, iOUT = CL
dvOUT
dt . When iOUT is a constant, the rate is a constant.Consider the following current-mirror load, differential amplifiers:
CL
VBias
ISS
M1 M2
M3 M4
VDD
M5
vGS1+
-vGS2
+-
vG2
-
vOUT
iOUT
vG1
-
iD1 iD2
iD3 iD4
-
+
CL
VBias IDD
M1 M2
M3 M4
VDD
M5
vSG1
+
-vSG2
+
-
vG2
-
vOUT
iOUT
vG1
-
iD1 iD2
iD3 iD4
-
+
Fig. 5.2-11B
++
Note that slew rate can only occur when the differential input signal is large enough tocause ISS (IDD) to flow through only one of the differential input transistors.
SR = ISS
CL =
IDD
CL If CL = 5pF and ISS = 10μA, the slew rate is SR = 2V/μs.
(For the BJT differential amplifier slewing occurs at ±100mV whereas for the MOSFETdifferential amplifier it can be ±2V or more.)
Lecture 190 – Differential Amplifier (3/27/10) Page 190-23
CMOS Analog Circuit Design © P.E. Allen - 2010
DIFFERENTIAL AMPLIFIERS WITH CURRENT SOURCE LOADSCurrent-Source Load Differential AmplifierGives a truly balanced differential amplifier.
Also, the upper input common-mode range isextended.
However, a problem occurs if I1 I3 or if I2 I4.
VDD
IBias
M1 M2
M3 M4
M5
X2
I1 I2
I3 I4
v1 v2
v3 v4
M6
M7X1
X1X1
X1
X1 X1
Fig. 5.2-12
I5
I1I3
VDS1<VDS(sat) VDD0
0
Current
I1I3
VSD3<VSD(sat) VDD0
0
Current
Fig. 5.2-13 (a.) I1>I3. (b.) I3>I1.
vDS1 vDS1
Lecture 190 – Differential Amplifier (3/27/10) Page 190-24
CMOS Analog Circuit Design © P.E. Allen - 2010
A Differential-Output, Differential-Input AmplifierProbably the best way to solve the current mismatch problem is through the use ofcommon-mode feedback.Consider the following solution to the previous problem.
v1M1 M2
M3 M4
M5
VDD
VSS
IBias
VCM
v4v3
v2
MC2A
MC2B
MC1
MC3
MC4
MC5MB
I3 I4
IC4IC3
Fig. 5.2-14
Common-mode feed-back circuit
Self-resistancesof M1-M4
Operation:• Common mode output voltages are sensed at the gates of MC2A and MC2B and
compared to VCM.• The current in MC3 provides the negative feedback to drive the common mode output
voltage to the desired level.• With large values of output voltage, this common mode feedback scheme has flaws.
Lecture 190 – Differential Amplifier (3/27/10) Page 190-25
CMOS Analog Circuit Design © P.E. Allen - 2010
Common-Mode Stabilization of the Diff.-Output, Diff.-Input Amplifier - ContinuedThe following circuit avoids the large differential output signal swing problems.
v1M1 M2
M3 M4
M5
VDD
VSS
IBias
VCM
v4v3
v2MC2
RCM1
MC1
MC3
MC4
MC5MB
I3 I4
IC4IC3
Fig. 5.2-145
Common-mode feed-back circuit
Self-resistancesof M1-M4
RCM2
Note that RCM1 and RCM2 must not load the output of the differential amplifier.
(We will examine more CM feedback schemes in Lecture 280.)
Lecture 190 – Differential Amplifier (3/27/10) Page 190-26
CMOS Analog Circuit Design © P.E. Allen - 2010
DESIGN OF DIFFERENTIAL AMPLIFIERSDesign of a CMOS Differential Amplifier with a Current Mirror LoadDesign Considerations:
Constraints SpecificationsPower supplyTechnologyTemperature
Small-signal gainFrequency response (CL)ICMRSlew rate (CL)Power dissipation
RelationshipsAv = gm1Rout
-3dB = 1/RoutCL
VIC(max) = VDD - VSG3 + VTN1
VIC(min) = VSS +VDS5(sat) + VGS1 = VSS +VDS5(sat) + VGS2
SR = ISS/CL
Pdiss = (VDD+|VSS|)x(All dc currents flowing from VDD or to VSS)
ALA20
-
+vin M1 M2
M3 M4
M5
vout
VDD
VSS
VBias
CL
I5
Lecture 190 – Differential Amplifier (3/27/10) Page 190-27
CMOS Analog Circuit Design © P.E. Allen - 2010
Design of a CMOS Differential Amplifier with a Current Mirror Load - Continued
Schematic-wise, the design procedure is illustrated asshown:
Procedure:1.) Pick ISS to satisfy the slew rate knowing CL orthe power dissipation2.) Check to see if Rout will satisfy the frequencyresponse, if not change ISS or modify circuit
3.) Design W3/L3 (W4/L4) to satisfy the upper ICMR
4.) Design W1/L1 (W2/L2) to satisfy the gain
5.) Design W5/L5 to satisfy the lower ICMR
6.) Iterate where necessary
ALA20
-
+vin M1 M2
M3 M4
M5
vout
VDD
VSS
VBias+
-
CL
VSG4+
-
gm1Rout
Min. ICMR I5I5 = SR·CL,
ω-3dB, Pdiss
Max. ICMR
Lecture 190 – Differential Amplifier (3/27/10) Page 190-28
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 190-2 - Design of a MOS Differential Amp. with a Current Mirror LoadDesign the currents and W/L values of the current mirror load MOS differential amplifierto satisfy the following specifications: VDD = -VSS = 2.5V, SR 10V/μs (CL=5pF), f-3dB
100kHz (CL=5pF), a small signal gain of 100V/V, -1.5V ICMR 2V and Pdiss 1mWUse the parameters of K N’=110μA/V2, K P’=50μA/V2, VTN=0.7V, VTP=-0.7V
N=0.04V-1 and P=0.05V-1.
Solution1.) To meet the slew rate, ISS 50μA. For maximum Pdiss, ISS 200μA.
2.) f-3dB of 100kHz implies that Rout 318k . Therefore Rout = 2
( N+ P)ISS 318k
ISS 70μA Thus, pick ISS = 100μA
3.) VIC(max) = VDD - VSG3 + VTN1 2V = 2.5 - VSG3 + 0.7
VSG3 = 1.2V = 2·50μA
50μA/V2(W3/L3) + 0.7
W3L3 =
W4L4 =
2(0.5)2 = 8
4.) 100=gm1Rout=gm1
gds2+gds4 = 2·110μA/V2(W1/L1)
(0.04+0.05) 50μA = 23.31W1L1
W1L1=
W2L2 =18.4
Lecture 190 – Differential Amplifier (3/27/10) Page 190-29
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 190-2 - Continued
5.) VIC(min) = VSS +VDS5(sat)+VGS1 -1.5 = -2.5+VDS5(sat)+2·50μA
110μA/V2(18.4) + 0.7
VDS5(sat) = 0.3 - 0.222 = 0.0777 W5L5 =
2ISSKN’VDS5(sat)2 = 150.6
We probably should increase W1/L1 to reduce VGS1. If we choose W1/L1 = 40, thenVDS5(sat) = 0.149V and W5/L5 = 41. (Larger than specified gain should be okay.)
Lecture 190 – Differential Amplifier (3/27/10) Page 190-30
CMOS Analog Circuit Design © P.E. Allen - 2010
SUMMARY• Differential amplifiers are compatible with the matching properties of IC technology• The differential amplifier has two modes of signal operation:
- Differential mode- Common mode
• Differential amplifiers are excellent input stages for voltage amplifiers• Differential amplifiers can have different loads including:
- Current mirrors- MOS diodes- Current sources/sinks- Resistors
• The small signal performance of the differential amplifier is similar to the invertingamplifier in gain, output resistance and bandwidth
• The large signal performance includes slew rate and the linearization of thetransconductance
• The design of CMOS analog circuits uses the relationships of the circuit to design the dccurrents and the W/L ratios of each transistor
Lecture 200 Low Input Resistance Amplifiers (3/27/10) Page 200-1
CMOS Analog Circuit Design © P.E. Allen - 2010
LECTURE 200 – LOW INPUT RESISTANCE AMPLIFIERS – THECOMMON GATE, CASCODE AND CURRENT AMPLIFIERS
LECTURE ORGANIZATIONOutline• Voltage driven common gate amplifiers• Voltage driven cascode amplifier• Non-voltage driven cascode amplifier – the Miller effect• Further considerations of cascode amplifiers• Current amplifiers• SummaryCMOS Analog Circuit Design, 2nd Edition ReferencePages 199-218
Lecture 200 Low Input Resistance Amplifiers (3/27/10) Page 200-2
CMOS Analog Circuit Design © P.E. Allen - 2010
VOLTAGE-DRIVEN COMMON GATE AMPLIFIERCommon Gate AmplifierCircuit:
Large Signal Characteristics:VOUT(max) VDD – VDS3(sat)
VOUT(min) VDS1(sat) + VDS2(sat)
Note VDS1(sat) = VON1
060609-01
VDD
VPBias1
VNBias1
VNBias2
vOUTM3
M2
M1
VDD
vIN
vOUT
VNBias2
RL
IBias vIN
060609-02VON1
VT2
VON2VON1+VON2
VDD VON3
vOUT
vINVNBias2
Lecture 200 Low Input Resistance Amplifiers (3/27/10) Page 200-3
CMOS Analog Circuit Design © P.E. Allen - 2010
Small Signal Performance of the Common Gate AmplifierSmall signal model:
Rin
060609-03
gm2vgs2
+
−vgs2
rds2
rds3
rds1vin vout
Rout
gm2vs2+
−vs2
rds2
rds3
rds1vin vout
RoutRin i1
vout = gm2vs2 rds2
rds2+rds3 rds3 = gm2rds2rds3
rds2+rds3 vin Av =voutvin
= +gm2rds2rds3
rds2+rds3
Rin = Rin’||rds1, Rin’ is found as follows
vs2 = (i1 - gm2vs2)rds2 + i1rds3 = i1(rds2 + rds3) - gm2 rds2vs2
Rin' = vs2i1 =
rds2 + rds31 + gm2rds2 Rin = rds1||
rds2 + rds31 + gm2rds2
Rout rds2||rds3
Lecture 200 Low Input Resistance Amplifiers (3/27/10) Page 200-4
CMOS Analog Circuit Design © P.E. Allen - 2010
Influence of the Load on the Input Resistance of a Common Gate AmplifierConsider a common gate amplifier with a general load:
VDD
VNBias1
VNBias2
vOUT
M2
M1vIN
Load
VDD
VNBias1
VNBias2
vOUT
M2
M1vIN
VDD
VPBias1
VNBias1
VNBias2
vOUT
M3
M2
M1vIN
070420-01
VDDVPBias1
VNBias1
VNBias2
vOUTM3
M2
M1vIN
Rin1 Rin2
VPBias2M4
Rin3
From the previous page, the input resistance to the common gate configuration is,
Rin = rds2 + RLoad1 + gm2rds2
For the various loads shown, Rin becomes:
Rin1 = rds2
1+gm2rds2
1gm2
Rin2 = rds2+rds3
1+ gm2rds2
2gm2
Rin3 = rds2+rds4gm3rds3
1+ gm2rds2 rds!!!
The input resistance of the common gate configuration depends on the load at the drain
Lecture 200 Low Input Resistance Amplifiers (3/27/10) Page 200-5
CMOS Analog Circuit Design © P.E. Allen - 2010
Frequency Response of the Common Gate AmplifierCircuit:
060609-04
VDD
VPBias1
VNBias1
VNBias2
vOUTM3
M2
M1vIN
Cgd3Cgd2 Cbd2
Cbd3
CL gm2Vs2+
−Vs2
rds2
rds3
rds1Vin VoutCout
The frequency response can be found by replacing rds3 in the previous slide with,
rds3 rds3
srds3Cout + 1 where Cout = Cgd2 + Cgd3 + Cbd2 + Cbd3 + CL
Av(s) = VoutVin
= + gm2rds2rds3
rds2+rds31
srds2rds3Cout
rds2+rds3 + 1 = +
gm2rds2rds3rds2+rds3
1
1 -sp1
where p1 = -1
rds2rds3 Coutrds2+rds3
-3dB = |p1|
Lecture 200 Low Input Resistance Amplifiers (3/27/10) Page 200-6
CMOS Analog Circuit Design © P.E. Allen - 2010
VOLTAGE-DRIVEN CASCODE AMPLIFIERCascode† Amplifier
060609-05
VDD
VPBias1
VNBias2
vOUTM3
M2
M1vIN
Advantages of the cascode amplifier:• Increases the output resistance and gain (if M3 is cascaded also)• Eliminates the Miller effect when the input source resistance is large
† “Cascode” = “Cascaded triode” see H. Wallman, A.B. Macnee, and C.P. Gadsden, “A Low-Noise Amplifier, Proc. IRE, vol. 36, pp. 700-708, June
1948.
Lecture 200 Low Input Resistance Amplifiers (3/27/10) Page 200-7
CMOS Analog Circuit Design © P.E. Allen - 2010
Large-Signal Characteristics of the Cascode Amplifier
0 1 2 3 4 5
I D (
mA
)
vOUT
0 1 2 3 4 5v O
UT
vIN
M2
M1
vIN
vOUT
ID
5V
+-
+
-
W3L3
=2μm1μm
W1L1
= 2μm1μm
Fig. 5.3-2
C
M3
2.3V
A B CD
E
G H
I K
F
J1
0
2
3
4
5
M3 saturated
EHIK
J
M3 active
vIN=5.0VvIN=4.0V
vIN=4.5V
vIN=1.0V
vIN=1.5V
vIN=2.0V
vIN=2.5V
0.0
0.1
0.2
0.3
0.4
0.5vIN=3.5VvIN=3.0V
D
A,B
G F
M2 activeM2 saturated
M1 sat-urated
M1active
3.4V
W2L2
= 2μm1μm
M3
M1 sat. when VGG2-VGS2 VGS1-VT vIN 0.5(VGG2+VTN) where VGS1=VGS2
M2 sat. when VDS2 VGS2-VTN vOUT-VDS1 VGG2-VDS1-VTN vOUT VGG2-VTNM3 is saturated when VDD-vOUT VDD - VGG3 - |VTP| vOUT VGG3 + |VTP|
Lecture 200 Low Input Resistance Amplifiers (3/27/10) Page 200-8
CMOS Analog Circuit Design © P.E. Allen - 2010
Large-Signal Voltage Swing Limits of the Cascode AmplifierMaximum output voltage, vOUT(max):
vOUT(max) = VDD Minimum output voltage, vOUT(min):
Referencing all potentials to the negative power supply (ground in this case), we mayexpress the current through each of the devices, M1 through M3, as
iD1 = 1 (VDD - VT1)vDS1 -vDS1
2
2 1(VDD - VT1)vDS1
iD2 = 2 (VGG2 - vDS1 - VT2)(vOUT - vDS1) -(vOUT - vDS1)2
2
2(VGG2 - vDS1 - VT2)(vOUT - vDS1)and
iD3 = 3
2 (VDD VGG3 |VT3|)2
where we have also assumed that both vDS1 and vOUT are small, and vIN = VDD.
Solving for vOUT by realizing that iD1 = iD2 = iD3 and 1 = 2 we get,
vOUT(min) =3
2 2 (VDD VGG3 |VT3|)21
VGG2 VT2 +1
VDD VT1
Lecture 200 Low Input Resistance Amplifiers (3/27/10) Page 200-9
CMOS Analog Circuit Design © P.E. Allen - 2010
Small-Signal Midband Performance of the Cascode AmplifierSmall-signal model:
gm1vgs1 rds1
+
-vout
vin =vgs1
rds2
rds3
gm2vgs2= -gm2v1
+
-
Small-signal model of cascode amplifier neglecting the bulk effect on M2.
+
-
v1
G1 D1=S2 D2=D3
S1=G2=G3
gm1vin rds1
+
-vout
vin
rds2
rds3
+
-
+
-
v1
G1 D1=S2 D2=D3
1gm2
C2 gm2v1 C3
Simplified equivalent model of the above circuit. Fig. 5.3-3
C1
Using nodal analysis, we can write,[gds1 + gds2 + gm2]v1 gds2vout = gm1vin
[gds2 + gm2]v1 + (gds2 + gds3)vout = 0
Solving for vout/vin yieldsvoutvin
= gm1(gds2 + gm2)
gds1gds2 + gds1gds3 + gds2gds3 + gds3gm2
gm1gds3
= 2K'1W 1L1ID 23
(Intuitive analysis give the same result with much less effort.)The small-signal output resistance is,
rout = [rds1 + rds2 + gm2rds1rds2]||rds3 rds3
Lecture 200 Low Input Resistance Amplifiers (3/27/10) Page 200-10
CMOS Analog Circuit Design © P.E. Allen - 2010
Frequency Response of the Cascode AmplifierSmall-signal model (RS = 0):whereC1 = Cgd1,
C2 = Cbd1+Cbs2+Cgs2, and
C3 = Cbd2+Cbd3+Cgd2+Cgd3+CL
The nodal equations now become:(gm2 + gds1 + gds2 + sC1 + sC2)v1 gds2vout = (gm1 sC1)vin
and (gds2 + gm2)v1 + (gds2 + gds3 + sC3)vout = 0
Solving for Vout(s)/Vin(s) gives,
Vout(s)Vin(s) =
11 + as + bs2
(gm1 sC1)(gds2 + gm2)gds1gds2 + gds3(gm2 + gds1 + gds2)
where
a = C3(gds1 + gds2 + gm2) + C2(gds2 + gds3) + C1(gds2 + gds3)
gds1gds2 + gds3(gm2 + gds1 + gds2)
and
b = C3(C1 + C2)
gds1gds2 + gds3(gm2 + gds1 + gds2)
gm1vin rds1
+
-vou
vin
rds2
rds3
+
-
+
-
v1
G1 D1=S2 D2=D3
1gm2
C2 gm2v1 C3
Fig. 5.3-4A
C1
Lecture 200 Low Input Resistance Amplifiers (3/27/10) Page 200-11
CMOS Analog Circuit Design © P.E. Allen - 2010
A Simplified Method of Finding an Algebraic Expression for the Two PolesAssume that a general second-order polynomial can be written as:
P(s) = 1 + as + bs2 = 1s
p1 1
sp2
= 1 s 1p1
+1p2
+ s2
p1p2
Now if |p2| >> |p1|, then P(s) can be simplified as
P(s) 1 s
p1 +
s2
p1p2
Therefore we may write p1 and p2 in terms of a and b as
p1 = 1
a and p2 = a
bApplying this to the previous problem gives,
p1 = [gds1gds2 + gds3(gm2 + gds1 + gds2)]
C3(gds1 + gds2 + gm2) + C2(gds2 + gds3) + C1(gds2 + gds3) gds3C3
The nondominant root p2 is given as
p2 = [C3(gds1 + gds2 + gm2) + C2(gds2 + gds3) + C1(gds2 + gds3)]
C3(C1 + C2) gm2
C1 + C2
Assuming C1, C2, and C3 are the same order of magnitude, and gm2 is greater than gds3,then |p1| is smaller than |p2|. Therefore the approximation of |p2| >> |p1| is valid.
Note that there is a right-half plane zero at z1 = gm1/C1.
Lecture 200 Low Input Resistance Amplifiers (3/27/10) Page 200-12
CMOS Analog Circuit Design © P.E. Allen - 2010
NON-VOLTAGE DRIVEN CASCODE AMPLIFIER – THE MILLER EFFECTMiller EffectConsider the following inverting amplifier:
Solve for the input impedance:
Zin(s) = V1I1
I1 = sCM(V1 – V2) = sCM(V1 + AvV1) = sCM(1 + Av)V1Therefore,
Zin(s) = V1I1 =
V1sCM(1 + Av)V1 =
1sCM(1 + Av) =
1sCeq
The Miller effect can take Cgd = 5fF and make it look like a 0.5pF capacitor in parallelwith the input of the inverting amplifier (Av -100).
If the source resistance is large, this creates a dominant pole at the input.
+
−V1
I1-Av +
−V2 = -AvV1
CM
060610-03
Lecture 200 Low Input Resistance Amplifiers (3/27/10) Page 200-13
CMOS Analog Circuit Design © P.E. Allen - 2010
Simple Inverting Amplifier Driven with a High Source ResistanceExamine the frequency
response of a current-source loadinverter driven from a highresistance source:
Assuming the input is Iin, thenodal equations are, [G1 + s(C1 + C2)]V1 sC2Vout = Iin and (gm1 sC2)V1+[G3+s(C2+C3)]Vout = 0
where G1 = Gs (=1/Rs), G3 = gds1 + gds2, C1 = Cgs1, C2 = Cgd1 and C3 = Cbd1+Cbd2 + Cgd2.
Solving for Vout(s)/Vin(s) gives
Vout(s)Vin(s) =
(sC2 gm1)G1G1G3+s[G3(C1+C2)+G1(C2+C3)+gm1C2]+(C1C2+C1C3+C2C3)s2 or,
Vout(s)Vin(s) =
gm1G3
[1 s(C2/gm1)]
1+[R1(C1+C2)+R3(C2+C3)+gm1R1R3C2]s+(C1C2+C1C3+C2C3)R1R3s2
Assuming that the poles are split allows the use of the previous technique to get,
p1 = 1
R1(C1+C2)+R3(C2+C3)+gm1R1R3C2
1gm1R1R3C2
andp2 gm1C2
C1C2+C1C3+C2C3
vin Rs
VGG2
VDD
vout
M2
M1
Rs
RsRs
VinC1
C2
C3 R3
C1 ≈ Cgs1
C2 = Cgd1
C3 = Cbd1 + Cbd2 + Cgd2
R3 = rds1||rds2 Fig.
+
-
V1gm1V1
The Miller effect has caused the input pole, 1/R1C1, to be decreased by a value of gm1R3.
Lecture 200 Low Input Resistance Amplifiers (3/27/10) Page 200-14
CMOS Analog Circuit Design © P.E. Allen - 2010
How Does the Cascode Amplifier Solve the Miller Effect?Cascode amplifier:
060610-02
+vIN�
-
+
vOUT�
−
M2
M1
M3
VDD
Cgd1Rs2+
−
v1
RS
vS�
VPBias1
VNBias2
The Miller effect causes Cgs1 to be increased by the value of 1 + (v1/vin) and appear inparallel with the gate-source of M1 causing a dominant pole to occur.
The cascode amplifier eliminates this problem by keeping the value of v1/vin small bymaking the value of Rs2 approximately 2/gm2.
Lecture 200 Low Input Resistance Amplifiers (3/27/10) Page 200-15
CMOS Analog Circuit Design © P.E. Allen - 2010
Comparison of the Inverting and Cascode Non-Voltage Driven AmplifiersThe dominant pole of the inverting amplifier with a large source resistance was found tobe
p1(inverter) = 1
R1(C1+C2)+R3(C2+C3)+gm1R1R3C2
1gm1R1R3C2
Now if a cascode amplifier is used, R3, can be approximated as 2/gm of the cascodingtransistor (assuming the drain sees an rds to ac ground).
p1(cascode) = 1
R1(C1+C2)+2
gm(C2+C3)+gm1R1
2gm
C2
= 1
R1(C1+C2)+2
gm(C2+C3)+2R1C2
1
R1(C1+3C2)
Thus we see that p1(cascode) >> p1(inverter).
Lecture 200 Low Input Resistance Amplifiers (3/27/10) Page 200-16
CMOS Analog Circuit Design © P.E. Allen - 2010
FURTHER CONSIDERATIONS OF CASCODE AMPLIFIERSHigh Gain and High Output Resistance Cascode AmplifierIf the load of the cascodeamplifier is a cascodecurrent source, then bothhigh output resistanceand high voltage gain isachieved.
The output resistance is,
rout [gm2rds1rds2] [gm3rds3rds4] = I
-1.5D
1 2
2K'2(W/L)2+
3 4
2K'3(W/L)3Knowing rout, the gain is simply
Av = gm1rout gm1{[gm2rds1rds2] [gm3rds3rds4]} 2K'1(W/L)1I
-1D
1 2
2K'2(W/L)2+
3 4
2K'3(W/L)3
060609-07
VDD
VPBias1
VPBias2
VNBias2
vin
vout
Rout
M3
M4
M2
M1gm1vin
rds1
gm2v1 gmbs2v1 rds2 gm3v4 gmbs3v4 rds3
rds4v1
+
-
v4
+
-
vout
+
-
G1 D1=S2 D4=S3
D2=D3
G2=G3=G4=S1=S4
vin
+
-
Lecture 200 Low Input Resistance Amplifiers (3/27/10) Page 200-17
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 200-1 - Comparison of the Cascode Amplifier PerformanceCalculate the small-signal voltage gain, output resistance, the dominant pole, and the
nondominant pole for the low-gain, cascode amplifier and the high-gain, cascodeamplifier. Assume that ID = 200 microamperes, that all W /L ratios are 2μm/1μm, andthat the parameters of Table 3.1-2 are valid. The capacitors are assumed to be: Cgd = 3.5fF, Cgs = 30 fF, Cbsn = Cbdn = 24 fF, Cbsp = Cbdp = 12 fF, and CL = 1 pF.
SolutionThe low-gain, cascode amplifier has the following small-signal performance:
Av = 37.1V/VRout = 125kp1 -gds3/C3 1.22 MHzp2 gm2/(C1+C2) 605 MHz.
The high-gain, cascode amplifier has the following small-signal performance:Av = 414V/VRout = 1.40 Mp1 1/RoutC3 108 kHzp2 gm2/(C1+C2) 579 MHz
(Note at this frequency, the drain of M2 is shorted to ground by the load capacitance, CL)
Lecture 200 Low Input Resistance Amplifiers (3/27/10) Page 200-18
CMOS Analog Circuit Design © P.E. Allen - 2010
Designing Cascode AmplifiersPertinent design equations for the simple cascode amplifier.
+vIN�
-
+
vOUT�
-
M2
M1
M3
VDD
VGG3
VGG2
Fig. 5.3-7
I
vOUT(min) =VDS1(sat) + VDS2(sat)
2IKN(W1/L1)
vOUT(max) = VDD - VSD3(sat)
2IKN(W2/L2)
+=
2IKP(W3/L3)
=VDD -
I = PdissVDD
= (SR)·Cout
|Av| = gm1gds3
= 2KN(W1/L1)λP
2I
I = KPW3
2L3(VDD - VGG3-|VTP|)2
VGG2 = VDS1(sat) + VGS2
Lecture 200 Low Input Resistance Amplifiers (3/27/10) Page 200-19
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 200-2 - Design of a Cascode AmplifierThe specs for a cascode amplifier are Av = -50V/V, vOUT(max) = 4V, vOUT(min) = 1.5V,VDD=5V, and Pdiss=1mW. The slew rate with a 10pF load should be 10V/μs or greater.
SolutionThe slew rate requires a current greater than 100μA while the power dissipation
requires a current less than 200μA. Compromise with 150μA. Beginning with M3, W3L3
= 2I
KP[VDD-vOUT(max)]2 = 2·15050(1)2 = 6
From this find VGG3: VGG3 = VDD - |VTP| - 2I
KP(W3/L3) = 5 - 1 - 2·15050·6 = 3V
Next, W1L1
= (Av )2I
2KN =
(50·0.05)2(150)2·110 = 2.73
To design W2/L2, we will first calculate VDS1(sat) and use the vOUT(min) specification to
define VDS2(sat). VDS1(sat) = 2I
KN(W1/L1) = 2·150
110·4.26 = 0.8V
Subtracting this value from 1.5V gives VDS2(sat) = 0.7V.W2L2
= 2I
KNVDS2(sat)2 = 2·150
110·0.72 = 5.57
Finally, VGG2 = VDS1(sat) + 2I
KN(W2/L2) + VTN = 0.8V+ 0.7V + 0.7V = 2.2V
Lecture 200 Low Input Resistance Amplifiers (3/27/10) Page 200-20
CMOS Analog Circuit Design © P.E. Allen - 2010
CURRENT AMPLIFIERSWhat is a Current Amplifier?• An amplifier that has a defined output-input current relationship• Low input resistance• High output resistanceApplication of current amplifiers:
iS RS RL
ii io
CurrentAmplifier
Ai iS RS
RL
iiio
CurrentAmplifier
Aiii -
+
Single-ended input. Differential input. Fig. 5.4-1
RS >> Rin and Rout >> RL
Advantages of current amplifiers:• Currents are not restricted by the power supply voltages so that wider dynamic
ranges are possible with lower power supply voltages.• -3dB bandwidth of a current amplifier using negative feedback is independent of the
closed loop gain.
Lecture 200 Low Input Resistance Amplifiers (3/27/10) Page 200-21
CMOS Analog Circuit Design © P.E. Allen - 2010
Frequency Response of a Current Amplifier with Current FeedbackConsider the following current amplifier with resistivenegative feedback applied.
Assuming that the small-signal resistance looking intothe current amplifier is much less than R1 or R2,
io = Ai(i1-i2) = Ai vinR1
- ioSolving for io gives
io = Ai
1+Ai vinR1
vout = R2io = R2R1
Ai
1+Ai vin
If Ai(s) = Ao
sA
+ 1 , then
vout
vin =
R2
R1
1
1+1
Ai(s) =
R2
R1
Ao
sA
+(1+Ao) =
R2
R1
Ao
1+Ao
1s
A(1+Ao) +1
-3dB = A(1+Ao)
R2i2io
Aii1
-
+R1 vout
vin
Fig. 5.4-2
Lecture 200 Low Input Resistance Amplifiers (3/27/10) Page 200-22
CMOS Analog Circuit Design © P.E. Allen - 2010
Bandwidth Advantage of a Current Feedback AmplifierThe unity-gainbandwidth is,
GB = |Av(0)| -3dB = R2Ao
R1(1+Ao) · A(1+Ao) = R2
R1 Ao· A =
R2
R1 GBi
where GBi is the unity-gainbandwidth of the current amplifier.
Note that if GBi is constant, then increasing R2/R1 (the voltage gain) increases GB.
Illustration:
Ao dB
ωA
R2R1
>1
R2R1
GB1 GB2
Current Amplifier
0dB
Voltage Amplifier,
log10(ω)
Magnitude dB
Fig. 7.2-10
(1+Ao)ωA
GBi
= K
R1Voltage Amplifier, > KR2
1+AoAo dB
1+AoAo dBK
Note that GB2 > GB1 > GBi
The above illustration assumes that the GB of the voltage amplifier realizing the voltagebuffer is greater than the GB achieved from the above method.
Lecture 200 Low Input Resistance Amplifiers (3/27/10) Page 200-23
CMOS Analog Circuit Design © P.E. Allen - 2010
Current Amplifier using the Simple Current MirrorVDD VDD
I1 I2iin iout
M1 M2
Current Amplifier
iin iout
gm1vin
+
-
vinrds1 gm2vin rds2C1 C3
RL
Fig. 5.4-3
C2
≈ 0R
Rin = 1
gm1 Rout =
11Io
and Ai = W 2/L2
W 1/L1 .
Frequency response:
p1 = -(gm1+gds1)
C1+C2 =
-(gm1+gds1)Cbd1+Cgs1+Cgs2+Cgd2
-gm1
Cbd1+Cgs1+Cgs2+Cgd2
Note that the bandwidth can be almost doubled by including the resistor, R.(R removes C
gs1 from p1)
Lecture 200 Low Input Resistance Amplifiers (3/27/10) Page 200-24
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 200-3 - Performance of a Simple Current Mirror as a Current AmplifierFind the small-signal current gain, Ai, the input resistance, Rin, the output resistance
Rout, and the -3dB frequency in Hertz for the current amplifier of previous slide if 10I1 = I2= 100μA and W2/L2 = 10W1/L1 = 10μm/1μm. Assume that Cbd1 = 10fF, Cgs1 = Cgs2 =100fF, and Cgs2 = 50fF.
SolutionIgnoring channel modulation and mismatch effects, the small-signal current gain,
Ai = W2/L2
W1/L1 10A/A.
The small-signal input resistance, Rin, is approximately 1/gm1 and is
Rin 1
2KN(1/1)10μA = 1
46.9μS = 21.3k
The small-signal output resistance is equal to
Rout = 1NI2
= 250k .
The -3dB frequency is
-3dB = 46.9μS260fF = 180.4x106 radians/sec. f-3dB = 28.7 MHz
Lecture 200 Low Input Resistance Amplifiers (3/27/10) Page 200-25
CMOS Analog Circuit Design © P.E. Allen - 2010
Wide-Swing, Cascode Current Mirror Implementation of a Current Amplifier
060610-01
+
M1 M2
M4
VDD
iout
vOUT
M3
−
+
−
IIN
VDD
IOUT
vIN
iin
VNBias2
Rin 1
gm1, Rout rds2gm4rds4, and Ai =
W2/L2W1/L1
Lecture 200 Low Input Resistance Amplifiers (3/27/10) Page 200-26
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 200-4 - Current Amplifier Implemented by the Wide-Swing, CascodeCurrent Mirror
Assume that IIN and IOUT of the wide-swing cascode current mirror are 100μA.Find the value of Rin, Rout, and Ai if the W/L ratios of all transistors are 182μm/1μm.
Solution
The input resistance requires gm1 which is 2·110·182·100 = 2mS
Rin 500
From our knowledge of the cascode configuration, the small signal output resistanceshould be
Rout gm4rds4rds2 = (2001μS)(250k )(250k ) = 125M
Because VDS1 = VDS2, the small-signal current gain is
Ai = W2/L2W1/L1 = 1
Simulation results using the level 1 model for this example giveRin= 497 , Rout = 164.7M and Ai = 1.000 A/A.
The value of VON for all transistors is
VON = 2·100μA
110μA/V2·182 = 0.1V
Lecture 200 Low Input Resistance Amplifiers (3/27/10) Page 200-27
CMOS Analog Circuit Design © P.E. Allen - 2010
Low-Input Resistance Current AmplifierTo decrease Rin below 1/gm
requires the use of negative,shunt feedback. Considerthe following example.
Feedback concept:Input resistance without feedback rds1.
Loop gain gm1
gds1
gm3
gds3 assuming that the resistances of I1 and I3 are very large.
Rin = Rin(no fb.)
1 + Loop gain rds1
gm1rds1gm3rds3 =
1gm1gm3rds3
Small signal analysis:iin = gm1vgs1 - gds1vgs3
and vgs3 = -vin vgs1 = vin - (gm3 vgs3rds3) = vin(1+gm3rds3)
iin = gm1(1+gm3rds3)vin + gds1vin gm1gm3rds3vin Rin 1
gm1gm3rds3
VGG3
M1
M3
M2
VDD VDD
I1 I2 ioutiin
I3
Current Amplifier
gm1vgs1 rds1rds3
gm3vgs3 +
-vgs1
+
-
vgs3
+
-
vin
iin
Fig. 5.4-5
i = 0
Lecture 200 Low Input Resistance Amplifiers (3/27/10) Page 200-28
CMOS Analog Circuit Design © P.E. Allen - 2010
Use of Blackman’s Formula to Find the Input Resistance of Previous SlideRecall that the resistance seen looking into port X is given as,
Rx = Rx(k=0)1 + RR(port shorted)1 + RR(port opened)
The small signal circuit (from the previous slide) is,Choosing gm1 as k, we see that,
Rx(k=0) = rds1
The circuits for calculating the shorted and open return-ratios are:
RR(vx = 0): -vc
vc' = 0 RR(ix = 0): vc = - vgs3(1+ gm3rds3) = - gm1rds1 (1+ gm3rds3)vc’
RR(ix = 0) = -vc
vc' = gm1rds1 (1+ gm3rds3)
Finally,
Rx = Rin = rds1 1 + 0
1 + gm1rds1(1+ gm3rds3) 1
gm1gm3rds3
Lecture 200 Low Input Resistance Amplifiers (3/27/10) Page 200-29
CMOS Analog Circuit Design © P.E. Allen - 2010
Differential-Input, Current AmplifiersDefinitions for the differential-mode, i
ID, and common-mode, i
IC, input currents of the
differential-input current amplifier.
+
-
i1
i2iID
iIC2
iIC2
iO
Fig. 5.4-6
iO = A
IDi
ID ± A
ICi
IC = A
ID(i
1 - i
2) ± A
IC
i1+i
2
2Implementations:
I I2I
VDD VDD VDD
i1
i2 i2
iO
i1-i2M1 M2 M3 M4
iO
VDD
i1 i2M1 M2
M3 M4
M5 M6
VGG1
VGG2
Fig. 5.4-7
Lecture 200 Low Input Resistance Amplifiers (3/27/10) Page 200-30
CMOS Analog Circuit Design © P.E. Allen - 2010
SUMMARY• Low input resistance amplifiers use the source as the input terminal with the gate
generally on ground• The input resistance to the common gate amplifier depends on what is connected to the
drain• The voltage driven common gate/common source amplifier has one dominant pole• The current driven common gate/common source amplifier has two dominant poles• The cascode amplifier eliminates the input dominant pole for the current driven common
gate/common source amplifier• Current amplifiers have a low input resistance, high output resistance, and a defined
output-input current relationship• Input resistances less than 1/g
m require feedback
However, all feedback loops have internal poles that cause the benefits of negativefeedback to vanish at high frequencies.In addition, feedback loops can have a slow time constant from a pole-zero pair.
• Voltage amplifiers using a current amplifier have high values of gain-bandwidth• Current amplifiers are useful at low power supplies and for switched current
applications
Lecture 210 – Output Amplifiers (3/27/10) Page 210-1
CMOS Analog Circuit Design © P.E. Allen - 2010
LECTURE 210 – OUTPUT AMPLIFIERSLECTURE ORGANIZATION
Outline• Introduction• Class A Amplifiers• Push-Pull Amplifiers• Bipolar Junction Transistor Output Amplifiers• Using Negative Feedback to Reduce the Output Resistance• SummaryCMOS Analog Circuit Design, 2nd Edition ReferencePages 218-229
Lecture 210 – Output Amplifiers (3/27/10) Page 210-2
CMOS Analog Circuit Design © P.E. Allen - 2010
INTRODUCTIONGeneral Considerations of Output Amplifiers
f1(vIN)
f2(vIN)
i1
i2 RL vOUT
VDD
VSS
Buffer
vINiOUT
+
-
i1
i2=IQ iOUT
t
Cur
rent
iOUT
t
Cur
rent
i1
i2
iOUTt
Cur
rent
i1
i2
Class A
Class AB
Class B
Fig. 5.5-005
Requirements:1.) Provide sufficient output power in the form of
voltage or current.2.) Avoid signal distortion.3.) Be efficient4.) Provide protection from abnormal conditions
(short circuit, over temperature, etc.)Types of Output Amplifiers:1.) Class A amplifiers2.) Source followers3.) Push-pull amplifiers4.) Substrate BJT amplifiers5.) Amplifiers using negative
shunt feedback
Lecture 210 – Output Amplifiers (3/27/10) Page 210-3
CMOS Analog Circuit Design © P.E. Allen - 2010
Output Current Requirements for an Output AmplifierConsider the current requirements placed by the load on the output amplifier:
OutputAmplifier +
vOUT
−
CL RL
iOUT
070422-01
Imax due to RL
Imax due to RL
Imax due to CL
vOUT
t
Result:|iOUT| > CL·SR
|iOUT| > vOUT(peak)
RL
Fortunately, the maximum current for the resistor and capacitor do not occur at the sametime.
Lecture 210 – Output Amplifiers (3/27/10) Page 210-4
CMOS Analog Circuit Design © P.E. Allen - 2010
Output Resistance Requirements for an Output AmplifierIn order to avoid attenuation of the amplifier voltage signal, the output resistance of theamplifier must be less than the load resistance.
OutputAmplifier
+
−RL vOUT
070422-02
tRout
vOA
vOA(t)vOA(t)
Vol
ts
vOUT(t) =RL
RL+Rout
vIN
To avoid attenuation of the amplifier voltage signal, Rout << RL.
Lecture 210 – Output Amplifiers (3/27/10) Page 210-5
CMOS Analog Circuit Design © P.E. Allen - 2010
Separation of the Amplifier Bias from the Load ResistanceUnfortunately, when a low load resistance is connected to the output of an amplifier, thebias conditions can be changed.
Solution:1.) Use a coupling capacitance for singled-ended power supplies.2.) Redefine the output analog ground as (VDD/2).
3.) Use dc coupling for split power supplies.VDD
VBP1
vOUT
vIN IQ RL
070422-04
VDD
VBP1
vOUT
vIN IQ RL
VSS
0VIDC = 0
VDD
VBP1
vOUT
vIN IQ RL
0.5VDD
VDD
VBP1
vOUT
vIN IQ RL
Loss of biascurrentthrough RL
070422-03
Lecture 210 – Output Amplifiers (3/27/10) Page 210-6
CMOS Analog Circuit Design © P.E. Allen - 2010
CLASS A AMPLIFIERSCurrent source load inverter
A Class A circuit hascurrent flow in the MOSFETsduring the entire period of asinusoidal signal.Characteristics of Class Aamplifiers:• Unsymmetrical sinking andsourcing• Linear• Poor efficiency
Efficiency = PRL
PSupply =
vOUT(peak)2
2RL(VDD-VSS)IQ
=
vOUT(peak)2
2RL
(VDD -VSS)(VDD-VSS)
2RL
= vOUT(peak)VDD -VSS
2
Maximum efficiency occurs when vOUT(peak) = VDD = |VSS| which gives 25%.
CL RL
M2
M1
VGG2
VDD
vIN
vOUTiOUTIQ
iD1
Fig. 5.5-1
iDVDD+|VSS|
VDD
vOUT
RL
IQ
IQRL IQRLVSS
RL dominatesas the load line
VSS
Lecture 210 – Output Amplifiers (3/27/10) Page 210-7
CMOS Analog Circuit Design © P.E. Allen - 2010
Optimum Value of Load ResistorDepending on the value of RL, the signal swing can be symmetrical or asymmetrical.
(This ignores the limitations of the transistor.)
Fig. 040-03
iD1
VDD+|VSS|
VDD
vDS1
RL
IQ
IQRL IQRL
Minimum RL formaximum swing
0
0
Smaller RL
Larger RL
VSS
Lecture 210 – Output Amplifiers (3/27/10) Page 210-8
CMOS Analog Circuit Design © P.E. Allen - 2010
Small-Signal Performance of the Class A AmplifierAlthough we have considered the small-signal performance of the Class A amplifier as thecurrent source load inverter, let us include the influence of the load.The modified small-signal model:
gm1vinvin rds1 rds2 RL
+
-
+
-
voutC2
C1
Fig. 5.5-2
The small-signal voltage gain is:vout
vin =
-gm1
gds1+gds2+GL
The small-signal frequency response includes:A zero at
z = gm1
Cgd1
and a pole at
p = -(gds1+gds2+GL)
Cgd1+Cgd2+Cbd1+Cbd2+CL
Lecture 210 – Output Amplifiers (3/27/10) Page 210-9
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 210-1 - Design of a Simple Class-A Output Stage
Assume that KN’=2KP’=100μA/V2, VTN = 0.5V and VTP = -0.5V. Design the W/L ratiosof M1 and M2 so that a voltage swing of ±1V and a slew rate of 1 V/μs is achieved if RL= 1 k and CL = 1000 pF. Assume VDD = |VSS| = 2V and VGG2 = 0V. Let L = 1 μm andassume that Cgd1 = 100fF. Find the voltage gain and roots of this output amplifier.
SolutionLet us first consider the effects of RL and CL.
iOUT(peak) = ±1V/1k = ±1000μA and CL·SR = 10-9·106 = 1000μA
Since the current for CL and RL occur at different times, choose a bias current of 1mA.
W 1L1
= 2(IOUT
-+IQ)
KN’(VDD+|VSS| -VTN)2 =
4000100·(3.5)2
3μm1μm
and
W 2L2
= 2IOUT
+
KP’(VDD-VGG2-|VTP|)2 =
200050·(1.5)2
18μm1μm
The small-signal performance is Av = -0.775 V/V.
The roots are, zero = gm1/Cgd1 1.23GHz and pole 1/(RLCL) -159.15 kHz
Lecture 210 – Output Amplifiers (3/27/10) Page 210-10
CMOS Analog Circuit Design © P.E. Allen - 2010
Broadband Harmonic DistortionThe linearity of an amplifier can be characterized by its influence on a pure sinusoidal
input signal.Assume the input is,
Vin( ) = Vp sin( t)
The output of an amplifier with distortion will beVout( ) = a1Vp sin ( t) + a2Vp sin (2 t) +...+ anVp sin(n t)
Harmonic distortion (HD) for the ith harmonic can be defined as the ratio of themagnitude of the ith harmonic to the magnitude of the fundamental.For example, second-harmonic distortion would be given as
HD2 = a2a1
Total harmonic distortion (THD) is defined as the square root of the ratio of the sum of alof the second and higher harmonics to the magnitude of the first or fundamental
Thus, THD can be expressed as THD = [a
22 + a
23 +...+ a
2n]1/2
a1
The distortion of the class A amplifier is good for small signals and becomes poor atmaximum output swings because of the nonlinearity of the voltage transfer curve forlarge-signal swing
Lecture 210 – Output Amplifiers (3/27/10) Page 210-11
CMOS Analog Circuit Design © P.E. Allen - 2010
Class-A Source FollowerThe class-A source follower has lower output resistance and less attenuation of theamplifier voltage signal.N-Channel Source Follower Voltage transfer curve:with current sink bias:
Maximum output voltage swings:vOUT(min) VSS - VON2 (if RL is large)
or vOUT(min) -IQRL (if RL is small)
vOUT(max) = VDD - VON1 (if vIN > VDD) or vOUT(max) VDD - VGS1
M3
Fig. 040-01
IQ
VDD
vIN
vOUT
iOUT
M1
M2
VSS
VSS
VDD
VSS
RL
vIN
vOUT
Fig. 040-02
VGS1
VDD-VON1
|VSS|+VON2
VDD-VON1+VGS1
|VSS|+VON2+VGS1
IQRL<|VSS|+VON2
VDD-VGS
VDD
|VSS|
Triode
Triode
Lecture 210 – Output Amplifiers (3/27/10) Page 210-12
CMOS Analog Circuit Design © P.E. Allen - 2010
Output Voltage Swing of the FollowerThe previous results do not include the bulk effect on VT1 of VGS1.
Therefore,
VT1 = VT01 + [ 2| F| -vBS- 2| F|] VT01+ vSB = VT01+ 1 vOUT(max)-VSS
vOUT(max)-VSS VDD-VSS-VON1-VT1 = VDD-VSS-VON1-VT01- 1 vOUT(max)-VSS
Define vOUT(max)-VSS = vOUT’(max)
which gives the quadratic,
vOUT’(max)+ 1 vOUT’(max)-(VDD-VSS -VON1-VT01)=0
Solving the quadratic gives,
vOUT’(max) 12
4 - 1
2 12+4(VDD-VSS-VON1-VT01) + 12+ 4(VDD-VSS-VON1-VT01)
4
If VDD = 2.5V, N = 0.4V1/2, VTN1= 0.7V, and VON1 = 0.2V, then vOUT’(max) = 3.661V
andvOUT(max) = 3.661-2.5 = 0.8661V
Lecture 210 – Output Amplifiers (3/27/10) Page 210-13
CMOS Analog Circuit Design © P.E. Allen - 2010
Maximum Sourcing and Sinking Currents for the Source FollowerMaximum Sourcing Current (into a short circuit):We assume that the transistors are in saturation andVDD = -VSS = 2.5V , thus
IOUT(sourcing) = K’1W 1
2L1 [VDD vOUT VT1]2-IQ
where vIN is assumed to be equal to VDD.
If W1/L1 =10 and if vOUT = 0V, then
VT1 = 1.08V IOUT equal to 1.11 mA.
However, as vOUT increases above 0V, the current rapidly decreases.
Maximum Sinking Current:For the current sink load, the sinking current is limited by the bias current.IOUT(sinking) = IQEfficiency of the Class A, source follower:
Same as the Class A, common source which is 25% maximum efficiency
M3
Fig. 040-01
IQ
VDD
vIN
vOUT
iOUT
M1
M2
VSS
VSS
VDD
VSS
RL
Lecture 210 – Output Amplifiers (3/27/10) Page 210-14
CMOS Analog Circuit Design © P.E. Allen - 2010
Small Signal Performance of the Source FollowerSmall-signal model:
VoutVin =
gm1gds1 + gds2 + gm1 + gmbs1+GL
gm1gm1 + gmbs1+GL
gm1RL1 +gm1RL
If VDD = -VSS = 2.5V, Vout = 0V, W1/L1 = 10μm/1 μm, W2/L2 = 1μm/1 μm,and ID = 500 μA, then:For the current sink load follower (RL = ):
Vout
Vin = 0.869V/V, if the bulk effect were ignored, then
Vout
Vin = 0.963V/V
For a finite load, RL = 1000 :Vout
Vin = 0.512V/V
Fig. 040-04
gm1vgs1
vin rds1 rds2 RL
+
-
+
-
voutC2
C1
vgs1+ -
gmbs1vbs1
gm1vin
vin rds1 rds2 RL
+
-
+
-
voutC2
C1
vgs1+ -
gmbs1voutgm1vout
Lecture 210 – Output Amplifiers (3/27/10) Page 210-15
CMOS Analog Circuit Design © P.E. Allen - 2010
Small Signal Performance of the Source Follower - ContinuedThe output resistance is:
Rout = 1
gm1 + gmbs1 + gds1 + gds2
For the current sink load follower:Rout = 830
The frequency response of the source follower:Vout(s)Vin(s) =
(gm1 + sC1)gds1 + gds2 + gm1 + gmbs1 + GL + s(C1 + C2)
whereC1 = capacitances connected between the input and output CGS1
C2 = Cbs1 +Cbd2 +Cgd2(or Cgs2) + CL
z = - gm1
C1 and p -
gm1+GLC1+C2
The presence of a LHP zero leads to the possibility that in most cases the pole and zerowill provide some degree of cancellation leading to a broadband response.
Lecture 210 – Output Amplifiers (3/27/10) Page 210-16
CMOS Analog Circuit Design © P.E. Allen - 2010
PUSH-PULL AMPLIFIERSPush-Pull Source FollowerCan both sink and sourcecurrent and provide a slightlylower output resistance.
Efficiency:Depends on how the transistorsare biased.
• Class B - one transistor has current flow for only 180° of the sinusoid (half period)
Efficiency = PRL
PVDD =
vOUT(peak)2
2RL
(VDD -VSS)12
2vOUT(peak)RL
= 2 vOUT(peak)VDD -VSS
Maximum efficiency occurs when vOUT(peak) =VDD and is 78.5%
• Class AB - each transistor has current flow for more than 180° of the sinusoid.Maximum efficiency is between 25% and 78.5%
VDD
vINvOUT
iOUT
M1
M2 VDD
VBias
VBias
Fig. 060-01
VDD
vIN
vOiOUT
M1
M2 VDDVDD
VDD
VGG
M3
M4
M5
M6
RL RL
VSS
VSS VSS VSS
VSS
VSS
Lecture 210 – Output Amplifiers (3/27/10) Page 210-17
CMOS Analog Circuit Design © P.E. Allen - 2010
Illustration of Class B and Class AB Push-Pull, Source FollowerOutput current and voltage characteristics of the push-pull, source follower (RL = 1k ):
-2V
-1V
0V
1V
2V
-2 -1 0 1 2Vin(V)
1mA
0mA
-1mA
vout
vG1
vG2
iD1
iD2
Class B, push-pull, source follower
-2V
-1V
0V
1V
2V
-2 -1 0 1 2Vin(V)
1mA
0mA
-1mA
vout
vG1 iD1
iD2
Class AB, push-pull, source follower Fig. 060-02
vG2
Comments:• Note that vOUT cannot reach the extreme values of VDD and VSS
• IOUT+(max) and IOUT-(max) is always less than VDD/RL or VSS/RL
• For vOUT = 0V, there is quiescent current flowing in M1 and M2 for Class AB
• Note that there is significant distortion at vIN =0V for the Class B push-pull follower
Lecture 210 – Output Amplifiers (3/27/10) Page 210-18
CMOS Analog Circuit Design © P.E. Allen - 2010
Small-Signal Performance of the Push-Pull FollowerModel:
gm1vgs1
vin rds1 rds2 RL
+
-
+
-
voutC2
C1
Fig. 060-03
vgs1+ -
gmbs1vbs1 gm2vgs2
gm1vin
vinrds1 rds2
RL
+
-
+
-
voutC2
C1
vgs1+ -
gmbs1voutgm1voutgm21
gmbs2vbs2
gm2vin gmbs2voutgm2vout
voutvin
= gm1 + gm2
gds1+gds2+gm1+gmbs1+gm2+gmbs2+GL
Rout = 1
gds1+gds2+gm1+gmbs1+gm2+gmbs2 (does not include RL)
If VDD = -VSS = 2.5V, Vout = 0V, ID1 = ID2 = 500μA, and W/L = 20μm/2μm, Av = 0.787(RL= ) and Rout = 448 .A zero and pole are located at
z = -(gm1+gm2)
C1 p =
-(gds1+gds2+gm1+gmbs1+gm2+gmbs2+GL)C1+C2
.
These roots will be at high frequencies because the associated resistances are small.
Lecture 210 – Output Amplifiers (3/27/10) Page 210-19
CMOS Analog Circuit Design © P.E. Allen - 2010
Push-Pull, Common Source AmplifiersSimilar to the class A but can operate as class B providing higher efficiency.
CL RL
vIN vOUT
iOUT
VDD
VTR2
VTR1
M2
M1
Fig. 060-04VSS
Comments:• The batteries VTR1 and VTR2 are necessary to control the bias current in M1 and M2.
• The efficiency is the same as the push-pull, source follower.
Lecture 210 – Output Amplifiers (3/27/10) Page 210-20
CMOS Analog Circuit Design © P.E. Allen - 2010
Illustration of Class B and Class AB Push-Pull, Inverting AmplifierOutput current and voltage characteristics of the push-pull, inverting amplifier (RL =1k ):
-2V
-1V
0V
1V
2V
-2V -1V 0V 1V 2V
-2mA
-1mA
0mA
1mA
2mA
vIN
iD1
iD2
vG2
vG1
vOUT
Class B, push-pull, inverting amplifier.
-2V
-1V
0V
1V
2V
-2V -1V 0V 1V 2V
-2mA
-1mA
0mA
1mA
2mA
vIN
iD1
iD2
vG2
vG1
vOUT
Class AB, push-pull, inverting amplifier. Fig.060-06
iD1 iD2
iD2
iD1
Comments:• Note that there is significant distortion at vIN =0V for the Class B inverter
• Note that vOUT cannot reach the extreme values of VDD and VSS
• IOUT+(max) and IOUT-(max) is always less than VDD/RL or VSS/RL
• For vOUT = 0V, there is quiescent current flowing in M1 and M2 for Class AB
Lecture 210 – Output Amplifiers (3/27/10) Page 210-21
CMOS Analog Circuit Design © P.E. Allen - 2010
Practical Implementation of the Push-Pull, Common Source Amplifier – Method 1
CL RL
vIN vOUT
iOUT
VDD
M2
M1 M3
M4
M5 M6
M7 M8
VGG3
VGG4
Fig. 060-05VSS
VGG3 and VGG4 can be used to bias this amplifier in class AB or class B operation.
Note, that the bias current in M6 and M8 is not dependent upon VDD or VSS (assumingVGG3 and VGG4 are not dependent on VDD and VSS).
Lecture 210 – Output Amplifiers (3/27/10) Page 210-22
CMOS Analog Circuit Design © P.E. Allen - 2010
Practical Implementation of the Push-Pull, Common Source Amplifier – Method 2VDD
VSS
Ib
Ib
I=2Ib
M1
M2
M3 M4
M5
M6
M7
M8 M9
M10
vin+
vin-
I=2Ib
Fig. 060-055
In steady-state, the current through M5 and M6 is 2Ib. If W4/L4 = W9/L9 and W3/L3 =W 8/L8, then the currents in M1 and M2 can be determined by the following relationship:
I1 = I2 = Ib W 1/L1W 7/L7
= Ib W 2/L2
W 10/L10
If vin+ goes low, M5 pulls the gates of M1 and M2 high. M4 shuts off causing all of the
current flowing through M5 (2Ib) to flow through M3 shutting off M1. The gate of M2 ishigh allowing the buffer to strongly sink current. If vin
- goes high, M6 pulls the gates ofM1 and M2 low. As before, this shuts off M2 and turns on M1 allowing strong sourcing.
Lecture 210 – Output Amplifiers (3/27/10) Page 210-23
CMOS Analog Circuit Design © P.E. Allen - 2010
Additional Methods of Biasing the Push-Pull Common-Source Amplifier
050423-10
VB1VB2 vOUT
vIN
IBias
VDD
050423-08
VDD
vOUT
vIN
VDD -VT+VSat
VDD -VT+2VSat
VT+2VSat
Lecture 210 – Output Amplifiers (3/27/10) Page 210-24
CMOS Analog Circuit Design © P.E. Allen - 2010
BIPOLAR JUNCTION TRANSISTOR OUTPUT AMPLIFIERSWhat about the use of BJTs?
Comments:• Can use either
substrate or lateralBJTs.
• Small-signal output resistance is 1/gm which can easily be less than 100 .
• Unfortunately, only PNP or NPN BJTs are available but not both on a standard CMOStechnology.
• In order for the BJT to sink (or source) large currents, the base current, iB, must belarge. Providing large currents as the voltage gets to extreme values is difficult forMOSFET circuits to accomplish.
• If one considers the MOSFET driver, the emitter can only pull to within vBE+VON of thepower supply rails. This value can be 1V or more.
vout
CL
Q1
VDD
M2
vout
CL
Q1
VDD
M2
p-well CMOS n-well CMOS
iB
iB
Fig. 5.5-8A
M3
M3
VDD
VSS VSSVSS
Lecture 210 – Output Amplifiers (3/27/10) Page 210-25
CMOS Analog Circuit Design © P.E. Allen - 2010
Low Output Resistance using BJTsThe output resistance of a class A BJT stage is:
Rout = r 1 + RB
1+ F =
1gm1 +
RB1+ F
Note that the second term must be less than 1/gm1 in orderto achieve the low output resistance possible.
Consequently, the driver for the BJT should be a MOSfollower as shown:
Rout = r 1 + 1/gm3
1+ F =
1gm1 +
1gm3(1+ F)
1gm1
We will consider the BJT as an output stage in more detaillater.
vIN
RB
Rout
VDD
VBN1
Q1
M2
070423-02
vIN Rout
VDD
VBN1
Q1
M2
070423-03
M3
VDD
M4
Lecture 210 – Output Amplifiers (3/27/10) Page 210-26
CMOS Analog Circuit Design © P.E. Allen - 2010
USING NEGATIVE FEEDBACK TO REDUCE THE OUTPUT RESISTANCEConceptUse negative shunt feedback – Class A implementation:
+-
vOUTvIN
A
VDDVBP1
M2
M1
vOUTvIN
VDDVBP1
M2
M1
VDDVBP1
M3 M4
M5 M6
M7
070423-01
Rout = rds1||rds2
1+Loop Gain 1
2gm2rds
10 if gm = 500μS and gmrds 100.
The actual value of Rout will be influenced by the value of RL, particularly if it is small.
Lecture 210 – Output Amplifiers (3/27/10) Page 210-27
CMOS Analog Circuit Design © P.E. Allen - 2010
Push-Pull Implementation
CL RL
vIN vOUT
iOUT
VDD
M2
M1Fig. 060-07
+-
+-
ErrorAmplifier
ErrorAmplifier
VSS
Rout = rds1||rds2
1+Loop Gain
Comments:• Can achieve output resistances as low as 10 .• If the error amplifiers are not balanced, it is difficult to control the quiescent current in
M1 and M2• Great linearity because of the strong feedback• Can be efficient if operated in class B or class AB• We will consider this circuit in more detail in a later lecture.
Lecture 210 – Output Amplifiers (3/27/10) Page 210-28
CMOS Analog Circuit Design © P.E. Allen - 2010
Simple Implementation of Neg., Shunt Feedback to Reduce the Output Resistance
CL RL
vIN vOUT
iOUT
VDD
M2
M1
Fig. 060-08
R1 R2
VSS
Loop gain R1
R1+R2
gm1+gm2gds1+gds2+GL
Rout = rds1||rds2
1+R1
R1+R2
gm1+gm2gds1+gds2+GL
Let R1 = R2, RL = , IBias = 500μA, W1/L1 = 100μm/1μm and W2/L2 = 200μm/1μm.
Thus, gm1 = 3.316mS, gm2 = 3.162mS, rds1 = 50k and rds2 = 40k .
Rout = 50k ||40k
1+0.53316+3162
25+20 =
22.22k1+0.5(143.9) = 304 (Rout = 5.42k if RL = 1k )
Lecture 210 – Output Amplifiers (3/27/10) Page 210-29
CMOS Analog Circuit Design © P.E. Allen - 2010
Boosting the Transconductance of the Source FollowerThe following configuration allows the output resistance of the source follower to bedecreased by a factor of K, where K is the current ratio between M4 and M3.
VDD
1:K
vIN
vOUT
VBN1
M1
M2
M3 M4
Rout
070423-04
Rout = 1
gm1K
Lecture 210 – Output Amplifiers (3/27/10) Page 210-30
CMOS Analog Circuit Design © P.E. Allen - 2010
SUMMARY• The objectives are to provide output power in form of voltage and/or current.• In addition, the output amplifier should be linear and be efficient.• Low output resistance is required to provide power efficiently to a small load resistance• High source/sink currents are required to provide sufficient output voltage rate due to
large load capacitances.• Types of output amplifiers considered:
Class A amplifierSource followerClass B and AB amplifierUse of BJTsNegative shunt feedback
Lecture 220 – Compensation of Op Amps (3/27/10) Page 220-1
CMOS Analog Circuit Design © P.E. Allen - 2010
LECTURE 220 – INTRODUCTION TO OP AMPSLECTURE OUTLINE
Outline• Op Amps• Categorization of Op Amps• Compensation of Op Amps• Miller Compensation• Other Forms of Compensation• Op Amp Slew Rate• SummaryCMOS Analog Circuit Design, 2nd Edition ReferencePages 243-269
Lecture 220 – Compensation of Op Amps (3/27/10) Page 220-2
CMOS Analog Circuit Design © P.E. Allen - 2010
OP AMPSWhat is an Op Amp?
The op amp (operational amplifier) is a high gain, dc coupled amplifier designed tobe used with negative feedback to precisely define a closed loop transfer function.The basic requirements for an op amp:• Sufficiently large gain (the accuracy of the signal processing determines this)• Differential inputs• Frequency characteristics that permit stable operation when negative feedback is
appliedOther requirements:• High input impedance• Low output impedance• High speed/frequency
Lecture 220 – Compensation of Op Amps (3/27/10) Page 220-3
CMOS Analog Circuit Design © P.E. Allen - 2010
Why Op Amps?The op amp is designed to be used with single-loop, negative feedback to accomplishprecision signal processing as illustrated below.
060625-01
+−
Σ
F(s)
A(s)
Op Amp
Feedback Network
Vin(s) Vout(s)Av(s)
Vout(s)Vin(s)
+
−
F(s)Vf(s) Vf(s)
Single-Loop Negative Feedback Network Op Amp Implementation of a Single-LoopNegative Feedback Network
The voltage gain, Vout(s)Vin(s) , can be shown to be equal to,
Vout(s)Vin(s) =
Av(s)1+Av(s)F(s)
If the product of Av(s)F(s) is much greater than 1, then the voltage gain becomes,
Vout(s)Vin(s)
1F(s) The precision of the voltage gain is defined by F(s).
Lecture 220 – Compensation of Op Amps (3/27/10) Page 220-4
CMOS Analog Circuit Design © P.E. Allen - 2010
OP AMP CHARACTERIZATIONLinear and Static Characterization of the CMOS Op AmpA model for a nonideal op amp that includes some of the linear, static nonidealities:
060625-03
+
-v2
v1
v1CMRR
VOS
Ricm
Ricm
en2
Cid Rid
Rout vout
Ideal Op Amp
*
Cicm
Cicm
whereRid = differential input resistanceCid = differential input capacitanceRicm = common mode input resistanceRicm = common mode input capacitanceVOS = input-offset voltageCMRR = common-mode rejection ratio (when v1=v2 an output results)e2n = voltage-noise spectral density (mean-square volts/Hertz)
Lecture 220 – Compensation of Op Amps (3/27/10) Page 220-5
CMOS Analog Circuit Design © P.E. Allen - 2010
Linear and Dynamic Characteristics of the Op AmpDifferential and common-mode frequency response:
Vout(s) = Av(s)[V1(s) - V2(s)] ± Ac(s) V1(s)+V2(s)
2
Differential-frequency response:
Av(s) = Av0
sp1
- 1s
p2- 1
sp3
- 1 ··· =
Av0 p1p2p3···(s -p1)(s -p2)(s -p3)···
where p1, p2, p3,··· are the poles of the differential-frequency response (ignoring zeros).
0dB
20log10(Av0)
|Av(jω)| dB
AsymptoticMagnitude
ActualMagnitude
ω1
ω2 ω3ω
-6dB/oct.
-12dB/oct.
-18dB/oct.
GB
Fig. 110-06
Lecture 220 – Compensation of Op Amps (3/27/10) Page 220-6
CMOS Analog Circuit Design © P.E. Allen - 2010
Other Characteristics of the Op AmpPower supply rejection ratio (PSRR):
PSRR = VDDVOUT
Av(s) = Vo/Vin (Vdd = 0)Vo/Vdd (Vin = 0)
Input common mode range (ICMR):ICMR = the voltage range over which the input common-mode signal can varywithout influence the differential performance
Slew rate (SR):SR = output voltage rate limit of the op amp
Settling time (Ts):
+-
Settling Time
Final Value
Final Value + ε
Final Value - ε
ε
ε
vOUT(t)
t00
vOUTvIN
Fig. 110-07Ts
Upper Tolerance
Lower Tolerance
Lecture 220 – Compensation of Op Amps (3/27/10) Page 220-7
CMOS Analog Circuit Design © P.E. Allen - 2010
OP AMP CATEGORIZATIONClassification of CMOS Op Amps
Conversion
Classic DifferentialAmplifier
Modified DifferentialAmplifier
Differential-to-single endedLoad (Current Mirror)
Source/SinkCurrent Loads
MOS DiodeLoad
TransconductanceGrounded Gate
TransconductanceGrounded Source
Class A (Sourceor Sink Load)
Class B(Push-Pull)
Voltageto Current
Currentto Voltage
Voltageto Current
Currentto Voltage
Hierarchy
FirstVoltageStage
SecondVoltageStage
CurrentStage
Table 110-01
Lecture 220 – Compensation of Op Amps (3/27/10) Page 220-8
CMOS Analog Circuit Design © P.E. Allen - 2010
Two-Stage CMOS Op AmpClassical two-stage CMOS op amp broken into voltage-to-current and current-to-voltagestages:
+
--
+
vin
M1 M2
M3 M4
M5
M6
M7
vout
VDD
VSSV→I I→V V→I I→V
voutvin
VBias
Fig. 6.1-8
Lecture 220 – Compensation of Op Amps (3/27/10) Page 220-9
CMOS Analog Circuit Design © P.E. Allen - 2010
Folded Cascode CMOS Op AmpFolded cascode CMOS op amp broken into stages.
060118-10VSS
VDD
M1 M2
M6
M4
M3
M5
M7
M8
M10
M9
M11
VBias
VBias
VPBias1
+
-vin vout
+
-
V→I I→I I→V
voutvin
VPBias2
Lecture 220 – Compensation of Op Amps (3/27/10) Page 220-10
CMOS Analog Circuit Design © P.E. Allen - 2010
COMPENSATION OF OP AMPSCompensationObjective
Objective of compensation is to achieve stable operation when negative feedback isapplied around the op amp.Types of Compensation1. Miller - Use of a capacitor feeding back around a high-gain, inverting stage.
• Miller capacitor only• Miller capacitor with an unity-gain buffer to block the forward path through the
compensation capacitor. Can eliminate the RHP zero.• Miller with a nulling resistor. Similar to Miller but with an added series resistance
to gain control over the RHP zero.2. Self compensating - Load capacitor compensates the op amp (later).3. Feedforward - Bypassing a positive gain amplifier resulting in phase lead. Gain can beless than unity.Because compensation plays such a strong role in design, it is considered beforedesign.
Lecture 220 – Compensation of Op Amps (3/27/10) Page 220-11
CMOS Analog Circuit Design © P.E. Allen - 2010
Single-Loop, Negative Feedback SystemsBlock diagram:
A(s) = differential-mode voltage gain of theop amp
F(s) = feedback transfer function from theoutput of op amp back to the input.
Definitions:• Open-loop gain = L(s) = -A(s)F(s)
• Closed-loop gain = Vout(s)Vin(s) =
A(s)1+A(s)F(s)
Stability Requirements:The requirements for stability for a single-loop, negative feedback system is,
|A(j 360°)F(j 360°)| = |L(j 360°)| < 1 _ |A(j 0°)F(j 0°)| = |L(j 0°)| < 1where 360°= 0° is defined as
Arg[-A(j 0°)F(j 0°)] = Arg[L(j 0°)] = 0°= 360°Another convenient way to express this requirement is
Arg[-A(j 0dB)F(jw0dB)] = Arg[L(j 0dB)] > 0°where 0dBis defined as
|A(j 0dB)F(j 0dB)| = |L(j 0dB)| = 1
A(s)
F(s)
Σ-
+Vin(s) Vout(s)
Fig. 120-01
Lecture 220 – Compensation of Op Amps (3/27/10) Page 220-12
CMOS Analog Circuit Design © P.E. Allen - 2010
Illustration of the Stability Requirement using Bode Plots
060625-07
|A(j
ω)F
(jω
)|
0dB
Arg
[-A
(jω
)F(j
ω)]
180
225
270
315
360 ω0dBω
ω
-20dB/decade
-40dB/decade
ΦM
Frequency (rads/sec.)A measure of stability is given by the phase when |A(j )F(j )| = 1. This phase is calledphase margin.
Phase margin = M = 360° - Arg[-A(j 0dB)F(j 0dB)] = 360° - Arg[L(j 0dB)]
Lecture 220 – Compensation of Op Amps (3/27/10) Page 220-13
CMOS Analog Circuit Design © P.E. Allen - 2010
Why Do We Want Good Stability?Consider the step response of second-order system which closely models the closed-loopgain of the op amp connected in unity gain.
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
0 5 10 15
45°50°
55°
60°65°
70°vout(t)Av0
ωot = ωnt (sec.)Fig. 120-03
+-
A “good” step response is one that quickly reaches its final value.Therefore, we see that phase margin should be at least 45° and preferably 60° or larger.(A rule of thumb for satisfactory stability is that there should be less than three rings.)Note that good stability is not necessarily the quickest rise time.
Lecture 220 – Compensation of Op Amps (3/27/10) Page 220-14
CMOS Analog Circuit Design © P.E. Allen - 2010
Uncompensated Frequency Response of Two-Stage Op AmpsTwo-Stage Op Amps:
Fig. 120-04
-
+vin
M1 M2
M3 M4
M5
M6
M7
vout
VDD
VSS
VBias+
-
-
+vin
Q1 Q2
Q3 Q4
Q5
Q6
Q7
vout
VCC
VEE
VBias+
-
Small-Signal Model:
vout
Fig. 120-05
gm1vin2
R1 C1
+
-v1
gm2vin2 gm4v1 R2 C2 gm6v2
+
-v2 R3 C3
+
-
D1, D3 (C1, C3) D2, D4 (C2, C4) D6, D7 (C6, C7)
Note that this model neglects the base-collector and gate-drain capacitances for purposesof simplification.
Lecture 220 – Compensation of Op Amps (3/27/10) Page 220-15
CMOS Analog Circuit Design © P.E. Allen - 2010
Uncompensated Frequency Response of Two-Stage Op Amps - ContinuedFor the MOS two-stage op amp:
R1 1
gm3 ||rds3||rds1 1
gm3 R2 = rds2|| rds4 and R3 = rds6|| rds7
C1 = Cgs3+Cgs4+Cbd1+Cbd3 C2 = Cgs6+Cbd2+Cbd4 and C3 = CL +Cbd6+Cbd7For the BJT two-stage op amp:
R1 = 1
gm3 ||r 3||r 4||ro1||ro31
gm3 R2 = r 6|| ro2|| ro4 r 6 and R3 = ro6|| ro7
C1 = C 3+C 4+Ccs1+Ccs3 C2 = C 6+Ccs2+Ccs4 and C3 = CL+Ccs6+Ccs7
Assuming the pole due to C1 is much greater than the poles due to C2 and C3 gives,
voutgm1vinR2 C2 gm6v2
+
-v2 R3 C3
+
-
Fig. 120-06
Voutgm1VinRI CI gmIIVI
+
-VI RII CII
+
-
The locations for the two poles are given by the following equations
p’1 = -1
RICIand p’2 =
-1RIICII
where RI (RII) is the resistance to ground seen from the output of the first (second) stageand CI (CII) is the capacitance to ground seen from the output of the first (second) stage.
Lecture 220 – Compensation of Op Amps (3/27/10) Page 220-16
CMOS Analog Circuit Design © P.E. Allen - 2010
Uncompensated Frequency Response of an Op Amp (F(s) = 1)
060625-08
0dB
Avd(0) dB
-20dB/decade
log10(ω)
log10(ω)
180°
270°
360°
Phase Shift
GB
|p1'|
-40dB/decade
315°
225°
-45/decade
-45/decade
|p2'|
|A(j
ω)|
Arg
[-A
(jω
)]
ω0dB
If we assume that F(s) = 1 (this is the worst case for stability considerations), then theabove plot is the same as the loop gain.Note that the phase margin is much less than 45° ( 6°).Therefore, the op amp must be compensated before using it in a closed-loopconfiguration.
Lecture 220 – Compensation of Op Amps (3/27/10) Page 220-17
CMOS Analog Circuit Design © P.E. Allen - 2010
MILLER COMPENSATIONMiller Compensation of the Two-Stage Op Amp
Fig. 120-08
-
+vin
M1 M2
M3 M4
M5
M6
M7
vout
VDD
VSS
VBias+
-
-
+vin
Q1 Q2
Q3 Q4
Q5
Q6
Q7
VCC
VEE
VBias+
-
CM
CI
Cc
CII
vout
CI
Cc
CII
CM
The various capacitors are:Cc = accomplishes the Miller compensation
CM = capacitance associated with the first-stage mirror (mirror pole)
CI = output capacitance to ground of the first-stage
CII = output capacitance to ground of the second-stage
Lecture 220 – Compensation of Op Amps (3/27/10) Page 220-18
CMOS Analog Circuit Design © P.E. Allen - 2010
Compensated Two-Stage, Small-Signal Frequency Response Model SimplifiedUse the CMOS op amp to illustrate:1.) Assume that gm3 >> gds3 + gds1
2.) Assume that gm3
CM >> GB
Therefore,
-gm1vin2 CM
1gm3 gm4v1
gm2vin2 C1 rds2||rds4
gm6v2 rds6||rds7 CL
v1 v2Cc
+
-
vout
Fig. 120-09
rds1||rds3
gm1vin rds2||rds4 gm6v2 rds6||rds7CII
v2Cc
+
-
voutCI
+
-vin
Same circuit holds for the BJT op amp with different component relationships.
Lecture 220 – Compensation of Op Amps (3/27/10) Page 220-19
CMOS Analog Circuit Design © P.E. Allen - 2010
General Two-Stage Frequency Response Analysiswhere gmI = gm1 = gm2, RI = rds2||rds4, CI = C1
and gmII = gm6, RII = rds6||rds7, CII = C2 = CL
Nodal Equations: -g
mIV
in = [G
I + s(C
I + C
c)]V2 - [sC
c]V
out and 0 = [g
mII - sC
c]V2 + [G
II + sC
II + sC
c]V
out
Solving using Cramer’s rule gives,V
out(s)
Vin(s) =
gmI
(gmII
- sCc)
GIG
II+s [G
II(C
I+C
II)+G
I(C
II+C
c)+g
mIIC
c]+s2[C
IC
II+C
cC
I+C
cC
II]
= A
o[1 - s (C
c/g
mII)]
1+s [RI(C
I+C
II)+R
II(C2+C
c)+g
mIIR
1R
IIC
c]+s2[R
IR
II(C
IC
II+C
cC
I+C
cC
II)]
where, Ao = g
mIg
mIIR
IR
II
In general, D(s) = 1-sp1
1-sp2
= 1-s 1p1
+1p2
+s2
p1p2 D(s) 1-
sp1
+ s2
p1p2 , if |p2|>>|p1|
p1 =-1
RI(C
I+C
II)+R
II(CII+C
c)+g
mIIR
1R
IIC
c
-1g
mIIR
1R
IIC
c
, z =g
mII
Cc
gmIVin RI gmIIV2 RII CII
V2Cc
+
-VoutCI
+
-Vin
Fig.120-10
p2 =-[RI(CI+CII)+RII(CII+Cc)+gmIIR1RIICc]
RIRII(CICII+CcCI+CcCII)-gmIICc
CICII+CcCI+CcCII
-gmII
CII, CII > Cc > CI
Lecture 220 – Compensation of Op Amps (3/27/10) Page 220-20
CMOS Analog Circuit Design © P.E. Allen - 2010
Summary of Results for Miller Compensation of the Two-Stage Op AmpThere are three roots of importance:1.) Right-half plane zero:
z1= gmII
Cc =
gm6
Cc
This root is very undesirable- it boosts the magnitude while decreasing the phase.2.) Dominant left-half plane pole (the Miller pole):
p1 -1
gmIIRIRIICc =
-(gds2+gds4)(gds6+gds7)gm6Cc
This root accomplishes the desired compensation.3.) Left-half plane output pole:
p2 -gmII
CII
-gm6
CL
p2 must be unity-gainbandwidth or satisfactory phase margin will not be achieved.Root locus plot of the Miller compensation:
jω
σ
Cc=0Open-loop poles
Closed-loop poles, Cc≠0
p2 p2' p1p1' z1 Fig. 120-11
Lecture 220 – Compensation of Op Amps (3/27/10) Page 220-21
CMOS Analog Circuit Design © P.E. Allen - 2010
Compensated Open-Loop Frequency Response of the Two-Stage Op Amp
060118-10
0dB
Avd(0) dB
-20dB/decade
log10(ω)
log10(ω)
Phase Margin
180°
270°
360°
Phase Shift
GB
-40dB/decade
315°
225°
|p1'|
No phase margin
Uncompensated
Compensated
-45/decade
-45/decade
|p2'||p1| |p2|
|A(j
ω)F
(jω
)|A
rg[-
A(j
ω)F
(jω
)|
Compensated
Uncompensated
F(jω)=1
F(jω)=1
Note that the unity-gainbandwidth, GB, is
GB = Avd(0)·|p1| = (gmIgmIIRIRII)1
gmIIRIRIICc =
gmI
Cc =
gm1
Cc =
gm2
Cc
Lecture 220 – Compensation of Op Amps (3/27/10) Page 220-22
CMOS Analog Circuit Design © P.E. Allen - 2010
Conceptually, where do these roots come from?1.) The Miller pole:
|p1| 1
RI(gm6RIICc)
2.) The left-half plane output pole:
|p2| gm6CII
3.) Right-half plane zero (One source of zeros is frommultiple paths from the input to output):
vout = -gm6RII(1/sCc)
RII + 1/sCc v’ +
RII
RII + 1/sCc v’’ =
-RII
gm6
sCc- 1
RII + 1/sCc v
where v = v’ = v’’.
VDD
CcRII
vout
vI
M6RI
≈gm6RIICcFig. 120-13
VDD
CcRII
vout
M6CII
GB·Cc
1 ≈ 0
VDD
RII
vout
M6CII
Fig. 120-14
VDD
CcRII
vout
v'v''
M6
Fig. 120-15
Lecture 220 – Compensation of Op Amps (3/27/10) Page 220-23
CMOS Analog Circuit Design © P.E. Allen - 2010
Further Comments on p2The previous observations on p2 can be proved as follows:
Find the resistance RCc seen by the compensation capacitor, Cc.
060626-02
VDD
RII
RI
M6
RCc
RIRII
+
−vgs6
gm6vgs6
vx
ix ixRCc
Cc
vx = ixRI + (ix + gm6vgs6)RII = ixRI + (ix + gm6ixRI)RIITherefore,
RCc = vxix = RI + (1 + gm6RI)RII gm6RIRII
The frequency at which Cc begins to become a short is,1Cc
< gm6RIRII or > 1
gm6RIRII Cc |p1|
Thus, at the frequency where CII begins to short the output, Cc is acting as a short.
Lecture 220 – Compensation of Op Amps (3/27/10) Page 220-24
CMOS Analog Circuit Design © P.E. Allen - 2010
Influence of the Mirror PoleUp to this point, we have neglected the influence of the pole, p3, associated with thecurrent mirror of the input stage. A small-signal model for the input stage that includesC3 is shown below:
gm3rds31
rds1
gm1Vin
rds2
i3
i3 rds4C3
+
-Vo1
2gm2Vin
2
Fig. 120-16
The transfer function from the input to the output voltage of the first stage, Vo1(s), can bewritten as
Vo1(s)Vin(s) =
-gm12(gds2+gds4)
gm3+gds1+gds3gm3+ gds1+gds3+sC3
+ 1 -gm1
2(gds2+gds4) sC3 + 2gm3sC3 + gm3
We see that there is a pole and a zero given as
p3 = - gm3C3
and z3 = - 2gm3C3
Lecture 220 – Compensation of Op Amps (3/27/10) Page 220-25
CMOS Analog Circuit Design © P.E. Allen - 2010
Summary of the Conditions for Stability of the Two-Stage Op Amp• Unity-gainbandwith is given as:
GB = Av(0)·|p1| =(gmIgmIIRIRII)·1
gmIIRIRIICc =
gmICc
= (gm1gm2R1R2)·1
gm2R1R2Cc =
gm1Cc
• The requirement for 45° phase margin is:
±180° - Arg[Loop Gain] = ±180° - tan-1 |p1| - tan-1 |p2| - tan-1 z = 45°
Let = GB and assume that z 10GB, therefore we get,
±180° - tan-1GB|p1| - tan-1
GB|p2| - tan-1
GBz = 45°
135° tan-1(Av(0)) + tan-1GB|p2| + tan-1(0.1) = 90° + tan-1
GB|p2| + 5.7°
39.3° tan-1GB|p2|
GB|p2| = 0.818 |p2| 1.22GB
• The requirement for 60° phase margin:
|p2| 2.2GB if z 10GB
• If 60° phase margin is required, then the following relationships apply:gm6Cc >
10gm1Cc gm6 > 10gm1 and
gm6C2 >
2.2gm1Cc Cc > 0.22C2
Lecture 220 – Compensation of Op Amps (3/27/10) Page 220-26
CMOS Analog Circuit Design © P.E. Allen - 2010
OTHER FORMS OF COMPENSATIONFeedforward CompensationUse two parallel paths to achieve a LHP zero for lead compensation purposes.
CcA
VoutVi
InvertingHigh GainAmplifier
CII RII
RHP Zero Cc-A
VoutVi
InvertingHigh GainAmplifier
CII RII
LHP Zero
A
CII RIIVi Vout
Cc
gmIIVi
+
-
+
- Fig.430-09
Cc
VoutVi +1
LHP Zero using Follower
Vout(s)Vin(s) =
ACcCc + CII
s + gmII/ACc
s + 1/[RII(Cc + CII)]
To use the LHP zero for compensation, a compromise must be observed.• Placing the zero below GB will lead to boosting of the loop gain that could deteriorate
the phase margin.• Placing the zero above GB will have less influence on the leading phase caused by the
zero.Note that a source follower is a good candidate for the use of feedforward compensation.
Lecture 220 – Compensation of Op Amps (3/27/10) Page 220-27
CMOS Analog Circuit Design © P.E. Allen - 2010
Self-Compensated Op AmpsSelf compensation occurs when the load capacitor is the compensation capacitor (cannever be unstable for resistive feedback)
Fig. 430-10
-
+vin vout
CL
+
-Gm
Rout(must be large)
Increasing CL
|dB|
Av(0) dB
0dB ω
Rout
-20dB/dec.
Voltage gain:vout
vin = Av(0) = GmRout
Dominant pole:
p1 = -1
RoutCL
Unity-gainbandwidth:
GB = Av(0)·|p1| = Gm
CL
Stability:Large load capacitors simply reduce
GB but the phase is still 90° at GB.
Lecture 220 – Compensation of Op Amps (3/27/10) Page 220-28
CMOS Analog Circuit Design © P.E. Allen - 2010
FINDING ROOTS BY INSPECTIONIdentification of Poles from a Schematic1.) Most poles are equal to the reciprocal product of the resistance from a node to groundand the capacitance connected to that node.2.) Exceptions (generally due to feedback):
a.) Negative feedback:
-A
R1
C2
C1
C3
-A
R1
C2
C1 C3(1+A)RootID01
b.) Positive feedback (A<1):
+A
R1
C2
C1
C3
+A
R1
C2
C1 C3(1-A)RootID02
Lecture 220 – Compensation of Op Amps (3/27/10) Page 220-29
CMOS Analog Circuit Design © P.E. Allen - 2010
Identification of Zeros from a Schematic1.) Zeros arise from poles inthe feedback path.
If F(s) = 1
sp1
+1 ,
then VoutVin
= A(s)
1+A(s)F(s) = A(s)
1+A(s)1
sp1
+1
=A(s)
sp1
+1
sp1
+1+ A(s)
2.) Zeros are also created by two paths from the input to theoutput and one of more of the paths is frequency dependent.3.) Zeros also come from simple RC networks.
VoutVin
= s + 1/(R1C1)
s + 1/(R1||R2)C1
vin vout
F(s)
A(s)Σ−
+RootID03
VDD
CcRII
vout
v'v''
M6
070425-01C1
R1 R2Vin Vout
+
−
+
−070425−02
Lecture 220 – Compensation of Op Amps (3/27/10) Page 220-30
CMOS Analog Circuit Design © P.E. Allen - 2010
CMOS OP AMP SLEW RATESlew Rate of a Two-Stage CMOS Op AmpRemember that slew rate occurs when currents flowing in a capacitor become limitedand is given as
Ilim = C dvC
dt where vC is the voltage across the capacitor C.
SR+ = minI5
Cc,I6-I5-I7
CL =
I5
Cc because I6>>I5 SR- = min
I5
Cc,I7-I5
CL =
I5
Cc if I7>>I5.
Therefore, if CL is not too large and if I7 is significantly greater than I5, then the slew rateof the two-stage op amp should be, I5/Cc.
Lecture 220 – Compensation of Op Amps (3/27/10) Page 220-31
CMOS Analog Circuit Design © P.E. Allen - 2010
SUMMARY• Op amps achieve accuracy by using negative feedback• Compensation is required to insure that the feedback loop is stable• The degree of stability is measured by phase margin and is necessary to achieve small
settling times• A compensated op amp will have one dominant pole and all other poles will be greater
than GB• A two-stage op amp requires some form of Miller compensation• A high output resistance op amp is compensated by the load capacitor• Poles of a CMOS circuit are generally equal to the negative reciprocal of the product of
the resistance to ground from a node times the sum of the capacitances connected tothat node.
• The slew rate of the two-stage op amp is equal to the input differential stage currentsink/source divided by the Miller capacitor
Lecture 230 – Design of Two-Stage Op Amps (3/27/10) Page 230-1
CMOS Analog Circuit Design © P.E. Allen - 2010
LECTURE 230 – DESIGN OF TWO-STAGE OP AMPSLECTURE OUTLINE
Outline• Steps in Designing an Op Amp• Design Procedure for a Two-Stage Op Amp• Design Example of a Two-Stage Op Amp• Right Half Plane Zero• PSRR of the Two-Stage Op Amp• SummaryCMOS Analog Circuit Design, 2nd Edition ReferencePages 269-293
Lecture 230 – Design of Two-Stage Op Amps (3/27/10) Page 230-2
CMOS Analog Circuit Design © P.E. Allen - 2010
STEPS IN DESIGNING A CMOS OP AMPSteps1.) Choosing or creating the basic structure of the op amp.
This step is results in a schematic showing the transistors and their interconnections.This diagram does not change throughout the remainder of the design unless thespecifications cannot be met, then a new or modified structure must be developed.
2.) Selection of the dc currents and transistor sizes.Most of the effort of design is in this category.Simulators are used to aid the designer in this phase.
3.) Physical implementation of the design.Layout of the transistorsFloorplanning the connections, pin-outs, power supply buses and groundsExtraction of the physical parasitics and re-simulationVerification that the layout is a physical representation of the circuit.
4.) Fabrication5.) Measurement
Verification of the specificationsModification of the design as necessary
Lecture 230 – Design of Two-Stage Op Amps (3/27/10) Page 230-3
CMOS Analog Circuit Design © P.E. Allen - 2010
Design InputsBoundary conditions:
1. Process specification (VT, K', Cox, etc.)2. Supply voltage and range3. Supply current and range4. Operating temperature and range
Requirements:1. Gain2. Gain bandwidth3. Settling time4. Slew rate5. Common-mode input range, ICMR6. Common-mode rejection ratio, CMRR7. Power-supply rejection ratio, PSRR8. Output-voltage swing9. Output resistance
10. Offset11. Noise12. Layout area
Lecture 230 – Design of Two-Stage Op Amps (3/27/10) Page 230-4
CMOS Analog Circuit Design © P.E. Allen - 2010
Outputs of Op Amp DesignThe basic outputs of design are:1.) The topology2.) The dc currents3.) The W and L values of transistors4.) The values of components
060625-06
-
+vin
M1 M2
M3 M4
M5
M6
M7
vout
VDD
VSS
VBias
CL
+
-
Cc
W/L ratios
Topology
DC Currents
L
W
Op amp circuit or systems
specifications
Design ofCMOS
Op Amps
Componentvalues
C R
50µA
Lecture 230 – Design of Two-Stage Op Amps (3/27/10) Page 230-5
CMOS Analog Circuit Design © P.E. Allen - 2010
Some Practical Thoughts on Op Amp Design1.) Decide upon a suitable topology.
• Experience is a great help• The topology should be the one capable of meeting most of the specifications• Try to avoid “inventing” a new topology but start with an existing topology
2.) Determine the type of compensation needed to meet the specifications.• Consider the load and stability requirements• Use some form of Miller compensation or a self-compensated approach
3.) Design dc currents and device sizes for proper dc, ac, and transient performance.• This begins with hand calculations based upon approximate design equations.• Compensation components are also sized in this step of the procedure.• After each device is sized by hand, a circuit simulator is used to fine tune the
designTwo basic steps of design:1.) “First-cut” - this step is to use hand calculations to propose a design that has
potential of satisfying the specifications. Design robustness is developed in this step.2.) Optimization - this step uses the computer to refine and optimize the design.
Lecture 230 – Design of Two-Stage Op Amps (3/27/10) Page 230-6
CMOS Analog Circuit Design © P.E. Allen - 2010
A DESIGN PROCEDURE FOR THE TWO-STAGE CMOS OP AMPUnbuffered, Two-Stage CMOS Op Amp
-
+
vin
M1 M2
M3 M4
M5
M6
M7
vout
VDD
VSS
VBias+
-
Cc
CL
Fig. 6.3-1
Notation:
Si = W i
Li = W/L of the ith transistor
Lecture 230 – Design of Two-Stage Op Amps (3/27/10) Page 230-7
CMOS Analog Circuit Design © P.E. Allen - 2010
DC Balance Conditions for the Two-Stage Op AmpFor best performance, keep all transistors insaturation.M4 is the only transistor that cannot be forcedinto saturation by internal connections orexternal voltages.Therefore, we develop conditions to force M4 tobe in saturation.1.) First assume that VSG4 = VSG6. This willcause “proper mirroring” in the M3-M4 mirror.Also, the gate and drain of M4 are at the samepotential so that M4 is “guaranteed” to be insaturation.
2.) If VSG4 = VSG6, then I6 = S6
S4I4
3.) However, I7 = S7
S5I5 =
S7
S5 (2I4)
4.) For balance, I6 must equal I7 S6
S4=
2S7
S5called the “balance conditions”
5.) So if the balance conditions are satisfied, then VDG4 = 0 and M4 is saturated.
-
+vin
M1 M2
M3 M4
M5
M6
M7
vo
VDD
VSS
VBias+
-
Cc
CL
-+VSG6
-+VSG4
I4
I5
I7
I6
Fig. 6.3-1A
Lecture 230 – Design of Two-Stage Op Amps (3/27/10) Page 230-8
CMOS Analog Circuit Design © P.E. Allen - 2010
Summary of the Design Relationships for the Two-Stage Op Amp
Slew rate SR = I5Cc
(Assuming I7 >>I5 and CL > Cc)
First-stage gain Av1 = gm1
gds2 + gds4 =
2gm1I5(l2 + l4)
Second-stage gain Av2 = gm6
gds6 + gds7 =
gm6I6(l6 + l7)
Gain-bandwidth GB = gm1Cc
Output pole p2 = -gm6CL
RHP zero z1 = gm6Cc
60° phase margin requires that gm6 = 2.2gm2(CL/Cc) if all other roots are 10GB.
Positive ICMR Vin(max) = VDD - I5b3
- |VT03|(max) + VT1(min))
Negative ICMR Vin(min) = VSS + I5b1
+ VT1(max) + VDS5(sat)
Lecture 230 – Design of Two-Stage Op Amps (3/27/10) Page 230-9
CMOS Analog Circuit Design © P.E. Allen - 2010
Op Amp SpecificationsThe following design procedure assumes that specifications for the following parametersare given.1. Gain at dc, Av(0)2. Gain-bandwidth, GB3. Phase margin (or settling time)4. Input common-mode range, ICMR5. Load Capacitance, CL
6. Slew-rate, SR7. Output voltage swing8. Power dissipation, Pdiss
-
+
vin M1 M2
M3 M4
M5
M6
M7
vout
VDD
VSS
VBias+
-
Cc
CL
VSG4+
-
Max. ICMRand/or p3
VSG6+
-
Vout(max)
I6
gm6 or Proper Mirroring
VSG4=VSG6
Cc ≈ 0.2CL(PM = 60°)
GB =gm1Cc
Min. ICMR I5 I5 = SR·Cc Vout(min)
Fig. 160-02
Lecture 230 – Design of Two-Stage Op Amps (3/27/10) Page 230-10
CMOS Analog Circuit Design © P.E. Allen - 2010
Unbuffered Op Amp Design ProcedureThis design procedure assumes that the gain at dc (Av), unity gain bandwidth (GB), inputcommon mode range (Vin(min) and Vin(max)), load capacitance (CL), slew rate (SR),settling time (Ts), output voltage swing (Vout(max) and Vout(min)), and power dissipation(Pdiss) are given. Choose the smallest device length which will keep the channelmodulation parameter constant and give good matching for current mirrors.1. From the desired phase margin, choose the minimum value for Cc, i.e. for a 60° phase
margin we use the following relationship. This assumes that z 10GB.Cc > 0.22CL
2. Determine the minimum value for the “tail current” (I5) from
I5 = SR .Cc
3. Design for S3 from the maximum input voltage specification.
S3 = I5
K'3[VDD Vin(max) |VT03|(max) + VT1(min)]2
4. Verify that the pole of M3 due to Cgs3 and Cgs4 (= 0.67W3L3Cox) will not be dominantby assuming it to be greater than 10 GB
gm32Cgs3 > 10GB.
Lecture 230 – Design of Two-Stage Op Amps (3/27/10) Page 230-11
CMOS Analog Circuit Design © P.E. Allen - 2010
Unbuffered Op Amp Design Procedure - Continued5. Design for S1 (S2) to achieve the desired GB.
gm1 = GB . Cc S2 = gm12
K'1I5
6. Design for S5 from the minimum input voltage. First calculate VDS5(sat) then find S5.
VDS5(sat) = Vin(min) - VSS- I5
1 -VT1(max) 100 mV S5 = 2I5
K'5[VDS5(sat)]2
7. Find S6 by letting the second pole (p2) be equal to 2.2 times GB and assuming thatVSG4 = VSG6.
gm6 = 2.2gm2(CL/Cc) and gm6gm4
= 2KP'S6I6
2KP'S4I4 =
S6S4
I6I4
= S6S4
S6 = gm6gm4
S4
8. Calculate I6 from
I6 = gm62
2K'6S6
Check to make sure that S6 satisfies the Vout(max) requirement and adjust as necessary.
9. Design S7 to achieve the desired current ratios between I5 and I6.S7 = (I6/I5)S5 (Check the minimum output voltage requirements)
Lecture 230 – Design of Two-Stage Op Amps (3/27/10) Page 230-12
CMOS Analog Circuit Design © P.E. Allen - 2010
Unbuffered Op Amp Design Procedure - Continued10. Check gain and power dissipation specifications.
Av = 2gm2gm6
I5(l2 + l4)I6(l6 + l7) Pdiss = (I5 + I6)(VDD + |VSS|)
11. If the gain specification is not met, then the currents, I5 and I6, can be decreased orthe W/L ratios of M2 and/or M6 increased. The previous calculations must be recheckedto insure that they are satisfied. If the power dissipation is too high, then one can onlyreduce the currents I5 and I6. Reduction of currents will probably necessitate increase ofsome of the W/L ratios in order to satisfy input and output swings.12. Simulate the circuit to check to see that all specifications are met.
Lecture 230 – Design of Two-Stage Op Amps (3/27/10) Page 230-13
CMOS Analog Circuit Design © P.E. Allen - 2010
DESIGN EXAMPLE OF A TWO-STAGE OP AMPExample 230-1 - Design of a Two-Stage Op Amp
If KN’=120μA/V2, KP’= 25μA/V2, VTN = |VTP| = 0.5V, N = 0.06V-1, and P =
0.08V-1, design a two-stage, CMOS op amp that meets the following specifications.Assume the channel length is to be 0.5μm and the load capacitor is CL = 10pF.
Av > 3000V/V VDD =2.5V GB = 5MHz SR > 10V/μs
60° phase margin 0.5V<Vout range < 2V ICMR = 1.25V to 2V Pdiss 2mW
Solution1.) The first step is to calculate the minimum value of the compensation capacitor Cc,
Cc > (2.2/10)(10 pF) = 2.2 pF
2.) Choose Cc as 3pF. Using the slew-rate specification and Cc calculate I5.
I5 = (3x10-12)(10x106) = 30 μA
3.) Next calculate (W/L)3 using ICMR requirements (use worst case thresholds ±0.15V).
(W/L)3 = 30x10-6
(25x10-6)[2.5 - 2 - .65 + 0.35]2 = 30 (W/L)3 = (W/L)4 = 30
Lecture 230 – Design of Two-Stage Op Amps (3/27/10) Page 230-14
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 230-1 - Continued4.) Now we can check the value of the mirror pole, p3, to make sure that it is in factgreater than 10GB. Assume the Cox = 6fF/μm2. The mirror pole can be found as
p3 -gm32Cgs3
= - 2K’pS3I3
2(0.667)W3L3Cox = -1.25x109(rads/sec)
or 199 MHz. Thus, p3, is not of concern in this design because p3 >> 10GB.
5.) The next step in the design is to calculate gm1 to get
gm1 = (5x106)(2 )(3x10-12) = 94.25μS
Therefore, (W/L)1 is
(W/L)1 = (W/L)2 = gm12
2K’NI1 =
(94.25)2
2·120·15 = 2.47 3.0 (W/L)1 = (W/L)2 = 3
6.) Next calculate VDS5,
VDS5 = 1.25 -30x10-6
120x10-6·3 - .65 = 0.31V
Using VDS5 calculate (W/L)5 from the saturation relationship.
(W/L)5 = 2(30x10-6)
(120x10-6)(0.31)2 = 5.16 6 (W/L)5 = 6
Lecture 230 – Design of Two-Stage Op Amps (3/27/10) Page 230-15
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 230-1 - Continued7.) For 60° phase margin, we know that
gm6 10gm1 942.5μS
Assuming that gm6 = 942.5μS and knowing that gm4 = 150μS, we calculate (W/L)6 as
(W/L)6 = 30 942.5x10-6
(150x10-6) = 188.5 190 (W/L)6 = 190
8.) Calculate I6 using the small-signal gm expression:
I6 = (942.5x10-6)2
(2)(25x10-6)(188.5) = 94.2μA 95μA
Calculating (W/L)6 based on Vout(max), gives a value of 15. Since 190 exceeds thespecification and gives better phase margin, we choose (W/L)6 = 190 and I6 = 95μA.
With I6 = 95μA the power dissipation is Pdiss = 2.5V·(30μA+95μA) = 0.3125mW
9.) Finally, calculate (W/L)7
(W/L)7 = 6 95x10-6
30x10-6 = 19 20 (W/L)7 = 20
Let us check the Vout(min) specification although the W/L of M7 is so large that this isprobably not necessary. The value of Vout(min) is
Vout(min) = VDS7(sat) = (2·95)/(120·20) = 0.281V
which is less than required. At this point, the first-cut design is complete.
Lecture 230 – Design of Two-Stage Op Amps (3/27/10) Page 230-16
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 230-1 - Continued10.) Now check to see that the gain specification has been met
Av = (94.25x10-6)(942.5x10-6)
15x10-6(.06 + .08)95x10-6(.06 + .08) = 3,180V/V
which barely exceeds the specifications. Since we are at 2xLmin, it won’t do any good toincrease the channel lengths. Decreasing the currents or increasing W6/L6 will help.
The figure below shows the results of the first-cut design. The W/L ratios shown donot account for the lateral diffusion discussed above. The next phase requires simulation.
Lecture 230 – Design of Two-Stage Op Amps (3/27/10) Page 230-17
CMOS Analog Circuit Design © P.E. Allen - 2010
RIGHT-HALF PLANE ZEROControlling the Right-Half Plane ZeroWhy is the RHP zero a problem?Because it boosts the magnitude but lags the phase - the worst possible combination forstability.
060626-03
jω
σ
jω1
jω2
jω3
θ1θ2
θ3
180 > θ1 > θ2 > θ3
z1
LoopGain
0dB log10ω
log10ω360°
180°
RHP Zero Boost
RHP Zero Lag
Loop PhaseShift
Solution of the problem:The compensation comes from the feedback path through Cc, but the RHP zero
comes from the feedforward path through Cc so eliminate the feedforward path!
Lecture 230 – Design of Two-Stage Op Amps (3/27/10) Page 230-18
CMOS Analog Circuit Design © P.E. Allen - 2010
Use of Buffer to Eliminate the Feedforward Path through the Miller CapacitorModel:
The transferfunction is givenby the followingequation,
Vo(s)Vin(s) =
(gmI)(gmII)(RI)(RII)1 + s[RICI + RIICII + RICc + gmIIRIRIICc] + s2[RIRIICII(CI + Cc)]
Using the technique as before to approximate p1 and p2 results in the following
p1 -1
RICI + RIICII + RICc + gmIIRIRIICc
-1gmIIRIRIICc
and
p2 -gmIICc
CII(CI + Cc)
Comments:Poles are approximately what they were before with the zero removed.For 45° phase margin, |p2| must be greater than GB
For 60° phase margin, |p2| must be greater than 1.73GB
Fig. 430-0
InvertingHigh-GainStage
Cc
vOUT gmIvin RIgmIIVI
RII CII
VICc
+
-VoCI
+
-Vin Vout
+1
Lecture 230 – Design of Two-Stage Op Amps (3/27/10) Page 230-19
CMOS Analog Circuit Design © P.E. Allen - 2010
Use of Buffer with Finite Output Resistance to Eliminate the RHP ZeroAssume that the unity-gain buffer has an output resistance of Ro.
Model:
InvertingHigh-GainStage
+1Cc
vOUT gmIvin RIgmIIVI
RII CII
VICc
+
-
VoutCI
+
-Vin Ro
Ro
Vout
Fig. 430-03
Ro
It can be shown that if the output resistance of the buffer amplifier, Ro, is not neglectedthat another pole occurs at,
p4 -1
Ro[CICc/(CI + Cc)]
and a LHP zero at
z2 -1
RoCc
Closer examination shows that if a resistor, called a nulling resistor, is placed in serieswith Cc that the RHP zero can be eliminated or moved to the LHP.
Lecture 230 – Design of Two-Stage Op Amps (3/27/10) Page 230-20
CMOS Analog Circuit Design © P.E. Allen - 2010
Use of Nulling Resistor to Eliminate the RHP Zero (or turn it into a LHP zero)†
InvertingHigh-GainStage
Cc
vOUT
Rz
gmIvin RIgmIIVI RII CII
Cc
+
-
VoutCI
+
-Vin
Rz
Fig. 430-04
VI
Nodal equations:
gmIVin + VIRI
+ sCIVI + sCc
1 + sCcRz (VI - Vout) = 0
gmIIVI + VoRII
+ sCIIVout + sCc
1 + sCcRz (Vout - VI) = 0
Solution:
Vout(s)Vin(s) =
a{1 - s[(Cc/gmII) - RzCc]}1 + bs + cs2 + ds3
where
† W,J. Parrish, "An Ion Implanted CMOS Amplifier for High Performance Active Filters", Ph.D. Dissertation, 1976, Univ. of CA., Santa Barbara.
a = gmIgmIIRIRIIb = (CII + Cc)RII + (CI + Cc)RI + gmIIRIRIICc + RzCcc = [RIRII(CICII + CcCI + CcCII) + RzCc(RICI + RIICII)]d = RIRIIRzCICIICc
Lecture 230 – Design of Two-Stage Op Amps (3/27/10) Page 230-21
CMOS Analog Circuit Design © P.E. Allen - 2010
Use of Nulling Resistor to Eliminate the RHP - ContinuedIf Rz is assumed to be less than RI or RII and the poles widely spaced, then the roots ofthe above transfer function can be approximated as
p1 -1
(1 + gmIIRII)RICc
-1gmIIRIIRICc
p2 -gmIICc
CICII + CcCI + CcCII
-gmIICII
p4 = -1
RzCI
and
z1 = 1
Cc(1/gmII - Rz)
Note that the zero can be placed anywhere on the real axis.
Lecture 230 – Design of Two-Stage Op Amps (3/27/10) Page 230-22
CMOS Analog Circuit Design © P.E. Allen - 2010
A Design Procedure that Allows the RHP Zero to Cancel the Output Pole, p2
We desire that z1 = p2 in terms of the previous notation.
Therefore,1
Cc(1/gmII - Rz) =
-gmIICII
The value of Rz can be found as
Rz = Cc + CII
Cc (1/gmII)
With p2 canceled, the remaining roots are p1 and p4(the pole due to Rz) . For unity-gainstability, all that is required is that
|p4| > Av(0)|p1| = Av(0)
gmIIRIIRICc =
gmI
Cc
and (1/RzCI) > (gmI/Cc) = GB
Substituting Rz into the above inequality and assuming CII >> Cc results in
Cc > gmIgmII
CICII
This procedure gives excellent stability for a fixed value of CII ( CL).
Unfortunately, as CL changes, p2 changes and the zero must be readjusted to cancel p2.
jω
Fig. 430-06σ
-p4 -p2 -p1 z1
Lecture 230 – Design of Two-Stage Op Amps (3/27/10) Page 230-23
CMOS Analog Circuit Design © P.E. Allen - 2010
Incorporating the Nulling Resistor into the Miller Compensated Two-Stage Op AmpCircuit:
We saw earlier that the roots were:
p1 = - gm2AvCc
= - gm1AvCc
p2 = - gm6CL
p4 = - 1
RzCIz1 =
-1RzCc - Cc/gm6
where Av = gm1gm6RIRII.
(Note that p4 is the pole resulting from the nulling resistor compensation technique.)
VDD
VSS
IBias
CL
CcCM vout
VBVA
M1 M2
M3 M4
M5
M6
M7M9
M10
M11
M12
vin+vin-
M8
Fig. 160-03
VC
Lecture 230 – Design of Two-Stage Op Amps (3/27/10) Page 230-24
CMOS Analog Circuit Design © P.E. Allen - 2010
Design of the Nulling Resistor (M8)For the zero to be on top of the second pole (p2), the following relationship must hold
Rz = 1
gm6
CL + CcCc
= Cc+CL
Cc
12K’PS6I6
The resistor, Rz, is realized by the transistor M8 which is operating in the active regionbecause the dc current through it is zero. Therefore, Rz, can be written as
Rz = vDS8iD8
|VDS8=0
= 1
K’PS8(VSG8-|VTP|)
The bias circuit is designed so that voltage VA is equal to VB.
|VGS10| |VT| = |VGS8| |VT| VSG11 = VSG6W 11L11
= I10I6
W 6L6
In the saturation region
|VGS10| |VT| = 2(I10)
K'P(W10/L10) = |VGS8| |VT|
Rz = 1
K’PS8
K’PS102I10
= 1S8
S10
2K’PI10
Equating the two expressions for Rz givesW 8L8
= Cc
CL + Cc
S10S6I6I10
Lecture 230 – Design of Two-Stage Op Amps (3/27/10) Page 230-25
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 230-2 - RHP Zero CompensationUse results of Ex. 230-1 and design compensation circuitry so that the RHP zero is
moved from the RHP to the LHP and placed on top of the output pole p2. Use devicedata given in Ex. 230-1.Solution
The task at hand is the design of transistors M8, M9, M10, M11, and bias currentI10. The first step in this design is to establish the bias components. In order to set VAequal to VB, then VSG11 must equal VSG6. Therefore,
S11 = (I11/I6)S6
Choose I11 = I10 = I9 = 15μA which gives S11 = (15μA/95μA)190 = 30.
The aspect ratio of M10 is essentially a freeparameter, and will be set equal to 1. There must besufficient supply voltage to support the sum of VSG11,VSG10, and VDS9. The ratio of I10/I5 determines the(W/L) of M9. This ratio is
(W/L)9 = (I10/I5)(W/L)5 = (15/30)(6) = 3
Now (W/L)8 is determined to be
(W/L)8 = 3pF
3pF+10pF 1·190·95μA
15μA = 8
Lecture 230 – Design of Two-Stage Op Amps (3/27/10) Page 230-26
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 230-2 - ContinuedIt is worthwhile to check that the RHP zero has been moved on top of p2. To do this, firstcalculate the value of Rz. VSG8 must first be determined. It is equal to VSG10, which is
VSG10 = 2I10
K’PS10 + |VTP| =
2·1525·1 + 0.5 = 1.595V
Next determine Rz.
Rz = 1
K’PS8(VSG10-|VTP|) = 106
25·8(1.595-.7) = 4.564k
The location of z1 is calculated as
z1 = -1
(4.564 x 103)(3x10-12) -
3x10-12
950x10-6
= -94.91x106 rads/sec
The output pole, p2, is
p2 = -950x10-6
10x10-12 = -95x106 rads/sec
Thus, we see that for all practical purposes, the output pole is canceled by the zerothat has been moved from the RHP to the LHP.
The results of this design are summarized below where L = 0.5μm. W 8 = 4μm W 9/L9 = 1.5μm W 10 = 0.5μm and W 11 = 15 μm
Lecture 230 – Design of Two-Stage Op Amps (3/27/10) Page 230-27
CMOS Analog Circuit Design © P.E. Allen - 2010
An Alternate Form of Nulling Resistor
To cancel p2,
z1 = p2 Rz =
Cc+C
L
gm6AC
C
= 1
gm6B
Which gives
gm6B = g
m6A
Cc
Cc+C
L
In the previous example,g
m6A = 950μS, Cc = 3pF
and CL = 10pF.
Choose I6B = 10μA to get
gm6B = gm6ACc
Cc + CL
2KPW 6BI6B
L6B =
Cc
Cc+CL
2KPW 6AID6
L6A
orW 6B
L6B =
313
2
I6A
I6B W 6A
L6A =
313
2 9510 (190) = 96.12 W6B = 48μm
-
+vin
M1 M2
M3 M4
M5
M6
M7
vou
VDD
VSS
VBias+
-
CcCL
M11 M10
M6B
M8 M9
Fig. 6.3-4A
Lecture 230 – Design of Two-Stage Op Amps (3/27/10) Page 230-28
CMOS Analog Circuit Design © P.E. Allen - 2010
Increasing the Magnitude of the Output Pole†
The magnitude of the output pole , p2, can be increased by introducing gain in the Millercapacitor feedback path. For example,
VDD
VSS
VBias
Cc
M6
M7
M8
M9M10
M12M11
vOUTIin R1 R2 C2
rds8
gm8Vs8
Cc
VoutV1
+
-
+
-
+
-Vs8
Iin R1 R2 C2gm8Vs8
VoutV1
+
-
+
-
+
-Vs8
1gm8
Cc
gm6V1
gm6V1
Cgd6
Cgd6
Fig. 6.2-15B
The resistors R1 and R2 are defined as
R1 = 1
gds2 + gds4 + gds9 and R2 =
1gds6 + gds7
where transistors M2 and M4 are the output transistors of the first stage.Nodal equations:
Iin = G1V1-gm8Vs8 = G1V1-gm8sCc
gm8 + sCc Vout and 0 = gm6V1+ G2+sC2+
gm8sCcgm8+sCc
Vout
† B.K. Ahuja, “An Improved Frequency Compensation Technique for CMOS Operational Amplifiers,” IEEE J. of Solid-State Circuits, Vol. SC-18,
No. 6 (Dec. 1983) pp. 629-633.
Lecture 230 – Design of Two-Stage Op Amps (3/27/10) Page 230-29
CMOS Analog Circuit Design © P.E. Allen - 2010
Increasing the Magnitude of the Output Pole - ContinuedSolving for the transfer function Vout/Iin gives,
VoutIin
= -gm6G1G2
1 +
sCcgm8
1 + sCc
gm8+
C2G2
+CcG2
+gm6CcG1G2
+ s2CcC2gm8G2
Using the approximate method of solving for the roots of the denominator gives
p1 = -1
Ccgm8
+CcG2
+C2G2
+gm6CcG1G2
-6
gm6rds2Cc
and p2 -gm6rds2Cc
6CcC2
gm8G2
= gm8rds2G2
6 gm6C2
= gm8rds
3 |p2’|
where all the various channel resistance have been assumed to equal rds and p2’ is theoutput pole for normal Miller compensation.Result: Dominant pole is approximately the same and the output pole is increased by gmrds.
Lecture 230 – Design of Two-Stage Op Amps (3/27/10) Page 230-30
CMOS Analog Circuit Design © P.E. Allen - 2010
Increasing the Magnitude of the Output Pole - ContinuedIn addition there is a LHP zero at -gm8/sCc and a RHP zero due to Cgd6 (shown dashedin the previous model) at gm6/Cgd6.
Roots are:
jω
σgm6Cgd6
-gm8Cc
-gm6gm8rds3C2
-1gm6rdsCc Fig. 6.2-16A
Concept:
Rout = rds7||3
gm6gm8rds8 3
gm6gm8rds8
Therefore, the output pole isapproximately,
|p2| gm6gm8rds8
3CII
VDD
Ccrds7
vout
M6 CII
GB·Cc
1 ≈ 0
VDD
vout
M6CII
M8
gm8rds8
Fig. Fig. 430-08
rds73
Lecture 230 – Design of Two-Stage Op Amps (3/27/10) Page 230-31
CMOS Analog Circuit Design © P.E. Allen - 2010
POWER SUPPLY REJECTION RATIO OF THE TWO-STAGE OP AMPWhat is PSRR?
PSRR = Av(Vdd=0)Add(Vin=0)
How do you calculate PSRR?You could calculate Av and Add and divide,however
+
- VDD
VSS
Vdd
Vout
V2
V1
V2
V1
Av(V1-V2)
±AddVddVss
Vout
Fig. 180-02
Vout = AddVdd + Av(V1-V2) = AddVdd - AvVout Vout(1+Av) = AddVdd
Vout
Vdd =
Add
1+Av
Add
Av =
1PSRR+
(Good for frequencies up to GB)
+
- VDD
VSS
Vdd
V2
V1Vss
VoutVin
Fig.180-01
Lecture 230 – Design of Two-Stage Op Amps (3/27/10) Page 230-32
CMOS Analog Circuit Design © P.E. Allen - 2010
Approximate Model for PSRR+
M1 M2
M3 M4
M5
M6
M7
Vout
VDD
VSS
VBias
Cc
CII
Vdd
CI
Fig. 180-05
Cc
Vdd Rout
Vout
Other sourcesof PSRR+ besides Cc
1RoutCc
ω
VoutVdd
0dB
1.) The M7 current sink causes VSG6 to act like a battery.
2.) Therefore, Vdd couples from the source to gate of M6.3.) The path to the output is through any capacitance from gate to drain of M6.Conclusion:
The Miller capacitor Cc couples the positive power supply ripple directly to the output.
Must reduce or eliminate Cc.
Lecture 230 – Design of Two-Stage Op Amps (3/27/10) Page 230-33
CMOS Analog Circuit Design © P.E. Allen - 2010
Approximate Model for PSRR-
What is Zout?
Zout = Vt
It It = gmIIV1 = gmII
gmIVt
GI+sCI+sCc
Thus, Zout = GI+s(CI+Cc)
gmIgMII
Vout
Vss =
1+rds7
Zout
1 = s(Cc+CI) + GI+gmIgmIIrds7
s(Cc+CI) + GIPole at
-GI
Cc+CI
The negative PSRR is much better than the positive PSRR.
M1 M2
M3 M4
M5
M6
M7
Vout
VDD
VSS
VBias
Cc
CII
Vss
CI
Fig. 180-11
VBias connected to VSS
rds7
vout
ZoutVss
rds7
Path through Cgd7is negligible
Fig.180-12
Vtrds6||rds7
VoutCI
Cc
+
-V1
+
-gmIVoutgmIIV1RI
CII+Cgd7It
Lecture 230 – Design of Two-Stage Op Amps (3/27/10) Page 230-34
CMOS Analog Circuit Design © P.E. Allen - 2010
SUMMARY• The output of the design of an op amp is
- Schematic- DC currents- W/L ratios- Component values
• Design procedures provide an organized approach to creating the dc currents, W/Lratios, and the component values
• The right-half plane zero causes the Miller compensation to deteriorate• Methods for eliminating the influence of the RHP zero are:
- Nulling resistor- Increasing the magnitude of the output pole
• The PSRR of the two-stage op amp is poor because of the Miller capacitance, however,methods exist to eliminate this problem
• The two-stage op amp is a very general and flexible op amp
Lecture 240 Cascode Op Amps (3/28/10) Page 240-1
CMOS Analog Circuit Design © P.E. Allen - 2010
LECTURE 240 – CASCODE OP AMPSLECTURE ORGANIZATION
Outline• Lecture Organization• Single Stage Cascode Op Amps• Two Stage Cascode Op Amps• SummaryCMOS Analog Circuit Design, 2nd Edition ReferencePages 293-310
Lecture 240 Cascode Op Amps (3/28/10) Page 240-2
CMOS Analog Circuit Design © P.E. Allen - 2010
Cascode Op AmpsWhy cascode op amps?
• Control of the frequency behavior• Can get more gain by increasing the output resistance of a stage• In the past section, PSRR of the two-stage op amp was insufficient for many
applications• A two-stage op amp can become unstable for large load capacitors (if nulling resistor
is not used)• The cascode op amp leads to wider ICMR and/or smaller power supply requirements
Where Should the Cascode Technique be Used?
• First stage -
Good noise performanceRequires level translation to second stageDegrades the Miller compensation
• Second stage -
Self compensatingIncreases the efficiency of the Miller compensation Increases PSRR
Lecture 240 Cascode Op Amps (3/28/10) Page 240-3
CMOS Analog Circuit Design © P.E. Allen - 2010
SINGLE STAGE CASCODE OP AMPSSimple Single Stage Cascode Op Amp
060627-01
-
+ vin
M1 M2
M3 M4
M5
vo1
VDD
VSS
VNBias1
+
-
VBias
2vin2
-
+
MC2MC1
MC4MC3
-
+ vin
M1 M2
M3 M4
M5
VDD
VSS
+
-
2vin2
-+
MC2MC1
MC4MC3
MB1 MB2
MB3 MB4
MB5
-
+
VBias
Implementation of the floating voltage VBiaswhich must equal2VON + VT.
VPBias2
VNBias1
VPBias2
Rout of the first stage is RI (gmC2rdsC2rds2)||(gmC4rdsC4rds4)
Voltage gain = vo1
vin = gm1RI [The gain is increased by approximately 0.5(gMCrdsC)]
As a single stage op amp, the compensation capacitor becomes the load capacitor.
Lecture 240 Cascode Op Amps (3/28/10) Page 240-4
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 240-1 Single-Stage, Cascode Op Amp PerformanceAssume that all W/L ratios are 10 μm/1 μm, and that IDS1 = IDS2 = 50 μA of single
stage op amp. Find the voltage gain of this op amp and the value of CI if GB = 10 MHz.Use KN’ = 120μA/V2, KP’ = 25μA/V2, VTN = 0.5V, VTP = -0.5V, N = 0.06V-1 and P =
0.08V-1.Solution
The device transconductances aregm1 = gm2 = gmI = 346.4 μS
gmC1 = gmC2 = 346.4μS
gmC3 = gmC4 = 158.1 μS.
The output resistance of the NMOS and PMOS devices is 0.333 M and 0.25 M ,respectively.
RI = 7.86 M
Av(0) = 2,722 V/V.
For a unity-gain bandwidth of 10 MHz, the value of CI is 5.51 pF.
What happens if a 100pF capacitor is attached to this op amp?GB goes from 10MHz to 0.551MHz.
Lecture 240 Cascode Op Amps (3/28/10) Page 240-5
CMOS Analog Circuit Design © P.E. Allen - 2010
060627-02
+
−vIN
vOUT
M1 M2
M3 M4
M5 M6
M7 M8
M9
VDD
VNB1
-A
-A-A
+
−vIN
vOUT
M1 M2
M3 M4
M5 M6
M7 M8
M9
VDD
VNB1 M10
VNB1
VDD VDDVPB1
M11 M12
M13 M14
M15
M16
Enhanced Gain, Single Stage, Cascode Op Amp
From inspection, we can write the voltage gain as,
Av = vOUTvIN
= gm1Rout where Rout = (Ards6gm6rds8)|| (Ards2gm4rds4)
Since A gmrds/2 the voltage gain would be equal to 100,000 to 500,000.
Output is not optimized for maximum signal swing.
Lecture 240 Cascode Op Amps (3/28/10) Page 240-6
CMOS Analog Circuit Design © P.E. Allen - 2010
TWO-STAGE, CASCODE OP AMPSTwo-Stage Op Amp with a Cascoded First-Stage
070427-01
Cc
-
+vin
M1 M2
M3 M4
M5
vo1
VDD
VSS
VBias+
-
R
2vin2-
+
MC2MC1
MC4MC3
MB1 MB2
MB3 MB4
MB5
-
+
VBias
MT1
MT2
M6
M7
vout
ID6
W6/L6
VSG6
= VSD4
VSG6 =
VSD4+VSDC4
W6’/L6’<< W6/L6
VT6
Current
Volts
• MT1 and MT2 are required for level shiftingfrom the first-stage to the second.
• The PSRR+ is improved by the presence of MT1• Internal loop pole at the gate of M6 may cause
the Miller compensation to fail.• The voltage gain of this op amp could easily be 100,000V/V
σ
jω
z1p1p2p3Fig. 6.5-2A
Lecture 240 Cascode Op Amps (3/28/10) Page 240-7
CMOS Analog Circuit Design © P.E. Allen - 2010
Two-Stage Op Amp with a Cascode Second-Stage
Av = gmIgmIIRIRIIwhere gmI = gm1 = gm2, gmII = gm6,
RI = 1
gds2 + gds4 =
2( 2 + 4)ID5
and
RII = (gmC6rdsC6rds6)||(gmC7rdsC7rds7)
Comments:• The second-stage gain has greatly
increased improving the Miller compensation
• The overall gain is approximately (gmrds)3 or very large
• Output pole, p2, is approximately the same if Cc is constant
• The zero RHP is the same if Cc is constant
• PSRR is poor unless the Miller compensation is removed (then the op amp becomesself compensated)
-
+
vin
M1 M2
M3 M4
M5
M6
M7
vout
VDD
VSS
VBias+
-
Cc
CL
VBP
VBN
MC6
MC7
Fig. 6.5-3
Rz
Lecture 240 Cascode Op Amps (3/28/10) Page 240-8
CMOS Analog Circuit Design © P.E. Allen - 2010
A Balanced, Two-Stage Op Amp using a Cascode Output Stage
vout = gm1gm8
gm3
vin2 +
gm2gm6
gm4
vin2 RII
= gm1
2 +gm2
2 kvin RII = gm1·k·RII vinwhereRII = (gm7rds7rds6)||(gm12rds12rds11)and
k = gm8gm3 =
gm6gm4
This op amp is balanced because thedrain-to-ground loads for M1 and M2 are identical.
TABLE 1 - Design Relationships for Balanced, Cascode Output Stage Op Amp.
Slew rate = Iout
CLGB =
gm1gm8
gm3CLAv =
12
gm1gm8
gm3
+g
m2gm6
gm4
RII
Vin(max) = VDD I5
3
1/2 |VTO3|(max) +VT1(min) Vin(min) = VS S + VDS5 +
I5
1
1/2 + VT1(min)
060627-03
-
+
vin
M1 M2
M3
M4
M5
M6
M11
vout
VDD
VSS
+
-
CL
M9
M10
M8
M12
M7VPB2
VNB2
VNB1
Lecture 240 Cascode Op Amps (3/28/10) Page 240-9
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 240-2 Design of Balanced, Cascoded Output Stage Op AmpDesign a balanced, cascoded output stage op amp using the procedure outlined
above. The specifications of the design are as follows:VDD = 2.5 V (VSS = 0) Slew rate = 5 V/μs with a 50 pF load
GB = 10 MHz with a 25 pF load Av 5000
Input CMR = 1V to +2 V 0.5V < Output swing < 2 V
Use KN’=120μA/V2, KP’= 25μA/V2, VTN = |VTP| = 0.5V, N = 0.06V-1, and P =
0.08V-1and let all device lengths be 0.5 μm.Solution
While numerous approaches can be taken, we shall follow one based on the abovespecifications. The steps will be numbered to help illustrate the procedure.1.) The first step will be to find the maximum source/sink current. This is found from theslew rate.
Isource/Isink = CL slew rate = 50 pF(5 V/μs) = 250 μA
2.) Next some W/L constraints based on the maximum output source/sink current aredeveloped. Under dynamic conditions, all of I5 will flow in M4; thus we can write
Max. Iout(source) = (S6/S4)I5 and Max. Iout(sink) = (S8/S3)I5
The maximum output sinking current is equal to the maximum output sourcing current ifS3 = S4, S6 = S8, and S10 = S11
Lecture 240 Cascode Op Amps (3/28/10) Page 240-10
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 240-2 - Continued3.) Choose I5 as 100 μA. This current (which can be changed later) gives
S6 = 2.5S4 and S8 = 2.5S3
Note that S8 could equal S3 if S11 = 2.5S10. This would minimize the power dissipation.
4.) Next design for +0.5V output capability. We shall assume that the output mustsource or sink the 250μA at the peak values of output. First consider the negative outputpeak. Since there is 0.5V difference between VSS(0V) and the minimum output, letVDS11(sat) = VDS12(sat) = 0.25 V (we continue to ignore the bulk effects). Under themaximum negative peak assume that I11 = I12 = 250 μA. Therefore
0.25 = 2I11
K'NS11 =
2I12K'NS12
= 500 μA
(120 μA/V2)S11
which gives S11 = S12 = 67 and S9 = S10 = 67. For a maximum output voltage of 2V, weget
0.25 = 2I6
K'PS6 =
2I7K'PS7
= 500 μA
(25 μA/V2)S6
which gives S6 = S7 = S8 = 320 and S3 = S4 = (320/2.5) = 128.
Lecture 240 Cascode Op Amps (3/28/10) Page 240-11
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 240-2 - Continued5.) Now we must consider the possibility of conflict among the specifications.
First consider the input CMR. S3 has already been designed as 67. Using ICMRrelationship, we find that S3 should be at least 8. A larger value of S3 will give a highervalue of Vin(max) so that we continue to use S3 = 67 which gives Vin(max) = 2.32V.
Next, check to see if the larger W/L causes a pole below the gainbandwidth.Assuming a Cox of 6fF/μm2 gives the first-stage pole of
p3 = -gm3
Cgs3+Cgs8 =
- 2K’PS3I3(0.667)(W3L3+W8L8)Cox
= 3.125x109 rads/sec or 497 MHz
which is much greater than 10GB.6.) Next we find gm1 (gm2). There are two ways of calculating gm1.
(a.) The first is from the Av specification. The gain is
Av = (gm1/2gm4)(gm6 + gm8) RII
Note, a current gain of k can be introduced by making S6/S4 (S8/S3 = S11/S3) equal to k.
gm6
gm4 =
gm11
gm3 =
2KP’·S6·I62KP’·S4·I4 = k
Calculating the various transconductances we get gm4 = 566 μS, gm6 = gm7 = gm8 = 1414μS, gm11 = gm12 = 1414 μS, rds6 = rd7 = 100 k , and rds11 = rds12 = 133 k . Assumingthat the gain Av must be greater than 5000 and k = 2.5 gives gm1 > 221 μS.
Lecture 240 Cascode Op Amps (3/28/10) Page 240-12
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 240-2 - Continued (b.) The second method of finding gm1 is from the GB specifications. Multiplying thegain by the dominant pole (1/CIIRII) gives
GB = gm1(gm6 + gm8)
2gm4CL
Assuming that CL= 25 pF and using the specified GB gives gm1 = 628 μS.
Since this is greater than 221μS, we choose gm1 = gm2 = 628μS. Knowing I5 gives S1 =S2 = 32.9 33.
8.) The next step is to check that S1 and S2 are large enough to meet the +1V input CMRspecification. Use the saturation formula we find that VDS5 is 0.341 V. This gives S5 = 15.The gain becomes Av = 14,182V/V and GB = 10 MHz for a 25 pF load. We shall assumethat exceeding the specifications in this area is not detrimental to the performance of theop amp.9.) Knowing the currents and W/L values, the bias voltages VNB1, VNB2 and VPB2 can bedesigned.The W/L values resulting from this design procedure are shown below. The powerdissipation for this design is seen to be 350μA·2.5V = 0.875 mW.
S1 = S2 = 33 S3 = S4 = 128 S5 = 15S6 = S7 = S
8 = 320 S9 = S10 = S11 = S12 = 67
Lecture 240 Cascode Op Amps (3/28/10) Page 240-13
CMOS Analog Circuit Design © P.E. Allen - 2010
Technological Implications of the Cascode Configuration
Fig. 6.5-5
�� ��������Poly IIPoly I
n+ n+n-channel
p substrate/well
A B C D
Thinoxide
A
B
C
D
If a double poly CMOS process is available, inter-node parasitics can be minimized.As an alternative, one should keep the drain/source between the transistors to a minimumarea.
Fig. 6.5-5A
�� �����Poly I
n+ n+n-channel
p substrate/well
A B C D
Thinoxide
A
B
C
D
Poly I
Minimum Polyseparation
����n-channeln+
Lecture 240 Cascode Op Amps (3/28/10) Page 240-14
CMOS Analog Circuit Design © P.E. Allen - 2010
Input Common Mode Range for Two Types of Differential Amplifier Loads
vicm
M1 M2
M3 M4
M5
VDD
VSS
VBias+
-
+
-
VSG3
M1 M2
M3 M4
M5
VDD
VSS
VBias+
-
+
-
VSD3
VBP
+
-
VSD4
+
-
VSD4
VDD-VSG3+VTN
VSS+VDS5+VGS1
InputCommon
ModeRange
vicm
VDD-VSD3+VTN
VSS+VDS5+VGS1
InputCommon
ModeRange
Differential amplifier witha current mirror load. Fig. 6.5-6
Differential amplifier withcurrent source loads.
In order to improve the ICMR, it is desirable to use current source (sink) loads withoutlosing half the gain.The resulting solution is the folded cascode op amp.
Lecture 240 Cascode Op Amps (3/28/10) Page 240-15
CMOS Analog Circuit Design © P.E. Allen - 2010
The Folded Cascode Op Amp
Comments:• I4 and I5, should be designed so that I6 and I7 never become zero (i.e. I4=I5=1.5I3)
• This amplifier is nearly balanced (would be exactly if RA was equal to RB)
• Self compensating• Poor noise performance, the gain occurs at the output so all intermediate transistors
contribute to the noise along with the input transistors. (Some first stage gain can beachieved if RA and RB are greater than gm1 or gm2.
060628-04
VPB1
M4 M5
RAI6
VPB2 RB
I4 I5
VDD
I7M6 M7
VNB2
M8 M9
M10 M11
+−
vIN
vOUT
VNB1
I1 I2
M1 M2
M3I3
CL
Lecture 240 Cascode Op Amps (3/28/10) Page 240-16
CMOS Analog Circuit Design © P.E. Allen - 2010
Small-Signal Analysis of the Folded Cascode Op AmpModel:
Recalling what welearned about theresistance looking intothe source of thecascode transistor;
RA = rds6+(1/gm10)1 + gm6rds6
1
gm6 and RB =
rds7 + RII1 + gm7rds7
RII
gm7rds7 where RII gm9rds9rds11
The voltage transfer function can be found as follows. The current i10 is written as
i10 = -gm1(rds1||rds4)vin2[RA + (rds1||rds4)]
-gm1vin2
and the current i7 can be expressed as
i7 = gm2(rds2||rds5)vin
2RII
gm7rds7+ (rds2||rds5)
= gm2vin
2 1 +RII(gds2+gds5)
gm7rds7
= gm2vin2(1+k) where k =
RII(gds2+gds5)gm7rds7
The output voltage, vout, is equal to the sum of i7 and i10 flowing through Rout. Thus,voutvin
= gm12 +
gm22(1+k) Rout =
2+k2+2k gmIRout
060628-02
gm1vin2 rds1 rds4
rds6
gm6vgs6RA
gm2vin2 rds2 rds5
rds7
gm7vgs7
RII
RB
i10
i10+
-vgs7
+
-vgs6
+
-vout
i7
1gm10
Lecture 240 Cascode Op Amps (3/28/10) Page 240-17
CMOS Analog Circuit Design © P.E. Allen - 2010
Intuitive Analysis of the Folded Cascode Op AmpAssume that a voltage of V is applied. Weknow that
RA(M6) 1/gm6 and RB(M7) rds
The currents flowing to the output are,gm1 V
2 + gm2 V
4The output resistance is approximately,
Rout (gm9rds9rds11)||[ gm7rds7(rds2||rds5)]
gmrds2
3
Therefore, the approximate voltage gain is,
voutvin
= gm1
2 +gm24 Rout
3gm4 Rout =
gm2rds2
4
While the analysis is simpler than small signal analysis, the value of k defined in theprevious slide is 1.
Lecture 240 Cascode Op Amps (3/28/10) Page 240-18
CMOS Analog Circuit Design © P.E. Allen - 2010
Frequency Response of the Folded Cascode Op AmpThe frequency response of the folded cascode op amp is determined primarily by theoutput pole which is given as
pout = -1
Rout'Coutwhere Rout’ =
2+k2+2k Rout
where Cout is all the capacitance connected from the output of the op amp to ground.
All other poles must be greater than GB = gm1/Cout. The approximate expressions foreach pole is1.) Pole at node A: pA - gm6/(Cgs+ 2Cdb)
2.) Pole at node B: pB - gm7/(Cgs+ 2Cdb)
3.) Pole at drain of M6: p6 -gm10/(2Cgs+ 2Cdb)
4.) Pole at source of M8: p8 -(gm8rds8gm10)/(Cgs+ Cdb)
5.) Pole at source of M9: p9 -gm9/(Cgs+ Cdb)
where the approximate expressions are found by the reciprocal product of the resistanceand parasitic capacitance seen to ground from a given node. One might feel that becauseRB is approximately rds that this pole also might be small. However, at frequencieswhere this pole has influence, Cout, causes Rout to be much smaller making pB also non-dominant.
Lecture 240 Cascode Op Amps (3/28/10) Page 240-19
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 240-3 - Folded Cascode, CMOS Op AmpAssume that all gmN = gmP = 100μS, rdsN = 2M , rdsP = 1M , and CL = 10pF. Find allof the small-signal performance values for the folded-cascode op amp.
RII = 0.4G , RA = 10k , and RB = 4M k = 0.4x109(0.3x10-6)
100 = 1.2
voutvin
= 2+1.22+2.4 (100)(57.143) = 4,156V/V
Rout = RII ||[gm7rds7(rds5||rds2)] = 400M ||[(100)(0.667M )] = 57.143M
|pout| = 1
RoutCout =
157.143M ·10pF = 1,750 rads/sec. 278Hz GB = 1.21MHz
Lecture 240 Cascode Op Amps (3/28/10) Page 240-20
CMOS Analog Circuit Design © P.E. Allen - 2010
PSRR of the Folded Cascode Op Amp
Consider the following circuit used to model the PSRR-:
Vout
Vss
Cgd11
M11
M9
VDD
R
Fig. 6.5-9A
Vss Vout
Cgd9
Rout
+
-
Cgd9
VGS11
VGSG9
Vss
Vss
Vss
rds11
Cout
rds9
This model assumes that gate, source and drain of M11 and the gate and source of M9 allvary with VSS.
We shall examine Vout/Vss rather than PSRR-. (Small Vout/Vss will lead to large PSRR-.)
The transfer function of Vout/Vss can be found as
VoutVss
sCgd9Rout
sCoutRout+1 for Cgd9 < Cout
The approximate PSRR- is sketched on the next page.
Lecture 240 Cascode Op Amps (3/28/10) Page 240-21
CMOS Analog Circuit Design © P.E. Allen - 2010
Frequency Response of the PSRR- of the Folded Cascode Op Amp
VoutVss
GB
Cgd9Rout
|PSRR-|
dB
0dB
Fig. 6.5-10A
log10(ω)
1
Cout
Cgd9
Other sources of Vss injection, i.e. rds9
Dominantpole frequency
|Avd(ω)|
We see that the PSRR of the cascode op amp is much better than the two-stage op ampwithout any modifications to improve the PSRR.
Lecture 240 Cascode Op Amps (3/28/10) Page 240-22
CMOS Analog Circuit Design © P.E. Allen - 2010
Design Approach for the Folded-Cascode Op Amp
Step Relationship Design Equation/Constraint Comments1 Slew Rate I3 = SR·CL2 Bias currents in
output cascodesI4 = I5 = 1.2I3 to 1.5I3 Avoid zero current in
cascodes3 Maximum output
voltage,vout(max)
S5=2I5
KP’VSD52 , S7=2I7
KP’VSD72 , (S4=S5 and S6= S7)VSD5(sat)=VSD7(sat)= 0.5[VDD-Vout(max)]
4 Minimum outputvoltage, vout(min) S11=
2I11KN’VDS112 , S9=
2I9KN’VDS92 , (S10=S11and S8=S9)
VDS9(sat)=VDS11(sat)= 0.5[Vout(min)-VSS]
5GB =
gm1CL
S1=S2= gm12
KN’I3 =
GB2CL2
KN’I3
6 Minimum inputCM S3 =
2I3
KN’ Vin(min)-VSS- (I3/KN’S1) -VT12
7 Maximum inputCM S4 = S5 =
2I4KP’ VDD-Vin(max)+VT1
2 S4 and S5 must meet orexceed value in step 3
8 DifferentialVoltage Gain
voutvin
= gm1
2 +gm2
2(1+k) Rout = 2+k
2+2k gmIRout k = RII(gds2+gds4)
gm7rds79 Power dissipation Pdiss = (VDD-VSS)(I3+I10+I11)
Lecture 240 Cascode Op Amps (3/28/10) Page 240-23
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 240-4 Design of a Folded-Cascode Op AmpDesign a folded-cascode op amp if the slew rate is 10V/μs, the load capacitor is 10pF, themaximum and minimum output voltages are 2V and 0.5V for a 2.5V power supply, theGB is 10MHz, the minimum input common mode voltage is +1V and the maximum inputcommon mode voltage is 2.5V. The differential voltage gain should be greater than3,000V/V and the power dissipation should be less than 5mW. Use KN’=120μA/V2,
KP’= 25μA/V2, VTN = |VTP| = 0.5V, N = 0.06V-1, and P = 0.08V-1. Let L = 0.5 μm.
SolutionFollowing the approach outlined above we obtain the following results.
I3 = SR·CL = 10x106·10-11 = 100μA
Select I4 = I5 = 125μA.
Next, we see that the value of 0.5(VDD-Vout(max)) is 0.5V/2 or 0.25V. Thus,
S4 = S5 = 2·125μA
25μA/V2·(0.25V)2 = 2·125·16
25 = 160
and assuming worst case currents in M6 and M7 gives,
S6 = S7 = 2·125μA
25μA/V2(0.25V)2 = 2·125·16
25 = 160 The value of 0.5(Vout(min)-|VSS|) is 0.25V which gives the value of S8, S9, S10 and S11 as
S8 = S9 = S10 = S11 = 2·I8
KN’VDS82 = 2·125
120·(0.25)2 = 20
Lecture 240 Cascode Op Amps (3/28/10) Page 240-24
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 240-4 - ContinuedIn step 5, the value of GB gives S1 and S2 as
S1 = S2 = GB2·CL2
KN’I3 =
(20 x106)2(10-11)2
120x10-6·100x10-6 = 32.9 33
The minimum input common mode voltage defines S3 as
S3 = 2I3
KN’ Vin(min)-VSS-I3
KN’S1- VT1
2 =
200x10-6
120x10-6 1.0+0-100
120·33 -0.5 2 = 14.3 15
We need to check that the values of S4 and S5 are large enough to satisfy the maximuminput common mode voltage. The maximum input common mode voltage of 2.5 requires
S4 = S5 2I4
KP’[VDD-Vin(max)+VT1]2 = 2·125μA
25x10-6μA/V2[0.5V]2 = 40
which is less than 160. In fact, with S4 = S5 = 160, the maximum input common modevoltage is 2.75V.The power dissipation is found to be
Pdiss = 2.5V(125μA+125μA) = 0.625mW
Lecture 240 Cascode Op Amps (3/28/10) Page 240-25
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 240-4 - ContinuedThe small-signal voltage gain requires the following values to evaluate:
S4, S5: gm = 2·125·25·160 = 1000μS and gds = 125x10-6·0.08 = 10μS
S6, S7: gm = 2·75·25·1600 = 774.6μS and gds = 75x10-6·0.08 = 6μS
S8, S9, S10, S11: gm = 2·75·120·20 = 600μS and gds = 75x10-6·0.06 = 4.5μS
S1, S2: gmI = 2·50·120·33 = 629μS and gds = 50x10-6(0.06) = 3μS
Thus,
RII gm9rds9rds11 = (600μS)1
4.5μS1
4.5μS = 29.63M
Rout 29.63M ||(774.6μS)1
6μS1
10μS+3μS = 7.44M
k = RII(gds2+gds4)
gm7rds7 =
7.44M (3μS+10μS)(6μS)774.6μS = 0.75
The small-signal, differential-input, voltage gain is
Avd = 2+k
2+2k gmIRout = 2+0.752+1.5 0.629x10-3·7.44x106 = (0.786)(4680) = 3,678 V/V
The gain is slightly larger than the specified 3,000 V/V.
Lecture 240 Cascode Op Amps (3/28/10) Page 240-26
CMOS Analog Circuit Design © P.E. Allen - 2010
Comments on Folded Cascode Op Amps• Good PSRR• Good ICMR• Self compensated• Can cascade an output stage to get extremely high gain with lower output resistance
(use Miller compensation in this case)• Need first stage gain for good noise performance• Widely used in telecommunication circuits where large dynamic range is required
Lecture 240 Cascode Op Amps (3/28/10) Page 240-27
CMOS Analog Circuit Design © P.E. Allen - 2010
Enhanced-Gain, Folded Cascode Op AmpsIf more gain is needed, the folded cascode opamp can be enhanced to boost the outputimpedance even higher as follows.
Voltage gain = gm1Rout,
whereRout [Ards7gm7(rds1||rds5)]||
(Ards9gm9rds11)
Since A gmrds the voltage gain would be in the range of 100,000 to 500,000.
Note that to achieve maximum output swing, it will be necessary to make sure that M5and M11 are biased with VDS = VDS(sat).
060718-03
vOUT
M4M5
M3
M7
M8 M9
M10 M11
M6
VDD
VPB1
-A
-A-A
+
−vIN
M1 M2
VNB1
Lecture 240 Cascode Op Amps (3/28/10) Page 240-28
CMOS Analog Circuit Design © P.E. Allen - 2010
What are the Enhancement Amplifiers?Requirements:1.) Need a gain of gmrds.
2.) Must be able to set the dc voltage at its input to get wide-output voltage swing.Possible Enhancement Amplifiers:
060718-05
VDD
VPB1
VPB2
VNB1VDD-VSD(Sat)
vin
vout
M1 M2
M3
M4
M5
M6
-A
vin
vout
VDD
VPB1
VNB2
VNB1
vin
vout
VDS(Sat)M1 M2
M3
M4
M5
M6
vout
-A
vin
Lecture 240 Cascode Op Amps (3/28/10) Page 240-29
CMOS Analog Circuit Design © P.E. Allen - 2010
Enhanced-Gain, Folded Cascode Op AmpDetailed realization:
Lecture 240 Cascode Op Amps (3/28/10) Page 240-30
CMOS Analog Circuit Design © P.E. Allen - 2010
Frequency Response of the Enhanced Gain Cascode Op AmpsNormally, the frequency response of the cascode op amps would have one dominant poleat the output. The frequency response would be,
Av(s) = gm1Rout(1/sCout)Rout +1/sCout
= gm1Rout
sRoutCout +1 = gm1Rout
1 -sp1
If the amplifier used to boost the output resistance had no frequency dependence then thefrequency response would be as follows.
060629-02
0dB
40dB
60dB
80dB
100dBEnhanced Gain Cascode Op Amp
Normal CascodeOp Amp
|p1(enh)| GBlog10ω
Gain (db)
|p1|
Lecture 240 Cascode Op Amps (3/28/10) Page 240-31
CMOS Analog Circuit Design © P.E. Allen - 2010
Frequency Response of the Enhanced Gain Cascode Op Amp – Continued• Does the pole in the feedback amplifier A have an influence?
Although the output resistance can be modeled as,
Rout’ RoutAo
1-s
p2Ao
1-s
p2
it has no influence on the frequency response because Cout has shorted out anyinfluence a change in Rout might have.
• Higher order poles come from a diversion of the current flow in the op amp to groundrather than the intended destination of the current to the output. These poles thatdivert the current are:
- Pole at the source of M6 (Agm6/C6) - Pole at the source of M7 (Agm7/C7)
- Pole at the drain of M8 (gm10/C8) - Pole at the source of M9 (Agm9/C6)
- Pole at the drain of M10 (gm8rds8gm10/C10)
Note that the enhancement amplifiers cause most of the higher-order poles to be movedout by |A|. However, each of the enhancement amplifiers introduce a pole at their outputwhich is approximately -1/[rds(Cgs+2Cdb+2Cgd)]. These poles become the dominantpoles that limit GB.
Lecture 240 Cascode Op Amps (3/28/10) Page 240-32
CMOS Analog Circuit Design © P.E. Allen - 2010
SUMMARY• Cascode op amps give additional flexibility to the two-stage op amp
- Increase the gain- Control the dominant and nondominant poles
• Enhanced gain, cascode amplifiers provide additional gain and are used when highgains are needed
• Folded cascode amplifier is an attractive alternate to the two-stage op amp- Wider ICMR- Self compensating- Good PSRR
Lecture 250 – Measurement and Simulation of Op amps (3/28/10) Page 250-1
CMOS Analog Circuit Design © P.E. Allen - 2010
LECTURE 250 – SIMULATION AND MEASUREMENT OF OPAMPS
LECTURE ORGANIZATIONOutline• Introduction• Open Loop Gain• CMRR and PSRR• A general method of measuring Avd, CMRR, and PSRR
• Other op amp measurements• Simulation of a Two-Stage Op Amp• Op amp macromodels• SummaryCMOS Analog Circuit Design, 2nd Edition ReferencePages 310-341
Lecture 250 – Measurement and Simulation of Op amps (3/28/10) Page 250-2
CMOS Analog Circuit Design © P.E. Allen - 2010
INTRODUCTIONSimulation and Measurement ConsiderationsObjectives:• The objective of simulation is to verify and optimize the design.• The objective of measurement is to experimentally confirm the specifications.Similarity between Simulation and Measurement:• Same goals• Same approach or techniqueDifferences between Simulation and Measurement:• Simulation can idealize a circuit
- All transistor electrical parameters are ideally matched- Ideal stimuli
• Measurement must consider all nonidealities- Physical and electrical parameter mismatches- Nonideal stimuli- Parasistics
Lecture 250 – Measurement and Simulation of Op amps (3/28/10) Page 250-3
CMOS Analog Circuit Design © P.E. Allen - 2010
OPEN LOOP GAINSimulating or Measuring the Open-Loop Transfer Function of the Op AmpCircuit (Darkened op amp identifies the op amp under test):
Simulation:This circuit will give the voltage transferfunction curve. This curve should identify:
1.) The linear range of operation2.) The gain in the linear range3.) The output limits4.) The systematic input offset voltage5.) DC operating conditions, power dissipation6.) When biased in the linear range, the small-signal frequency response can be
obtained7.) From the open-loop frequency response, the phase margin can be obtained (F = 1)
Measurement:This circuit probably will not work unless the op amp gain is very low.
Fig. 240-01
+ -VOSvIN
vOUTVDD
VSSRLCL
Lecture 250 – Measurement and Simulation of Op amps (3/28/10) Page 250-4
CMOS Analog Circuit Design © P.E. Allen - 2010
A More Robust Method of Measuring the Open-Loop Frequency ResponseCircuit:
vIN vOUT
VDD
VSSRLCLRC
Fig. 240-02Resulting Closed-Loop Frequency Response:
dB
log10(w)
Av(0)
1RC RC
Av(0)
Op AmpOpen LoopFrequencyResponse
Fig. 240-03
0dB
Make the RC product as large as possible.
Lecture 250 – Measurement and Simulation of Op amps (3/28/10) Page 250-5
CMOS Analog Circuit Design © P.E. Allen - 2010
CMRR AND PSRRSimulation of the Common-Mode Voltage Gain
VOSvout
VDD
VSSRLCL
+ -
vcm
+
-
Fig. 6.6-5
Make sure that the output voltage of the op amp is in the linear region.Divide (subtract dB) the result into the open-loop gain to get CMRR.
Lecture 250 – Measurement and Simulation of Op amps (3/28/10) Page 250-6
CMOS Analog Circuit Design © P.E. Allen - 2010
Simulation of CMRR of an Op AmpNone of the above methods are really suitable for simulation of CMRR.Consider the following:
VDD
VSS
Vcm
Vout
V2
V1
V2
V1
Av(V1-V2)
±AcVcmVcm
Vout
Vcm
Vcm
+
-
Fig. 6.6-7
Vout
= Av(V1-V2) ±A
cm
V1+V2
2 = -AvVout ± AcmVcm
Vout
= ±A
cm
1+Av
Vcm
±Acm
Av
Vcm
|CMRR| =A
v
Acm
=V
cm
Vout
Lecture 250 – Measurement and Simulation of Op amps (3/28/10) Page 250-7
CMOS Analog Circuit Design © P.E. Allen - 2010
Direct Simulation of PSRRCircuit:
VDD
VSS
Vdd
Vout
V2
V1
V2
V1
Av(V1-V2)
±AddVddVss
Vss = 0
Fig. 6.6-9
+
-
Vout
= Av(V1-V2) ±A
ddV
dd = -AvVout ± AddVdd
Vout
= ±A
dd
1+Av
Vdd
±Add
Av
Vdd
PSRR+ =A
v
Add
=V
dd
Vout
and PSRR- =A
v
Ass
=V
ss
Vout
Works well as long as CMRR is much greater than 1.
Lecture 250 – Measurement and Simulation of Op amps (3/28/10) Page 250-8
CMOS Analog Circuit Design © P.E. Allen - 2010
A GENERAL METHOD OF MEASURING AVD, CMRR, AND PSRR
General Principle of the MeasurementCircuit:
vOS
vOUTVDD
VSSRLCL
+
-
100kΩ
100kΩ
10kΩ
10Ω
vSET
vI
070429-01"Op Amp"
+-
vSET
vOUT = -vSET
100kΩ 100kΩ
"Op Amp"
The amplifier under test is shown as the darkened op amp.Principle:
Apply the stimulus to the output of the op amp under test and see how the inputresponds. Note that:
vOUT = - vSET and vI vOS1000
Lecture 250 – Measurement and Simulation of Op amps (3/28/10) Page 250-9
CMOS Analog Circuit Design © P.E. Allen - 2010
Measurement of Open-Loop GainMeasurement configuration:
Avd = VoutVid
= VoutVi
Vos 1000Vi
Therefore, Avd = 1000Vout
Vos
Sweep Vout as a function of frequency, invert the result and multiply by 1000 to getAvd (j ).
060701-01
Vos
VDD
VSSRLCL
+
-
+- 100kΩ
100kΩ
10kΩ
10Ω
Vout
Vi
Vout
Lecture 250 – Measurement and Simulation of Op amps (3/28/10) Page 250-10
CMOS Analog Circuit Design © P.E. Allen - 2010
Measurement of CMRRMeasurement Configuration:Note that the whole amplifier is stimulated byVicm while the input responds to this change.
The definition of the common-mode rejectionratio is
CMRR = Avd
Acm =
(vout/vid)(vout/vicm)
However, in the above circuit the value of vout
is the same so that we get
CMRR = vicm
vid
But vid = vi and vos 1000vi = 1000vid vid = vos
1000
Substituting in the previous expression gives, CMRR = vicm
vos
1000
= 1000 vicm
vos
Make a frequency sweep of Vicm, invert the result and multiply by 1000 to get CMRR.
vos
vOUTVDD
VSSRLCL
+
-
+- 100kΩ
100kΩ
10kΩ
10Ω
vicm
vi
Fig. 240-08
vicm
Lecture 250 – Measurement and Simulation of Op amps (3/28/10) Page 250-11
CMOS Analog Circuit Design © P.E. Allen - 2010
Measurement of PSRRMeasurement Configuration:The definition of the positive power supply rejectionratio is
PSRR+ = Avd
Acm =
(Vout/Vid)(Vout/Vdd)
However, in the above circuit the value of Vout is thesame so that we get
PSRR+ = Vdd
Vid
But Vid = Vi and Vos 1000Vi = 1000Vid Vid =Vos
1000
Substituting in the previous expression gives, PSRR+ = Vdd
Vos
1000
= 1000 Vdd
Vos
Make a frequency sweep of Vdd, invert the result and multiply by 1000 to get PSRR+.
(Same procedure holds for PSRR-.)
Vos
VoutVDD
VSSRLCL
+
-
100kΩ
100kΩ
10kΩ
10Ω
Vdd
Vi
070429-02
Vss
Lecture 250 – Measurement and Simulation of Op amps (3/28/10) Page 250-12
CMOS Analog Circuit Design © P.E. Allen - 2010
OTHER OP AMP MEASUREMENTSSimulation or Measurement of ICMR
vIN
vOUTVDD
VSSRLCL
+
-
Fig.240-11
ICMR
IDD
vOUT
vIN
1
1
Also, monitor IDD or ISS.
ISS
Initial jump in sweep is due to the turn-on of M5.Should also plot the current in the input stage (or the power supply current).
Lecture 250 – Measurement and Simulation of Op amps (3/28/10) Page 250-13
CMOS Analog Circuit Design © P.E. Allen - 2010
Measurement or Simulation of Slew Rate and Settling Time
vin
voutVDD
VSSRLCL
+
-
IDD Settling ErrorTolerance
1
+SR
1
-SR
Peak Overshoot
Feedthrough
vin
vout
Settling Time
Volts
t
Fig. 240-14
If the slew rate influences the small signal response, then make the input step size smallenough to avoid slew rate (i.e. less than 0.5V for MOS).
Lecture 250 – Measurement and Simulation of Op amps (3/28/10) Page 250-14
CMOS Analog Circuit Design © P.E. Allen - 2010
Phase Margin and Peak Overshoot RelationshipIt can be shown (Appendix C of the text) that:
Phase Margin (Degrees) = 57.2958cos-1[ 4 4+1 - 2 2] Overshoot (%)
= 100 exp-
1- 2
For example, a 5% overshootcorresponds to a phase margin ofapproximately 64°.
0
10
20
30
40
50
60
70
80
Phas
e M
argi
n (D
egre
es)
1.0
10
0 0.2 0.4 0.6 0.8 1
Ove
rsho
ot (
%)
Phase Margin Overshoot
100
0.1
ζ= 12Q
070429-03
20
5
Lecture 250 – Measurement and Simulation of Op amps (3/28/10) Page 250-15
CMOS Analog Circuit Design © P.E. Allen - 2010
SIMULATION OF A TWO-STAGE CMOS OP AMPExample 250-1 Simulation of a Two-Stage CMOS Op Amp
An op amp designed using the procedure described in Lecture 230 is to be simulatedby SPICE. The device parameters to be used are those of Tables 3.1-2 and 3.2-1 of thetextbook CMOS Analog Circuit Design.
-
+
vin
M1 M2
M3 M4
M5
M6
M7
vout
VDD = 2.5V
VSS = -2.5V
Cc = 3pF
CL =10pF
3μm1μm
3μm1μm
15μm1μm
15μm1μm
M84.5μm1μm
30μA
4.5μm1μm
14μm1μm
94μm1μm
30μA
95μA
Fig. 240-16
The specifications of this op amp are as follows where the channel length is to be 1μmand the load capacitor is CL = 10pF:
Av > 3000V/V VDD = 2.5V VSS = -2.5VGB = 5MHz SR > 10V/μs 60° phase marginVout range = ±2V ICMR = -1 to 2V Pdiss 2mW
Lecture 250 – Measurement and Simulation of Op amps (3/28/10) Page 250-16
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 250-1 – ContinuedBulk Capacitance Calculation:
If the values of the area and perimeter of the drain and source of each transistor areknown, then the simulator will calculate the values of CBD and CBs. Since there is nolayout yet, we estimate the values of the area and perimeter of the drain and source ofeach transistor as:
AS = AD W[L1 + L2 + L3]PS = PD 2W + 2[L1 + L2 + L3]
where L1 is the minimum allowable distance between the polysilicon and a contact in themoat (2μm), L2 is the length of a minimum-size square contact to moat (2μm), and L3 isthe minimum allowable distance between a contact to moat and the edge of the moat(2μm). (These values will be found from the physical design rules for the technology).
For example consider M1:
AS = AD = (3μm)x(2μm+2μm+2μm) = 18μm2
PS = PD = 2x3μm + 2x6μm = 19μm
Lecture 250 – Measurement and Simulation of Op amps (3/28/10) Page 250-17
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 250-1 - ContinuedOp Amp Subcircuit:
-
+vin vout
VDD
VSS
+
-6
2
1
8
9 Fig. 240-17
.SUBCKT OPAMP 1 2 6 8 9
M1 4 2 3 3 NMOS1 W=3U L=1U AD=18P AS=18P PD=18U PS=18U
M2 5 1 3 3 NMOS1 W=3U L=1U AD=18P AS=18P PD=18U PS=18U
M3 4 4 8 8 PMOS1 W=15U L=1U AD=90P AS=90P PD=42U PS=42U
M4 5 4 8 8 PMOS1 W=15U L=1U AD=90P AS=90P PD=42U PS=42U
M5 3 7 9 9 NMOS1 W=4.5U L=1U AD=27P AS=27P PD=21U PS=21U
M6 6 5 8 8 PMOS1 W=94U L=1U AD=564P AS=564P PD=200U PS=200U
M7 6 7 9 9 NMOS1 W=14U L=1U AD=84P AS=84P PD=40U PS=40U
M8 7 7 9 9 NMOS1 W=4.5U L=1U AD=27P AS=27P PD=21U PS=21U
CC 5 6 3.0P
.MODEL NMOS1 NMOS VTO=0.70 KP=110U GAMMA=0.4 LAMBDA=0.04 PHI=0.7
+MJ=0.5 MJSW=0.38 CGBO=700P CGSO=220P CGDO=220P CJ=770U CJSW=380P
+LD=0.016U TOX=14N
.MODEL PMOS1 PMOS VTO=-0.7 KP=50U GAMMA=0..57 LAMBDA=0.05 PHI=0.8
+MJ=0.5 MJSW=.35 CGBO=700P CGSO=220P CGDO=220P CJ=560U CJSW=350P +LD=0.014U TOX=14N
IBIAS 8 7 30U
.ENDS
Lecture 250 – Measurement and Simulation of Op amps (3/28/10) Page 250-18
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 250-1 - ContinuedPSPICE Input File for the Open-Loop Configuration:
EXAMPLE 250-1 OPEN LOOP CONFIGURATION
.OPTION LIMPTS=1000
VIN+ 1 0 DC 0 AC 1.0
VDD 4 0 DC 2.5
VSS 0 5 DC 2.5
VIN - 2 0 DC 0
CL 3 0 10P
X1 1 2 3 4 5 OPAMP...
(Subcircuit of previous slide)...
.OP
.TF V(3) VIN+
.DC VIN+ -0.005 0.005 100U
.PRINT DC V(3)
.AC DEC 10 1 10MEG
.PRINT AC VDB(3) VP(3)
.PROBE (This entry is unique to PSPICE)
.END
Lecture 250 – Measurement and Simulation of Op amps (3/28/10) Page 250-19
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 250-1 - ContinuedOpen-loop transfer characteristic:
-2
-1
0
1
2
-2 -1.5 -1.0 -0.5 0 0.5 1 1.5 2
v OU
T(V
)
vIN(mV)
2.5
-2.5
VOS
Fig. 240-18
Lecture 250 – Measurement and Simulation of Op amps (3/28/10) Page 250-20
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 250-1 - ContinuedOpen-loop transfer frequency response:
-40
-20
0
20
40
60
80
10 100 1000 104 105 106 107 108
Mag
nitu
de (
dB)
Frequency (Hz)
GB-200
-150
-100
-50
0
50
100
150
200
10 100 1000 104 105 106 107 108
Phas
e Sh
ift (
Deg
rees
)
Frequency (Hz)
GBPhase Margin
Fig. 6.6-16
Lecture 250 – Measurement and Simulation of Op amps (3/28/10) Page 250-21
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 250-1 - ContinuedInput common mode range:
EXAMPLE 250-1 UNITY GAIN CONFIGURATION.
.OPTION LIMPTS=501
VIN+ 1 0 PWL(0 -2 10N -2 20N 2 2U 2 2.01U -2 4U -2 4.01U
+ -.1 6U -.1 6.0 1U .1 8U .1 8.01U -.1 10U -.1)
VDD 4 0 DC 2.5 AC 1.0
VSS 0 5 DC 2.5
CL 3 0 20P
X1 1 3 3 4 5 OPAMP...
(Subcircuit of Table 6.6-1)...
.DC VIN+ -2.5 2.5 0.1
.PRINT DC V(3)
.TRAN 0.05U 10U 0 10N
.PRINT TRAN V(3) V(1)
.AC DEC 10 1 10MEG
.PRINT AC VDB(3) VP(3)
.PROBE (This entry is unique to PSPICE)
.END
Note the usefulness of monitoring thecurrent in the input stage to determinethe lower limit of the ICMR.
vin
vout
VDD
VSS
+
-3
3
1
4
5
Fig. 6.6-16A
Subckt.
-3
-2
-1
0
1
2
3
4
-3 -2 -1 0 1 2 3vO
UT
(V)
vIN(V)
ID(M5)
0
10
20
30
40
ID(M
5) μ
A
Input CMR
Fig. 240-21
Lecture 250 – Measurement and Simulation of Op amps (3/28/10) Page 250-22
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 250-1 - ContinuedPositive PSRR:
-20
0
20
40
60
80
10 100 1000 104 105 106 107 108
|PSR
R+(jω
)| dB
Frequency (Hz)
-100
-50
0
50
100
10 100 1000 104 105 106 107 10
Arg
[PSR
R+(jω
)] (
Deg
rees
)
Frequency (Hz)
100
Fig. 240-22
This PSRR+ is poor because of the Miller capacitor. The degree of PSRR+ deteriorationwill be better shown when compared with the PSRR-.
Lecture 250 – Measurement and Simulation of Op amps (3/28/10) Page 250-23
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 250-1 - ContinuedNegative PSRR:
10 100 1000 104 105 106 107 108
|PSR
R- (
jω)|
dB
Frequency (Hz)
-200
-150
-100
-50
0
50
100
150
200
10 100 1000 104 105 106 107 108
Arg
[PSR
R- (
jω)]
(D
egre
es)
Frequency (Hz)
20
40
60
80
100
120
Fig. 240-23
PSRR+
Lecture 250 – Measurement and Simulation of Op amps (3/28/10) Page 250-24
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 250-1 - ContinuedLarge-signal and small-signal transient response:
-1.5
-1
-0.5
0
0.5
1
1.5
0 1 2 3 4 5
Vol
ts
Time (Microseconds)
-0.15
-0.1
-0.05
0
0.05
0.1
0.15
2.5 3.0 3.5 4.0 4.5
Vol
ts
Time (Microseconds)
vin(t)
vout(t)
vin(t)
vout(t)
Fig. 240-24
M6
M7
vout
VDD
VSS
VBias-
Cc
CL
+
95μA
iCc iCL dvoutdt
Fig. 240-25
Why the negative overshoot on the slew rate?If M7 cannot sink sufficient current then the output stage
slews and only responds to changes at the output via thefeedback path which involves a delay.
Note that -dvout/dt -2V/0.3μs = -6.67V/μs. For a10pF capacitor this requires 66.7μA and only 95μA-66.7μA= 28μA is available for Cc. For the positive slew rate, M6can provide whatever current is required by the capacitorsand can immediately respond to changes at the output.
Lecture 250 – Measurement and Simulation of Op amps (3/28/10) Page 250-25
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 250-1 - ContinuedComparison of the Simulation Results with the Specifications of Example 250-1:
Specification(Power supply = ±2.5V)
Design Simulation
Open Loop Gain >5000 10,000GB (MHz) 5 MHz 5 MHzInput CMR (Volts) -1V to 2V -1.2 V to 2.4 V,Slew Rate (V/μsec) >10 (V/μsec) +10, -7(V/μsec)Pdiss (mW) < 2mW 0.625mW
Vout range (V) ±2V +2.3V, -2.2V
PSRR+ (0) (dB) - 87PSRR- (0) (dB) - 106Phase margin (degrees) 60° 65°Output Resistance (k ) - 122.5k
Lecture 250 – Measurement and Simulation of Op amps (3/28/10) Page 250-26
CMOS Analog Circuit Design © P.E. Allen - 2010
Relative Overshoots of Ex. 250-1Why is the negative-going overshootlarger than the positive-going overshooton the small-signal transient response ofthe last slide?Consider the following circuit andwaveform:
During the rise time,iCL = CL(dvout/dt )= 10pF(0.2V/0.1μs) = 20μA and iCc = 3pf(2V/μs) = 6μA
i6 = 95μA + 20μA + 6μA = 121μA gm6 = 1066μS (nominal was 942.5μS)
During the fall time, iCL = CL(-dvout/dt) = 10pF(-0.2V/0.1μs) = -20μA
and iCc = -3pf(2V/μs) = -6μA
i6 = 95μA - 20μA - 6μA = 69μA gm6 = 805μS
The dominant pole is p1 (RIgm6RIICc)-1 but the GB is gmI/Cc = 94.25μS/3pF =31.42x106 rads/sec and stays constant. Thus we must look elsewhere for the reason.Recall that p2 gm6/CL which explains the difference.
p2(95μA) = 94.25x106 rads/sec, p2(121μA) = 106.6 x106 rads/sec, and p2(69μA) =80.05 x106 rads/sec. Thus, the phase margin is less during the fall time than the rise time.
M6
M7
vout
VDD = 2.5V
VSS = -2.5V
CcCL
VBias
95μA
94/1i6iCL
0.1V
-0.1V
0.1μs 0.1μs
t
Fig. 240-26
iCc
Lecture 250 – Measurement and Simulation of Op amps (3/28/10) Page 250-27
CMOS Analog Circuit Design © P.E. Allen - 2010
OP AMP MACROMODELSWhat is a Macromodel?A macromodel uses resistors, capacitors, inductors, controlled sources, and some activedevices (mostly diodes) to capture the essence of the performance of a complex circuitlike an op amp without modeling every internal component of the op amp.Small Signal, Frequency Independent Op Amp Macromodel
vov1
v2
A Rid
v1
v2
Ro
voAvdRo
(v1-v2)
o
Rid
v1
v2
RoAvd (v1-v2)
1
3
1
2
3
2
4
v
(a.) (b.) (c.) Fig. 010-01
Figure 1 - (a.) Op amp symbol. (b.) Thevenin form. (c.) Norton form.
Rid
1
2
Ric1
Ric2
vo
-
+3
Ro
Linear Op Amp Macromodel
Avcv12Ro
Avcv22RoAvd(v1-v2)
Ro
Fig. 010-03
Figure 2 - Simple op amp model including differential and common mode behavior.
Lecture 250 – Measurement and Simulation of Op amps (3/28/10) Page 250-28
CMOS Analog Circuit Design © P.E. Allen - 2010
Small Signal, Frequency Dependent Op Amp Macromodel
Avd(s) = Avd(0)
(s/ 1) + 1 where 1= 1
R1C1 (dominant pole)
Model Using Passive Components:
Rid
v1
v2
vo1
2R1 C1
Avd(0)R1
(v1-v2)
3
Fig. 010-04
Figure 3 - Macromodel for the op amp including the frequency response of Avd.Model Using Passive Components with Constant Output Resistance:
Rid
v1
v2
vo31
2R1 C1 Ro
v3Ro
4
Avd(0)R1
(v1-v2)
Fig. 010-05
Figure 4 - Frequency dependent model with constant output resistance.
Lecture 250 – Measurement and Simulation of Op amps (3/28/10) Page 250-29
CMOS Analog Circuit Design © P.E. Allen - 2010
Large Signal, Frequency Independent Op Amp Macromodel
Nonlinear Op Amp Macromodel
10 vo
-
+3
Ro
Avcv42Ro 11
D6+
-
+
-
D5
VOH VOL
Avcv52Ro
Rid
1
2 5
Ric1
Ric2
7D1 D2
+
-
+
-
RLIM 4
6
D3 D49+
-
+
-
RLIM
8
VIH1
VIH2 VIL2
VIL1
AvdRo
(v4-v5)
Fig. 010-10
Figure 5 - Op amp macromodel that limits the input and output voltages.
Rid
v1
v2
Ro
vo31
2AvdRo
(v1-v2)7+
-
8+
-
D1
D2
D3
D4D5 D6
ILimit VOH VOL
45
6
Fig. 010-13
Figure 6 – Technique for current limiting and a macromodel for output voltage andcurrent limiting.
D1
D2
D3
D4
ILimit
Io Io
Io2
ILimit2
Io2
Io2
Io2
ILimit2
Fig. 010-12
Lecture 250 – Measurement and Simulation of Op amps (3/28/10) Page 250-30
CMOS Analog Circuit Design © P.E. Allen - 2010
Large Signal, Frequency Dependent Op Amp MacromodelSlew Rate:
dvo
dt = ±ISR
C1 = Slew Rate
Rid
v1
v2
vo3
1
2R1
C1Avd(0)R1
(v1-v2)
D1
D2
D3
D4
6
7Ro
v4-v5Ro
45
ISR
Fig. 010-15
Figure 7 – Slew rate macromodel for an op amp.Results for a unity gain op amp in slew:
-10V
-5V
0V
5V
10V
0μs 2μs 4μs 6μs 8μs 10μs
InputVoltage
OutputVoltage
Time Fig. 010-16
Lecture 250 – Measurement and Simulation of Op amps (3/28/10) Page 250-31
CMOS Analog Circuit Design © P.E. Allen - 2010
SUMMARY• Simulation and measurement of op amps has both similarities and differences• Measurement of open loop gain is very challenging – the key is to keep the quiescent
point output of the op amp well defined• The method of stimulating the output of the op amp or power supplies and letting the
input respond results in a robust method of measuring open loop gain, CMRR, and PSRR• Carefully investigate any deviations or aberrations from expected behavior in the
simulation and experimental results• Macromodels are useful for modeling the op amp without including every individual
transistor
Lecture 260 – Buffered Op Amps (3/28/10) Page 260-1
CMOS Analog Circuit Design © P.E. Allen - 2010
LECTURE 260 – BUFFERED OP AMPSLECTURE ORGANIZATION
Outline• Introduction• Open Loop Buffered Op Amps• Closed Loop Buffered Op Amps• Use of the BJT in Buffered Op Amps• SummaryCMOS Analog Circuit Design, 2nd Edition ReferencePages 352-368
Lecture 260 – Buffered Op Amps (3/28/10) Page 260-2
CMOS Analog Circuit Design © P.E. Allen - 2010
INTRODUCTIONBuffered Op AmpsWhat is a buffered op amp?
Buffered op amps are op amps with the ability to drive a low output resistance and/ora large output capacitance. This requires:
- An output resistance typically in the range of 10 Ro 1000
- Ability to sink and source sufficient current (CL·SR)
+
−Op Amp Buffer
RoutLarge
RoutSmall
vIN vOUTvOUT’
070430-01
Types of buffered op amps:- Open loop using output amplifiers- Closed loop using negative shunt feedback to reduce the output resistance of the op
amp
Lecture 260 – Buffered Op Amps (3/28/10) Page 260-3
CMOS Analog Circuit Design © P.E. Allen - 2010
OPEN LOOP BUFFERED OP AMPSThe Class A Source Follower as a Buffer• Simple
• Small signal gain gm
gm + gmbs + GL < 1
• Low efficiency
• Rout = 1
gm + gmbs 500 to 1000
• Level shift from input to output• Maximum upper output voltage is limited• Broadbanded as the pole and zero due to the source follower are close so compensation
is typically not a problem
060118-10
VNBias1
VDD
M1
M2
vIN
vOUT
Lecture 260 – Buffered Op Amps (3/28/10) Page 260-4
CMOS Analog Circuit Design © P.E. Allen - 2010
The Push-Pull Follower as a Buffer• Voltage loss from 2 cascaded followers
Av gm3
gm3 + gmbs3
gm1gm1 + gmbs1 + GL
< 1
• Higher efficiency
• Rout 0.5
gm + gmbs 250 to 500
• Current in M1 and M2 determined by:VGS4 + VSG3 = VGS1 + VSG2
2I6Kn'(W4/L4) +
2I5Kp'(W3/L3)
= 2I1
Kn'(W1/L1) + 2I2
Kp'(W2/L2)
Use the W/L ratios to define I1 and I2 from I5 and I6• Maximum positive and negative output voltages are limited
060706-02
VNBias1
VDD
M1
M2
vIN vOUT
VDD
VDD
M4VDD
VPBias1
VDD
M5
M3
M6
+−
VSG3
I5
I6
+−
VSG2+−
VGS4
+−
VGS1
I1
I2
Lecture 260 – Buffered Op Amps (3/28/10) Page 260-5
CMOS Analog Circuit Design © P.E. Allen - 2010
Two-Stage Op Amp with Follower
-
+vin
M1 M2
M3 M4
M5
M6
M7VNBias
Cc
CL
I5 I7
060706-03
VDD
M8
M9
vout
I9
Power dissipation now becomes (I5 + I7 + I9)VDD
Gain becomes,
Av = gm1
gds2+gds4 gm6
gds6+gds7 gm8
gm8+ gmbs8+gds8+gds9
Lecture 260 – Buffered Op Amps (3/28/10) Page 260-6
CMOS Analog Circuit Design © P.E. Allen - 2010
Source-Follower, Push-Pull Output Op Amp
vout
VDD
VDD
Cc
-
+vin
M1 M2
M3
VSS
R1
M5
M6
R1
M7
M8
R1
M13
M14
VSS
VDD
VSS
M22
M21
IBias
M9
M10
M11
M12
M4
M17
M18
M15
M16
M19
M20
Fig. 7.1-1
CL
Buffer
-+VSG18
-+VSG21
-
+VGS19
-
+VGS22
I17
I20
Rout 1
gm21+gm22 1000 , Av(0)=65dB (IBias=50μA), and GB = 60MHz for CL = 1pF
Note the bias currents through M18 and M19 vary with the signal.
Lecture 260 – Buffered Op Amps (3/28/10) Page 260-7
CMOS Analog Circuit Design © P.E. Allen - 2010
Compensation of Op Amps with Output AmplifiersCompensation of a three-stage amplifier:This op amp introduces a third pole, p’3 (whatabout zeros?)With no compensation,
Vout(s)Vin(s) =
-Avo
sp’1 - 1
sp’2 - 1
sp’3 - 1
Illustration of compensation choices:
p1'p2'p3' p1
p2
p3
jω
σp1'p2'p3' p1
p2
p3=
jω
σ
Miller compensation applied around both the second and the third stage.
Miller compensation applied around the second stage only. Fig. 7.1-5
Compensated polesUncompensated poles
vin vout+-
x1v2
Unbufferedop amp
Outputstage
Polesp1' and p2'
Pole p3'
+
-
Fig. 7.1-4
CL RL
Lecture 260 – Buffered Op Amps (3/28/10) Page 260-8
CMOS Analog Circuit Design © P.E. Allen - 2010
Crossover-Inverter, Buffer Stage Op AmpPrinciple: If the buffer has high output resistance and voltage gain (common source), thisis okay if when loaded by a small RL the gain of this stage is approximately unity.
060706-04
-
+vin
M1 M2
M3 M4
M5
M6M7
vout
VDD
VSS
C2
RL
+-
C1
Cross over stage Output StageInputstage
vin'
IBias
• This buffer trades gain for the ability to drive a low load resistance• The load resistance should be fixed in order to avoid changes in the buffer gain• The push-pull common source output will give good output voltage swing capability
Lecture 260 – Buffered Op Amps (3/28/10) Page 260-9
CMOS Analog Circuit Design © P.E. Allen - 2010
Crossover-Inverter, Buffer Stage Op Amp - ContinuedHow does the output buffer work?The two inverters, M1-M3 and M2-M4 are designed to work over different regions of thebuffer input voltage, vin’.
Consider the idealized voltage transfer characteristic of the crossover inverters:
060706-05
VDDVA
M6 Active
M6 Satur-ated
M5 Active
M5 Saturated
VB
M1-M3Inverter
M2-M4Inverter
0 vin'
M1 M2
M3 M4M7
vout
VDD
VSS
C2C1
vin'
M6
M5 RL
voutVDD
VSS
IBias
Crossover voltage VC = VB-VA 0
VC is designed to be small and positive for worst case variations in processing.
Lecture 260 – Buffered Op Amps (3/28/10) Page 260-10
CMOS Analog Circuit Design © P.E. Allen - 2010
Large Output Current BufferIn the case where the load consists of a large capacitor, the ability to sink and source alarge current is much more important than reducing the output resistance. Consequently,the common-source, push-pull is ideal if the quiescent current can be controlled.A possible implementation:
If W4/L4 = W9/L9 andW 3/L3 = W8/L8, then thequiescent currents in M1and M2 can be determinedby the followingrelationship:
I1 = I2 = Ib W 1/L1W 7/L7
= Ib W 2/L2
W 10/L10
When vin is increased, M6 turns off M2 and turns on M1 to source current. Similarly,when vin is decreased, M5 turns off M1 and turns on M2 to sink current.
VDD
VSS
Ib
Ib
I=2Ib
M1
M2
M3 M4
M5
M6
M7
M8 M9
M10
vin
I=2Ib
vout
070430-07
vin
VDD
VSS
vout
Lecture 260 – Buffered Op Amps (3/28/10) Page 260-11
CMOS Analog Circuit Design © P.E. Allen - 2010
CLOSED LOOP BUFFERED OP AMPSPrinciple
Use negative shunt feedback to reduce the output resistance of the buffer.
Av+
−vIN
vOUT
ROUTRo
070430-02
RL
• Output resistance
ROUT = Ro
1 + Av
• Watch out for the case when RL causes Av to decrease.
• The bandwidth will be limited by the feedback (i.e. at high frequencies, the gain of Avdecreases causing the output resistance to increase.
Lecture 260 – Buffered Op Amps (3/28/10) Page 260-12
CMOS Analog Circuit Design © P.E. Allen - 2010
Two Stage Op Amp with a Gain Boosted, Source Follower Buffer
-
+vin
M1 M2
M3 M4
M5
M6
M7VNBias
Cc
I5 I7
070430-03
VDD
M11
vout
I11
1:K
M8
M9 M10
Rout
Rout 1
gm8K
Power dissipation now becomes (I5 + I7 + I11)VDD
Gain becomes,
Av = gm1
gds2+gds4 gm6
gds6+gds7 gm8K
gm8K+ gmbs8K +GL
Lecture 260 – Buffered Op Amps (3/28/10) Page 260-13
CMOS Analog Circuit Design © P.E. Allen - 2010
Gain Boosted, Source-Follower, Push-Pull Output Op AmpVDD
Cc
-
+vin
M1 M2
M3
VSS
M5
M6
M7
M8
R1
M13
M14
VSS
VDD
M21
IBias
M9
M10
M11
M12
M4
M17
M18
M15
M16
M19
M20
Gain Enhanced Buffer
-+VSG18
-+VSG21
-
+VGS19
-
+VGS22
I17
I20M23
M24
+VT+2VON
-
vout
1:K
M22
M23 M24
Rout
M25 M261:K
070430-04
Rout 1
K(gm21+gm22) 1000
K 100
Av(0)=65dB (IBias=50μA)
Note the bias currents through M18 and M19 vary with the signal.
Lecture 260 – Buffered Op Amps (3/28/10) Page 260-14
CMOS Analog Circuit Design © P.E. Allen - 2010
Common Source, Push Pull Buffer with Shunt FeedbackTo get low output resistance using MOSFETs, negative feedback must be used.Ideal implementation:
CL RL
viin vout
iout
VDD
M2
M1
Fig. 7.1-5A
+-
+-
ErrorAmplifier
ErrorAmplifier
VSS
+-
GainAmplifier
Comments:• The output resistance will be equal to rds1||rds2 divided by the loop gain
• If the error amplifiers are not perfectly matched, the bias current in M1 and M2 is notdefined
Lecture 260 – Buffered Op Amps (3/28/10) Page 260-15
CMOS Analog Circuit Design © P.E. Allen - 2010
Low Output Resistance Op Amp - ContinuedOffset correction circuitry:
-
+vin
A1
M16 M9
vout
VDD
VSS
VBias+
-
Cc
+-
+-
+-M8
M17
M8A
M13M6A
M6
M12 M11
M10
A2
VOS
Error Loop
Fig. 7.1-6
Unbufferedop amp
The feedback circuitry of the two error amplifiers tries to insure that the voltages inthe loop sum to zero. Without the M9-M12 feedback circuit, there is no way to adjust theoutput for any error in the loop. The circuit works as follows:When VOS is positive, M6 tries to turn off and so does M6A. IM9 reduces thus reducingIM12. A reduction in IM12 reduces IM8A thus decreasing VGS8A. VGS8A ideally decreasesby an amount equal to VOS. A similar result holds for negative offsets and offsets in EA2.
Lecture 260 – Buffered Op Amps (3/28/10) Page 260-16
CMOS Analog Circuit Design © P.E. Allen - 2010
Low Output Resistance Op Amp - ContinuedError amplifiers:
vinM1 M2
M3 M4
M5
M6
M6A
vout
VDD
VSS
VBias+
-
Cc1
A1 amplifier
MR1
070430-05
A2 amplifier
vin
VBias+
-
M2A M1A
M5A
M4A M3A
MR2
Cc2
Basically a two-stage op amp with the output push-pull transistors as the second-stage ofthe op amp.
Lecture 260 – Buffered Op Amps (3/28/10) Page 260-17
CMOS Analog Circuit Design © P.E. Allen - 2010
Low Output Resistance Op Amp - Complete Schematic
Short circuit protection(max. output ±60mA):MP3-MN3-MN4-MP4-MP5MN3A-MP3A-MP4A-MN4A-MN5A
Rout rds6||rds6A
Loop Gain 50k5000 = 10
M2
M3 M4
M5
M1
vout
VDD
VSS
VBiasN+
-
Cc
+-
VBiasP+
-
Cc1
M16M3H M4H MP4
MP3
MP5
MR1
M8
M17 MN3 MN4
M6
M6A
M13 M12 M11
MR2Cc2
M8A
M9
MN5A
MN4A
MN3A
MP4A
MP3A
M4HA
M4A M3A
M3HA
M1AM2A
M5Avin+
-
Fig. 7.1-8
M10
RC
R1 RL CL
CC
C1
gm1 gm6
Lecture 260 – Buffered Op Amps (3/28/10) Page 260-18
CMOS Analog Circuit Design © P.E. Allen - 2010
Simpler Implementation of Negative Feedback to Achieve Low Output Resistance
Output Resistance:
Rout = Ro
1+LG where
Ro = 1
gds6+gds7
and
|LG| = gm22gm4
(gm6+gm7)Ro
Therefore, the output resistance is:
Rout = 1
(gds6+gds7) 1 +gm2
2gm4 (gm6+gm7)Ro
-
+vin
M1 M2
M3 M4
M5
M6
M7
vout
VDD
VSS
CL
M8
M10
M9
Fig. 7.1-9
1/1 10/1200μA 10/1
10/1 10/1
1/1
1/1
1/1
10/1 10/1
Lecture 260 – Buffered Op Amps (3/28/10) Page 260-19
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 260-1 - Low Output Resistance Using Shunt Negative Feedback BufferFind the output resistance of above op amp using the model parameters of KN’ =
120μA/V2, KP’ = 25μA/V2, N = 0.06V-1 and P = 0.08V-1.
SolutionThe current flowing in the output transistors, M6 and M7, is 1mA which gives Ro of
Ro = 1
( N+ P)1mA = 10000.14 = 7.143k
To calculate the loop gain, we find that gm2 = 2KN’·10·100μA = 490μS
gm4 = 2KP’·1·100μA = 70.7μSand
gm6 = 2KP’·10·1000μA = 707μS
Therefore, the loop gain is
|LG| = 490
2·70.7 (0.707+0.071)7.143 = 19.26
Solving for the output resistance, Rout, gives
Rout = 7.143k1 + 19.26 = 353 (Assumes that RL is large)
Lecture 260 – Buffered Op Amps (3/28/10) Page 260-20
CMOS Analog Circuit Design © P.E. Allen - 2010
USE OF THE BJT IN BUFFERED OP AMPSSubstrate BJTsIllustration of an NPN substrate BJT available in a p-well CMOS technology:
������
����
n- substrate (Collector)
p- well (Base)
n+ (Emitter) p+
��n+
Emitter Base Collector(VDD)
Collector (VDD)
Emitter
Base
Fig. 7.1-10
Comments:• gm of the BJT is larger than the FET so that the output resistance w/o feedback is lower
• Collector current will be flowing in the substrate• Current is required to drive the BJT• Only an NPN or a PNP bipolar transistor is available
Lecture 260 – Buffered Op Amps (3/28/10) Page 260-21
CMOS Analog Circuit Design © P.E. Allen - 2010
A Lateral Bipolar Transistorn-well CMOS technology:• It is desirable to have the lateral
collector current much larger than thevertical collector current.
• Triple well technology allows thecurrent of the vertical collector to avoidflowing in the substrate.
• Lateral BJT generally has goodmatching.
060221-01
p+
n-well
n+
Substrate
E LCBVC
STI STI
LC
STI Lateral Collector
Emitter
Base
VerticalCollector
p+ p+
Lecture 260 – Buffered Op Amps (3/28/10) Page 260-22
CMOS Analog Circuit Design © P.E. Allen - 2010
A Field-Aided Lateral BJTUse minimum channel length to
enhance beta:ßF 50 to 100 depending on the
process
060221-02
p+
n-well
n+
Substrate
BVC
STI STI
LC
STI Lateral Collector Emitter
Base
VerticalCollector
p+ p+p+
E LC
Keeps carriers fromflowing at the surfaceand reduces 1/f noise
Lecture 260 – Buffered Op Amps (3/28/10) Page 260-23
CMOS Analog Circuit Design © P.E. Allen - 2010
Two-Stage Op Amp with a Class-A BJT Output Buffer StagePurpose of the M8-M9 sourcefollower:1.) Reduce the output resistance
(includes whatever is seen fromthe base to ground divided by1+ F)
2.) Reduces the output load at thedrains of M6 and M7
Small-signal output resistance :
Rout r 10 + (1/gm9)
1+ßF =
1gm10
+ 1
gm9(1+ßF)
= 51.6 +6.7 = 58.3 where I10=500μA, I8=100μA, W9/L9=100 and ßF is 100
vOUT(max) = VDD - VSD8(sat) - vBE10 = VDD - 2KP’
I8(W8/L8) - Vt lnIc10Is10
Voltage gain:voutvin
gm1
gds2+gds4
gm6gds6+gds7
gm9gm9+gmbs9+gds8+g 10
gm10RL1+gm10RL
Compensation will be more complex because of the additional stages.
M1 M2
M3 M4
M5
M6
M7
vout
VDD
VSS
CcCL
IBias
Q10
M11
M12
M13
Fig. 7.1-11
M8
M9
Output Buffer
RL
vin
+
-
Lecture 260 – Buffered Op Amps (3/28/10) Page 260-24
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 260-2 - Designing the Class-A, Buffered Op AmpUse an n-well, 0.25μm CMOS technology to design an op amp using a class-A, BJT
output stage to give the following specifications. Assume the channel length is to be0.5μm. The FETs have the model parameters of KN’ = 120μA/V2, KP’ = 25μA/V2, VTN =
|VTP| = 0.5V, N = 0.06V-1 and P = 0.08V-1 along with the BJT parameters of Is =10-14A and ßF = 50.VDD = 2.5V VSS = 0V GB = 5MHz Avd(0) 2500V/V Slew rate 10V/μsRL = 500 Rout 50 CL = 100pF ICMR = +1V to 2V
SolutionA quick comparison shows that the
specifications of this problem are similarto the folded cascode op amp that wasdesigned in Ex. 240-3. Borrowing thatdesign for this example results in thefollowing op amp.
Therefore, the goal of this examplewill be the design of M12 through Q15 tosatisfy the slew rate and output resistancerequirements.
070430
VPB1
M4 M5Rout
I6
VPB2
I4 I5
VDD
I7M6 M7
VNB2
M8 M9
M10M11
+−
vIN
vO
VNB1
I1 I2
M1 M2
M3I3
C
VNB1
VPB1
M12
M13
M14
Q15
I12
I15
Lecture 260 – Buffered Op Amps (3/28/10) Page 260-25
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 260-2 – ContinuedBJT follower (Q15):
SR = 10V/μs and 100pF capacitor give I15 = 1mA.
Assuming the gate of M14 is connected to the gate of M5, the W /L ratio of M14becomes
W14/L14 = (1000μA/125μA)160 = 1280 W14 = 640μm
I15 = 1mA 1/gm15 = 0.0258V/1mA = 25.8
MOS follower:To source 1mA, the BJT requires 20μA (ß =50) from the MOS follower (M12-M13). Therefore, select a bias current of 100μA for M13. If the gates of M3 and M13 areconnected together, then
W13/L13 = (100μA/100μA)15 = 15 W13 = 7.5μm
To get Rout = 50 , if 1/gm15 is 25.8 , then design gm12 as1
gm15 =
1gm12(1+ßF) = 24.2 gm12 =
1(24.2 )(1+ßF) =
124.2·51 = 810μS
gm12 and I12 W/L = 27.3 30 W12 = 15μm
Lecture 260 – Buffered Op Amps (3/28/10) Page 260-26
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 260-2 - Continued
To calculate the voltage gain of the MOS follower we need to find gmbs9 ( N = 0.4 V).
gmbs12 = gm12 N
2 2 F + VBS12 =
810·0.42 0.5+0.55 = 158μS
where we have assumed that the value of VSB12 is approximately 1.25V – 0.7V = 0.55V.
AMOS = 810μS
810μS+158μS+6μS+8μS = 0.825
The voltage gain of the BJT follower is
ABJT = 500
25.8+500 = 0.951 V/V
Thus, the gain of the op amp isAvd(0) = (3,678)(0.825)(0.951) = 2,885 V/V
The power dissipation of this amplifier is, Pdiss. = 2.5V(125μA+125μA+100μA+1000μA) = 3.375mW
The signal swing across the 500 load resistor will be restricted to ±0.5V due to the1000μA output current limit.
Lecture 260 – Buffered Op Amps (3/28/10) Page 260-27
CMOS Analog Circuit Design © P.E. Allen - 2010
SUMMARY• A buffered op amp requires an output resistance between 10 Ro 1000
• Output resistance using MOSFETs only can be reduced by,- Source follower output (1/gm)
- Negative shunt feedback (frequency is a problem in this approach)• Use of substrate (or lateral) BJT’s can reduce the output resistance because gm is
larger than the gm of a MOSFET
• Adding a buffer stage to lower the output resistance will most likely complicate thecompensation of the op amp
Lecture 270 – High Speed Op Amps (3/28/10) Page 270-1
CMOS Analog Circuit Design © P.E. Allen - 2010
LECTURE 270 – HIGH SPEED OP AMPSLECTURE ORGANIZATION
Outline• Extending the GB of conventional op amps• Cascade Amplifiers
- Voltage amplifiers- Voltage amplifiers using current feedback
• SummaryCMOS Analog Circuit Design, 2nd Edition ReferencePages 368-384
Lecture 270 – High Speed Op Amps (3/28/10) Page 270-2
CMOS Analog Circuit Design © P.E. Allen - 2010
INCREASING THE GB OF OP AMPSWhat is the Influence of GB on the Frequency Response?The unity-gainbandwidth represents a limit in the trade-off between closed loop voltagegain and the closed-loop -3dB frequency.Example of a gain of -10 voltage amplifier:
0dB
20dB
|Avd(0)| dB
Magnitude
log10(ω)GBωA ω-3dB
Op amp frequency response
Amplifier with a gain of -10
Fig. 7.2-1
What defines the GB?We know that
GB = gm
C
where gm is the transconductance that converts the input voltage to current and C is thecapacitor that causes the dominant pole.This relationship assumes that all higher-order poles are greater than GB.
Lecture 270 – High Speed Op Amps (3/28/10) Page 270-3
CMOS Analog Circuit Design © P.E. Allen - 2010
What is the Limit of GB?The following illustrates whathappens when the next higher pole isnot greater than GB:
For a two-stage op amp, the polesand zeros are:
1.) Dominant pole p1 = -gm1
Av(0)Cc
2.) Output pole p2 = -gm6
CL
3.) Mirror pole p3 = -gm3
Cgs3+Cgs4 and z3 = 2p3
4.) Nulling pole p4 = -1
RzCI
5.) Nulling zero z1 = -1
RzCc-(Cc/gm6)
0dB
20dB
|Avd(0)| dB
Magnitude
log10(ω)GBωA ω-3dB
Op amp frequency response
Amplifier with a gain of -10
Fig. 7.2-2
Next higher pole-40dB/dec
Lecture 270 – High Speed Op Amps (3/28/10) Page 270-4
CMOS Analog Circuit Design © P.E. Allen - 2010
Higher-Order PolesFor reasonable phase margin, the smallest higher-order pole should be 2-3 times largerthan GB if all other higher-order poles are larger than 10GB.
060709-01
-GB-10GB
Dominantpole
Smallest non-dominant pole
Larger non-dominant poles
GB
10GB0dB
Av(0) dB
GBAv(0)
log10ω
If the higher-order poles are not greater than 10GB, then the distance from GB to thesmallest non-dominant pole should be increased for reasonable phase margin.
Lecture 270 – High Speed Op Amps (3/28/10) Page 270-5
CMOS Analog Circuit Design © P.E. Allen - 2010
Increasing the GB of a Two-Stage Op Amp1.) Use the nulling zero to cancel the closest pole beyond the dominant pole.2.) The maximum GB would be equal to the magnitude of the second closest pole beyond
the dominant pole.3.) Adjust the dominant pole so that 2.2GB (second closest pole beyond the dominant
pole)Illustration which assumes that p2 is the next closest pole beyond the dominant pole:
0dB
|Avd(0)| dB
Magnitude
log10(ω)
Fig. 7.2-3
-40dB/dec
-p1-p2 = z1-p4-p3
|p1| |p2|
|p4||p3|
-60dB/dec-80dB/dec
Before cancellingp2 by z1 and increasing p1
jωσ
|p1|
GB
-p1New Old
GBIncrease
OldGBNew
Old New
Lecture 270 – High Speed Op Amps (3/28/10) Page 270-6
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 270-1 - Increasing the GB of the Op Amp Designed in Ex. 230-1Use the two-stage op amp designed
in Example 230-1 and apply the aboveapproach to increase the gainbandwidthas much as possible. Use the capacitorvalues in the table shown along with Cox= 6fF/μm2.Solution1.) First find the values of p2, p3, and p4.
a.) From Ex. 230-2, we see thatp2 = -95x106 rads/sec.
b.) p3 was found in Ex. 6.3-1 asp3 = -1.25x109 rads/sec. (alsothere is a zero at -2.5x109
rads/sec.)
-
+vin
M1 M2
M3 M4
M5
M6
M7
vout
VDD = 2.5V
VSS = -2.5V
Cc = 3pF
CL =10pF
3μm1μm
3μm1μm
15μm1μm
15μm1μm
M84.5μm1μm
30μA
4.5μm1μm
14μm1μm
94μm1μm
30μA
95μA
Fig. 7.2-3A
Rz
Type P-Channel N-Channel UnitsCGSO 220 10-12 220 10-12 F/mCGDO 220 10-12 220 10-12 F/mCGBO 700 10-12 700 10-12 F/mCJ 560 10-6 770 10-6 F/m2CJSW 350 10-12 380 10-12 F/mMJ 0.5 0.5MJSW 0.35 0.38
Lecture 270 – High Speed Op Amps (3/28/10) Page 270-7
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 270-1 - Continued(c.) To find p4, we must find CI which is the output capacitance of the first stage of theop amp. CI consists of the following capacitors,
CI = Cbd2 + Cbd4 + Cgs6 + Cgd2 + Cgd4
For Cbd2 the width is 1.5μm L1+L2+L3=3μm AS/AD=4.5μm2 and PS/PD=9μm.For Cbd4 the width is 15μm L1+L2+L3=3μm AS/AD=45μm2 and PS/PD=36μm.From Table 3.2-1:
Cbd2 = (4.5μm2)(770x10-6F/m2) + (9μm)(380x10-12F/m) = 3.47fF+3.42fF 6.89fF
Cbd4 = (45μm2)(560x10-6F/m2) + (36μm)(350x10-12F/m) = 25.2fF+12.6F 37.8fF
Cgs6 in saturation is,
Cgs6=CGDO·W6+0.67(CoxW 6L6)=(220x10-12)(85x10-6)+(0.67)(6x10-15)(42.5) = 18.7fF + 255fF = 273.7fF
Cgd2 = 220x10-12x1.5μm = 0.33fF and Cgd4 = 220x10-12x15μm = 3.3fF
Therefore, CI = 6.9fF + 37.8fF + 273.7fF + 0.33fF + 3.3fF = 322fF. Although Cbd2 andCbd4 will be reduced with a reverse bias, let us use these values to provide a margin.Thus let CI be 322fF.
In Ex. 230-2, Rz was 4.564k which gives p4 = - 0.680x109 rads/sec.
Lecture 270 – High Speed Op Amps (3/28/10) Page 270-8
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 270-1 - ContinuedTherefore, the roots are:
jω
σ x 109
-1-2-3
z3 = -2.5G p3 = -1.25G p4 = -0.68G
p2 = -0.095G New GB
070503-01
When p2 is cancelled, the next smaller pole is p4 which will define the new GB. 2.)Using the nulling zero, z1, to cancel p2, gives p4 as the next smallest pole.For 60° phase margin GB = |p4|/2.2 if the next smallest pole is more than 10GB.
GB = 0.680x109/2.2 = 0.309x109 rads/sec. or 49.2MHz.This value of GB is designed from the relationship that GB = gm1/Cc. Assuming gm1 is
constant, then Cc = gm1/GB = (94.25x10-6)/(0.309x109) = 307fF. It might be useful toincrease gm1 in order to keep Cc above the surrounding parasitic capacitors (Cgd6 =18.7fF). The success of this method assumes that there are no other roots with amagnitude smaller than 10GB.
The result of this example is to increase the GB from 5MHz to 49MHz.
Lecture 270 – High Speed Op Amps (3/28/10) Page 270-9
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 270-2 - Increasing the GB of the Folded Cascode Op Amp of Ex. 240-4Use the folded-cascode op amp designed in
Example 240-4 and apply the above approach toincrease the gainbandwidth as much as possible.Assume that the drain/source areas are equal to2μm times the width of the transistor and that allvoltage dependent capacitors are at zero voltage.Solution
The poles of the folded cascode op amp are:
pA -1
RACA (the pole at the source of M6 )
pB -1
RBCB (the pole at the source of M7)
p6 -gm10
C6 (the pole at the drain of M6)
p8 -gm8rds8gm10
C8 (the pole at the source of M8)
p9 -gm9C9 (the pole at the source of M9)
060628-04
VPB1
M4 M5
RAI6
VPB2 RB
I4 I5
VDD
I7M6 M7
VNB2
M8 M9
M10 M11
+−
vIN
vOU
VNB1
I1 I2
M1 M2
M3I3
CL
Lecture 270 – High Speed Op Amps (3/28/10) Page 270-10
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 270-2 - ContinuedLet us evaluate each of these poles.1.) For pA, the resistance RA is approximately equal to gm6 and CA is given as
CA = Cgs6 + Cbd1 + Cgd1 + Cbd4 + Cbs6 + Cgd4From Ex. 240-4, gm6 = 774.6μS and capacitors giving CA are found as,
Cgs6 = (220x10-12·80x10-6) + (0.67)(80μm·0.5μm·6fF/μm2) = 177.6fF
Cbd1 = (770x10-6)(16.5x10-6·2x10-6) + (380x10-12)(37x10-6) = 39.5fF
Cgd1 = (220x10-12·16.5x10-6) = 3.6fF
Cbd4 = Cbs6 = (560x10-6)(80x10-6·2x10-6) + (350x10-12)(2·82x10-6) = 147fFand
Cgd4 = (220x10-12)(80x10-6) = 17.6fFTherefore,
CA = 177.6fF + 39.5fF + 3.6fF + 147fF + 17.6fF + 147fF = 0.532pFThus,
pA = -774.6x10-6
0.532x10-12 = -1.456x109 rads/sec.
2.) For the pole, pB, the capacitance connected to this node isCB = Cgd2 + Cbd2 + Cgs7 + Cgd5 + Cbd5 + Cbs7
Lecture 270 – High Speed Op Amps (3/28/10) Page 270-11
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 270-2 - ContinuedThe various capacitors above are found as
Cgd2 = (220x10-12·16.5x10-6) = 3.6fFCbd2 = (770x10-6)(16.5x10-6·2x10-6) + (380x10-12)(37x10-6) = 39.5fF
Cgs7 = (220x10-12·80x10-6) + (0.67)(80μm·0.5μm·6fF/μm2) = 177.6fFCgd5 = (220x10-12)(80x10-6) = 17.6fF
andCbd5 = Cbs7 = (560x10-6)(80x10-6·2x10-6) + (350x10-12)(2·82x10-6) = 147fF
The value of CB is the same as CA and gm6 is assumed to be the same as gm7 giving pB =pA = -1.456x109 rads/sec.3.) For the pole, p6, the capacitance connected to this node is
C6= Cbd6 + Cgd6 + Cgs10 + Cgs11+ Cbd8 + Cgd8
The various capacitors above are found asCbd6 = (560x10-6)(80x10-6·2x10-6) + (350x10-12)(2·82x10-6) = 147fFCgs10 = Cgs11 = (220x10-12·10x10-6) + (0.67)(10μm·0.5μm·6fF/μm2) = 22.2fFCbd8 = (770x10-6)(10x10-6·2x10-6) + (380x10-12)(2·12x10-6) = 24.5fFCgd8 = (220x10-12)(10x10-6) = 2.2fF and Cgd6 = Cgd5 =17.6fF
Therefore,C6 = 147fF + 17.6fF + 22.2fF + 22.2fF + 2.2fF + 17.6fF = 0.229pF
Lecture 270 – High Speed Op Amps (3/28/10) Page 270-12
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 270-2 - ContinuedFrom Ex. 240-4, gm6 = 774.6x10-6. Therefore, p6, can be expressed as
-p6 = 774.6x10-6
0.229x10-12 = 3.38x109 rads/sec.
4.) Next, we consider the pole, p8. The capacitance connected to this node isC8= Cbd10 + Cgd10 + Cgs8 + Cbs8
These capacitors are given as,Cbs8 = Cbd10 = (770x10-6)(10x10-6·2x10-6) + (380x10-12)(2·12x10-6) = 24.5fF
Cgs8 = (220x10-12·10x10-6) + (0.67)(10μm·0.5μm·6fF//μm2) = 22.2fFand
Cgd10 = (220x10-12)(10x10-6) = 2.2fFThe capacitance C8 is equal to
C8 = 24.5fF + 2.2fF + 22.2fF + 24.5fF = 73.4FFUsing the values of Ex. 240-4 of 600μS, the pole p8 is found as,
-p8 = gm8rds8 gm10/C8 = -600μS·600μS·/4.5μS·73.4fF = -1090x109 rads/sec.
5.) The capacitance for the pole at p9 is identical with C8. Therefore, since gm9 is600μS, the pole p9 is -p9 = 8.17x109 rads/sec.
Lecture 270 – High Speed Op Amps (3/28/10) Page 270-13
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 270-2 - ContinuedThe poles are summarized below:
pA = -1.456x109 rads/sec pB = -1.456x109 rads/sec p6 = -3.38x109 rads/sec
p8 = -1090x109 rads/sec p9 = -8.17x109 rads/secjω
σ x 109-1 -2 -3
p9 = -8.17G p6 = -3.38GpA = pB
= -1.456G New GB = 0.2x109
070503-02 -4 -5 -6 -7 -8
p8 = -1090G
The smallest of these poles is pA or pB. Since p6 is not much larger than pA or pB, wewill find the new GB by dividing pA or pB by 4 (which is guess rather than 2.2) to get364x106 rads/sec. Thus the new GB will be 364/2 or 58MHz.Checking our guess gives a phase margin of,
PM = 90° - 2tan-1(0.364/1.456) - tan-1(0.364/3.38) = 56° which is okayThe magnitude of the dominant pole is given as
pdominant = GB/Avd(0) = 364x106/3,678 = 99,000 rads/sec.
The value of load capacitor that will give this pole isCL = (pdominant·Rout)-1 = (99x103·7.44M )-1 = 1.36pF
Therefore, the new GB = 58MHz compared with the old GB = 10MHz.
Lecture 270 – High Speed Op Amps (3/28/10) Page 270-14
CMOS Analog Circuit Design © P.E. Allen - 2010
Elimination of Higher-Order PolesThe minimum circuitry for a cascode op amp is shown below:
060710-01
vin + VNB1
vin + VPB1
VNB2
VPB2
VDD
M1
M2
M3
M4
vout
CL
Dominant Pole
Non-dominant
Pole
Non-dominant
Pole
If the source-drain area between M1 and M2 and M3 and M4 can be minimized, the non-dominant poles will be quite large.
Lecture 270 – High Speed Op Amps (3/28/10) Page 270-15
CMOS Analog Circuit Design © P.E. Allen - 2010
Dynamically Biased, Push-Pull, Cascode Op Amp
M1
M2
M3
M4
M6
M7
vout
VDD
VSS
C1
M5
M8
C2
vin+IB
φ1
φ1
φ1 φ2
φ2
φ2
vin-
+-VB2
+-VB1
Fig.7.2-5
Push-pull, cascode amplifier: M1-M2 and M3-M4Bias circuitry: M5-M6-C2 and M7-M8-C1
Lecture 270 – High Speed Op Amps (3/28/10) Page 270-16
CMOS Analog Circuit Design © P.E. Allen - 2010
Dynamically Biased, Push-Pull, Cascode Op Amp - ContinuedOperation:
M6
M7
VDD
VSS
C1
M5
M8
C2
vin+IB
+-VB2
+-VB1
+
-VDD-VB2-vin+
+
-vin+-VSS-VB1
M1
M2
M3
M4
vout
VDD
VSS
C1
C2
vin-
+
-VDD-VB2-vin+
+
-vin+-VSS-VB1
VDD-VB2-(vin+-vin-)
VSS+VB1-(vin+-vin-)
Equivalent circuit during the φ1 clock period Equivalent circuit during the φ2 clock period.Fig. 7.2-6
Lecture 270 – High Speed Op Amps (3/28/10) Page 270-17
CMOS Analog Circuit Design © P.E. Allen - 2010
Dynamically Biased, Push-Pull, Cascode Op Amp - ContinuedThis circuit will operate on both clock phases† .
† S. Masuda, et. al., “CMOS Sampled Differential Push-Pull Cascode Op Amp,” Proc. of 1984 International Symposium on Circuits and Systems,
Montreal, Canada, May 1984, pp. 1211-12-14.
M1
M2
M3
M4
M6
M7
vout
VDD
VSS
C1
M5
M8
C2
vin+IB φ2
φ1
φ1
φ1vin-
+
-VB2
+
-VB1
Fig. 7.2-7
C4
C3
φ2
φ2
φ2 φ1
φ1 φ2
φ2 φ1
Performance (1.5μm CMOS):• 1.6mW dissipation• GB 130MHz (CL=2.2pF)• Settling time of 10ns (CL=10pF)
This amplifier was used with a28.6MHz clock to realize a 5th-orderswitched capacitor filter having acutoff frequency of 3.5MHz.
Lecture 270 – High Speed Op Amps (3/28/10) Page 270-18
CMOS Analog Circuit Design © P.E. Allen - 2010
CASCADED AMPLIFIERS USING VOLTAGE AMPLIFIERSBandwidth of Cascaded AmplifiersCascading of low-gain, wide-bandwidth amplifiers:
060710-02
Ao s/ω1+1
Vin Vout
Ao s/ω1+1
Ao s/ω1+1
A1 A2 An
Ao s/ω1+1
n
Overall gain is Aon
-3dB frequency is,
-3dB = 1 21/n-1
If Ao = 10, 1 = 300 x106 rads/sec. and n = 3, then
Overall gain is 60dB and -3dB = 0.51 1 = 480x106 rads/sec. 76.5 MHz
Lecture 270 – High Speed Op Amps (3/28/10) Page 270-19
CMOS Analog Circuit Design © P.E. Allen - 2010
Voltage Amplifier Suitable for Cascading
060710-03
VDD
Vout +−
Vin+
−
Μ1 Μ2Μ3 Μ4Μ5
VNB1
VPB1 VPB1
Μ6
Μ7
I7
I3 I4I5 I6
I1 I2
Voltage Gain:
VoutVin
= gm1gm3 =
Kn'(W1/L1)(I3+I5)Kp' (W3/L3)I3
-3dB gm3Cgs1
Lecture 270 – High Speed Op Amps (3/28/10) Page 270-20
CMOS Analog Circuit Design © P.E. Allen - 2010
Ex. 270-3 - Design of a Voltage Amplifier for CascadingDesign the previous voltage amplifier for a gain of Ao = 10 and a power dissipation of nomore than 1mW. The design should permit Ao to be well defined. What is the -3dB forthis amplifier and what would be the -3dB for a cascade of three identical amplifiers?
SolutionTo enhance the accuracy of the gain, we replace M3and M4 with NMOS transistors to avoid thevariation of the transconductance parameter. Thisassumes a p-well technology to avoid bulk effects.The gain of 10 requires,
W1L1 (I3+I5) = 100
W3L3 I3
If VDD = 2.5V, then 2(I3+I5)·2.5V = 1000μW.
Therefore, I3+I5 = 200μA. Let I3 = 20μA and W1/L1 = 10W3/L3.
Choose W1/L1 = 5μm/0.5μm which gives W3/L3 = 0.5μm/0.5μm. M5 and M6 aredesigned to give I5 = 180μA and M7 is designed to give I7 = 400μA.
The dominant pole is gm3/Cout.
060711-01
VDD
Vout +−
Vin+
−
Μ1 Μ2Μ3 Μ4Μ5
VNB1
VPB1 VPB1
Μ6
Μ7
I7
I3 I4I5 I6
I1 I2
Lecture 270 – High Speed Op Amps (3/28/10) Page 270-21
CMOS Analog Circuit Design © P.E. Allen - 2010
Ex. 270-3 – ContinuedCout = Cgs3+Cbs3+Cbd1+Cbd5+Cgd1+Cgd5+Cgs1(next stage) Cgs3 + Cgs1
Using Cox = 60.6x10-4 F/m2, we get,
Cout (2.5+0.25)x10-12 m2x 60.6x10-4 F/m2 = 16.7fF Cout 20fF
gm3 = 2·120·1·20 μS = 69.3μS
Dominant pole 69.3μS/20fF = 34.65x108 rads/sec. f-3dB = 551MHz
The bandwidth of three identical cascaded amplifiers giving a low-frequency gain of60dB would have a f-3dB of
f-3dB(Overall) = f-3dB 21/3-1 = 551MHz (0.5098) = 281MHz.
Pdiss = 3mW
060711-02
log10(f)
dB
60
40
20
0
-60dB/dec.
-40dB/dec.
-20dB/dec.
551MHz
281MHz
3 cascaded stages
2 cascaded stages
Single stage
Lecture 270 – High Speed Op Amps (3/28/10) Page 270-22
CMOS Analog Circuit Design © P.E. Allen - 2010
A 71 MHz CMOS Programmable Gain Amplifier†
Uses 3 ac-coupled stages.First stage (0-20dB, common gate for impedance matching and NF):
vout
VDD
vout
CMFB
VBP
VBN
0dB2dB
VB1
vin
VB1
vin
0dB 2dB
M2dB M0dB M2dBM0dB
M2 M2
M3
Fig. 7.2-137A
Rin = 330 to match source driving requirement
All current sinks are identical for the differential switches.Dominant pole at 150MHz.
† P. Orsatti, F. Piazza, and Q. Huang, “A 71 MHz CMOS IF-Basdband Strip for GSM, IEEE JSSC, vol. 35, No. 1, Jan. 2000, pp. 104-108.
Lecture 270 – High Speed Op Amps (3/28/10) Page 270-23
CMOS Analog Circuit Design © P.E. Allen - 2010
A 71 MHz PGA – ContinuedSecond stage (-10dB to 20dB):
M2 M2
M3
M2 M2
M3
CMFB
-10dB
-10dB
vout vout
VBP
VBN
vin vin
Fig. 7.2-137A
M5
M4
M6
M2dB M0dB
0dBLoad -10dB
Load
M5
M4
M6
M2dBM0dB
0dB 2dB0dB2dB
VDD
Dominant pole is also at 150MHzFor VDD = 2.5V, at 60dB gain, the total current is 2.6mA
IIP3 +1dBm
Lecture 270 – High Speed Op Amps (3/28/10) Page 270-24
CMOS Analog Circuit Design © P.E. Allen - 2010
CASCADED AMPLIFIERS USING CURRENT FEEDBACK AMPLIFIERSAdvantages of Using Current FeedbackWhy current feedback?• Higher GB• Less voltage swing more dynamic rangeWhat is a current amplifier?
Requirements:io = Ai(i1-i2)
Ri1 = Ri2 = 0
Ro =
Ideal source and load requirements:Rsource =
RLoad = 0
Ri2
i1
i2io
+
-
CurrentAmplifier
Ri1
Ro
Fig. 7.2-8A
Lecture 270 – High Speed Op Amps (3/28/10) Page 270-25
CMOS Analog Circuit Design © P.E. Allen - 2010
Bandwidth Advantage of a Current Feedback AmplifierConsider the inverting voltage amplifiershown using a current amplifier withnegative current feedback:
The output current, io, of the currentamplifier can be written as
io = Ai(s)(i1-i2) = -Ai(s)(iin + io)The closed-loop current gain, io/iin, can befound as
ioiin =
-Ai(s)1+Ai(s)
However, vout = ioR2 and vin = iinR1. Solving for the voltage gain, vout/vin gives
voutvin =
ioR2iinR1 =
-R2R1
Ai(s)1+Ai(s)
If Ai(s) = Ao
(s/ A) + 1 , then
vinvout
+-
+-
i1
i2 io
io
vout
CurrentAmplifier
R1R2iin
VoltageBufferFig. 7.2-9
voutvin =
-R2R1
Ao1+Ao
A(1+Ao)s + A(1+Ao) Av(0) =
-R2AoR1(1+Ao) and -3dB = A(1+Ao)
Lecture 270 – High Speed Op Amps (3/28/10) Page 270-26
CMOS Analog Circuit Design © P.E. Allen - 2010
Bandwidth Advantage of a Current Feedback Amplifier - ContinuedThe unity-gainbandwidth is,
GB = |Av(0)| -3dB = R2Ao
R1(1+Ao) · A(1+Ao) = R2
R1 Ao· A =
R2
R1 GBi
where GBi is the unity-gainbandwidth of the current amplifier.
Note that if GBi is constant, then increasing R2/R1 (the voltage gain) increases GB.
Illustration:
Ao dB
ωA
R2R1
>1
R2R1
GB1 GB2
Current Amplifier
0dB
Voltage Amplifier,
log10(ω)
Magnitude dB
Fig. 7.2-10
(1+Ao)ωA
GBi
= K
R1Voltage Amplifier, > KR2
1+AoAo dB
1+AoAo dBK
Note that GB2 > GB1 > GBi
The above illustration assumes that the GB of the voltage amplifier realizing the voltagebuffer is greater than the GB achieved from the above method.
Lecture 270 – High Speed Op Amps (3/28/10) Page 270-27
CMOS Analog Circuit Design © P.E. Allen - 2010
Current Feedback AmplifierIn a current mirror implementation of the current amplifier, it is difficult to make the inputresistance sufficiently small compared to R1.
This problem can be solved using a transconductance input stage shown in the followingblock diagram:
060711-04
GMAi
RF
VinVout
+
−
VoutVin =
-GMRFAi1 +Ai
Lecture 270 – High Speed Op Amps (3/28/10) Page 270-28
CMOS Analog Circuit Design © P.E. Allen - 2010
Differential Implementation of the Current Feedback AmplifierVDD
060712-01
Rin
RF RF+ −Vout
VPB1
VPB2
VNB2
M1 M2
1:n 1:n
Vin+ Vin
-
Iin = gm1
1+ 0.5gm1Rin
Vin+- Vin
-
2 and Vout = n (2RF)
1+n Iin
VoutVin
2nRFRin
Lecture 270 – High Speed Op Amps (3/28/10) Page 270-29
CMOS Analog Circuit Design © P.E. Allen - 2010
A 20dB Voltage Amplifier using a Current AmplifierThe following circuit is a programmable voltage amplifier with up to 20dB gain:
M1
VDD
VSS
R1
+1 +1
VBias
+ -vout
vin+ vin-
M2
x2= 1/4
x4=1/8
x2= 1/4
x4=1/8
x1=1/2
x1=1/2
R2 R2
Fig. 7.2-135A
R1 and the current mirrors are used for gain variation while R2 is fixed.
Lecture 270 – High Speed Op Amps (3/28/10) Page 270-30
CMOS Analog Circuit Design © P.E. Allen - 2010
Programmability of the Previous StageInput OTA:
Changes GM in 6dB steps.
Lecture 270 – High Speed Op Amps (3/28/10) Page 270-31
CMOS Analog Circuit Design © P.E. Allen - 2010
Programmability of the Voltage Stage – Cont’dCurrent Amplifier:
Changes RF in 2dB steps
(RF20dB = 2.1k , RF18dB = 1.6k , RF16dB = 1.3k , and RF14dB = 5k .)
RFTotal = 10k .
Lecture 270 – High Speed Op Amps (3/28/10) Page 270-32
CMOS Analog Circuit Design © P.E. Allen - 2010
Frequency Response of the Current Feedback PGA Stage0.5pF load:
Lecture 270 – High Speed Op Amps (3/28/10) Page 270-33
CMOS Analog Circuit Design © P.E. Allen - 2010
Frequency Response of the Entire 60dB PGAIncludes output buffer:
Lecture 270 – High Speed Op Amps (3/28/10) Page 270-34
CMOS Analog Circuit Design © P.E. Allen - 2010
SUMMARY• Increasing the GB of an op amp requires that the magnitude of all non-dominant poles
are much greater than GB from the origin of the complex frequency plane• The practical limit of GB for an op amp is approximately 5-10 times less than the
magnitude of the smallest non-dominant pole ( 100MHz)• To achieve high values of GB it is necessary to eliminate the non-dominant poles
(which come from parasitics) or increase the magnitude of the non-dominant poles• The best way to achieve high-bandwidth amplifiers is to cascade high-bandwidth
voltage amplifiers• If the gain of the high-bandwidth voltage amplifiers is well defined, then it is not
necessary to use negative feedback around the amplifier• Amplifiers with well defined gains are obtainable with a -3dB bandwidth of 100MHz
Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10) Page 280-1
CMOS Analog Circuit Design © P.E. Allen - 2010
LECTURE 280 – DIFFERENTIAL-IN, DIFFERENTIAL-OUT OPAMPS
LECTURE ORGANIZATIONOutline• Introduction• Examples of differential output op amps• Common mode output voltage stabilization• SummaryCMOS Analog Circuit Design, 2nd Edition ReferencePages 384-393
Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10) Page 280-2
CMOS Analog Circuit Design © P.E. Allen - 2010
INTRODUCTIONWhy Differential Output Op Amps?• Cancellation of common mode signals including clock feedthrough• Increased signal swing
v1
v2
v1-v2t
t
t
A
-AA
-A
2A
-2A Fig. 7.3-1
• Cancellation of even-order harmonicsSymbol:
-
+vin vout+
-
-
+
-
+
Fig. 7.3-1A
Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10) Page 280-3
CMOS Analog Circuit Design © P.E. Allen - 2010
Common Mode Output Voltage StabilizationIf the common mode gain not small, it may cause the common mode output voltage to
be poorly defined.Illustration:
VDD
vod
t
070506-01
VSS
0
VDD
vod
t
VSS
0
VDD
vod
t
VSS
0
CM output voltage properly defined,Vcm = 0
CM output voltage too large,Vcm
= 0.5VDD CM output voltage too small, Vcm
= 0.5VSS
Remember that:vOUT = Avd(vID) ± Acm(vCM)
Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10) Page 280-4
CMOS Analog Circuit Design © P.E. Allen - 2010
EXAMPLES OF DIFFERENTIAL OUTPUT OP AMPS (OTA’S)Two-Stage, Miller, Differential-In, Differential-Out Op Amp
Note that theupper ICMR is
VDD - VSGP + VTN
(OCMR) = VDD+ |VSS| - VSDP(sat) - VDSN(sat)
The maximum peak-to-peak output voltage 2·OCMR
Conversion between differential outputs and single-ended outputs:
vod CL
+
-+-+
-vid
+
-vo1 2CL
+
-+-+
-vid
+
-
vo2+
-2CL
Fig. 7.3-4
vi1 M1 M2
M3 M4
M5
M6M8
VDD
VSS
VBN+-
Cc
M9
Cc
VBP+-
vi2
vo1voRzRz
M7
Fig. 7.3-3
Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10) Page 280-5
CMOS Analog Circuit Design © P.E. Allen - 2010
Two-Stage, Miller, Differential-In, Differential-Out Op Amp with Push-Pull Output
vi1M1 M2
M3 M4
M5
M6
M7
VDD
VSS
VBN+
-
Cc
M9
Cc
VBP+-
vi2
vo1 vo2RzRz
M8
Fig. 7.3-6
M10 M12
M13
M14
Comments:• Able to actively source and sink output current• Output quiescent current poorly defined
Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10) Page 280-6
CMOS Analog Circuit Design © P.E. Allen - 2010
Folded-Cascode, Differential Output Op Amp
060717-01
VPB1
M4 M5
I6 VPB2
I4 I5
VDD
I7M6 M7
VNB2
M8 M9
M10 M11
+−
vIN
vOUT
VNB1
I1 I2
M1 M2
M3I3
CL
VNB1
+−CL
• No longer has the low-frequency asymmetry in signal path gains.• Class A
Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10) Page 280-7
CMOS Analog Circuit Design © P.E. Allen - 2010
Enhanced-Gain, Folded-Cascode, Differential Output Op Amp
What about the A amplifier?Below is the upper A amplifier:
060718-02
VDD
VPB1
VPB2 VPB2
VNB1 VBias
vin+ vin
-
vout+vout
- M1M2 M3
M4
M5 M6
M7 M8
M9 M10
M11M12
Note that VBias controls the dc voltage at theinput of the A amplifier through the negativefeedback loop.
• Balanced inputs• Class A
060718-01
vOUT
M4M5
M3
M7
M8 M9
M10 M11
M6
VDD
VPB1
+
−vIN
M1 M2
VNB1
A+− +
−
+− +
−A
+−
VPB1
Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10) Page 280-8
CMOS Analog Circuit Design © P.E. Allen - 2010
Push-Pull Cascode Op Amp with Differential-OutputsVDD
VSS
VBias
R2 M22
M23
R1
M19
M20
M1 M2
M3 M4M5 M6M7 M8
M9 M10
M11
M12M13
M14
M15 M16M17
M18
M21
vo1vi1 vi2
vo2
Fig. 7.3-8
• Output quiescent currents are well defined• Self-biased circuits can be replaced with VNB2 and VPB2
Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10) Page 280-9
CMOS Analog Circuit Design © P.E. Allen - 2010
Folded-Cascode, Push-Pull, Differential Output Op Amp
060717-02
VPB1
M6 M7
I6
VPB2I4
I7
I9M8 M9
VNB2
M10 M11
M12 M13
+−
vIN
vOUTVNB1
I3
I2
M2 M3
M5I5
CL+−CL
I1
M1
VNB2
M18M19
M20M21
VPB1
M14 M15
I16 VPB2
I14 I15
VDD
I17M16 M17
M4
I8
0.5gm1vin
0.5gm3vin
0.5gm2vin
0.5gm4vin
0.5gm3vin
0.5gm4vin0.5gm2vin
0.5gm1vin
I6 = I7 = I14 = I15 > 0.5I5I5 = I1 + I2 + I3 + I4
Av = gmRout(diff)
Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10) Page 280-10
CMOS Analog Circuit Design © P.E. Allen - 2010
Enhanced-Gain, Folded-Cascode with Push-Pull Outputs
060718-06
VPB1
M6 M7
M8 M9
M20
M19
M18
M21
+−
vIN
VNB1
M2 M3
M5CL+−CL
M1
VNB2M14
M17M16
M15
VPB1
M10 M11
VPB2
VDD
M12 M13M4
vOUT
A+− +
−
+− +
−AVNB2
• Gain approaches gm3rds
3
Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10) Page 280-11
CMOS Analog Circuit Design © P.E. Allen - 2010
Cross-Coupled Differential Amplifier StageThe cross-coupled input stage allows the push-pull output quiescent current to be welldefined.
Operation:Voltage loop vi1 - vi2 = -VGS1+ vGS1 + vSG4 - VSG4 = VSG3 - vSG3 - vGS2 + VGS2
Using the notation for ac, dc, and total variables gives,vi2 - vi1 = vid = (vsg1 + vgs4) = -(vsg3 + vgs2)
If gm1 = gm2 = gm3 = gm4, then half of the differential input is applied across eachtransistor with the correct polarity.
i1 = gm1vid
2 = gm4vid
2 and i2 = -gm2vid
2 = -gm3vid
2
M1 M2
M3 M4
VGS2
VSG4
VGS1
VSG3
i1
i1i2
i2
vi1 vi2
Fig. 7.3-9
vGS1+
-
vSG4+
-vSG3
+
-
vGS2+
-
Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10) Page 280-12
CMOS Analog Circuit Design © P.E. Allen - 2010
Class AB, Differential Output Op Amp using a Cross-Coupled Differential InputStage
M1 M2
M3 M4
M5 M6
M7
VDD
VSS
VBias+
-
R1
M24
M25
R2
M27
M28
M8M9 M10
M11 M12
M13
M14
M15
M16
M17 M18
M19 M20
M21 M22
M26
M23
vo2
vi2vi1
vo1
Fig. 7.3-10
Quiescent output currents are defined by the current in the input cross-coupleddifferential amplifier.
Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10) Page 280-13
CMOS Analog Circuit Design © P.E. Allen - 2010
COMMON MODE OUTPUT VOLTAGE STABILIZATIONCommon Mode Feedback Circuits
Because the common mode gain is undefined, any common mode signal at the inputcan cause the output common mode voltage to be improperly defined. The commonmode output voltage is stabilized by sensing the common mode output voltage and usingnegative feedback to adjust the common mode voltage to the desired value.Model for the Output of Differential Output Op Amps:
VDD
io1(source) Ro1
vo1
io1(sink) Ro3
io2(source)
io2(sink)
Ro2
Ro4
vo2
VDD
io1(source) Ro1
vo1
Io1(sink) Ro3
io2(source)
Io2(sink)
Ro2
Ro4
vo2
Class A Output Push-Pull Output 060718-08
Roi represents the self-resistance of the output sink/sources.
1.) If the common mode output voltage increases the sourcing current is too large.2.) If the common mode output voltage decreases the sinking current is too large.
Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10) Page 280-14
CMOS Analog Circuit Design © P.E. Allen - 2010
Conceptual View of Common-Mode Feedback
060718-09
VDD
VCMREF
+
−
vo2vo1
OutputStageModel
Common ModeSensing Circuit
Function of the common-mode feedback circuit:1.) If the common-mode output voltage increases, decrease the upper currents sources orincrease the lower current sink until the common-mode voltage is equal to VCMREF.
2.) If the common-mode output voltage decreases, increase the upper currents sources ordecrease the lower current sink until the common-mode voltage is equal to VCMREF.
Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10) Page 280-15
CMOS Analog Circuit Design © P.E. Allen - 2010
Two-Stage, Miller, Differential-In, Differential-Out Op Amp with Common-ModeFeedback
vi1 M1 M2
M3 M4
M5
M6M7
VDD
VSS
VBN+-
Cc
M9
Cc
VBP
+
-
vi2
vo1vo2RzRz
M8
Fig. 7.3-12
M10 M11
Comments:• Simple• Unreferenced – value of common mode output voltage determined by the circuit
characteristics
Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10) Page 280-16
CMOS Analog Circuit Design © P.E. Allen - 2010
Common Mode Feedback CircuitsImplementation of common mode feedback circuit:
060718-10
vi1M1 M2
M3 M4
M5
VDD
IBias
VCM
vo1
MC2A
MC2B
MC1
MC3MC4
MC5MB
I3 I4IC4IC3
Common-mode feed-back circuit
Ro1 Ro2
vi2
vo2
This scheme can be applied to any differential output amplifier.CM Loop Gain = -gmC1Ro1 which can be large if the output of the differential outputamplifier is cascaded or a gain-enhanced cascode.The common-mode loop gain may need to be compensated for proper dynamicperformance.
Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10) Page 280-17
CMOS Analog Circuit Design © P.E. Allen - 2010
Common Mode Feedback Circuits – ContinuedThe previous circuit suffers when the input common mode voltage is low because thetransistors MC2A and MC2B have a poor negative input common mode voltage.The following circuit alleviates this disadvantage:
060718-11
vi1M1 M2
M3 M4
M5
VDD
IBias
VCM
vo2vo1
vi2MC2MC1
MC3
MC4
MC5MB
I3 I4
IC4IC3Common-mode feed-back circuit
RCM1 RCM2
Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10) Page 280-18
CMOS Analog Circuit Design © P.E. Allen - 2010
An Improved Common-Mode Feedback CircuitThe resistance loading of the previous circuit can be avoided in the following CMfeedback implementation:
VDD
060718-12
VCMREF
RCM RCM
vo1 vo2
CM Correction Circuitry
M1 M2 M3 M4
M5 M6
This circuit is capable of sustaining a large differential voltage without loading the outputof the differential output op amp.
Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10) Page 280-19
CMOS Analog Circuit Design © P.E. Allen - 2010
Frequency Response of the CM Feedback CircuitConsider the following CM feedback circuit implementation:
070506-02
VPB1
M4 M5
VPB2
VDD
M6 M7
VNB2M8
M10M11
+−
vIN
vOUT
VNB1
M1 M2
M3 VCMREF
+−
M9
M12
M13 M14
M15 M16
CcCc
The CM feedback path has two poles – one at the gates of M10 and M11 and thedominant output pole of the differential output op amp.Can compensate with Miller capacitors as shown.
Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10) Page 280-20
CMOS Analog Circuit Design © P.E. Allen - 2010
Improved CM Feedback Frequency ResponseThe circuit on the previous page can be modified to eliminate the pole at the gates ofM10 and M11 as follows:
060718-14
VPB1
M4 M5
VPB2
VDD
M6 M7
VNB2M8
M10 M11
+−
vin
vo1
VNB1
M1 M2
M3
VCMREF
M9
M12
M13 M14
M16M15
VNB1
VNB2
M17
M18M19
vo2
• The need for compensation of the common mode loop no longer exists since there isonly one dominant pole
• The dominant pole of the differential amplifier becomes the dominant pole of thecommon mode feedback
Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10) Page 280-21
CMOS Analog Circuit Design © P.E. Allen - 2010
A Common Mode Feedback Correction Scheme for Discrete Time ApplicationsCorrection Scheme:
Ccm+
-+-+
-vid
vo1
vo2CMbias
φ1 φ2
Ccm Vocm
φ1 φ2
φ1
φ1
φ1 Fig. 7.3-14 Operation:1.) During the 1 phase, both Ccm are charged to the desired value of Vocm and CMbias
= Vocm.
2.) During the 2 phase, the Ccm capacitors are connected between the differentialoutputs and the CMbias node. The average value applied to the CMbias node will beVocm.
Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10) Page 280-22
CMOS Analog Circuit Design © P.E. Allen - 2010
Example of a Common-Mode Output Voltage Stabilization Scheme for Discrete-Time ApplicationsCommon modeadjustment phase:Switches S1, S2 and S3are closed. C1 and C2are charged to the valuenecessary for I12 and I13to keep the commonmode output voltage atVCM.
Amplification phase:Switches S4 and S5 areclosed. If the commonmode output voltage isnot at VCM, the currentsI12 and I13 will changeto force the value of the common mode output voltage back to VCM.
070506-03
VPB1
M4 M5VPB2
VDD
M6 M7
VNB2M8
M10 M11
+−
vIN
vOUT
VNB1
M1 M2
M3VCM
+−
M9
M12 M13 M14
M15
C1
C2
VNB1
S4
S5
S1
S2
S3
I12
I13
Discrete time common mode correction circuit
Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10) Page 280-23
CMOS Analog Circuit Design © P.E. Allen - 2010
Correction of Channel Charge and Clock FeedthroughIn the discrete-time common mode correction schemes, the switches can introduce
error due to channel charge and clock feedthrough.Through simulation, these errors can be predicted and corrected by applying a
correction signal superimposed upon the error signal to achieve the desired (target)common mode voltage.General principle:
CMFBAmplifier
CMFBSense
DifferentialOutputs
VBias
Vcm (Target voltage)
Unwanted ChargeInjection Error
ErrorSignal
CorrectionSignal
ΔV
Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10) Page 280-24
CMOS Analog Circuit Design © P.E. Allen - 2010
SUMMARY• Advantages of differential output op amps:
- 6 dB increase in signal amplitude- Cancellation of even harmonics- Cancellation of common mode signals including clock feedthrough
• Disadvantages of differential output op amps:- Need for common mode output voltage stabilization- Compensation of common mode feedback loop- Difficult to interface with single-ended circuits
• Most differential output op amps are truly balanced• For push-pull outputs, the quiescent current should be well defined• Common mode feedback schemes include,
- Continuous time- Discrete time
Lecture 290 – Low Power and Low Noise Op Amps (3/28/10) Page 290-1
CMOS Analog Circuit Design © P.E. Allen - 2010
LECTURE 290 – LOW POWER AND LOW NOISE OP AMPSLECTURE ORGANIZATION
Outline• Review of subthreshold operation• Low power op amps• Review of MOSFET noise modeling and analysis• Low noise op amps• SummaryCMOS Analog Circuit Design, 2nd Edition ReferencePages 393-414
Lecture 290 – Low Power and Low Noise Op Amps (3/28/10) Page 290-2
CMOS Analog Circuit Design © P.E. Allen - 2010
REVIEW OF SUBTHRESHOLD OPERATIONSubthreshold OperationMost micropower op amps use transistors in the subthreshold region.Subthreshold characteristics:
The model that hasbeen developed forthe large signal sub-threshold operationis:
iD = It WL exp
vGS-VTnVt
1 +vDSVA
where vDS > 0 and VDS(sat) = VON = VGS -VT = 2nVt
Small-signal model:
gm = diDdvGS
|Q = It
WL
ItnVt
expvGS-VT
nVt1 +
vDSVA
= IDnVt
= qIDnkT =
IDVt
Cox
Cox+Cjs
gds = diD
dvDS |Q
IDVA
����100nA
1μA
Weak Inversion
Transition
Strong InversionSquare Law
Exponential
iD
vGS
iD
vDSVT
100nAvGS =VT
vGS ≤VT
Fig. 7.4-0A1V 2V000
0
Lecture 290 – Low Power and Low Noise Op Amps (3/28/10) Page 290-3
CMOS Analog Circuit Design © P.E. Allen - 2010
Boundary Between Subthreshold and Strong InversionIt is useful to develop a means of estimating when a MOSFET is making the transitionbetween subthreshold and strong inversion to know when to use the proper model.The relationship developed is based on the following concept:
We will solve for the value of vGS(actually vGS -VT) and find the draincurrent where these two values areequal [vGS(tran.) -VT)].
The large signal expressions for eachregion are:
Subthreshold-
iD It WL exp
vGS-VTnVt
vGS-VT = nVt lniD
It(W/L) nVt 1 -It(W/L)
iDif 0.5 < iD/(ItW/L).
Strong inversion-
iD = K'W2L vGS-VT
2 vGS-VT = 2iD
K'(W/L)
iD
vGSVT
iD = (vGS-VT)2K‘W2L
iD =nVt
vGS-VTItWL
exp( )iD(tran.)
vGS(tran.)070507-01
Lecture 290 – Low Power and Low Noise Op Amps (3/28/10) Page 290-4
CMOS Analog Circuit Design © P.E. Allen - 2010
Boundary Between Subthreshold and Strong Inversion - ContinuedEquating the two large signal expressions gives,
nVt 1 -It(W/L)
iD = 2iD
K'(W/L) n2Vt2 1 -
It(W/L)iD
2 =
2iDK'(W/L)
Expanding gives,
n2Vt2
It2(W/L)2
iD2 -2 It(W/L)
iD + 1 n2Vt2 =
2iDK'(W/L) if (ItW/L)/iD < 0.5
Therefore we get,
iD(tran.) = K'W2L n2Vt
2
For example, if K’ = 120μA/V2, W/L = 100, and n = 2, then at room temperature thevalue of drain current at the transition between subthreshold and strong inversion is
iD(tran.) = 120μA/V2100
2 4·(0.026)2 = 16.22μA
One will find for UDSM technology, that weak inversion or subthreshold operation canoccur at large currents for large values of W/L.
Lecture 290 – Low Power and Low Noise Op Amps (3/28/10) Page 290-5
CMOS Analog Circuit Design © P.E. Allen - 2010
LOW POWER OP AMPSTwo-Stage, Miller Op Amp Operating in Weak Inversion
-
+vin
M1 M2
M3 M4
M5
M6
M7
vout
VDD
VSS
VBias+
-
Cc
CL
Fig.7.4-1
Low frequency response:
Avo = gm2gm6 ro2ro4
ro2 + ro4
ro6ro7ro6 + ro7
= 1
n2n6(kT/q)2( 2 + 4)( 6 + 7) (No longer 1ID
)
GB and SR:
GB = ID1
(n1kT/q)C and SR = ID5C = 2
ID1C = 2GB n1
kTq = 2GBn1Vt
Lecture 290 – Low Power and Low Noise Op Amps (3/28/10) Page 290-6
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 290-1 Gain and GB Calculations for Subthreshold Op Amp.Calculate the gain, GB, and SR of the op amp shown above. The currents are ID5 =
200 nA and ID7 = 500 nA. The device lengths are 1 μm. Values for n are 1.5 and 2.5 forp-channel and n-channel transistors respectively. The compensation capacitor is 5 pF.The channel length modulation parameters are N = 0.06V-1 and P = 0.08V-1. Assumethat the temperature is 27 °C. If VDD = 1.5V and VSS = -1.5V, what is the powerdissipation of this op amp?SolutionThe low-frequency small-signal gain is,
Av = 1
(1.5)(2.5)(0.026)2(0.06 + 0.08)(0.06 + 0.08) = 20,126 V/VThe gain bandwidth is
GB = 100x10-9
2.5(0.026)(5x10-12) = 307,690 rps 49.0 kHzThe slew rate is
SR = (2)(307690)(2.5)(0.026) = 0.04 V/μsThe power dissipation is,
Pdiss = 3(0.7μA) =2.1μW
Lecture 290 – Low Power and Low Noise Op Amps (3/28/10) Page 290-7
CMOS Analog Circuit Design © P.E. Allen - 2010
Push-Pull Output Op Amp in Weak InversionFirst stage gain is,
Avo = gm2gm4
= ID2n4VtID4n2Vt
= ID2n4ID4n2
1
Total gain is,
Avo = gm1(S6/S4)(gds6 + gds7) =
(S6/S4)( 6 + 7)n1Vt
At room temperature (Vt = 0.0259V) andfor typical device lengths, gains of 60dBcan be obtained.The GB is,
GB = gm1
C S6S4 =
gm1bC
where b is the current ratio between M4:M6 and M3:M8.
vou
VDD
VSS
VBias+
-
Cc
M1 M2
M3 M4
M5
M6
M7
M8
M9
vi2
Fig. 7.4-2
Lecture 290 – Low Power and Low Noise Op Amps (3/28/10) Page 290-8
CMOS Analog Circuit Design © P.E. Allen - 2010
Increasing the Gain of the Previous Op Amp1.) Can reduce the currents in M3and M4 and introduce gain in thecurrent mirrors.2.) Use a cascode output stage(can’t use self-biased cascode,currents are too low).
Av = gm1+gm2
2 Rout
= gm1
gds6gds10
gm10+
gds7gds11
gm11
=
I52nnVt
I72 n2
I7nnVt
+I72 p2
I7npVt
= I5
2I7 1
nnVt2(nn n
2+np p2)
Can easily achieve gains greater than 80dB with power dissipation of less than 1μW.
M6
M7
vout
VDD
VSS
VBias
+
-
Cc
M1 M2
M3 M4
M5
M8
M9
vi2
M10
M11M12
M13M14
M15
vi1
I5
+
-
VT+2VON
+
-
VT+2VON
Fig. 7.4-3A
Lecture 290 – Low Power and Low Noise Op Amps (3/28/10) Page 290-9
CMOS Analog Circuit Design © P.E. Allen - 2010
Increasing the Output Current for Weak Inversion OperationA significant disadvantage of the weak inversion is that very small currents are availableto drive output capacitance so the slew rate becomes very small.Dynamically biased differential amplifier input stage:
Note that the sinking current for M1 and M2 isIsink = I5 + A(i2-i1) + A(i1-i2) where (i2-i1) and (i1-i2) are only positive or zero.
If vi1>vi2, then i2>i1 and the sinking current is increased by A(i2-i1).
If vi2>vi1, then i1>i2 and the sinking current is increased by A(i1-i2).
Lecture 290 – Low Power and Low Noise Op Amps (3/28/10) Page 290-10
CMOS Analog Circuit Design © P.E. Allen - 2010
Dynamically Biased Differential Amplifier - ContinuedHow much output current is available from this circuit if there is no current gain from theinput to output stage?Assume transistors M18 through M21 are equal to M3 and M4 and that transistors M22through M27 are all equal.
LetW28
L28 = A
W26
L26 and
W29
L29 = A
W27
L27
The output current available can be found by assuming that vin = vi1-vi2 > 0.
i1 + i2 = I5 + A(i2-i1)
The ratio of i2 to i1 can be expressed as
i2i1 = exp
vin
nVt
If the output current is iOUT = b(i2-i1) then combining the above two equations gives,
iOUT = bI5 exp
vin
nVt- 1
(1+A) - (A-1)expvin
nVt
iOUT = when A = 2.16 and vin
nVt = 1
where b corresponds to any current gain through current mirrors (M6-M4 and M8-M3).
Lecture 290 – Low Power and Low Noise Op Amps (3/28/10) Page 290-11
CMOS Analog Circuit Design © P.E. Allen - 2010
Overdrive of the Dynamically Biased Differential AmplifierThe enhanced output current isaccomplished by the use of positivefeedback (M28-M2-M19-M28).The loop gain is,
LG = gm28
gm4
gm19
gm26 = A
gm19
gm4 = A
Note that as the output currentincreases, the transistors leave the weakinversion region and the above analysisis no longer valid.
A = 0
A = 0.3A = 1
A = 1.5
A = 2
IOUT
I5
2
1
00 1 2
vIN nVt Fig. 7.4-5
Lecture 290 – Low Power and Low Noise Op Amps (3/28/10) Page 290-12
CMOS Analog Circuit Design © P.E. Allen - 2010
Increasing the Output Current for Strong Inversion OperationAn interesting technique is to bias the output transistor of a current mirror in the activeregion and then during large overdrive cause the output transistor to become saturatedcausing a significant current gain.Illustration:
+Vds2
-
i1 i2
M1 M2
070507-02
Vds1(sat)=Vds2(sat)0.1Vds2(sat)
100µA
530µA
i2 for W2/L2 = 5.3(W1/L1)
Volts
Cur
rent
i2 for W2/L2 = W1/L1+
VGS-
VGS
VGS
Lecture 290 – Low Power and Low Noise Op Amps (3/28/10) Page 290-13
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 290-2 Current Mirror with M2 operating in the Active RegionAssume that M2 has a voltage across the drain-source of 0.1Vds(sat). Design the
W2/L2 ratio so that I1 = I2 = 100μA if W1/L1 = 10. Find the value of I2 if M2 issaturated.Solution
Using the value of KN’ = 120μA/V2, we find that the saturation voltage of M2 is
Vds1(sat) = 2I1
KN’ (W2/L2) = 200
120·10 = 0.408V
Now using the active equation of M2, we set I2 = 100μA and solve for W2/L2.
100μA = KN’(W2/L2)[Vds1(sat)·Vds2 - 0.5Vds22]
= 120μA/V2 (W2/L2)[0.408·0.0408 - 0.5·0.04082]V2 = 1.898x106(W2/L2)
Thus,
100 =1.898(W2/L2)W2L2 = 52.7 53
Now if M2 should become saturated, the value of the output current of the mirror with100μA input would be 530μA or a boosting of 5.3 times I1.
Lecture 290 – Low Power and Low Noise Op Amps (3/28/10) Page 290-14
CMOS Analog Circuit Design © P.E. Allen - 2010
Implementation of the Current Mirror Boosting ConceptVDD
VSS
i1
i1
i2
i2
i2 i2i1 i1
ki2 ki1
ki1
M8
M7
M5
M6
M10
M14
M16
M12
M11
M15
M13
M9
M17
M18
M19
M20
M21 M22
M23 M24
vo2vo1
Fig.7.4-7
M1 M2
M3 M4
VBias
+
-
M25 M26
M27 M28
M29 M30
vi2vi1
ki2
k = overdrive factor of the current mirror
Lecture 290 – Low Power and Low Noise Op Amps (3/28/10) Page 290-15
CMOS Analog Circuit Design © P.E. Allen - 2010
A Better Way to Achieve the Current Mirror BoostingIt was found that when the current mirror boosting idea illustrated on the previous slidewas used that when the current increased through the cascode device (M16) that VGS16increased limiting the increase of VDS12. This can be overcome by the following circuit.
M1 M2
M3
M4M5
VDD
iin+IB iin
kiin
IB
1/1
1/1 1/1
50/1
210/1
Fig. 7.4-7A
Lecture 290 – Low Power and Low Noise Op Amps (3/28/10) Page 290-16
CMOS Analog Circuit Design © P.E. Allen - 2010
REVIEW OF MOSFET NOISE MODELING AND ANALYSISTransistor Noise Sources (Low-Frequency)Drain current model:
i 2n1
D
G
S
D
G
S
M1 M1
M1 isnoiseless
M1 isnoisy
Fig. 7.5-0A
i2n =
8kTgm
3 +(KF)IDfCoxL2
or i2n =
8kTgm(1+ )3 +
(KF)IDfCoxL2
if vBS 0
Recall that = gmbs
gm
Gate voltage model assuming common source operation:
e2n =
i2N
gm2 =
8kT3gm
+KF
2fCoxWLK’ or
e2n =
8kT3gm(1+ ) +
KF2fCoxWLK’ if vBS 0
D
G
S
D
G
S
M1 M1
M1 isnoiseless
M1 isnoisy
Fig. 7.5-0C
e2n1
*
Lecture 290 – Low Power and Low Noise Op Amps (3/28/10) Page 290-17
CMOS Analog Circuit Design © P.E. Allen - 2010
Minimization of Noise in Op Amps1.) Maximize the signal gain as close to the input as possible. (As a consequence, only
the input stage will contribute to the noise of the op amp.)2.) To minimize the 1/f noise:
a.) Use PMOS input transistors with appropriately selected dc currents and W and Lvalues.
b.) Use lateral BJTs to eliminate the 1/f noise.c.) Use chopper stabilization to reduce the low-frequency noise.
Noise Analysis1.) Insert a noise generator for each transistor that contributes to the noise. (Generally
ignore the current source transistor of source-coupled pairs.)2.) Find the output noise voltage across an open-circuit or output noise current into a
short circuit.3.) Reflect the total output noise back to the input resulting in the equivalent input noise
voltage.
Lecture 290 – Low Power and Low Noise Op Amps (3/28/10) Page 290-18
CMOS Analog Circuit Design © P.E. Allen - 2010
LOW NOISE OP AMPSA Low-Noise, Two-Stage, Miller Op Amp
M3 M4
M6
vout
VDD
VSS
VBias
Cc
+
-
vin+
-M1 M2
M8 M9
M7M5
M10
M11
Fig. 7.5-1
VDD
VSS
e2n3 e2
n4
VBias VBias
M1 M2
M3 M4
M8 M9
e2n2
e2n1
e2n6
e2n7
I5M7
M6
e2to
VSG7
*
*
*
*
* *
e2n8
*
e2n9
*
The total output-noise voltage spectral density, e2to, is as follows where gm8(eff) 1/rds1,
e2to = gm6
2RII2 e2n6+e
2n7 +RI2 gm12e
2n1+gm22e
2n2+gm32e
2n3+gm42e
2n4 + (e
2n8/rds12) + (e
2n9/rds22)
Divide by (gm1RIgm6RII)2 to get the eq. input-noise voltage spectral density, e2eq, as
e2eq =
e2to
(gm1gm6RIRII)2 = 2e
2n6
gm12RI2 + 2e
2n1 1+
gm3gm1
2 e2
n3
e2
n1+
e2
n8
gm12rds12e2
n1 2e
2n1 1+
gm3
gm1
2 e2n3
e2n1
where e 2n6 = e 2
n7, e 2n3 = e 2
n4, e 2n1 = e 2
n2 and e 2n8 = e 2
n9 and gm1RI is large.
Lecture 290 – Low Power and Low Noise Op Amps (3/28/10) Page 290-19
CMOS Analog Circuit Design © P.E. Allen - 2010
1/f Noise of a Two-Stage, Miller Op AmpConsider the 1/f noise:Therefore the noise generators are replaced by,
e2ni =
Bf WiLi
(V2/Hz) and i2ni =
2BK’IifLi2
(A2/Hz)
Therefore, the approximate equivalent input-noise voltage spectral density is,
e2eq = 2e
2n1 1 +
KN’BNKP’BP
L1L3
2 (V2/Hz)
Comments;
• Because we have selected PMOS input transistors, e2
n1 has been minimized if wechoose W1L1 (W2L2) large.
• Make L1<<L3 to remove the influence of the second term in the brackets.
Lecture 290 – Low Power and Low Noise Op Amps (3/28/10) Page 290-20
CMOS Analog Circuit Design © P.E. Allen - 2010
Thermal Noise of a Two-Stage, Miller Op AmpLet us focus next on the thermal noise:The noise generators are replaced by,
e2ni
8kT3gm
(V2/Hz) and i2ni
8kTgm3 (A2/Hz)
where the influence of the bulk has been ignored.The approximate equivalent input-noise voltage spectral density is,
e2eq = 2e
2n1 1+
gm3gm1
2 e2n3
e2n1
= 2e2n1 1 +
KNW 3L1KPW 1L3
(V2/Hz)
Comments:• The choices that reduce the 1/f noise also reduce the thermal noise.
Noise Corner:Equating the equivalent input-noise voltage spectral density for the 1/f noise and thethermal noise gives the noise corner, fc, as
fc = 3gmB
8kTWL
Lecture 290 – Low Power and Low Noise Op Amps (3/28/10) Page 290-21
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 290-3 Design of A Two-Stage, Miller Op Amp for Low 1/f Noise
Use the model parameters of KN’ = 120μA/V2, KP’ = 25μA/V2, and Cox = 6fF/μm2
along with the value of KF = 4x10-28 F·A for NMOS and 0.5x10-28 F·A for PMOS anddesign the previous op amp with ID5 = 100μA to minimize the 1/f noise. Calculate thecorresponding thermal noise and solve for the noise corner frequency. From thisinformation, estimate the rms noise in a frequency range of 1Hz to 100kHz. What is thedynamic range of this op amp if the maximum signal is a 1V peak-to-peak sinusoid?Solution1.) The 1/f noise constants, BN and BP are calculated as follows.
BN = KF
2CoxKN’ = 4x10-28F·A
2·60x10-4F/m2·120x10-6A/V2 = 1.33x10-22 (V·m)2
and
BP = KF
2CoxKP’ = 0.5x10-28F·A
2·60x10-4F/m2·25x10-6A/V2 = 1.67x10-22 (V·m)2
2.) Now select the geometry of the various transistors that influence the noiseperformance.
To keep e2n1 small, let W1 = 100μm and L1 = 1μm. Select W3 = 10μm and L3 =
20μm and letW8 and L8 be the same as W1 and L1 since they little influence on thenoise.
Lecture 290 – Low Power and Low Noise Op Amps (3/28/10) Page 290-22
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 290-3 - ContinuedOf course, M1 is matched with M2, M3 with M4, and M8 with M9.
e2n1 =
BPf W1L1
= 1.67x10-22
f·100μm·1μm = 1.67x10-12
f (V2/Hz)
e2eq = 2x
1.67x10-12
f 1 +120·1.3325·1.67
2 120
2 = 3.33x10-12
f 1.0365 = 3.452x10-12
f (V2/Hz)
Note at 100Hz, the voltage noise in a 1Hz band is 3.45x10-14V2(rms) or 0.186μV(rms).3.) The thermal noise at room temperature is
e2n1 =
8kT3gm
= 8·1.38x10-23·300
3·500x10-6 = 2.208x10-17 (V2/Hz)
which gives
e2eq = 2·2.208x10-17 1 +
120·10·125·100·20 = 4.416x10-17·1.155= 5.093x10-17 (V2/Hz)
4.) The noise corner frequency is found by equating the two expressions for e2eq to get
fc = 3.452x10-12
5.093x10-17 = 67.8kHz
This noise corner is indicative of the fact that the thermal noise is much less than the 1/fnoise.
Lecture 290 – Low Power and Low Noise Op Amps (3/28/10) Page 290-23
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 290-1 - Continued5.) To estimate the rms noise in the bandwidth from 1Hz to 100,000Hz, we will ignorethe thermal noise and consider only the 1/f noise. Performing the integration gives
Veq(rms)2 = 1
105
3.452x10-12
f df = 3.452x10-12[ln(100,000) - ln(1)] =
0.408x10-10 Vrms2 = 6.39 μVrmsThe maximum signal in rms is 0.353V. Dividing this by 6.39μV gives 55,279 or 94.85dBwhich is equivalent to more than 15 bits of resolution.6.) Note that the design of the remainder of the op amp will have little influence on thenoise and is not included in this example.
Lecture 290 – Low Power and Low Noise Op Amps (3/28/10) Page 290-24
CMOS Analog Circuit Design © P.E. Allen - 2010
Low-Noise Op Amp using Lateral BJT’s at the Input
vout
VDD
VSS
Cc = 1pF
VSS
Q1 Q2
M3 M4
M5
M6
M7
M8 M9
M10 M11
M12
M13M14
M15M16
R1=34kΩ
D1
Rz = 300Ω
48018
48018
1303.6
43.86.6
45.63.6
81.63.6
5113.61296
3.6
3841.2
2701.246.8
3.6
46.83.6
58.27.2
58.27.2
vi1vi2
Fig. 7.5-6
0
2
4
6
8
10
10 100 1000 104 105
Frequency (Hz)
Noi
se (
nV/
Hz) Eq. input noise voltage of low-noise op amp
Voltage noise of lateral BJT at 170μA
Fig. 7.5-7
Experimental noiseperformance:
Lecture 290 – Low Power and Low Noise Op Amps (3/28/10) Page 290-25
CMOS Analog Circuit Design © P.E. Allen - 2010
Summary of Experimental Performance for the Low-Noise Op AmpExperimental Performance Value
Circuit area (1.2μm) 0.211 mm2
Supply Voltages ±2.5 VQuiescent Current 2.1 mA-3dB frequency (at a gain of 20.8 dB) 11.1 MHzen at 1Hz 23.8 nV/ Hzen (midband) 3.2 nV/ Hzfc(en) 55 Hzin at 1Hz 5.2 pA/ Hzin (midband) 0.73 pA/ Hzfc(in) 50 HzInput bias current 1.68 μAInput offset current 14.0 nAInput offset voltage 1.0 mVCMRR(DC) 99.6 dBPSRR+(DC) 67.6 dBPSRR-(DC) 73.9 dBPositive slew rate (60 pF, 10 k load) 39.0 V/μSNegative slew rate (60 pF, 10 k load) 42.5 V/μS
Lecture 290 – Low Power and Low Noise Op Amps (3/28/10) Page 290-26
CMOS Analog Circuit Design © P.E. Allen - 2010
Chopper-Stabilized Op Amps - Doubly Correlated Sampling (DCS)Illustration of the use of chopper stabilization to remove the undesired signal, vu, form thedesired signal, vin.
+1
-1t
T fc = 1
vin
vu
voutvB vC
Vin(f)
Vu(f)
VB(f)
ffc0 2fc
f
f
3fcVC(f)
ffc0 2fc 3fc
A1 A2
Clock
VA(f)
ffc0 2fc 3fc
vA
Fig. 7.5-8
Lecture 290 – Low Power and Low Noise Op Amps (3/28/10) Page 290-27
CMOS Analog Circuit Design © P.E. Allen - 2010
Chopper-Stabilized AmplifierVDD
VSS
φ1
φ1
φ2
φ2
IBias
M1 M2
M3 M4
+
-
vin
VDD
VSS
φ1
φ1
φ2
φ2
IBias
M5 M6
M7 M8
Circuit equivalent during φ1 phase:
A1
+
-
-
+
A2
+
-
-
+
vu2vu1
vueq
Circuit equivalent during the φ2 phase:
A1
+
-
-
+
A2
+
-
-
+
vu2vu1
vueq
vueq = vu1 + vu2A1
vueq = -vu1 + A1
vu2 , vueq(aver) = vu2A1
Fig. 7.5-10
Chopper-stabilized Amplifier:
Lecture 290 – Low Power and Low Noise Op Amps (3/28/10) Page 290-28
CMOS Analog Circuit Design © P.E. Allen - 2010
Example of a Two-Stage, Chopper-Stablized Op Amp
070507-03
clkb
clk
clk
clkb
vnn
vnn
vnp
vnpVDD
clk clkb
clkclkb
clkb
clkclk
clkb
vnn
vnn
vnp
vnpVDD
VDD
M1 M2
M3 M4
Cc
M5VNB1M7
vout
M6
Lecture 290 – Low Power and Low Noise Op Amps (3/28/10) Page 290-29
CMOS Analog Circuit Design © P.E. Allen - 2010
Experimental Noise Response of the Chopper-Stabilized Amplifier
10
100
1000
0 10 20 30 40 50Frequency (kHz)
nV/
Hz
Without chopper
With chopperfc = 16kHz
With chopper fc = 128kHz
Fig. 7.5-11
Comments: • The switches in the chopper-stabilized op amp introduce a thermal noise equal to kT/C
where k is Boltzmann’s constant, T is absolute temperature and C are capacitorscharged by the switches (parasitics in the case of the chopper-stabilized amplifier).
• Requires two-phase, non-overlapping clocks. • Trade-off between the lowering of 1/f noise and the introduction of the kT/C noise.
Lecture 290 – Low Power and Low Noise Op Amps (3/28/10) Page 290-30
CMOS Analog Circuit Design © P.E. Allen - 2010
Improved Chopper OperationIn some cases, there are spurious signals in the neighborhood of the chopping
frequencies and its harmonics. These spurious signals such as common-modeinterference can mix to the baseband since the chopper amplifier is a time variant systemand therefore inherently nonlinear.
A bandpass filter centered atthe clock frequency can be used toeliminate the aliasing of thespurious signals and achieve areduction in effective offset.
Let = fc - fo
fo and be a given
bound of . It can be shown† thatthe achievable effective offset reduction, EOR, and the optimum Q for the bandpass filter,Qopt, is
EOR = 8Q
(1 + 8Q2 ) , <<1 and Qopt = 1/ 8
Improvements of 14dB reduction in effective offset are possible for = 0.8%.
† C. Menolfi and Q. Huang, “A Fully Integrated, Untrimmed CMOS Instrumentation Amplifier with Submicrovolt Offset,” IEEE J. of Solid-StateCircuits, vol. 34, no.8, March 1999, pp. 415-420.
Bandpass Filter
fc
InputModulator
InputAmplifier
OutputAmplifier
OutputModulator
vin vou
fo
041006-03
Lecture 290 – Low Power and Low Noise Op Amps (3/28/10) Page 290-31
CMOS Analog Circuit Design © P.E. Allen - 2010
SUMMARY• Operation of transistors for low power op amps is generally in weak inversion• Boosting techniques are needed to get output sourcing and sinking currents that are
larger than that available during quiescent operation• Be careful about using circuits at weak inversion, i.e. the self-biased cascode will cause
the resistor to be too large• Primary sources of noise for CMOS circuits is thermal and 1/f• Noise analysis:
1.) Insert a noise generator for each transistor that contributes to the noise.(Generally ignore the current source transistor of source-coupled pairs.)
2.) Find the output noise voltage across an open-circuit or output noise current into ashort circuit.
3.) Reflect the total output noise back to the input resulting in the equivalent inputnoise voltage.
• Noise is reduced in op amps by making the input stage gain as large as possible andreducing the noise of this stage as much as possible.
• The input stage noise can be reduced by using lateral BJTs (particularily the 1/f noise)• Doubly correlated sampling can transfer the noise at low frequencies to the clock
frequency (this technique is used to achieve low input offset voltage op amps).
Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-1
CMOS Analog Circuit Design © P.E. Allen - 2010
LECTURE 300 – LOW VOLTAGE OP AMPSLECTURE ORGANIZATION
Outline• Introduction• Low voltage input stages• Low voltage gain stages• Low voltage bias circuits• Low voltage op amps• SummaryCMOS Analog Circuit Design, 2nd Edition ReferencePages 415-432
Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-2
CMOS Analog Circuit Design © P.E. Allen - 2010
INTRODUCTIONImplications of Low-Voltage, Strong-Inversion Operation• Reduced power supply means decreased dynamic range• Nonlinearity will increase because the transistor is working close to VDS(sat)
• Large values of because the transistor is working close to VDS(sat)
• Increased drain-bulk and source-bulk capacitances because they are less reversebiased.
• Large values of currents and W/L ratios to get high transconductance• Small values of currents and large values of W/L will give smallVDS(sat)
• Severely reduced input common mode range• Switches will require charge pumps
Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-3
CMOS Analog Circuit Design © P.E. Allen - 2010
What are the Limits of Power Supply?The limit comes when there is no signal range left when the dc drops are subtracted fromVDD.
Minimum power supply (no signal swing range):
VDD(min.) = VT + 2VON
For differential amplifiers, the minimum powersupply is:
VDD(min.) = 3VON
However, to have any input common mode range, theeffective minimum power supply is,
VDD(min.) = VT + 2VON
060802-01
VDD
VPB1
VNB1
M1
M2 M3
M4
+
−
VON
VT+VON
+
−
+
−VT+VON
VON
+
−
060802-02
VPB1
VDD
VNB1
+
−VON
+
−VON
+
−VON +
−VT+VON
+
−VT+VON
M1 M2
M3 M4
M5
Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-4
CMOS Analog Circuit Design © P.E. Allen - 2010
Minimum Power Supply Limit – ContinuedThe previous consideration of the differential amplifier did not consider getting the signalout of the amplifier. This will add another VON.
060802-03
VPB1
VDD
VNB1
+
−VON
+
−VON
+
−VON +
−VT+VON
+
−VT+VON
M1 M2
M3 M4
M5
VPB1
VPB2M6
M7 M8
M9
+
−VON
VT+VON+
−
VT
Therefore,VDD(min.) = VT + 3VON
This could be reduced to 3VON with the floating battery but its implementation probablyrequires more than 3VON of power supply.
Note the output signal swing is VT + VON while the input common range is VON.
Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-5
CMOS Analog Circuit Design © P.E. Allen - 2010
LOW VOLTAGE INPUT STAGESInput Common Mode Voltage RangeMinimum power supply (ICMR = 0):
VDD(min) = VSD3(sat)-VT1+VGS1+VDS5(sat) = VSD3(sat)+VDS1(sat)+VDS5(sat)
Input common-mode range:Vicm(upper) = VDD - VSD3(sat) + VT1
Vicm(lower) = VDS5(sat) + VGS1
If the threshold magnitudes are 0.7V, VDD =1.5V and the saturation voltages are 0.3V, then
Vicm(upper) = 1.5 - 0.3 + 0.7 = 1.9V
and Vicm(lower) = 0.3 + 1.0 = 1.3V
giving an ICMR of 0.6V.
vicm M1 M2
M3 M4
M5
VDD
VDS5(sat)VBias
+
-
VBias+
-
VGS1
-VT1
VSD3(sat)
Fig. 7.6-3
Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-6
CMOS Analog Circuit Design © P.E. Allen - 2010
Increasing ICMR using Parallel Input StagesTurn-on voltage for the n-channel input:
Vonn = VDSN5(sat) + VGSN1
Turn-on voltage for the p-channel input:Vonp = VDD - VSDP5(sat) - VSGP1
The sum of Vonn and Vonp equals the minimumpower supply.
Regions of operation:VDD > Vicm > Vonp: (n-channel on and p-channel off) gm(eq) = gmN
Vonp Vicm Vonn: (n-channel on and p-channel on) gm(eq) = gmN + gmP
Vonn > Vicm > 0 : (n-channel off and p-channel on) gm(eq) = gmP
where gm(eq) is the equivalent input transconductance of the above input stage, gmN isthe input transconductance for the n-channel input and gmP is the input trans-conductance for the p-channel input.
VDD
MN1 MN2MP1 MP2
MP3MP4
MP5MN3MN4
MN5
IBias
M6
M7
Fig. 7.6-4
Vicm Vicm
0 VSDP5(sat)+VGSN1 VDD-VSDP5(sat)+VGSN1 VDD
gmN+gmP
gmNgmP
gm(eff)
Vicm
n-channel onn-channel off n-channel onp-channel onp-channel on p-channel off
Fig. 7.6-5
Vonn Vonp
Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-7
CMOS Analog Circuit Design © P.E. Allen - 2010
Removing the Nonlinearity in Transconductances as a Function of ICMRIncrease the bias current in the differentialamplifier that is on when the otherdifferential amplifier is off.
Three regions of operation depending on thevalue of Vicm:
1.) Vicm < Vonn: n-channel diff. amp. offand p-channel on with Ip = 4Ib:
gm(eff) = KP’W P
LP 2 Ib
2.) Vonn < Vicm < Vonp: both on with
In = Ip = Ib:
gm(eff) = KN’W N
LN Ib +
KP’W P
LP Ib
3.) Vicm > Vonp: p-channel diff. amp. off and n-channel on with In = 4Ib:
gm(eff) = KN’W N
LN 2 Ib
VDD
Ib
Ib1:3
3:1
MN1
MP1 MP2
MN2MB2 MB1
VB2 VB1
Inn
Ipp
Ip
In
VicmVicm
Fig. 7.6-6
Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-8
CMOS Analog Circuit Design © P.E. Allen - 2010
How Does the Current Compensation Work?Set VB1 = Vonn and VB2 = Vonp.
VonnMN1 MN2
MB1vicmvicm
IppIn
IbIf vicm >Vonn then In = Ib and Ipp=0
If vicm <Vonn then In = 0 and Ipp=Ib
VDD
Vonp
MP1 MP2
MB2vicmvicm
Inn Ip
IbIf vicm <Vonp then Ip = Ib and Inn=0
If vicm >Vonp then Ip = 0 and Inn=Ib
Fig. 7.6-6A
Result:gm(eff)
Vonn Vonp VDD
Vicm00
gmN=gmP
Fig. 7.6-7
The above techniques and many similar ones are good for power supply values down toabout 1.5V. Below that, different techniques must be used or the technology must bemodified (natural devices).
Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-9
CMOS Analog Circuit Design © P.E. Allen - 2010
Natural TransistorsNatural or native NMOS transistors normally have a threshold voltage around 0.1Vbefore the threshold is increased by increasing the p concentration in the channel.If these transistors are characterized, then they provide a means of achieving low voltageoperation.Minimum power supply (ICMR = 0):
VDD(min) = 3VON
Input common mode range:Vicm(upper) = VDD – VON + VT(natural)
Vicm(lower) = 2VON + VT(natural)
If VT(natural) VON = 0.1V, then
Vicm(upper) = VDD
Vicm(lower) = 3VON = 0.3V
Therefore,
ICMR = VDD - 3VON = VDD – 0.3V VDD(min) 1V
Matching tends to be better (less doping and magnitude is smaller).
Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-10
CMOS Analog Circuit Design © P.E. Allen - 2010
Bulk-Driven MOSFETA depletion device would permit large ICMR even with very small power supply voltagesbecause VGS is zero or negative.When a MOSFET is driven from the bulk with the gate held constant, it acts like adepletion transistor.Cross-section of an n-channelbulk-driven MOSFET:
Large signal equation:
iD = KN’W
2L VGS - VT0 - 2| F| - vBS + 2| F| 2
Small-signal transconductance:
gmbs = (2KN’W/L)ID
2 2| F| - VBS
����
p-well
n+
����n+
����n+
����p+ Channel
����������������
QP
QV
Bulk Drain Gate Source Substrate
VDDVGSVDSvBS
DepletionRegion
n substrateFig. 7.6-8
Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-11
CMOS Analog Circuit Design © P.E. Allen - 2010
Bulk-Driven MOSFET - ContinuedTransconductance characteristics:
Saturation: VDS > VBS – VP gives,
VBS = VP + VON
iD = IDSS 1 -VBSVP
2
Comments:• gm (bulk) > gm(gate) if VBS > 0
(forward biased )• Noise of both configurations are the same (any differences comes from the gate versus
bulk noise)• Bulk-driven MOSFET tends to be more linear at lower currents than the gate-driven
MOSFET• Very useful for generation of IDSS floating current sources.
0
500
1000
1500
2000
-3 -2 -1 0 1 2 3
Dra
in C
urre
nt (μ
A)
Gate-Source or Bulk-Source Voltage (Volts)
IDSS
Bulk-source driven
Gate-sourcedriven
Fig. 7.6-9
Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-12
CMOS Analog Circuit Design © P.E. Allen - 2010
Bulk-Driven, n-channel Differential AmplifierWhat is the ICMR?
Vicm(min) = VSS + VDS5(sat) + VBS1 = VSS + VDS5(sat) - |VP1| + VDS1(sat)
Note that Vicm can be less than VSS if |VP1| > VDS5(sat) + VDS1(sat)
Vicm(max) = ?
As Vicm increases, the current throughM1 and M2 is constant so the sourceincreases. However, the gate voltage staysconstant so that VGS1 decreases. Since thecurrent must remain constant through M1and M2 because of M5, the bulk-sourcevoltage becomes less negative causing VTN1
to decrease and maintain the currentsthrough M1 and M2 constant. If Vicm isincreased sufficiently, the bulk-sourcevoltage will become positive. However,current does not start to flow until VBS isgreater than 0.3 volts so the effectiveVicm(max) is
Vicm(max) VDD - VSD3(sat) - VDS1(sat) + VBS1.
VDD
VSS
M1 M2
M3 M4
M5M6
M7
IBiasvi1 vi2
Fig. 7.6-10
+ VBS1-
+ VBS2-
+ VGS-
Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-13
CMOS Analog Circuit Design © P.E. Allen - 2010
Illustration of the ICMR of the Bulk-Driven, Differential Amplifier
-50nA
0
50nA
100nA
150nA
Bul
k-So
urce
Cur
rent
Input Common-Mode Voltage-0.50V -0.25V 0.00V 0.25V 0.50V
200nA
250nA
Fig. 7.6-10A
Comments:• Effective ICMR is from VSS to VDD -0.3V
• The transconductance of the input stage can vary as much as 100% over the ICMRwhich makes it very difficult to compensate
Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-14
CMOS Analog Circuit Design © P.E. Allen - 2010
Reduction of VT through Forward Biasing the Bulk-Source
The bulk can be used to reduce the threshold sufficiently to permit low voltageapplications. The key is to control the amount of forward bias of the bulk-source.Current-Driven Bulk Technique†:
IBB
S
G
D
B
IBB
S
G
D
BIE
ICD ICS
Reduced Threshold MOSFET Parasitic BJT
n-well
p+ p+
n+
����
Source Drain
Gate
p- substrateLayout Fig. 7.6-19
Problem:Want to limit the BJT current to some value called, Imax.Therefore,
IBB = Imax
CS + CD + 1
† T. Lehmann and M. Cassia, “1V Power Supply CMOS Cascode Amplifier,” IEEE J. of Solid-State Circuits, Vol. 36, No. 7, 2001.
Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-15
CMOS Analog Circuit Design © P.E. Allen - 2010
Current-Driven Bulk TechniqueBias circuit for keeping the Imax definedindependent of BJT betas.
Note:ID,C = ICD + IDIS,E = ID + IE + IR
The circuit feedback causes a bulk biascurrent IBB and hence a bias voltage VBIASsuch that
IS,E = ID + IBB(1+ CS + CD) + IRUse VBias1 and VBias2 to set ID,C 1.1ID,IS,E 1.3ID and IR 0.1ID which sets IBB at 0.1ID assuming we can neglect ICS withrespect to ICD.
For this circuit to work, the following conditions must be satisfied:VBE < VTN + IRR and |VTP| + VDS(sat) < VTN + IRR
If |VTP| > VTN, then the level shifter IRR can be eliminated.
M1 M2
M3
M4M5
M6
M7
VDD
VSS
VBias1
M8
VBias2VBias
IBB
IS,E
ID,C
Fig. 7.6-20
R
IR
+
-
Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-16
CMOS Analog Circuit Design © P.E. Allen - 2010
LOW VOLTAGE GAIN STAGESCascade StagesSimple cascade of inverters:
060803-01
VDD
VPB1
VNB1
M1
M2 M3
M4
VPB1
M6
M5
VNB1
M7
M8
-gm1
R1
-gm2
R2
-gm3
R3
-gm4
R4
The problem with this approach is the number of poles that occur (one per stage) if theamplifier is to be used in a closed loop application.
Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-17
CMOS Analog Circuit Design © P.E. Allen - 2010
Nested Miller CompensationPrinciple: Use Miller compensationto split the poles within a feedbackloop.Compensating Results:1) Cm1 pushes p4 to higherfrequencies and p3 down to lowerfrequencies2) Cm2 pushes p2 to higherfrequencies and p1 down to lower frequencies
3) Cm3 pushes p3 to higher frequencies (feedback path) & pulls p1 further to lowerfrequenciesEquations:
GB gm1/C m3 p2 gm2/Cm3 p3 gm3Cm3/(Cm1Cm2) p4 gm4/CL
The objective is to get all poles larger than GB:GB < p2, p3, p4
060812-01
vinvout-gm3-gm2-gm1 -gm4
Cm3
Cm1Cm2
p1 p2 p3 p4
R2R1 R3 RL CL
Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-18
CMOS Analog Circuit Design © P.E. Allen - 2010
Illustration of the Nested Miller Compensation Technique
jω
σp4 p3 p2 p1
jω
σp4 p3 p2 p1
jω
σp4 p3p2 p1
jω
σp4 p3 p2 p1
Cm1
Cm2
Cm3
070508-01-GB
This approach is complicated by the feedforward paths which create RHP zeros.
Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-19
CMOS Analog Circuit Design © P.E. Allen - 2010
Elimination of the RHP ZerosThe following are least three ways in which the RHP zeros can be eliminated.
1.) Nulling resistor.
060803-02
VDD
VPB1
Rz1
Cc1
M2
M1
z1 = 1
Cc1(1/gm1 Rz1)
2.) Feedback only – buffer.
060803-03
VDD
VPB1
Cc1
M2
M1VPN1
VDD
M3
Increases the minimum powersupply by VON.
3.) Feedback only – gain.
060803-04
VDD
VPB1
Cc1M2
M1
VDD
VPB2
VNB1
M3
M4
M5
Increases the pole andincreases the minimumpower supply by VON.
Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-20
CMOS Analog Circuit Design © P.E. Allen - 2010
Use of LHP Zeros to Compensate Cascaded AmplifiersPrinciple: Feedforward around a noninverting stage creates a LHP zero or invertingfeedforward around an inverting stage also creates a LHP zero.Example of Multipath, Nested Miller Compensation†:
060803-05
R3
+gm4
VoutVin
C3
+gm2+gm1
R1
-gm3
R2,4
M1 M2M3 M4
CM1
CM2
M8
VNB1
M7
VDD
VPB1M5 M6
VRef1
M12
M11
VRef2
M14
Vout
C3Vin
M9 M10
M13
CM1CM2
Unfortunately, the analysis becomes quite complex - for the details refer to the referencebelow.
† R. Hogervorst and J. H. Huijsing, Design of Low-Voltage, Low-Power Operational Amplifier Cells, Kluwer Academic Publishers, 1996, pp. 127-131.
Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-21
CMOS Analog Circuit Design © P.E. Allen - 2010
CascodingPossibilities that trade off output resistance and headroom:
051205-01
VGG
ID
+
−vout
Rout
No Cascoding
VGG
ID
+
−
vout
Rout
Normal Cascoding
M1
M2Sat.
Sat.
VT+2Von
VGG
ID
+
−
vout
Rout
Reduced Headroom Cascoding
M1
M2Sat.
Act.
VT+2Von
VGG
ID
+
−
vout
Rout
Gate-Connected Cascode
M1
M2Sat.
Act.
NoCascode
NormalCascode
Reduced HeadroomCascode
Gate-ConnectedCascode
voutVon1 1
1 + ß1ß2 1 +
ß1ß2 (2x-x2) 2x +
ß1ß2 (2x-x2)
Routrds
1 2ß22ID
2ß2(x-0.5x2)
ß1(1-x) + ID x-0.5x2 2ß2(x-0.5x2)
ß1(1-x) + ID x-0.5x2
Note: vDS(active) = x·Von1 = x·(VGG–VT)x = 0.1 and ß2 = 9ß1 vout=1.145Von1 and Rout=1.45rds for reduced headroom cascode
Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-22
CMOS Analog Circuit Design © P.E. Allen - 2010
Solutions to the Low Headroom Problem – High Voltage Tolerant CircuitsHigh voltage tolerant transistors in standard CMOS†:
050416-02
Thick oxidetransistor Thick oxide
cascode
VDD(nom.)
VDD(nom.)
Upper gateswitchedto highestpotential
Retractable cascodecomposite transistor
(Transistor symbols with additional separation between the gate line and the channel linerepresent thick oxide transistors.)
† Anne-Johan Annema, et. Al., “5.5-V I/O in a 2.5-V 0.25μm CMOS Technology,” IEEE J. of Solid-State Circuits, Vol. 36, No. 3, March 2001, pp.
528-538.
Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-23
CMOS Analog Circuit Design © P.E. Allen - 2010
LOW VOLTAGE BIAS CIRCUITSA Low-Voltage Current Mirror with Wide Input and Output SwingsThe current mirror below requires a power supply of VT+3VON and has a Vin(min) =VON and a Vout(min) = 2VON (less for the regulated cascode output mirror).
iin
M1 M2
M3
VDD
IB
M4
M5
M6
M7
iout
I1-IB IB I2
or
iin
M1
M2
M3
VDD
IB1
M4
M5M6
M7
iout
I1 IB2 I2IB1
IB2
Fig. 7.6-13A
Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-24
CMOS Analog Circuit Design © P.E. Allen - 2010
Low-Voltage Current Mirrors using the Bulk-Driven MOSFETThe biggest problem with current mirrors is the large minimum input voltage required forpreviously examined current mirrors.If the bulk-driven MOSFET is biased with a current that exceeds IDSS then it isenhancement and can be used as a current mirror.
VDD
iin
iout
M1 M2
+
-VGS
+-
VBS+
-VGS
VDD
iin iout
M1 M2
+
-VGS1
+-
VBS1+
-VGS2
M3 M4
Simple bulk-driven current mirror
Cascodebulk-driven current mirror. Fig.7.6-11
+-
VBS3+
-VGS3
+-
VGS4
The cascode current mirror gives a minimum input voltage of less than 0.5V for currentsless than 100μA
0
1 10-5
2 10-5
3 10-5
4 10-5
5 10-5
6 10-5
0 0.2 0.4 0.6 0.8 1
Cascode Current MirrorAll W/L's = 200μm/4μm
Iout
(A
)
Vout (V)
Iin=50μA
Iin=40μA
Iin=30μA
Iin=20μA
Iin=10μA
2μm CMOS
Fig. 7.6-12
Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-25
CMOS Analog Circuit Design © P.E. Allen - 2010
Bandgap Topologies Compatible with Low Voltage Power Supply
VPTAT
VBE
IPTAT
VRef
VDD
Voltage-mode bandgap topology.
INL
VRef
VDD
IVBE
VDD
IPTAT
VDD
Current-mode bandgap topology.
VRef
VDD
IPTAT
VDDVDD
INL
IVBE
R2
R3
R1
Voltage-current mode bandgap topologyFig. 7.6-14
Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-26
CMOS Analog Circuit Design © P.E. Allen - 2010
Technique for Canceling the Bandgap CurvatureVDD
M1 M2 M3 M4
IVBE K1IPTAT
1:K2 1:K3
I2 INLK3INL
Cur
rent K2IVBE K1IPTAT
Temperature
INL
M2 activeM3 off
M2 sat.M3 on
Circuit to generate nonlinear correction term, INL. Illustration of the various currents.Fig. 7.6-16
INL = 0
K1IPTAT - K2IVBE ,,
K2IVBE > K1IPTAT
K2IVBE < K1IPTAT
The combination of the above concept with the previous slide yielded a curvature-corrected bandgap reference of 0.596V with a TC of 20ppm/C° from -15C° to 90C° usinga 1.1V power supply.† In addition, the line regulation was 408 ppm/V for 1.2 VDD 10Vand 2000 ppm/V for 1.1 VDD 10V. The quiescent current was 14μA.
† G.A. Rincon-Mora and P.E. Allen, “A 1.1-V Current-Mode and Piecewise-Linear Curvature-Corrected Bandgap Reference,” J. of Solid-State
Circuits, vol. 33, no. 10, October 1998, pp. 1551-1554.
Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-27
CMOS Analog Circuit Design © P.E. Allen - 2010
LOW VOLTAGE OP AMPSA Low Voltage Op Amp using Normal TechnologyVDD(min) = 3VON + VT (ICMR = VON):
060804-01
VDD
VPB1
VNB1
VPB2
vIN+
−
vOUTM1 M2
M3 M4
M5
M6 M7
M8 M9 M10
M11
Cc
Performance:Gain gm
2rds2
Miller compensatedOutput swing is VDD -2VONMax. CM input = VDD
Min. CM input = 2VON + VT
Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-28
CMOS Analog Circuit Design © P.E. Allen - 2010
A Low-Voltage, Wide ICMR Op AmpVDD(min) = 4VON + 2VT (ICMR = VDD):
3:1
1:3
041231-15
VDD
VDD-VT-VDS(sat)
VDD-VT-2VDS(sat)+ −
VT+VDS(sat)
VT+2VDS(sat)
vOUT
Performance:
Gain gm2rds
2, self compensated, and output swing is VDD -4VON
Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-29
CMOS Analog Circuit Design © P.E. Allen - 2010
An Alternate Low-Voltage, Wide ICMR Op AmpVDD(min) = 4VON + 2VT (ICMR = VDD):
3:1
1:3060804-02
VDD
+ − vOUT
VPB2
VPB1
VPB2
VNB2
VNB1
VNB2
Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-30
CMOS Analog Circuit Design © P.E. Allen - 2010
A 1-Volt, Two-Stage Op AmpUses a bulk-driven differential input amplifier.
vin+
vout
VDD=1V
IBias
Cc=30pF
CL
Rz=1kΩ
vin-
M1 M2
M3 M4Q5 Q6
M7
M8 M9 M10 M11M12
2000/2
400/2 400/2 400/2
6000/6 6000/6 3000/6 6000/6
Fig. 7.6-18
Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-31
CMOS Analog Circuit Design © P.E. Allen - 2010
Performance of the 1-Volt, Two-Stage Op AmpSpecification (VDD=0.5V, VSS=-0.5V) Measured Performance (CL = 22pF)
DC open-loop gain 49dB (Vicm mid range)Power supply current 300μAUnity-gainbandwidth (GB) 1.3MHz (Vicm mid range)Phase margin 57° (Vicm mid range)Input offset voltage ±3mVInput common mode voltage range -0.475V to 0.450VOutput swing -0.475V to 0.491VPositive slew rate +0.7V/μsecNegative slew rate -1.6V/μsecTHD, closed loop gain of -1V/V -60dB (0.75Vp-p, 1kHz sinewave)
-59dB (0.75Vp-p, 10kHz sinewave)THD, closed loop gain of +1V/V -59dB (0.75Vp-p, 1kHz sinewave)
-57dB (0.75Vp-p, 10kHz sinewave)Spectral noise voltage density 367nV/ Hz @ 1kHz
181nV/ Hz @ 10kHz,81nV/ Hz @ 100kHz444nV/ Hz @ 1MHz
Positive Power Supply Rejection 61dB at 10kHz, 55dB at 100kHz, 22dB at 1MHzNegative Power Supply Rejection 45dB at 10kHz, 27dB at 100kHz, 5dB at 1MHz
Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-32
CMOS Analog Circuit Design © P.E. Allen - 2010
A 1-Volt, Folded-Cascode OTA using the Current-Driven Bulk Technique
-
+vin M1 M2
M3 M4M5
M6
M7
vout
VDD
VSS
VBiasN
Cx
CL
VBiasP
M8
M9 M10
M11 M12
M13
M14M15
M16
M17
Fig. 7.6-21
Transistors with forward-biased bulks are in a shaded box.For large common mode input changes, Cx, is necessary to avoid slewing in the inputstage.To get more voltage headroom at the output, the transistors of the cascode mirror havetheir bulks current driven.
Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-33
CMOS Analog Circuit Design © P.E. Allen - 2010
A 1-Volt, Folded-Cascode OTA using the Current-Driven Bulk Technique -ContinuedExperimental results:
0.5μm CMOS, 40μA total bias current (Cx = 10pF)Supply Voltage 1.0V 0.8V 0.7V
Common-mode inputrange
0.0V-0.65V 0.0V-0.4V 0.0V-0.3V
High gain output range 0.35V-0.75V 0.25V-0.5V 0.2V-0.4VOutput saturation limits 0.1V-0.9V 0.15V-0.65V 0.1V-0.6V
DC gain 62dB-69dB 46dB-53dB 33dB-36dBGain-Bandwidth 2.0MHz 0.8MHz 1.3MHz
Slew-Rate (CL=20pF) 0.5V/μs 0.4V/μs 0.1V/μsPhase margin (CL=20pF) 57° 54° 48°
The nominal value of bulk current is 10nA gives a 10% increase in differential pairquiescent current assuming a BJT of 100.
Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-34
CMOS Analog Circuit Design © P.E. Allen - 2010
SUMMARY• Integrated circuit power supplies are rapidly decreasing (today 2-3Volts)• Classical analog circuit design techniques begin to deteriorate at 1.5-2 Volts• Approaches for lower voltage circuits:
- Use natural NMOS transistors (VT 0.1V)
- Drive the bulk terminal- Forward bias the bulk- Use depeletion devices
• The dynamic range will be compressed if the noise is not also reduced• Fortunately, the threshold reduction continues to allow the techniques of this section to
be used in today’s technology
Lecture 310 – Open-Loop Comparators (3/28/10) Page 310-1
CMOS Analog Circuit Design © P.E. Allen - 2010
LECTURE 310 – OPEN-LOOP COMPARATORSLECTURE ORGANIZATION
Outline• Characterization of comparators• Dominant pole, open-loop comparators• Two-pole, open-loop comparators• SummaryCMOS Analog Circuit Design, 2nd Edition ReferencePages 439-461
Lecture 310 – Open-Loop Comparators (3/28/10) Page 310-2
CMOS Analog Circuit Design © P.E. Allen - 2010
CHARACTERIZATION OF COMPARATORSWhat is a Comparator?The comparator is a circuit that compares one analog signal with another analog signalor a reference voltage and outputs a binary signal based on the comparison.The comparator is basically a 1-bit analog-to-digital converter:
060808-01
1-Bit Quantizer
1-BitEncoder
ReferenceVoltage
AnalogInput
1-Bit DigitalOutput
1-Bit ADC AnalogInput 1
AnalogInput 2
1-BitEncoder
1-Bit Quantizer
Comparator
Comparator symbol:
+-
vP
vNvO
Fig. 8.1-1
Lecture 310 – Open-Loop Comparators (3/28/10) Page 310-3
CMOS Analog Circuit Design © P.E. Allen - 2010
Noninverting and Inverting ComparatorsThe comparator output is binary with the two-level outputs defined as,
VOH = the high output of the comparator
VOL = the low level output of the comparator
Voltage transfer function of a Noninverting and Inverting Comparator:vo
VOH
vP-vN
VOL
Noninverting Comparator
vo
VOH
vP-vN
VOL
Inverting Comparator
Fig. 8.1-2A
Lecture 310 – Open-Loop Comparators (3/28/10) Page 310-4
CMOS Analog Circuit Design © P.E. Allen - 2010
Infinite Gain ComparatorVoltage transfer function curve:
vo
VOH
vP-vN
VOL Fig. 8.1-2
Model:
f0(vP-vN)+
vO
+
- -
vP
vN
vP-vN
Comparator
f0(vP-vN) = VOH for (vP-vN) > 0
VOL for (vP-vN) < 0 Fig. 8.1-3
Gain = Av = limV 0
VOH-VOL
V where V is the input voltage change
Lecture 310 – Open-Loop Comparators (3/28/10) Page 310-5
CMOS Analog Circuit Design © P.E. Allen - 2010
Finite Gain ComparatorVoltage transfer curve:
where for a noninverting comparator,VIH = smallest input voltage at which the output voltage is VOH
VIL = largest input voltage at which the output voltage is VOL
Model:
The voltage gain is Av = VOH VOLVIH VIL
vo
VOH
vP-vN
VOL Fig. 8.1-4
VIH
VIL
f1(vP-vN)+
vO
+
- -
vP
vN
vP-vN
Comparator
f1(vP-vN) =
VOH for (vP-vN) > VIH
VOL for (vP-vN) < VIL Fig. 8.1-5
Av(vP-vN) for VIL< (vP-vN)<VIH
Lecture 310 – Open-Loop Comparators (3/28/10) Page 310-6
CMOS Analog Circuit Design © P.E. Allen - 2010
Input Offset Voltage of a ComparatorVoltage transfer curve:
vo
VOH
vP-vN
VOL Fig. 8.1-6
VIH
VIL
VOS
VOS = the input voltage necessary to make the output equal VOH+VOL
2 when vP = vN.
Model:
f1(vP'-vN')+
vO
+
- -
vP
vN
vP'-vN'
Comparator Fig. 8.1-7
vP'
vN'
±VOS
Other aspects of the model:ICMR = input common mode voltage range (all transistors remain in saturation)Rin = input differential resistance
Ricm = common mode input resistance
Lecture 310 – Open-Loop Comparators (3/28/10) Page 310-7
CMOS Analog Circuit Design © P.E. Allen - 2010
Comparator NoiseNoise of a comparator is modeled as if the comparator were biased in the transitionregion.
��vo
VOH
vP-vN
VOL
Fig. 8.1-8
Rms Noise
Transition Uncertainty
Noise leads to an uncertainty in the transition region causing jitter or phase noise.
Lecture 310 – Open-Loop Comparators (3/28/10) Page 310-8
CMOS Analog Circuit Design © P.E. Allen - 2010
Input Common Mode RangeBecause the input is analog and normally differential, the input common mode range ofthe comparator is also important.Input common mode range (ICMR):
ICMR = the voltage range over which the input common-mode signal can varywithout influence the differential performance
As we have seen before, the ICMR is defined by the common-mode voltage range overwhich all MOSFETs remain in the saturation region.
Lecture 310 – Open-Loop Comparators (3/28/10) Page 310-9
CMOS Analog Circuit Design © P.E. Allen - 2010
Propagation Delay TimeRising propagation delay time:
vo
VOH
tVOL
vi
t
070509-01
VIH
VIL
vo = VOH+VOL
2
vi = VIH+VIL
2tpr
= vP-vN
tpf
Propagation delay time = Rising propagation delay time + Falling propagation delay time
2
= tpr + tpf
2
Lecture 310 – Open-Loop Comparators (3/28/10) Page 310-10
CMOS Analog Circuit Design © P.E. Allen - 2010
Linear Frequency Response – Dominant Single-PoleModel:
Av(s) = Av(0)sc
+ 1 =
Av(0)s c+1
whereAv(0) = dc voltage gain of the comparator
c = 1c = -3dB frequency of the comparator or the magnitude of the pole
Step Response:
vo(t) = Av(0) [1 - e-t/ c]Vin
whereVin = the magnitude of the step input.
Maximum slope of the step response:dvo(t)
dt = Av(0)
c e-t/ cVin
The maximum slope occurs at t = 0 giving,dvo(t)
dt |
t=0 = Av(0)
c Vin
Lecture 310 – Open-Loop Comparators (3/28/10) Page 310-11
CMOS Analog Circuit Design © P.E. Allen - 2010
Propagation Time DelayThe rising propagation time delay for a single-pole comparator is:
VOH-VOL
2 = Av(0) [1 - e-tp/ c]Vin tp = c ln 1
1 -VOH -VOL2Av(0)Vin
Define the minimum input voltage to the comparator as,
Vin(min) = VOH -VOL
Av(0) tp = c ln 1
1-Vin(min)
2Vin
Define k as the ratio, Vin, to the minimum input voltage, Vin(min),
k = Vin
Vin(min) tp = c ln 2k
2k-1
Thus, if k = 1, tp = 0.693 c.Illustration:
Obviously, the more overdriveapplied to the input, the smallerthe propagation delay time.
+
-
VOH
VOL
tp(max)0t0
VOH+VOL2
Vin > Vin(min)
Vin = Vin(min)
vin
vout
vout
Fig. 8.1-10tp
Lecture 310 – Open-Loop Comparators (3/28/10) Page 310-12
CMOS Analog Circuit Design © P.E. Allen - 2010
Dynamic Characteristics - Slew Rate of a ComparatorIf the rate of rise or fall of a comparator becomes large, the dynamics may be limited by
the slew rate.Slew rate comes from the relationship,
i = C dvdt
where i is the current through a capacitor and v is the voltage across it.If the current becomes limited, then the voltage rate becomes limited.Therefore for a comparator that is slew rate limited we have,
tp = T = V
SR = VOH- VOL
2·SR
whereSR = slew rate of the comparator.
If SR < |maximum slope|, then the comparator is slewing.
Lecture 310 – Open-Loop Comparators (3/28/10) Page 310-13
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 310-1 - Propagation Delay Time of a ComparatorFind the propagation delay time of an open loop comparator that has a dominant pole
at 103 radians/sec, a dc gain of 104, a slew rate of 1V/μs, and a binary output voltageswing of 1V. Assume the applied input voltage is 10mV.Solution
The input resolution for this comparator is 1V/104 or 0.1mV. Therefore, the 10mVinput is 100 times larger than vin(min) giving a k of 100. Therefore, we get
tp = 1
103 ln2·100
2·100-1 = 10-3 ln200199 = 5.01μs
For slew rate considerations, we get
Maximum slope = 104
10-3 ·10mV = 105 V/sec. = 0.1V/μs.
Therefore, the propagation delay time for this case is limited by the linear response and is5.01μs.
Lecture 310 – Open-Loop Comparators (3/28/10) Page 310-14
CMOS Analog Circuit Design © P.E. Allen - 2010
DOMINANT POLE, OPEN-LOOP COMPARATORSDominant Pole ComparatorsAny of the self-compensated op amps provide a straight-forward implementation of anopen loop comparator without any modification.The previous characterization gives the relationships for:1.) The static characteristics
• Gain• Input offset• Noise
2.) The dynamic characteristics• Linear frequency response• Slew rate response
Lecture 310 – Open-Loop Comparators (3/28/10) Page 310-15
CMOS Analog Circuit Design © P.E. Allen - 2010
Single-Stage Dominant Pole Comparator
060808-02
-
M1 M2
M3 M4
M5
vo
VDD
VNBias1
+
-
VBias
MC2MC1
MC4MC3VPBias2
vp vn
CL
• Gain gm2rds
2
• Slew rate = I5/CL
• Dominant pole = -1/(RoutCL) = -1/(gmrds2CL)
Lecture 310 – Open-Loop Comparators (3/28/10) Page 310-16
CMOS Analog Circuit Design © P.E. Allen - 2010
Folded-Cascode Comparator
060808-03
VPB1
M4 M5
VPB2
VDD
M6 M7VNB2
M8 M9
M10 M11
vPvOUT
VNB1
M1 M2
M3I3
CLvN
• Gain gm2rds
2
• Slew rate = I3/CL
• Dominant pole = -1/(RoutCL) -1/(gmrds2CL)
• Slightly improved ICMR
Lecture 310 – Open-Loop Comparators (3/28/10) Page 310-17
CMOS Analog Circuit Design © P.E. Allen - 2010
Enhanced-Gain, Folded-Cascode Comparator
060808-04
vOUT
M4M5
M3
M7
M8 M9
M10 M11
M6
VDD
VPB1
-A
-A-A
vP
M1 M2
VNB1
vN
CL
• Gain gm1Rout• Rout [Ards7gm7(rds1||rds5)]|| (Ards9gm9rds11)• Slew rate = I3/CL• Dominant pole = -1/(RoutCL)
Lecture 310 – Open-Loop Comparators (3/28/10) Page 310-18
CMOS Analog Circuit Design © P.E. Allen - 2010
TWO-POLE, OPEN-LOOP COMPARATORSTwo-Stage Comparator
The two-stage op amp without compensation is an excellent implementation of ahigh-gain, open-loop comparator.
060808-05
vp
M1 M2
M3 M4
M5
M6
M7
vout
VDD
VNB1+
-
CL
vn
• Much faster linear response – the two poles of the comparator are typically much largerthan the dominant pole of the self-compensated type of comparator.
• Be careful not to close the loop because the amplifier is uncompensated.
• Slew rate: SR- = I7CII
and SR+ = I6-I7CII
Lecture 310 – Open-Loop Comparators (3/28/10) Page 310-19
CMOS Analog Circuit Design © P.E. Allen - 2010
Performance of the Two-Stage, Open-Loop ComparatorWe know the performance should be similar to the uncompensated two-stage op amp.Emphasis on comparator performance:• Maximum output voltage
VOH = VDD - (VDD-VG6(min)-|VTP|) 1 - 1 -8I7
6(VDD-VG6(min)-|VTP|)2
• Minimum output voltageVOL = VSS
• Small-signal voltage gain
Av(0) = gm1
gds2+gds4
gm6
gds6+gds7
• PolesInput: Output:
p1 = -(gds2+gds4)
CI p2 =
-(gds6+gds7)CII
• Frequency response
Av(s) = Av(0)
sp1
- 1s
p2- 1
Lecture 310 – Open-Loop Comparators (3/28/10) Page 310-20
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 310-1 - Performance of a Two-Stage ComparatorEvaluate VOH, VOL, Av(0), Vin(min), p1, p2,for the two-stage comparator shown. Thelarge signal model parameters are KN’ =
110μA/V2, KP’ = 50μA/V2, VTN = |VTP| =
0.7V, N = 0.04V-1 and P = 0.05V-1.Assume that the minimum value of VG6 =0V and that CI = 0.2pF and CII = 5pF.
SolutionUsing the above relations, we find that
VOH = 2.5 - (2.5-0-0.7) 1 - 1 -8·234x10-6
50x10-6·38(2.5-0-0.7)2 = 2.2V
VOL is -2.5V. The gain can be found as Av(0) = 7696. Therefore, the input resolution isVin(min) = (VOH-VOL/Av(0) = 4.7V/7,696 = 0.611mV
Next, we find the poles of the comparator, p1 and p2. p1 = -(gds2 + gds4)/CI = 15x10-6(0.04+0.05)/0.2x10-12 = -6.75x106 (1.074MHz)
and
p2 = -(gds6 + gds7)/CII) =(95x10-6)(0.04+0.05)/5x10-12 = -1.71x106 (0.272MHz)
-
+
vin
M1 M2
M3 M4
M5
M6
M7
vout
VDD = 2.5V
VSS = -2.5V
CI = 0.2pFCII = 5p3µm
1µm3µm1µm
15µm1µm
15µm1µm
M84.5µm1µm
30µA
4.5µm1µm
14µm1µm
94µm1µm
30µA
95µA
070509-02
Lecture 310 – Open-Loop Comparators (3/28/10) Page 310-21
CMOS Analog Circuit Design © P.E. Allen - 2010
Linear Step Response of the Two-Stage ComparatorThe step response of a circuit with two real poles (p1 p2) is,
vout(t) = Av(0)Vin 1 +p2etp1
p1-p2-
p1etp2
p1-p2
Normalizing gives,
vout’(tn ) = vout(t)
Av(0)Vin = 1 -
mm-1e-tn +
1m-1e-mtn where m =
p2
p1 1 and tn = -tp1
If p1 = p2 (m =1), then vout’(tn) = 1 - etp1 + tp1etp1 = 1 - e-tn - tne-tn
0
0.2
0.4
0.6
0.8
1
0 2 4 6 8 10Normalized Time (tn = -tp1 )
Nor
mal
ized
Out
put V
olta
ge
m = 0.25m = 0.5m = 1m = 2
m = 4
m = p2p1
Fig. 8.2-2
Lecture 310 – Open-Loop Comparators (3/28/10) Page 310-22
CMOS Analog Circuit Design © P.E. Allen - 2010
Linear Step Response of the Two-Stage Comparator - ContinuedThe above results are valid as long as the slope of the linear response does not exceed theslew rate.• Slope at t = 0 is zero• Maximum slope occurs at (m 1)
tn(max) = ln(m)m-1
and isdvout’(tn(max))
dtn = m
m-1 exp-ln(m)m-1 - exp -m
ln(m)m-1
• For the two-stage comparator using NMOS input transistors, the slew rate is
SR- = I7CII
SR+ = I6-I7CII
= 0.5 6(VDD-VG6(min)-|VTP|)2 - I7
CII
Lecture 310 – Open-Loop Comparators (3/28/10) Page 310-23
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 310-2 - Step Response of Ex. 310-1Find the maximum slope of Ex. 310-1 and the time it occurs if the magnitude of the
input step is vin(min). If the dc bias current in M7 is 100μA, at what value of loadcapacitance, CL would the transient response become slew limited? If the magnitude ofthe input step is 100vin(min), what is the new value of CL at which slewing would occur?
Solution
The poles of the comparator were given in Ex. 310-1 as p1 = -6.75x106 rads/sec. andp2 = -1.71x106 rads/sec. This gives a value of m = 0.253. From the previous expressions,the maximum slope occurs at tn(max) = 1.84 secs. Dividing by |p1| gives t(max) =0.272μs. The slope of the transient response at this time is found as
dvout’(tn(max))dtn = -0.338[exp(-1.84) - exp(-0.253·1.84)] = 0.159 V/sec
Multiplying the above by |p1| gives dvout’(t(max))/dt = 1.072V/μs. If the slew rate is lessthan 1.072V/μs, the transient response will experience slewing. Therefore, if CL 100μA/1.072V/μs or 93.3pF, the comparator will slew.
If the input is 100vin(min), then we must unnormalize the output slope as follows.
dvout’(t( max))dt =
vin
vin(min) dvout’(t( max))
dt = 100·1.072V/μs = 107.2V/μs
Therefore, the comparator will slew with a load capacitance greater than 0.933pF.
Lecture 310 – Open-Loop Comparators (3/28/10) Page 310-24
CMOS Analog Circuit Design © P.E. Allen - 2010
Propagation Delay Time (Non-Slew)To find tp, we want to set 0.5(VOH-VOL) equal to vout(tn). However, vout(tn) given as
vout(tn) = Av(0)Vin 1 -m
m-1e-tn +1
m-1e-mtn
can’t be easily solved so approximate the step response as a power series to get
vout(tn) Av(0)Vin 1 -m
m-1 1-tn+tn
2
2 + ··· +1
m-1 1-mtn+m2tn
2
2 +··· mtn2Av(0)Vin
2
Therefore, set vout(tn) = 0.5(VOH-VOL)
VOH-VOL
2 mtpn
2Av(0)Vin
2or
tpn VOH-VOL
mAv(0)Vin =
Vin(min)mVin
= 1mk
This approximation is particularly good for large values of k.
Lecture 310 – Open-Loop Comparators (3/28/10) Page 310-25
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 310-3 - Propagation Delay Time of a Two-Pole Comparator (Non-Slew)Find the propagation time delay of Ex. 310-1 if Vin = 10mV, 100mV and 1V.
SolutionFrom Ex. 310-1 we know
that Vin(min) = 0.611mV and m= 0.253. For Vin = 10mV, k =16.366 which gives tpn 0.491.The propagation time delay isequal to 0.491/6.75x106 or72.9nS. This corresponds wellwith the figure shown wherethe normalized propagationtime delay is the time at whichthe amplitude is 1/2k or 0.031which corresponds to tpn ofapproximately 0.5. Similarly,for Vin = 100mV and 1V we geta propagation time delay of23ns and 7.3ns, respectively.
0
0.2
0.4
0.6
0.8
1
0 2 4 6 8 10Normalized Time (tn = tp1 = t/τ1)
Nor
mal
ized
Out
put V
olta
ge
m = 0.25m = 0.5m = 1m = 2
m = 4
m = p2p1
Fig. 8.2-2A
= 0.031
0.52
12k
tp = 6.75x1060.52 = 77ns
Lecture 310 – Open-Loop Comparators (3/28/10) Page 310-26
CMOS Analog Circuit Design © P.E. Allen - 2010
Initial Operating States for the Two-Stage, Open-Loop ComparatorWhat are the initial operating states for the two-stage, open-loop comparator? Thefollowing table summarizes the results for the two-stage, open-loop comparator shown.
Conditions Initial State of vo1 Initial State of vout
vG1>VG2, i1<ISS and i2>0 VDD-VSD4(sat) < vo1 < VDD VSS
vG1>>VG2, i1=ISS and i2=0 VDD VSS
vG1<VG2, i1>0 and i2<ISS vo1=VG2-VGS2,act(ISS/2), VSS if M5 act. VOH see equation below tabl
vG1<<VG2, i1>0 and i2<ISS VSS VOH see equation below tabl
vG2>VG1, i1>0 and i2<ISS VS2(ISS/2)<vo1<VS2(ISS/2)+VDS2(sat) VOH see equation below tabl
vG2>>VG1, i1>0 and i2<ISS VG1-VGS1(ISS/2) , VSS if M5 active VOH see equation below tabl
vG2<VG1, i1<ISS and i2>0 VDD-VSD4(sat) < vo1 < VDD VSS
vG2<<VG1, i1=ISS and i2=0 VDD VSS
VOH = VDD – (VDD-VG6(min)-|VTP|)
x 1 - 1 -8I7
6(VDD-VG6(min)-|VTP|)2
vG1 M1 M2
M3 M4
M5
M6
M7
vout
VDD
VSS
VBias+
-
CII
Fig. 8.2-3
vG2
i1 i2 CI
ISS
vo1
i4i3
Lecture 310 – Open-Loop Comparators (3/28/10) Page 310-27
CMOS Analog Circuit Design © P.E. Allen - 2010
Trip Point of an InverterIn order to determine the propagation delay time, it is
necessary to know when the second stage of the two-stagecomparator begins to “turn on”.Second stage:
Trip point:Assume that M6 and M7 are saturated. (We know that the
steepest slope occurs for this condition.)Equate i6 to i7 and solve for vin which becomes the trip point.
vin = VTRP = VDD - |VTP| - KN(W7/L7)KP(W6/L6) (VBias- VSS -VTN)
Example:If W7/L7 = W6/L6, VDD = 2.5V, VSS = -2.5V, and VBias = 0V the trip point for the
circuit above is
VTRP = 2.5 - 0.7 - 110/50 (0 +2.5 -0.7) = -0.870V
vin
M6
M7
vout
VDD
VSS
+
-i6
i7
Fig. 8.2-4
VBias
Lecture 310 – Open-Loop Comparators (3/28/10) Page 310-28
CMOS Analog Circuit Design © P.E. Allen - 2010
Propagation Delay Time of a Slewing, Two-Stage, Open-Loop ComparatorPreviously we calculated the propagation delay time for a nonslewing comparator.If the comparator slews, then the propagation delay time is found from
ii = Ci
dvi
dti = Ci vi
ti
whereCi is the capacitance to ground at the output of the i-th stage
The propagation delay time of the i-th stage is,
ti = ti = Ci
Vi
Ii
The propagation delay time is found by summing the delays of each stage.tp = t1 + t2 + t3 + ···
Lecture 310 – Open-Loop Comparators (3/28/10) Page 310-29
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 310-4 - Propagation Time Delay of a Two-Stage, Open-Loop ComparatorFor the two-stage comparator shown
assume that CI = 0.2pF and C II = 5pF.Also, assume that vG1 = 0V and that vG2
has the waveform shown. If the inputvoltage is large enough to cause slew todominate, find the propagation time delayof the rising and falling output of thecomparator and give the propagation timedelay of the comparator.
2.5V
-2.5V
t(μs)0V 0.2 0.4 0.60
Fig. 8.2-5
vG2
Solution1.) Total delay = sum of the first and second stage delays, t1 and t22.) First, consider the change of vG2 from -2.5V to 2.5V at 0.2μs.
The last row of table on Slide 310-28 gives vo1 = +2.5V and vout = -2.5V
3.) tf1, requires CI, Vo1, and I5. CI = 0.2pF, I5 = 30μA and V1 can be calculated byfinding the trip point of the output stage.
vG2
M1 M2
M3 M4
M5
M6
M7
vout
VDD = 2.5V
VSS = -2.5V
CII =5pF
3μm1μm
3μm1μm
4.5μm1μm
4.5μm1μm
M84.5μm1μm
30μA
4.5μm1μm
35μm1μm
38μm1μm
30μA
234μA
Fig. 8.2-5A
CI =0.2pF
vo1
vG1
Lecture 310 – Open-Loop Comparators (3/28/10) Page 310-30
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 310-4 - Continued4.) The trip point of the output stage by setting the current of M6 when saturated equalto 234μA.
6
2 (VSG6-|VTP|)2 = 234μA VSG6 = 0.7 + 234·250·38 = 1.196V
Therefore, the trip point of the second stage is VTRP2 = 2.5 - 1.196 = 1.304V
Therefore, V1 = 2.5V - 1.304V = VSG6 = 1.196V. Thus the falling propagation timedelay of the first stage is
tfo1 = 0.2pF 1.196V30μA = 8 ns
5.) The rising propagation time delay of the second stage requires CII, Vout, and I6. CII
is given as 5pF, Vout = 2.5V (assuming the trip point of the circuit connected to theoutput of the comparator is 0V), and I6 can be found as follows:
VG6(guess) 0.5[VG6(I6=234μA) + VG6(min)]
VG6(min) = VG1 - VGS1(ISS/2) + VDS2 -VGS1(ISS/2) = -0.7 - 2·15110·3 = -1.00V
VG6(guess) 0.5(1.304V-1.00V) = 0.152V
Therefore VSG6 = 2.348V and I6 = 6
2 (VSG6-|VTP|)2 = 38·50
2 (2.348 - 0.7)2 = 2,580μA
Lecture 310 – Open-Loop Comparators (3/28/10) Page 310-31
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 310-4 - Continued6.) The rising propagation time delay for the output can expressed as
trout = 5pF 2.5V
2580μA-234μA = 5.3 ns
Thus the total propagation time delay of the rising output of the comparator isapproximately 13.3 ns and most of this delay is attributable to the first stage.7.) Next consider the change of vG2 from 2.5V to -2.5V at 0.4μs. We shall assume thatvG2 has been at 2.5V long enough for the conditions of the table on Slide 310-28 to bevalid. Therefore, vo1 VSS = -2.5V and vout VDD. The propagation time delays for thefirst and second stages are calculated as
tro1 = 0.2pF 1.304V-(-1.00V)
30μA = 15.4 ns
tfout = 5pF 2.5V
234μA = 53.42ns
8.) The total propagation time delay of thefalling output is 68.82 ns. Taking theaverage of the rising and falling propagationtime delays gives a propagation time delayfor this two-stage, open-loop comparator ofabout 41.06ns. -3V
-2V
-1V
0V
1V
2V
3V
200ns 300ns 400ns 500ns 600ns
vout
vo1
Time Fig. 8.2-6
VTRP6 = 1.304V
Falling prop.delay timeRising prop.
delay time
Lecture 310 – Open-Loop Comparators (3/28/10) Page 310-32
CMOS Analog Circuit Design © P.E. Allen - 2010
SUMMARY• The two-stage, open-loop comparator has two poles which should as large as possible• The transient response of a two-stage, open-loop comparator will be limited by either
the bandwidth or the slew rate• It is important to know the initial states of a two-stage, open-loop comparator when
finding the propagation delay time• If the comparator is gainbandwidth limited then the poles should be as large as possible
for minimum propagation delay time• If the comparator is slew rate limited, then the current sinking and sourcing ability
should be as large as possible
Lecture 320 – Improved Open-Loop Comparators and Latches (3/28/10) Page 320-1
CMOS Analog Circuit Design © P.E. Allen - 2010
LECTURE 320 – IMPROVED OPEN-LOOP COMPARATORSAND LATCHES
LECTURE ORGANIZATIONOutline• Autozeroing• Hysteresis• Simple Latches• SummaryCMOS Analog Circuit Design, 2nd Edition ReferencePages 464-483
Lecture 320 – Improved Open-Loop Comparators and Latches (3/28/10) Page 320-2
CMOS Analog Circuit Design © P.E. Allen - 2010
AUTOZEROINGPrinciple of AutozeroingUse the comparator as an op amp to sample the dc input offset voltage and cancel theoffset during operation.
+-
VOS VOS+
-
IdealComparator
+-
VOS
IdealComparator
CAZ VOS+
-
+-
VOS
IdealComparator
CAZ
vIN vOUT
Model of Comparator. Autozero Cycle Comparison CycleFig. 8.4-1
Comments:• The comparator must be stable in the unity-gain mode (self-compensating comparators
are ideal, the two-stage comparator would require compensation to be switched induring the autozero cycle.)
• Complete offset cancellation is limited by charge injection
Lecture 320 – Improved Open-Loop Comparators and Latches (3/28/10) Page 320-3
CMOS Analog Circuit Design © P.E. Allen - 2010
Differential Implementation of Autozeroed Comparators
VOS+
-
+-
VOS
IdealComparator
CAZ
vIN-
vOUTφ1
φ1
φ1
φ2 +-
VOS
vOUT = VOS
VOS+ -
+-
VOS
Comparator during φ1 phase
Comparator during φ2 phaseDifferential Autozeroed Comparator
vOUT
Fig. 8.4-2
vIN+
φ2
vIN+
vIN-
Lecture 320 – Improved Open-Loop Comparators and Latches (3/28/10) Page 320-4
CMOS Analog Circuit Design © P.E. Allen - 2010
Single-Ended Autozeroed ComparatorsNoninverting:
+-φ2
φ2
φ1 CAZ
φ1
φ1vOUTvIN
Fig. 8.4-3Inverting:
+-φ2
CAZ
φ1
φ1
vOUTvIN
Fig. 8.4-4
Comment on autozeroing:Need to be careful about noise that gets sampled onto the autozeroing capacitor and
is present on the comparison phase of the process.
Lecture 320 – Improved Open-Loop Comparators and Latches (3/28/10) Page 320-5
CMOS Analog Circuit Design © P.E. Allen - 2010
HYSTERESISInfluence of Input Noise on the ComparatorComparator without hysteresis:
vin
voutVOH
VOL
Comparatorthreshold
t
t
Fig. 8.4-6A
Comparator with hysteresis:
vin
voutVOH
VOL
t
t
VTRP+
VTRP-
Fig. 8.4-6B
Lecture 320 – Improved Open-Loop Comparators and Latches (3/28/10) Page 320-6
CMOS Analog Circuit Design © P.E. Allen - 2010
Use of Hysteresis for Comparators in a Noisy EnvironmentTransfer curve of a comparator with hysteresis:
vOUT
vIN
VTRP+
VTRP-
VOH
VOL
Fig. 8.4-5
vOUT
vIN
VOH
VOL
00
R1R2
(VOH-VOL) VTRP+
VTRP-
Counterclockwise Bistable Clockwise Bistable
Hysteresis is achieved by the use of positive feedback• Externally• Internally
Lecture 320 – Improved Open-Loop Comparators and Latches (3/28/10) Page 320-7
CMOS Analog Circuit Design © P.E. Allen - 2010
Noninverting Comparator using External Positive FeedbackCircuit:
Upper Trip Point:Assume that vOUT =
VOL, the upper trip point occurs when,
0 = R1
R1+R2VOL +
R2
R1+R2VTRP
+ VTRP+ = -
R1
R2 VOL
Lower Trip Point:Assume that vOUT = VOH, the lower trip point occurs when,
0 = R1
R1+R2VOH +
R2
R1+R2VTRP
- VTRP- = -
R1
R2 VOH
Width of the bistable characteristic:
Vin = VTRP+-VTRP
- = R1
R2 VOH -VOL
vOUT
vIN
VOH
VOL
+-
vOUTvIN R1
R2
R1VOLR2
R1VOHR2
Fig. 8.4-7
00
R1R2
(VOH-VOL) -
-
Lecture 320 – Improved Open-Loop Comparators and Latches (3/28/10) Page 320-8
CMOS Analog Circuit Design © P.E. Allen - 2010
Inverting Comparator using External Positive FeedbackCircuit:
+- vOUT
vIN
R1R2
vOUT
vIN
VOH
VOL
R1VOHR1VOL
Fig. 8.4-8
00
R1R1+R2
(VOH-VOL)
R1+R2R1+R2
Upper Trip Point:
vIN = VTRP+ =
R1
R1+R2VOH
Lower Trip Point:
vIN = VTRP- =
R1
R1+R2VOL
Width of the bistable characteristic:
Vin = VTRP+-VTRP
- = R1
R1+R2 VOH -VOL
Lecture 320 – Improved Open-Loop Comparators and Latches (3/28/10) Page 320-9
CMOS Analog Circuit Design © P.E. Allen - 2010
Horizontal Shifting of the CCW Bistable CharacteristicCircuit:
Upper Trip Point:
VREF = R1
R1+R2VOL +
R2
R1+R2VTRP
+ VTRP+ =
R1+R2
R2VREF -
R1
R2 VOL
Lower Trip Point:
VREF = R1
R1+R2VOH +
R2
R1+R2VTRP
- VTRP- =
R1+R2
R2VREF -
R1
R2 VOH
Shifting Factor:
±R2
R1+R2 VREF
vOUT
vIN
VOH
VOL
+-
vOUTvIN R1
R2
R1VOHR2
Fig. 8.4-9
00
R1R2
(VOH-VOL)
VREFR1|VOL|
R2
R1+R2R2
VREF
Lecture 320 – Improved Open-Loop Comparators and Latches (3/28/10) Page 320-10
CMOS Analog Circuit Design © P.E. Allen - 2010
Horizontal Shifting of the CW Bistable CharacteristicCircuit:
+- vOUT
vIN
R1R2
Fig. 8.4-10
VREF
vOUT
vIN
VOH
VOL
R1|VOL|
00
R1 (VOH-VOL)
R1VOH
R1+R2
R2VREF
R1+R2
R1+R2
R1+R2
Upper Trip Point:
vIN = VTRP+ =
R1
R1+R2VOH +
R2
R1+R2VREF
Lower Trip Point:
vIN = VTRP- =
R1
R1+R2VOL +
R2
R1+R2VREF
Shifting Factor:
±R2
R1+R2 VREF
Lecture 320 – Improved Open-Loop Comparators and Latches (3/28/10) Page 320-11
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 320-1 Design of an Inverting Comparator with Hysteresis
Use the inverting bistable to design a high-gain, open-loop comparator having anupper trip point of 1V and a lower trip point of 0V if VOH = 2V and VOL = -2V.
Solution
Putting the values of this example into the above relationships gives
1 = R1
R1+R2 2 +
R2
R1+R2VREF
and
0 = R1
R1+R2 (-2) +
R2
R1+R2VREF
Solving these two equations gives 3R1 = R2 and VREF = (2/3)V.
Lecture 320 – Improved Open-Loop Comparators and Latches (3/28/10) Page 320-12
CMOS Analog Circuit Design © P.E. Allen - 2010
Hysteresis using Internal Positive FeedbackSimple comparator with internal positive feedback:
VSS
IBias
vo1 vo2
vi1 vi2M1 M2
M3 M4M6 M7
M5M8
VDD
Fig. 8.4-11
Lecture 320 – Improved Open-Loop Comparators and Latches (3/28/10) Page 320-13
CMOS Analog Circuit Design © P.E. Allen - 2010
Internal Positive Feedback - Upper Trip PointAssume that the gate of M1 is on ground and theinput to M2 is much smaller than zero. Theresulting circuit is:
M1 on, M2 off M3 on, M6 on (active), M4 andM7 off.
vo2 is high.
M6 wants to source the current i6 = W6/L6
W3/L3 i1
As vin begins to increase towards the trip point, thecurrent flow through M2 increases. When i2 = i6,the upper trip point will occur.
i5 = i1+i2 = i3+i6 = i3+W6/L6
W3/L3i3 = i3 1 +
W6/L6
W3/L3 i1 = i3 =
i51 + [(W6/L6)/(W3/L3)]
Also, i2 = i5 - i1 = i5 - i3Knowing i1 and i2 allows the calculation of vGS1 and vGS2 which gives
VTRP+ = vGS2 - vGS1 =
2i22
+ VT2 - 2i1
1 - VT1
VSS
vo1 vo2
M1 M2
M3 M4M6 M7
M5
VDD
Fig. 8.4-12A
I5
i1 = i3
vin
i2 = i6
Lecture 320 – Improved Open-Loop Comparators and Latches (3/28/10) Page 320-14
CMOS Analog Circuit Design © P.E. Allen - 2010
Internal Positive Feedback - Lower Trip PointAssume that the gate of M1 is on ground and the inputto M2 is much greater than zero. The resulting circuitis:
M2 on, M1 off M4 and M7 on, M3 and M6 off.vo1 is high.
M7 wants to source the current i7 = W7/L7
W4/L4 i2
As vin begins to decrease towards the trip point, thecurrent flow through M1 increases. When i1 = i7, thelower trip point will occur.
i5 = i1+i2 = i7+i4 = W7/L7
W4/L4i4 +i4 = i4 1 +
W7/L7
W4/L4 i2 = i4 =
i51 + [(W7/L7)/(W4/L4)]
Also, i1 = i5 - i2 = i5 - i4Knowing i1 and i2 allows the calculation of vGS1 and vGS2 which gives
VTRP- = vGS2 - vGS1 =
2i22
+ VT2 - 2i1
1 - VT1
Fig. 8.4-12BVSS
vo1 vo2
vi1M1 M2
M3 M4M6 M7
M5
VDD
I5
i2 = i4
vi1
i1 = i7
vi
Lecture 320 – Improved Open-Loop Comparators and Latches (3/28/10) Page 320-15
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 320-2 - Calculation of Trip Voltages for a Comparator with Hysteresis
Consider the circuit shown. If KN’ = 110μA/V2,KP’ = 50μA/V2, and VTN = |VTP| = 0.7V,calculate the positive and negative thresholdpoints if the device lengths are all 1 μm and thewidths are given as: W1 = W2 = W6 = W7 = 10 μmand W3 = W4 = 2 μm. The gate of M1 is tied toground and the input is the gate of M2. Thecurrent, i5 = 20 μA
Solution To calculate the positive trip point, assume
that the input has been negative and is headingpositive.
i6 = (W/L)6(W/L)3
i3 = (5/1)(i3) i3 = i5
1 + [(W/L)6/(W/L)3] = i1 = 20 μA1 + 5 = 3.33 μA
i2 = i5 i1 = 20 3.33 = 16.67 μA vGS1 = 2i1
11/2
+VT1 = 2·3.33(5)110
1/2+0.7 = 0.81V
vGS2 = 2i2
21/2
+ VT2 = 2·16.67(5)110
1/2 + 0.7 = 0.946V
VTRP+ vGS2 vGS1 = 0.946 0.810 = 0.136V
VSS
IBias
vo1 vo2
vi1 vi2M1 M2
M3 M4M6 M7
M5M8
VDD
Fig. 8.4-11
Lecture 320 – Improved Open-Loop Comparators and Latches (3/28/10) Page 320-16
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 320-2 - ContinuedDetermining the negative trip point, similar analysis yields
i4 = 3.33 μAi1 = 16.67 μAvGS2 = 0.81VvGS1 = 0.946VVTRP- vGS2 vGS1 = 0.81 0.946 = 0.136V
PSPICE simulation results of this circuit are shown below.
1
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
-0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5
vo2
(volts)
vin (volts) Fig. 8.4-13
Lecture 320 – Improved Open-Loop Comparators and Latches (3/28/10) Page 320-17
CMOS Analog Circuit Design © P.E. Allen - 2010
Complete Comparator with Internal Hysteresis
VSS
IBias
vout
vi1 vi2M1 M2
M3 M4M6 M7
M5M8
VDD
Fig. 8.4-14
M8M9
M10 M11
Lecture 320 – Improved Open-Loop Comparators and Latches (3/28/10) Page 320-18
CMOS Analog Circuit Design © P.E. Allen - 2010
Schmitt TriggerThe Schmitt trigger is a circuit that has better defined switching points.Consider the following circuit:
How does this circuit work?Assume the input voltage, vin, is low and the output
voltage, vout , is high.
M3, M4 and M5 are on and M1, M2 and M6 are off.When vin is increased from zero, M2 starts to turn on causingM3 to start turning off. Positive feedback causes M2 to turnon further and eventually both M1 and M2 are on and theoutput is at zero.
The upper switching point, VTRP+ is found as follows:
When vin is low, the voltage at the source of M2 (M3) is
vS2 = VDD-VTN3
VTRP+ = vin when M2 turns on given as VTRP
+ = VTN2 + vS2
VTRP+ occurs when the input voltage causes the currents in M3 and M1 to be equal.
vin
M1
M2
M3M4
M5
M6
vout
VDD
Fig. 8.4-15
Lecture 320 – Improved Open-Loop Comparators and Latches (3/28/10) Page 320-19
CMOS Analog Circuit Design © P.E. Allen - 2010
Schmitt Trigger – ContinuedThus, iD1 = 1( VTRP
+ - VTN1)2 = 3( VDD - vS2- VTN3) 2 = iD3
which can be written as, assuming that VTN2 = VTN3,
1( VTRP+ - VTN1) 2 = 3( VDD
– VTRP+)2 VTRP
+ = VTN1 + 3/ 1 VDD
1 + 3/ 1
The switching point, VTRP- is found in a similar manner and is:
5( VDD - VTRP- - VTP5)2 = 6( VTRP
-)2 VTRP- =
5/ 6 (VDD - VTP5)
1 + 5/ 6
The bistable characteristic is,
vin
vout
VDD
VDD0 0 VTRP- VTRP+
Fig. 8.4-16
Lecture 320 – Improved Open-Loop Comparators and Latches (3/28/10) Page 320-20
CMOS Analog Circuit Design © P.E. Allen - 2010
SIMPLE LATCHESRegenerative ComparatorsRegenerative comparators use positive feedback to accomplish the comparison of twosignals. Latches can have a faster switching speed than the previous comparators.NMOS and PMOS latch:
I1 I2
M1 M2
VDD
vo1 vo2
I1 I2
VDD
vo1 vo2
M1 M2
Fig. 8.5-3PMOS latchNMOS latch
Lecture 320 – Improved Open-Loop Comparators and Latches (3/28/10) Page 320-21
CMOS Analog Circuit Design © P.E. Allen - 2010
Operating Modes of the Latch
The latch has two modes of operation – enable or latch and Enable (enable_bar) or Latch(latch_bar).1.) During the Enable_bar, the latch is turned off (currents are removed) and theunknown inputs are applied to it. The parasitic capacitance at the latch nodes hold theunknown voltage.2.) During Enable, the latch is turned on, and the positive feedback acts on the appliedinputs and causes one side of the latch to go high and the other side to go low.Enable_bar:
060808-09
I1 I2
M1 M2
VDD
Vo1ʼ
I1 I2
VDD
M1 M2
PMOS latchNMOS latch
Enable Enable
Vo2ʼ Vo1ʼEnable Enable
Vo2ʼ
The inputs are initially applied to the outputs of the latch.Vo1’ = initial input applied to vo1
Lecture 320 – Improved Open-Loop Comparators and Latches (3/28/10) Page 320-22
CMOS Analog Circuit Design © P.E. Allen - 2010
Step Response of a Latch (Enable)Circuit:Ri and Ci are theresistance and capacitanceseen to ground from thei-th transistor.
Nodal equations:
gm1Vo2+G1Vo1+sC1 Vo1-Vo1’
s = gm1Vo2+G1Vo1+sC1V o1-C1Vo1’ = 0
gm2Vo1+G2Vo2+sC2 Vo2-Vo2’
s = gm2Vo1+G2Vo2+sC2V o2-C2Vo2’ = 0
Solving for Vo1 and Vo2 gives,
Vo1 = R1C1
sR1C1+1 Vo1’ - gm1R1
sR1C1+1 Vo2 = 1
s 1+1 Vo1’ - gm1R1
s 1+1 Vo2
Vo2 = R2C2
sR2C2+1 Vo2’ - gm2R2
sR2C2+1 Vo1 = 2
s 2+1 Vo2’ - gm2R2
s 2+1 Vo1
Defining the output, Vo, and input, Vi, as
Vo = Vo2-Vo1 and Vi = Vo2’-Vo1’
M2M1
I1 I2
vo2
VDD VDD
vo1
gm1Vo2 R1Vo1's
C1Vo1Vo2
+
-
+
-gm2Vo1 R2
Vo2's
C2Vo2
+
-
Fig. 8.5-4
Lecture 320 – Improved Open-Loop Comparators and Latches (3/28/10) Page 320-23
CMOS Analog Circuit Design © P.E. Allen - 2010
Step Response of the Latch - ContinuedSolving for Vo gives,
Vo = Vo2-Vo1 = s +1 Vi + gmRs +1 Vo
or
Vo = Vi
s +(1-gmR) =
Vi
1-gmRs
1-gmR + 1 =
’ Vi
s ’+1
where
’ = 1-gmR
Taking the inverse Laplace transform gives
vo(t) = Vi e-t/ ’ = Vi e-t(1-gmR) / egmRt/ Vi, if gmR >>1.
Define the latch time constant as
L = | ’| gmR = Cgm
= 0.67WLCox
2K’(W/L)I = 0.67Cox WL3
2K’I
if C Cgs.
Vout(t) = et/ L Vi
Lecture 320 – Improved Open-Loop Comparators and Latches (3/28/10) Page 320-24
CMOS Analog Circuit Design © P.E. Allen - 2010
Step Response of a Latch - ContinuedNormalize the output voltage by (VOH-VOL) to get
Vout(t)VOH-VOL
= et/ L Vi
VOH-VOL
which is plotted as,
The propagation delay time is
tp = L ln VOH- VOL
2 Vi
Note that the larger the Vi, thefaster the response.
0
0.2
0.4
0.6
0.8
1
0 1 2 3 4 5tτL
ΔVoutVOH-VOL 0.01
0.5 0.4 0.3
0.20.1
0.050.03
0.005
ΔVi
Fig. 8.5-5
VOH-VOL
Lecture 320 – Improved Open-Loop Comparators and Latches (3/28/10) Page 320-25
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 320-3 - Time Domain Characteristics of a Latch.
Find the propagation time delay for the NMOS if the W/L of the latch transistors is5μm/0.5μm and the latch dc current is 10μA when Vi = 0.1(VOH-VOL) and Vi =0.01(VOH-VOL).
SolutionThe transconductance of the latch transistors is
gm = 2·120·10·10 = 155μS
The output conductance is 0.6μS which gives gmR of 93V/V. Since gmR is greater than1, we can use the above results. Therefore the latch time constant is found as
L = 0.67Cox
WL3
2K’I = 0.67(60.6x10-4)(5·0.5)x10-24
2·120x10-6·10x10-6 = 0.131ns
Since the propagation time delay is the time when the output is 0.5(VOH-VOL), thenusing the above results or Fig. 8.5-5 we find for Vi = 0.01(VOH-VOL) that tp = 3.91 L =0.512ns and for Vi = 0.1(VOH-VOL) that tp = 1.61 L = 0.211ns.
Lecture 320 – Improved Open-Loop Comparators and Latches (3/28/10) Page 320-26
CMOS Analog Circuit Design © P.E. Allen - 2010
Comparator using a Latch with a Built-In Reference†
How does it operate?1.) Devices in shaded region operate in thetriode region.2.) When the latch/reset goes high, the uppercross-coupled inverter-latch regenerates. Thedrain currents of M5 and M6 are steered toobtain a final state determined by the mismatchbetween the R1 and R2 resistances.
1
R1 = KN W1L (vin+ - VT) +
W2L (VREF- - VT)
and
1
R2 = KN W1L (vin- - VT) +
W2L (VREF+ - VT)
3.) The input voltage which causes R1 = R2 is vin(threshold) = (W2/W1)VREF
W2/W1 = 1/4 generates a threshold of ±0.25VREF.
† T.B. Cho and P.R. Gray, “A 10b, 20Msamples/s, 35mW pipeline A/D Converter,” IEEE J. Solid-State Circuits, vol. 30, no. 3, pp. 166-172, March1995.
VDD
vin+ vin-
vout+ vout-
M1
M3
M5
M7M9
M2
M4
M6
M8
M10
φ1φ1
φ1 φ1
VREF+VREF-
M1M2
Latch/Reset
Latch/Rese
R1 R2
Fig. 8.5-6
Performance 20Ms/s & 200μW
Lecture 320 – Improved Open-Loop Comparators and Latches (3/28/10) Page 320-27
CMOS Analog Circuit Design © P.E. Allen - 2010
Simple, Low Power Latched Comparator†
VDD
vin+ vin-
vout+ vout-
M1
M3
M5
M7M9
M2
M4
M6
M8
M10
φ1φ1
φ1 φ1
Fig. 8.5-7
Dissipated 50μW when clocked at 2MHz.Self-referenced
† A. Coban, “1.5V, 1mW, 98-dB Delta-Sigma ADC”, Ph.D. dissertation, School of ECE, Georgia Tech, Atlanta, GA 30332-0250.
Lecture 320 – Improved Open-Loop Comparators and Latches (3/28/10) Page 320-28
CMOS Analog Circuit Design © P.E. Allen - 2010
Tail-Referenced LatchThe previous two latches experience poor input offsetvoltage characteristics because the input devices areworking in the linear region during the latch phase.The latch below keeps the input devices in the sat-uration region. The resulting larger gain of the inputdevices reduces the input offset voltage as shown.
The input offset voltage of the tail referencedlatch is compared between two latches with thereferenced latch for 100 samples. The x-axis is thedeviation from the mean of the first latch and the y-axis is the deviation of the mean of the second latch.
070511-01
VDD
Latch
vout-
vin+
Latch
Latch
vout+
vin-Vref
+ Vref-
M1 M2
All transistors are3.5μm/0.4μm excepM1 and M2
Lecture 320 – Improved Open-Loop Comparators and Latches (3/28/10) Page 320-29
CMOS Analog Circuit Design © P.E. Allen - 2010
CMOS LatchCircuit:
vout+
VDD
φLatch
φLatch
VREF
vout-vin
M1 M2
M3 M4
M5
M6
M7
M8
Fig. 8.5-8
Input offset voltage distribution:
0 5 10 15-5-10-150
10
20
�����������
������������N
umbe
rof
Sam
ples
Input offset voltage (mV)
L = 1.2μm(0.6μm Process)σ = 5.65
Fig. 8.5-9
Lecture 320 – Improved Open-Loop Comparators and Latches (3/28/10) Page 320-30
CMOS Analog Circuit Design © P.E. Allen - 2010
CMOS Latch with Different Inputs and Outputs
060808-10
VDDLatch_bar
LatchOutputs
LatchInputs
M1 M2
M3 M4
M5 M6
M7
When Latch_bar is high, M5, M6 and M7 are off and the latch is disabled and the outputsare shorted together.When Latch_bar is low, the input voltages stored at the sources of M1 and M2 will causeone of the latch outputs to be high and the other to be low.
The source of M1 and M2 that is higher will have a larger source-gate voltageresulting in a larger transconductance and more gain than the other transistor.
Lecture 320 – Improved Open-Loop Comparators and Latches (3/28/10) Page 320-31
CMOS Analog Circuit Design © P.E. Allen - 2010
MetastabilityMetastability is the condition where the latch cannot make a decision in the timeallocated. Normally due to the fact that the input is small (within the input resolutionrange).Metastability can be improved (reduced) by increasing the gain of the comparator bypreceding it with an amplifier to keep the signal input to the latch as large as possibleunder all conditions. The preamplifier also reduced the input offset voltage.
060808-11
VDDLatch_bar
Preamplifier
ComparatorInputs
Latch
LatchOutputs
LatchInputs
VNB1
Lecture 320 – Improved Open-Loop Comparators and Latches (3/28/10) Page 320-32
CMOS Analog Circuit Design © P.E. Allen - 2010
SUMMARY• Discrete-time comparators must work with clocks• Switched capacitor comparators use op amps to transfer charge and autozero• Regenerative comparators (latches) use positive feedback• The propagation delay of the regenerative comparator is slow at the beginning and
speeds up rapidly as time increases• The highest speed comparators will use a combination of open-loop comparators and
latches
Lecture 330 – High Speed Comparators (3/28/10) Page 330-1
CMOS Analog Circuit Design © P.E. Allen - 2010
LECTURE 330 – HIGH SPEED COMPARATORSLECTURE ORGANIZATION
Outline• Speed limitations of comparators• High speed comparators• SummaryCMOS Analog Circuit Design, 2nd Edition ReferencePages 461-464 and 483-487
Lecture 330 – High Speed Comparators (3/28/10) Page 330-2
CMOS Analog Circuit Design © P.E. Allen - 2010
SPEED LIMITATIONS OF COMPARATORSSpeed Limitations of ComparatorsThe speed of a comparator is limited by either:
• Linear response – response time is inversely proportional to the magnitude of poles
060810-01
jω
σIncrease for
speed Increasebandwidth
Gain
ω
vout
VOH
VOL
PropagationTime Delay
t
• Slew rate – delay is proportional to capacitance and inversely proportional tocurrent sinking or sourcing capability
VDD
060810-02
voutCL
ISource
ISink+
−
dvoutdt
= ICL
voutVOH
VOL
PropagationTime Delay
t
Lecture 330 – High Speed Comparators (3/28/10) Page 330-3
CMOS Analog Circuit Design © P.E. Allen - 2010
Maximizing the Linear ResponseConsider the amplifier of Example 270-3 given below:
060711-01
VDD
Vout +−
Vin+
−
Μ1 Μ2Μ3 Μ4Μ5
VNB1
VPB1 VPB1
Μ6
Μ7
I7
I3 I4I5 I6
I1 I2
One stage of this amplifier had a gain of 10 and a dominant pole at 551MHz. Theresponse of this amplifier to a step input is
Vout(t) = 10Vin (1-e-p1t)
If the output signal swing is 1V and the step is 0.1V, the propagation time delay is,
Vin(min) = 1/10 = 0.1V k = 1
tp = 1
p1 ln
2k2k-1 =
12 ·551x106 ln
22-1 = 0.20 ns
Lecture 330 – High Speed Comparators (3/28/10) Page 330-4
CMOS Analog Circuit Design © P.E. Allen - 2010
Trading Speed for Sensitivity (Gain)In the previous example, the gain was too small for good sensitivity. To enhance thesensitivity, cascade three of the gain of 10 stages. The result is,
+
−
+
−
10V/Vp1=551MHz
A1+
−
+
−
10V/Vp1=551MHz
A2+
−
+
−
10V/Vp1=551MHz
A3 VoutVin
The frequency response of this amplifier is,Vout(s)Vin(s) =
1000(1 + s/p1)3
The step response of this amplifier is
vout(t) = Ao2 Vinp13t2e-p1t
Ao2 Vinp13t2[1 - p1t + p12t2 - ···]
Ao2 Vinp13t2 if p1t<1
The propagation delay time is
tp2 = VOH-VOL
Ao
1Vinp13 =
1kp13 tp = 0.0049 ps if k = 1
The speed of the amplifier will be limited by the slew capability!
Lecture 330 – High Speed Comparators (3/28/10) Page 330-5
CMOS Analog Circuit Design © P.E. Allen - 2010
Maximizing Speed for Slew Rate LimitationThe key is to make the sourcing/sinking current large and the capacitance small.Best possible sinking/sourcing circuit in CMOS is:
VDD
060810-03
vIN vOUT
M1
M2
CL
ISource
ISink
Assuming a W/L ratio of 42 for M1 and 200 for M2, if the input can swing to VDD(=2.5V) and ground, the sourcing and sinking currents are:
ISourcing = Kp'W
2L (VDD – |VTP|)2 = 25·200
2 (2.5V-0.5)2 μA = 10.0 mA
ISinking = Kn'W
2L (VDD – VTN)2 = 120·42
2 (2.5V-0.5)2 μA = 10.1 mA
If larger currents are required, cascaded stages can be used to optimize the delay versusthe current output.
Lecture 330 – High Speed Comparators (3/28/10) Page 330-6
CMOS Analog Circuit Design © P.E. Allen - 2010
Driver Delay of a Push-Pull InverterIf too much current is required, the device sizes become large and the driver delay
increases. For the previous example, the input capacitance for the driver assuming Cox
6fF/μm2 and the channel lengths are 0.5μm, is,Cin = Cgs1 + Cgs2 = 2·(2/3) Cox(W1L1 + W2L2)
= 1.33·6fF/μm2(121μm2) = 0.968 pF
M1
M2200µm 0.5µm
42µm0.5µm
CLoadCin
Driver
070510-02
If the effective resistance of the driver is 30k , then the delay is 29 ns which is much toolarge.
Lecture 330 – High Speed Comparators (3/28/10) Page 330-7
CMOS Analog Circuit Design © P.E. Allen - 2010
Optimizing the Delay of a Chain of Push-Pull InvertersFor a series of N inverters as shown below, the W/L is increased by a factor of f for eachsucceeding stage.
Cin
W/L = 1
CLoad = fNCin
f f 2 f N-2 f N-1
070510-01
From the above figure we see that CLoad = f NCin _ N =
ln(CLoad /Cin)
ln f
The delay of a single, push-pull inverter can be expressed as,
tinv = inv
CjCj-1 + inv
where
inv = ReffCin (Reff is the effective output resistance of the inverter)
inv = CselfCin
= Cjunction
Cin(Cjunction is the bulk-drain capacitances)
Lecture 330 – High Speed Comparators (3/28/10) Page 330-8
CMOS Analog Circuit Design © P.E. Allen - 2010
Optimizing the Delay of a Chain of Push-Pull Inverters – ContinuedThe total delay of the chain of inverters is
ttotal = N inv
CjCj-1 + inv
Setting f = Cj
Cj-1 gives
ttotal =
ln(CLoad /Cin)
ln f inv (f + inv)
Plotting the total delay versus f for various values of inv shows that the optimum value off lies in the range of 2.5 to 4†.
† D.A. Hodges, H.G. Jackson, and R.A. Saleh, Analysis and Design of Digital Integrated Circuits in Deep Submicron Technology, 3rd ed., McGraw-
Hill Book Co., 2004, Chapter 6.
Lecture 330 – High Speed Comparators (3/28/10) Page 330-9
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 330-1 – Finding the Optimum Delay for a Chain of InvertersAssume that CLoad is 5pf, Cin = 50fF, inv = 10ps , and inv = 0.5. If f = 3.6, find theoptimal number of stages and the total delay of this chain of inverters.Solution
From above we get the optimal number of stages as,
N =
ln(CLoad /Cin)
ln f =
ln(100)ln 3.6
= 3.59
If we choose N = 4, then f can be recomputed as
ln f = 1
4 ln(100) f = 3.16
The total delay is,
ttotal = N inv
CjCj-1 + inv = 4·10ps(3.16 + 0.5) = 146ps
Lecture 330 – High Speed Comparators (3/28/10) Page 330-10
CMOS Analog Circuit Design © P.E. Allen - 2010
Self-Biased Differential Amplifier†
Not as good as the push-pull inverter but interesting.
Advantage:Large sink or source current with out a large quiescent current.
Disadvantage:Poor common mode range (vin
+ slower than vin-)
† M. Bazes, “Two Novel Full Complementary Self-Biased CMOS Differential Amplifiers,” IEEE Journal of Solid-State Circuits, Vol. 26, No. 2, Feb.1991, pp. 165-168.
M1 M2
M3 M4
M6
M5
VDD
VSS
vin+ vin-vout
M3 M4
M6
VDD
M1 M2
M5
VSS
vin+ vin-
VBias
VBias Extremelylarge sourcingcurrent
Fig. 8.3-4
Lecture 330 – High Speed Comparators (3/28/10) Page 330-11
CMOS Analog Circuit Design © P.E. Allen - 2010
Two-Stage Comparator with Increased SpeedClamp the input stage with 1/gm loads to decrease the signal swing and avoid slew ratelimitation in the first stage.
060808-06
Metal
vnM1 M2
M3
M4
M5
M6
vout
VDD
VBias+
-
CL
M9
M8
M7
vp
Comments:• Gain reduced Larger input resolution• Push-pull output Higher slew rates• Can increase the current drive by cascading the output stage
Lecture 330 – High Speed Comparators (3/28/10) Page 330-12
CMOS Analog Circuit Design © P.E. Allen - 2010
Comparators that Can Drive Large Capacitive Loads
060808-08
vnM1 M2
M3 M4
M5
M6
M7
vout
VDD
VNB1+
-
CL
M8
M9
M10
M11
vp
Comments:• Slew rate = 3V/μs into 50pF• Linear rise/fall time = 100ns into 50pF• Propagation delay time 1μs• Loop gain 32,000 V/V• The quiescent dc currents in the output stages are not well defined• Use the principle of optimizing the delay in cascaded inverters
Lecture 330 – High Speed Comparators (3/28/10) Page 330-13
CMOS Analog Circuit Design © P.E. Allen - 2010
HIGH SPEED COMPARATORSA Study in ExponentialsThe step response of an amplifier with a gain of Ao and a dominant pole at A is,
vout(t) = Ao[1 – exp(- At)] Vin
060810-04t
vout
AoVin
0Fast rising
Slow rising
The latch response to a step input of Vin is,
vout(t) = Vin expt
tL
060810-05t
vout
2.72Vin
0
Fast rising
Slow rising
τL
Lecture 330 – High Speed Comparators (3/28/10) Page 330-14
CMOS Analog Circuit Design © P.E. Allen - 2010
A High-Speed Comparator ArchitectureCascade an amplifier with a latch to take advantage of the exponential characteristics ofthe previous slide.
060810-06
Preamplifier
Latch+
−Vin Vo1
+
−
+
−VoutAo
In order to keep the bandwidth of the amplifier large, the gain will be small. To achieve
060810-08
Preamplifier n
Latch+
−Von
+
−
+
−Vout
+
−
Preamplifier 1
+
−Vin
Preamplifier 2
Vo1
+
−Vo2 Von-1Ao
1/n Ao1/n Ao
1/n
Gain = Ao
Therefore, the question is how many stages of the amplifier and what is the gain of eachstage for optimum results?
Lecture 330 – High Speed Comparators (3/28/10) Page 330-15
CMOS Analog Circuit Design © P.E. Allen - 2010
Ex. 330-2 – Optimizing the Propagation Time DelayA comparator consists of an amplifier cascaded with a latch as shown below. Theamplifier has a voltage gain of 10V/V and f-3dB = 100MHz and the latch has a time constantof 1ns. The maximum and minimum voltage swings of the amplifier and latch are VOH andVOL. When should the latch be enabled after the application of a step input to the amplifierof 0.05(VOH-VOL) to get minimum overall propagation time delay? What is the value of theminimum propagation time delay?
vin = 0.05(VOH-VOL) voutAmplifierAv(0)=10V/V
f-3dB=100MHz
LatchτL=1ns
Comparator
voa
vil
Enable
t=0
070606-01
SolutionThe solution is based on the figure shown.We note that,
voa(t) = 10[1-e- -3dBt]0.05(VOH-VOL).If we define the input voltage to the latch as,
vil = x·(VOH-VOL) then we can solve for t1 and t2 as follows:
VOH
VOL
Amplifier
Latch
t1
x(VOH-VOL)
t2t
S01E3S1
Lecture 330 – High Speed Comparators (3/28/10) Page 330-16
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 330-2 - Continuedx·(VOH-VOL) = 10[1-e- -3dBt1]0.05(VOH-VOL) x = 0.5[1-e- -3dBt1]
This gives,
t1 = 1-3dB
ln 1
1-2x
From the propagation time delay of the latch we get,
t2 = L ln VOH-VOL
2vil = L ln
12x
tp = t1 + t2 = 1-3dB
ln 1
1-2x + L ln 12x
dtp
dx = 0 gives
2x = 2 L -3dB
2+2 L -3dB =
0.42+0.4 = 0.3859 (x = 0.1930)
t1 = 10ns2 ln
11-0.3859 = 1.592ns·0.4875 = 0.7762 ns
and t2 = 1ns ln 1
0.3859 = 0.9522ns
tp = t1 + t2 = 0.776 ns + 0.952 ns = 1.728 ns
Lecture 330 – High Speed Comparators (3/28/10) Page 330-17
CMOS Analog Circuit Design © P.E. Allen - 2010
Minimizing the Propagation Delay Time in ComparatorsFacts: • The input signal is equal to Vin(min) for worst case
• Amplifiers have a step response with a negative argument in the exponential • Latches have a step response with a positive argument in the exponential • If the amplifiers rise too quickly, they will be slew limitedApproach: • Use a cascade of low-gain, wide-bandwidth amplifiers to take a small input signal and
amplify it without suffering slew limit • Use a latch to take the amplified input and quickly reach 0.5(VOH-VOL)
Lecture 330 – High Speed Comparators (3/28/10) Page 330-18
CMOS Analog Circuit Design © P.E. Allen - 2010
Minimization of the Propagation Delay TimeMinimization of tp:
Q. If the preamplifer consists of n stages of gain A having a single-pole response, what isthe value of n and A that gives minimum propagation delay time?A. n = 6 and A = 2.62 but this is a very broad minimum and n is usually 3 and A 6-7to save area.
070509-06
Preamplifier 3
Latch−
Vo3
+
−
+
−Vout
+
−
Preamplifier 1
+
−Vin
Preamplifier 2
Vo1
+Vo2Ao
1/3 Ao1/3 Ao
1/3
Gain = Ao
Lecture 330 – High Speed Comparators (3/28/10) Page 330-19
CMOS Analog Circuit Design © P.E. Allen - 2010
Fully Differential, Three-Stage Amplifier and Latch ComparatorCircuit:
060810-08
+
- +
-
FB
FB
Reset
Cv1
Cv2
+
- +
-
FB
FB
Reset
Cv3
Cv4
+
- +
-
FB
FB
Cv5
Cv6
vout
+
-
Clock
+vin -
FB
FB
FB
FB
Reset
FB
FB Latch
Sample
Reset
Sample
Comments:• Autozero and reset phase followed by comparison phase• In the autozero phase, switches labeled “Reset” and “FB” are closed.
• In the sample phase, switches labeled “Sample” and “ FB ” are closed.
• Can run as high as 200Msps
Lecture 330 – High Speed Comparators (3/28/10) Page 330-20
CMOS Analog Circuit Design © P.E. Allen - 2010
Preamplifier and Latch CircuitsGain:
Av = - gm1
gm3 = -
gm2
gm4 = -
KN’(W1/L1)Kp’(W3/L3)
Dominant Pole:
|pdominant| = gm3
C = gm4
Cwhere C is the capacitance seen from theoutput nodes to ground.
If (W1/L1)/(W3/L3) = 100 and thebias current is 100μA, then A = -3.85and the bandwidth is 15.9MHz if C =0.5pF.Comments:• If a buffer is used to reduce the output
capacitance, one must take into account the loss of the buffer.• The use of a preamplifier before the latch reduces the latch offset by the gain of the
preamplifier so that the offset is due to the preamplifier only.
VDD
VBias
FB
FB
Reset
LatchEnable
M1
M2
M3 M4
M5 M6
Q
Q
Preamplifier Latch
Fig. 8.6-4
Lecture 330 – High Speed Comparators (3/28/10) Page 330-21
CMOS Analog Circuit Design © P.E. Allen - 2010
An Improved PreamplifierCircuit:
VDD
M1 M2
M3 M4M5 M6
M7 M8M10
M9
M11 M12
VBiasN
VBias
VBiasP VBiasP
vout+vout-
vin+ vin-
FB FB
Reset
Fig. 8.6-5
Gain:
Av = - gm1
gm3 = -
KN’(W1/L1)I1KP’(W3/L3)I3 = -
KN’(W1/L1)KP’(W3/L3) 1+
I5I3
If I5 = 24I3, the gain is increased by a factor of 5
Lecture 330 – High Speed Comparators (3/28/10) Page 330-22
CMOS Analog Circuit Design © P.E. Allen - 2010
Improved Frequency Response of the AmplifierIf the ratio of transconductance W/L is much larger than the load W/L, the frequency
response will suffer. Using the technique of the previous slide, we can keep the ratio ofthe W/Ls to a more reasonable value. The result is higher frequency response.Amplifier of Example 270-3:
060711-01
VDD
Vout +−
Vin+
−
Μ1 Μ2Μ3 Μ4Μ5
VNB1
VPB1 VPB1
Μ6
Μ7
I7
I3 I4I5 I6
I1 I2
Gain = 20dBf-3dB = 551MHz
Lecture 330 – High Speed Comparators (3/28/10) Page 330-23
CMOS Analog Circuit Design © P.E. Allen - 2010
High-Speed CMOS ComparatorThe comparator used in a 12-bit, 200 Msps ADC is shown below†. The comparator isused in each of the 4-bit pipeline stages which requires 15 comparators.The comparators consist of three stages including (a.) differential input pairs, (b.) a cross-coupled latch, and (c.) an SR latch to hold the comparator output until the next clockcycle.
Vref1
vin1 vin2
Vref2VNB1
iout1
iout2
iin1iin2
VDD
φ1φ1
φ1
φ2
vout1
vout2
VDD
S
R Q
Q
NMOS Input Pair Latch SR-Latch 070511-01
† T. Liechti, “Design of a High-Seed 12-bit Differential Pipelined A/D Converter,” Diploma Project, Feb. 2004, Microelectronic Systems Laboratory,Swiss Federal Institute of Technology, Lausanne.
Lecture 330 – High Speed Comparators (3/28/10) Page 330-24
CMOS Analog Circuit Design © P.E. Allen - 2010
High Speed CMOS Comparator – ContinuedSchematic of the fully differential comparator:
Clock waveforms:
Mean comparator powerdissipation is 140μWunder typical conditions
Lecture 330 – High Speed Comparators (3/28/10) Page 330-25
CMOS Analog Circuit Design © P.E. Allen - 2010
High Speed CMOS Comparator – ContinuedTransistor sizes:Transistor M0a,
M0b,M0c,M0d
M1a,M1b
M2a,M2b,M2c,M2d
M3a,M3b
M4a,M4b
M5a,M5b
M6a,M6b
M7 M8a,M8b
M9a,M9b
M10a,M10b
M11aM11b
W(μm) 1.5 6 3.6 3 1 1 0.24 0.5 2 2.5 3 0.24L(μm) 1 2.5 0.18 0.18 0.18 0.18 0.18 0.18 0.18 0.18 0.18 0.18
Comparator offsets (worst case):
Lecture 330 – High Speed Comparators (3/28/10) Page 330-26
CMOS Analog Circuit Design © P.E. Allen - 2010
SUMMARY• Comparators are limited in speed either by bandwidth or slew rate• Increasing the magnitude of the poles improves the bandwidth limitations• Increasing the current sinking/sourcing ability improves the slew rate limitation• Most high speed comparators use a combination of preamplifier followed by a latch
- The preamplifier uses bandwidth to quickly build up the input- The latch uses positive feedback to take the signal to its final state
Lecture 340 – Characterization of DACs and Current Scaling DACs (5/1/10) Page 340-1
CMOS Analog Circuit Design © P.E. Allen - 2010
LECTURE 340 – CHARACTERIZATION OF DACS ANDCURRENT SCALING DACS
LECTURE ORGANIZATIONOutline• Introduction• Static characterization of DACs• Dynamic characterization of DACs• Testing of DACs• Current scaling DACs• SummaryCMOS Analog Circuit Design, 2nd Edition ReferencePages 613-626
Lecture 340 – Characterization of DACs and Current Scaling DACs (5/1/10) Page 340-2
CMOS Analog Circuit Design © P.E. Allen - 2010
INTRODUCTIONImportance of Data Converters in Signal Processing
PRE-PROCESSING(Filtering and analog to digital conversion)
DIGITAL PROCESSOR
(Microprocessor)
POST-PROCESSING (Digital to analog conversion and
filtering)
ANALOGSIGNAL(Speech,sensors,radar,etc.)
ANALOGOUTPUTSIGNAL
CONTROL
ANALOG A/D D/ADIGITAL ANALOG
Lecture 340 – Characterization of DACs and Current Scaling DACs (5/1/10) Page 340-3
CMOS Analog Circuit Design © P.E. Allen - 2010
Digital-Analog Converters
Digital SignalProcessing
SystemMicroprocessorsCompact disksRead only memoryRandom access memoryDigital transmissionDisk outputsDigital sensors
DIGITAL-ANALOG
CONVERTERFilter Amplifier
AnalogOutput
Reference Fig. 10.1-01
Characteristics:• Can be asynchronous or synchronous• Primary active element is the op amp
• Conversion time can vary from fast (one clock period, T) to slow (2No. of bits*T)
Lecture 340 – Characterization of DACs and Current Scaling DACs (5/1/10) Page 340-4
CMOS Analog Circuit Design © P.E. Allen - 2010
Analog-Digital Converters
060922-01
AnalogInput
Sampleand
Hold
Digital SignalProcessing
SystemMicroprocessorsCompact disksRead only memoryRandom access memoryDigital transmissionDisk outputsDigital sensors
ANALOG-DIGITAL
CONVERTER
Reference
Characteristics:• Can only be synchronous (the analog signal must be sampled and held during
conversion)• Primary active element is the comparator
• Conversion time can vary from fast (one clock period, T) to slow (2No. of bits*T)
Lecture 340 – Characterization of DACs and Current Scaling DACs (5/1/10) Page 340-5
CMOS Analog Circuit Design © P.E. Allen - 2010
STATIC CHARACTERISTICS OF DIGITAL-ANALOG CONVERTERSBlock Diagram of a Digital-Analog Converter
VREF DVREF vOUT =KDVREF
OutputAmplifier
ScalingNetwork
VoltageReference
Binary Switches
b0b1 b2 bN-1Figure 10.1-3
b0 is the most significant bit (MSB)
The MSB is the bit that has the most (largest) influence on the analog output
bN-1 is the least significant bit (LSB)
The LSB is the bit that has the least (smallest) influence on the analog output
Lecture 340 – Characterization of DACs and Current Scaling DACs (5/1/10) Page 340-6
CMOS Analog Circuit Design © P.E. Allen - 2010
Input-Output CharacteristicsIdeal input-output characteristics of a 3-bit DAC
1.000
0.875
0.750
0.625
0.500
0.375
0.250
0.125
0.000
Ana
log
Out
put V
alue
Nor
mal
ized
to V
RE
F
000 001 010 011 100 101 110 111Digital Input Code
Vertical ShiftedCharacteristic
Infinite ResolutionCharacteristic
1 LSB
Fig. 10.1-4
Lecture 340 – Characterization of DACs and Current Scaling DACs (5/1/10) Page 340-7
CMOS Analog Circuit Design © P.E. Allen - 2010
Definitions• Resolution of the DAC is equal to the number of bits in the applied digital input word.• The full scale (FS):
FS = Analog output when all bits are 1 - Analog output all bits are 0
FS = (VREF - VREF
2N ) - 0 = VREF 1 -1
2N
• Full scale range (FSR) is defined as
FSR = limN (FS) = VREF
• Quantization Noise is the inherent uncertainty in digitizing an analog value with a finiteresolution converter.
DigitalInput Code
0LSB
0.5LSB
1LSB
-0.5LSB
000 001 010 011 100 101 110 111
Quantization Noise
Fig. 10.1-5
Lecture 340 – Characterization of DACs and Current Scaling DACs (5/1/10) Page 340-8
CMOS Analog Circuit Design © P.E. Allen - 2010
More Definitions• Dynamic Range (DR) of a DAC is the ratio of the FSR to the smallest difference that can
be resolved (i.e. an LSB)
DR = FSR
LSB change = FSR
(FSR/2N) = 2N
or in terms of decibels DR(dB) = 6.02N (dB)
• Signal-to-noise ratio (SNR) for the DAC is the ratio of the full scale value to the rmsvalue of the quantization noise.
rms(quantization noise) = 1T
0
T
LSB2tT - 0.5 2dt =
LSB12 =
FSR2N 12
SNR = vOUT(rms)
(FSR/ 12 2N)• Maximum SNR (SNRmax) for a sinusoid is defined as
SNRmax = vOUTmax(rms)
(FSR/ 12 2N) = FSR/(2 2)
FSR/( 12 2N) = 6 2N
2or in terms of decibels
SNRmax(dB) = 20log1062N
2 = 10 log10(6)+20 log10(2N)-20 log10(2) = 1.76 + 6.02N dB
Lecture 340 – Characterization of DACs and Current Scaling DACs (5/1/10) Page 340-9
CMOS Analog Circuit Design © P.E. Allen - 2010
Even More Definitions• Effective number of bits (ENOB) can be defined from the above as
ENOB =
SNRActual - 1.766.02
where SNRActual is the actual SNR of the converter.
Comment:The DR is the amplitude range necessary to resolve N bits regardless of the amplitude ofthe output voltage.However, when referenced to a given output analog signal amplitude, the DR requiredmust include 1.76 dB more to account for the presence of quantization noise.Thus, for a 10-bit DAC, the DR is 60.2 dB and for a full-scale, rms output voltage, thesignal must be approximately 62 dB above whatever noise floor is present in the outputof the DAC.
Lecture 340 – Characterization of DACs and Current Scaling DACs (5/1/10) Page 340-10
CMOS Analog Circuit Design © P.E. Allen - 2010
Accuracy Requirements of the i-th Bit• The output of the i-th bit of the converter is expressed as:
The output of the i-th bit = VREF2i+1
2n
2n = 2n-i-1 LSBs
• The uncertainty of each bit must be less than ±0.5 LSB (assuming all other bits are ideal.Must use ±0.25 LSB if each bit has a worst case error.)
• The accuracy of the i-th bit is equal to the uncertainty divided by the output giving:
Accuracy of the i-th bit =±0.5 LSB2n-i-1 LSB =
12n-i =
1002n-i %
Result: The highest accuracy requirement is always the MSB (i = 0). The LSB bit only needs ±50% accuracy.
Example:What is the accuracy requirement for each of the bits of a 10 bit converter?
Assuming all other bits are ideal, the accuracy requirement per bit is given below.
Bit Number 0 1 2 3 4 5 6 7 8 9Accuracy % 0.098 0.195 0.391 0.781 1.563 3.125 6.25 12.5 25 50(If all other bits are worst case, the numbers above must be divided by 2.)
Lecture 340 – Characterization of DACs and Current Scaling DACs (5/1/10) Page 340-11
CMOS Analog Circuit Design © P.E. Allen - 2010
Offset and Gain ErrorsAn offset error is a constant difference between the actual finite resolution
characteristic and the ideal finite resolution characteristic measured at any vertical jump.A gain error is the difference between the slope of the actual finite resolution and the
ideal finite resolution characteristic measured at the right-most vertical jump.
Gain Error in a 3-bit DACOffset Error in a 3-bit DACA
nalo
g O
utpu
t Val
ue N
orm
aliz
ed to
VR
EF
000 001 010 011 100 101 110 111Digital Input Code
Ideal 3-bitResolution
Characteristic
1
7/8
6/8
5/8
4/8
3/8
2/8
1/8
0
Actual Characteristic
GainError
InfiniteResolution
Characteristic
Ana
log
Out
put V
alue
Nor
mal
ized
to V
RE
F
000 001 010 011 100 101 110 111Digital Input Code
OffsetError
1
7/8
6/8
5/8
4/8
3/8
2/8
1/8
0
Actual Characteristic
InfiniteResolution
Characteristic
Ideal 3-bitResolution
Characteristic
Fig. 10.1-6
Lecture 340 – Characterization of DACs and Current Scaling DACs (5/1/10) Page 340-12
CMOS Analog Circuit Design © P.E. Allen - 2010
Integral and Differential Nonlinearity• Integral Nonlinearity (INL) is the maximum difference between the actual finite
resolution characteristic and the ideal finite resolution characteristic measured vertically(% or LSB).
• Differential Nonlinearity (DNL) is a measure of the separation between adjacent levelsmeasured at each vertical jump (% or LSB).
DNL = Vcx – Vs = Vcx - Vs
Vs Vs =
VcxVs
-1 LSBs
where Vcx is the actual voltage change on a bit-to-bit basis and Vs is the ideal LSBchange of (VFSR/2N)
Example of a 3-bit DAC:
000 001 010 011 100 101 110 111
1808
28
38
48
58
68
78
88
Ana
log
Out
put V
olta
ge
Digital Input Code
Ideal 3-bit Characteristic
Actual 3-bit Characteristic
Infinite Resolution Characteristic
+1.5 LSB INL
-1 LSB INL
+1.5 LSB DNL
A-1.5 LSB DNL
Nonmonotonicity
Fig. 10.1-7
Lecture 340 – Characterization of DACs and Current Scaling DACs (5/1/10) Page 340-13
CMOS Analog Circuit Design © P.E. Allen - 2010
Example of INL and DNL of a Nonideal 4-Bit DacFind the ±INL and ±DNL for the 4-bit DAC shown.
15/16
14/16
13.16
12/16
11/16
10/16
9/16
8/16
7/16
6/16
5/16
4/16
3/16
2/16
1/16
0/160 10 0 0 0 0 0 0 1 1 1 1 1 1 10 0 0 0 1 1 1 1 0 0 0 0 1 1 1 10 0 1 1 0 0 1 1 0 0 1 1 0 0 1 10 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
b0b1b2b3
Ana
log
Out
put (
Nor
mal
ized
to F
ull S
cale
)
Digital Input Code
-1.5 LSB INL
-2 LSB DNL
Actual 4-bit DACCharacteristic
+1.5 LSB DNL
+1.5 LSB INL
Ideal 4-bit DACCharacteristic
-2 LSB DNL
Fig. 10.1-8
Lecture 340 – Characterization of DACs and Current Scaling DACs (5/1/10) Page 340-14
CMOS Analog Circuit Design © P.E. Allen - 2010
DYNAMIC CHARACTERISTICS OF DIGITAL-ANALOG CONVERTERSDynamic characteristics include the influence of time.Definitions• Conversion speed is the time it takes for the DAC to provide an analog output when the
digital input word is changed.Factor that influence the conversion speed:
Parasitic capacitors (would like all nodes to be low impedance)Op amp gainbandwidthOp amp slew rate
• Gain error of an op amp is the difference between the desired and actual output voltageof the op amp (can have both a static and dynamic influence)
Actual Gain = Ideal Gain x Loop Gain
1 + Loop Gain
Gain error = Ideal Gain-Actual Gain
Ideal Gain = 1
1+Loop Gain
Lecture 340 – Characterization of DACs and Current Scaling DACs (5/1/10) Page 340-15
CMOS Analog Circuit Design © P.E. Allen - 2010
Example of Influence of Op Amp Gain Error on DAC PerformanceAssume that a DAC using an op amp in the inverting configuration with C1 = C2 and
Avd(0) = 1000. Find the largest resolution of the DAC if VREF is 1V and assuming worstcase conditions.Solution
The loop gain of the inverting configuration is LG = C2
C1+C2 Avd(0) = 0.5 1000 = 500.
The gain error is therefore 1/501 0.002. The gain error should be less than thequantization noise of ±0.5LSB which is expressed as
Gain error = 1
501 0.002 VREF2N+1
Therefore the largest value of N that satisfies this equation is N = 7.
Lecture 340 – Characterization of DACs and Current Scaling DACs (5/1/10) Page 340-16
CMOS Analog Circuit Design © P.E. Allen - 2010
Influence of the Op Amp GainbandwidthSingle-pole response:
vout(t) = ACL[1 - e- Ht]vin(t)
whereACL = closed-loop gain
H = GB R1
R1+R2 or GB C2
C1+C2
To avoid errors in DACs (and ADCs), vout(t) must be within ±0.5LSB of the final value bythe end of the conversion time.Multiple-pole response:
Typically the response is underdamped like the following (see Appendix C of text).
+-
Settling Time
Final Value
Final Value + ε
Final Value - ε
ε
ε
vOUT(t)
t00
vOUTvIN
Ts
Upper Tolerance
Lower Tolerance
Fig. 6.1-7
Lecture 340 – Characterization of DACs and Current Scaling DACs (5/1/10) Page 340-17
CMOS Analog Circuit Design © P.E. Allen - 2010
Example of the Influence of GB and Settling Time on DAC PerformanceAssume that a DAC uses a switched capacitor noninverting amplifier with C1 = C2
using an op amp with a dominant pole and GB = 1MHz. Find the conversion time of an 8-bit DAC if VREF is 1V.Solution
From the results in Sections 9.2 and 9.3 of the text, we know that
H = C2
C1+C2 GB = (2 )(0.5)(106) = 3.141x106
and ACL = 1. Assume that the ideal output is equal to VREF. Therefore the value of theoutput voltage which is 0.5LSB of VREF is
1 - 1
2N+1 = 1 - e- H T
or2N+1 = e H T
Solving for T gives
T = N+1
H ln(2) = 0.693 N+1
H = 9
3.141 0.693 = 1.986μs
Lecture 340 – Characterization of DACs and Current Scaling DACs (5/1/10) Page 340-18
CMOS Analog Circuit Design © P.E. Allen - 2010
TESTING OF DACsInput-Output TestTest setup:
N-bitDACunder test
ADC withmore resolution
than DAC(N+2 bits)
DigitalSubtractor(N+2 bits)
DigitalWordInput
(N+2 bits)
Vout
ADCOutput Digital
ErrorOutput�
(N+2 bits)
Fig. 10.1-9
Comments:Sweep the digital input word from 000...0 to 111...1.The ADC should have more resolution by at least 2 bits and be more accurate than theerrors of the DACINL will show up in the output as the presence of 1’s in any bit.
If there is a 1 in the Nth bit, the INL is greater than ±0.5LSBDNL will show up as a change between each successive digital error output.The bits which are greater than N in the digital error output can be used to resolve the
errors to less than ±0.5LSB
Lecture 340 – Characterization of DACs and Current Scaling DACs (5/1/10) Page 340-19
CMOS Analog Circuit Design © P.E. Allen - 2010
Spectral TestTest setup:
Comments:Digital input pattern is selected to
have a fundamental frequency whichhas a magnitude of at least 6N dBabove its harmonics.
Length of the digital sequencedetermines the spectral purity of thefundamental frequency.
All nonlinearities of the DAC (i.e. INL and DNL) will cause harmonics of thefundamental frequency
The THD can be used to determine the SNR dB range between the magnitude of thefundamental and the THD. This SNR should be at least 6N dB to have an INL of less than±0.5LSB for an ENOB of N-bits.
Note that the noise contribution of VREF must be less than the noise floor due tononlinearities.
If the period of the digital pattern is increased, the frequency dependence of INL can bemeasured.
N-bitDACunder test
DigitalPattern
Generator(N bits)
Vout
Clock
DistortionAnalyzer
Vout
t
|Vout(jω)|
ωfsig
SpectralOutput
1000
0
1000
1
1001
1
1111
1
Noise floordue to non-linearities
VREF
Fig. 10.1-10
Lecture 340 – Characterization of DACs and Current Scaling DACs (5/1/10) Page 340-20
CMOS Analog Circuit Design © P.E. Allen - 2010
CURRENT SCALING DIGITAL-ANALOG CONVERTERSClassification of Digital-Analog Converters
Parallel
Voltage ChargeCurrent
Serial
Charge
Digital-Analog Converters
Voltage and Charge
Slow Fast Fig. 10.2-1
Lecture 340 – Characterization of DACs and Current Scaling DACs (5/1/10) Page 340-21
CMOS Analog Circuit Design © P.E. Allen - 2010
General Current Scaling DACs
+
-
I0
I1
I2
IN-1
RFvOUTCurrent
ScalingNetwork
Digital Input Word
VREF
Fig. 10.2-2
The output voltage can be expressed as
VOUT = -RF(I0 + I1 + I2 + ··· + IN-1)
where the currents I0, I1, I2, ... are binary weighted currents.
Lecture 340 – Characterization of DACs and Current Scaling DACs (5/1/10) Page 340-22
CMOS Analog Circuit Design © P.E. Allen - 2010
Binary-Weighted Resistor DACCircuit:
+
-
R
S0I0
VREF
2R
S1I1
4R
S2I2
2N-1R
SN-1
IN-1
IO
RF = K(R/2)
+
-
vOUT
Fig. 10.2-3RLSBRMSB
Comments:1.) RF can be used to scale the gain of the DAC. If RF = KR/2, then
vOUT=-RFIO = -KR
2b0R +
b12R +
b24R +···+
bN-12N-1R VREF vOUT=-K
b02 +
b14 +
b28 +···+
bN-12N VREF
where bi is 1 if switch Si is connected toVREF or 0 if switch Si is connected to ground.
2.) Component spread value = RMSBRLSB
= R
2N-1R = 1
2N-1
3.) Attributes:Insensitive to parasitics fast Large component spread valueTrimming required for large values of N Nonmonotonic
Lecture 340 – Characterization of DACs and Current Scaling DACs (5/1/10) Page 340-23
CMOS Analog Circuit Design © P.E. Allen - 2010
R-2R Ladder Implementation of the Binary Weighted Resistor DACUse of the R-2R concept toavoid large element spreads:
How does the R-2R ladder work?“The resistance seen to the right of anyof the vertical 2R resistors is 2R.”Attributes: • Not sensitive to parasitics
(currents through the resistors never change as Si is varied)
• Small element spread. Resistors made from same unit (2R consist of two in series or Rconsists of two in parallel)
• Not monotonic
+
-
R
S0
I0
VREF
2R I1 I2 IN-1
IO
RF = KR
+
-
vOUT
R
S1
2R
S2
2R
SN-1
2R
2R
Fig. 10.2-4
2R
R 2R
2R2R
RVREF
I
I
2I
2I
4I
4I
8I
Fig. 10.2-4(2R-R)
Lecture 340 – Characterization of DACs and Current Scaling DACs (5/1/10) Page 340-24
CMOS Analog Circuit Design © P.E. Allen - 2010
Current Scaling Using Binary Weighted MOSFET Current SinksCircuit:
+
-2N-1I 2I4I I
S0 SN-3 SN-2 SN-1R2
2N-1 matched FETs 4 matched FETs 2 matched FETs
TransistorArray
+
-
vOUT
IREF =I
VA+
-
A1
VA
+
-
b0 bN-3 bN-2 bN-1
Fig. 10.2-5
VDD
+ -A 2
Operation:vOUT = R2(bN-1·I + bN-2·2I + bN-3·4I + ··· + b0·2N-1·I)
If I = IREF = VREF
2NR2
, then vOUT = b02 +
b14 +
b28 + ··· +
bN-32N-2 +
bN-22N-1 +
bN-12N VREF
Attributes: Fast (no floating nodes) and not monotonic Accuracy of MSB greater than LSBs
Lecture 340 – Characterization of DACs and Current Scaling DACs (5/1/10) Page 340-25
CMOS Analog Circuit Design © P.E. Allen - 2010
High-Speed Current DACsCurrent scaling DAC using current switches:
060926-01
b0 b0
I2
RL
VDD
RL
b1 b1
I4
b2 b2
I8
bN-1 bN-1
I2N
+
−vOUT
vOUT = IRLb02 +
b14 +
b28 + ··· + +
bN-12N
where
bi = +1 if the bit is 1
-1 if the bit is 0A single-ended DAC can be obtained by replacing the left RL by a short.
Lecture 340 – Characterization of DACs and Current Scaling DACs (5/1/10) Page 340-26
CMOS Analog Circuit Design © P.E. Allen - 2010
High-Speed, High-Accuracy Current Scaling DACsThe accuracy is increased by using the same value of current for each switch as shown.
060926-02
d0 d0
I2N
RL
VDD
RL
d1 d1
I2N
d2 d2
I2N
d2N
I2N
+
−vOUT
d3 d3
I2N
N to 2N Encoder
b0 b1 b2 bN
d0 d1 d2 d3 d2N
d2Nd4 d4
I2N
d4
For a 4 bit DAC, there would be 16 current switches.The MSB bit would switch 8 of the current switches to one side.The next-MSB bit would switch 4 of the current switches to one side.Etc.
Lecture 340 – Characterization of DACs and Current Scaling DACs (5/1/10) Page 340-27
CMOS Analog Circuit Design © P.E. Allen - 2010
Increasing the Accuracy of the Current Switching DACThe accuracy of the previous DAC can be increased by using dynamic element matchingtechniques. This is illustrated below where a butterfly switching element allows theswitch control bits, di, to be “randomly” connected to any of the current switches.
060926-03
q0 q0
I2N
RL
VDD
RL
q1 q1
I2N
q2 q2
I2N
q2N
I2N
+
−vOUT
q3 q3
I2N
N to 2N Encoder
b0 b1 b2 bN
d0 d1 d2 d2N
q2Nq4 q4
I2N
d4
q0 q1 q2 q3 q2Nq4
d3
Butterfly Randomizer - Any di can be connected to any qi according to the dynamic element matching algorithm selected.
Lecture 340 – Characterization of DACs and Current Scaling DACs (5/1/10) Page 340-28
CMOS Analog Circuit Design © P.E. Allen - 2010
SUMMARY• DACs scale a voltage reference as an analog output according to a digital word input• Quantization noise is an inherent ±0.5 LSB uncertainty in digitizing an analog value with
a finite resolution converter• The most significant bit requires the greatest accuracy with the least significant bit
requiring the least accuracy• Integral Nonlinearity (INL) is the maximum difference between the actual finite
resolution characteristic and the ideal finite resolution characteristic measured vertically(% or LSB)
• Differential Nonlinearity (DNL) is a measure of the separation between adjacent levelsmeasured at each vertical jump (% or LSB)
• The limits to DAC speed include:- Parasitic capacitors- The op amp gainbandwidth- The op amp slew rate
• Current scaling DACs scale the reference voltage into binary-weighted currents that aresummed into to a resistor to obtain the analog output voltage.
• Current scaling DACs are generally fast but have large element spreads and are notmonotonic
Lecture 350 – Parallel DACs, Improved Resolution DACs and Serial DACs (3/28/10) Page 350-1
CMOS Analog Circuit Design © P.E. Allen - 2010
LECTURE 350 – PARALLEL DACS, IMPROVED DACRESOLUTION AND SERIAL DACS
LECTURE ORGANIZATIONOutline• Voltage scaling DACs• Charge scaling DACs• Extending the resolution of parallel DACs• Serial DACs• SummaryCMOS Analog Circuit Design, 2nd Edition ReferencePages 626-652
Lecture 350 – Parallel DACs, Improved Resolution DACs and Serial DACs (3/28/10) Page 350-2
CMOS Analog Circuit Design © P.E. Allen - 2010
VOLTAGE SCALING DIGITAL-ANALOG CONVERTERSGeneral Voltage Scaling Digital Analog Converter
vOUT
VoltageScalingNetwork
Digital Input Word
VREFDecoder
Logic
V1
V2
V3
V2N
Fig. 10.2-6
Operation:Creates all possible values of the analog output then uses a decoding network to
determine which voltage to select based on the digital input word.
Lecture 350 – Parallel DACs, Improved Resolution DACs and Serial DACs (3/28/10) Page 350-3
CMOS Analog Circuit Design © P.E. Allen - 2010
3-Bit Voltage Scaling Digital-Analog Converter
The voltage at any tap can be expressed as: vOUT = VREF
8 (n 0.5) = VREF16 (2n 1)
Attributes:• Guaranteed
monotonic• Compatible with
CMOStechnology
• Large area if N islarge
• Sensitive toparasitics
• Requires a buffer• Large current can
flow through theresistor string.
b2 b1 b0b2 b1 b0
VREF
R/2
R/2
8
7
6
5
4
3
2
1
R
R
R
R
R
R
R
vOUT
000 001 010 011 100 101 110 111
VREF8
2VREF8
3VREF8
4VREF8
5VREF8
6VREF8
7VREF8
VREF
0
Digital Input Code
v OU
T
(a.) (b.)
Figure 10.2-7 - (a.) Implementation of a 3-bit voltage scaling DAC. (b.) Input-output characteristics of Fig. 10.2-7(a.)
1116 VREF
Input = 101
Lecture 350 – Parallel DACs, Improved Resolution DACs and Serial DACs (3/28/10) Page 350-4
CMOS Analog Circuit Design © P.E. Allen - 2010
Alternate Realization of the 3-Bit Voltage Scaling DAC
b2 b1 b0
VREF
R/2
R/2
8
7
6
5
4
3
2
1
R
R
R
R
R
R
R
vOUT
3-to-8 Decoder
Fig. 10.2-8
Lecture 350 – Parallel DACs, Improved Resolution DACs and Serial DACs (3/28/10) Page 350-5
CMOS Analog Circuit Design © P.E. Allen - 2010
INL and DNL of the Voltage Scaling DACFind an expression for the INL and DNL of the voltage scaling DAC using a worst-caseapproach. For an n-bit DAC, assume there are 2n resistors between VREF and groundand that the resistors are numbered from 1 to 2n beginning with the resistor connected to
VREF and ending with the resistor connected to ground.Integral Nonlinearity
The voltage at the i-th resistor from the top is,
vi = (2n-i)R
(2n-i)R + iR VREF
where there are i resistors above vi and 2n-i below.For worst case, assume that i = 2n-1 (midpoint).
Define Rmax = R + R and Rmin = R - R.The worst case INL is
INL = v2n-1(actual) - v2n-1(ideal)Therefore,
INL = 2n-1(R+ R)VREF
2n-1(R+ R) + 2n-1(R- R) - VREF
2 = R
2R VREF
INL=2n
2nR
2R VREF=2n-1R
RVREF
2n =2n-1R
R LSBs
Differential NonlinearityThe worst case DNL is
DNL = vstep(act) - vstep(ideal)Substituting the actual andideal steps gives,
= (R± R)VREF
2nR - R VREF
2nR
= R± R
R -RR
VREF2n
= ± R
R VREF
2n Therefore,
DNL =± R
R LSBs
VREF
R1
R2
R3
Ri-1
Ri
Ri+1
R2n
R2n-1
1
2
3
i-2
i-1
i
i+1
2n-2
2n-1
2n
Vi
Fig. 10.2-085
Lecture 350 – Parallel DACs, Improved Resolution DACs and Serial DACs (3/28/10) Page 350-6
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 350-1 - Accuracy Requirements of a Voltage-Scaling Digital-AnalogConverter
If the resistor string of a voltage scaling digital-analog converter is a 5 μm widepolysilicon strip having a relative accuracy of ±1%, what is the largest number of bits thatcan be resolved and keep the worst case INL within ±0.5 LSB? For this number of bitswhat is the worst case DNL?Solution
From the previous page, we can write that
2n-1 R
R = 2n-11
100 12
This inequality can be simplified2n 100
which has a solution of n = 6. The value of the DNL for n = 6 is found from the previous page as
DNL = ±1
100 LSBs = ±0.01LSBs
(This is the reason the resistor string is monotonic.)
Lecture 350 – Parallel DACs, Improved Resolution DACs and Serial DACs (3/28/10) Page 350-7
CMOS Analog Circuit Design © P.E. Allen - 2010
CHARGE SCALING DIGITAL-ANALOG CONVERTERSGeneral Charge Scaling Digital-Analog Converter
vOUT
ChargeScalingNetwork
Digital Input Word
VREF
Fig. 10.2-9
General principle is to capacitively attenuate the referencevoltage. Capacitive attenuation is simply:
Calculate as if the capacitors were resistors. For example,
Vout =
1C2
1C1 +
1C2
VREF = C1
C1 + C2 VREF
C1
C2VREF
+
-
Vout
Fig. 10.2-9b
Lecture 350 – Parallel DACs, Improved Resolution DACs and Serial DACs (3/28/10) Page 350-8
CMOS Analog Circuit Design © P.E. Allen - 2010
Binary-Weighted, Charge Scaling DACCircuit:
Operation:1.) All switches
connected to groundduring 1.
2.) Switch Sicloses to VREF if bi = 1 or to ground if bi = 0.Equating the charge in the capacitors gives,
VREFCeq = VREF b0C +b1C2 +
b2C22 + ... +
bN-1C2N 1 = Ctot vOUT = 2C vOUT
which givesvOUT = [b02-1 + b12-2 + b22-3 + ... + bN-12-N]VREF
Equivalent circuit of the binary-weighted, chargescaling DAC is:Attributes:
• Accurate• Sensitive to parasitics• Not monotonic• Charge feedthrough occurs at turn on of switches
+
-
VREF
φ1
C2 2N-2 2N-1C
4C C C
2N-1C
φ2
S0
φ2 φ2 φ2 φ2
S1 S2 SN-2 SN-1
vOUT
TerminatingCapacitor
Fig. 10.2-10
+
-
VREF
Ceq.
2C - Ceq. vOUT
Fig. 10.2-11
Lecture 350 – Parallel DACs, Improved Resolution DACs and Serial DACs (3/28/10) Page 350-9
CMOS Analog Circuit Design © P.E. Allen - 2010
Integral Nonlinearity of the Charge Scaling DACAgain, we use a worst case approach. Assume an n-bit charge scaling DAC with the
MSB capacitor of C and the LSB capacitor of C/2n-1 and the capacitors have a toleranceof C/C.
The ideal output when the i-th capacitor only is connected to VREF is
vOUT (ideal) = C/2i-1
2C VREF = VREF
2i 2n
2n = 2n
2i LSBs
The maximum and minimum capacitance is Cmax = C + C and Cmin = C - C.Therefore, the actual worst case output for the i-th capacitor is
vOUT(actual) = (C± C)/2i-1
2C VREF = VREF
2i ± C·VREF2iC =
2n
2i ± 2n C2iC LSBs
Now, the INL for the i-th bit is given as
INL(i) = vOUT(actual) - vOUT(ideal) = ±2n C
2iC = 2n-i C
C LSBs
Typically, the worst case value of i occurs for i = 1. Therefore, the worst case INL is
INL = ± 2n-1C
C LSBs
Lecture 350 – Parallel DACs, Improved Resolution DACs and Serial DACs (3/28/10) Page 350-10
CMOS Analog Circuit Design © P.E. Allen - 2010
Differential Nonlinearity of the Charge Scaling DACThe worst case DNL for the binary weighted capacitor array is found when the MSB
changes. The output voltage of the binary weighted capacitor array can be written as
vOUT = Ceq.
(2C-Ceq.) + Ceq. VREF
where Ceq are capacitors whose bits are 1 and (2C - Ceq) are capacitors whose bits are 0.
The worst case DNL can be expressed as
DNL = vstep(worst case)
vstep(ideal) - 1 =
vOUT(1000....) - vOUT(0111....)LSB - 1 LSBs
The worst case choice for the capacitors is to choose C1 larger by C and the remainingcapacitors smaller by C giving,
C1=C+ C, C2 = 12(C- C),...,Cn-1=
12n-2(C- C), Cn=
12n-1(C- C), and Cterm=
12n-1(C- C)
Note that n
Cii=2
+ Cterm = C2+ C3+···+ Cn-1+ Cn+ Cterm = C- C
Lecture 350 – Parallel DACs, Improved Resolution DACs and Serial DACs (3/28/10) Page 350-11
CMOS Analog Circuit Design © P.E. Allen - 2010
Differential Nonlinearity of the Charge Scaling DAC - Continued
vOUT(1000...) = C+ C
(C+ C)+(C- C) VREF = C+ C
2C VREF
= C+ C
2C VREF 2n
2n = 2nC+ C
2C LSBs
and
vOUT(0111...) = (C- C) -Cterm
(C+ C)+(C- C) VREF = (C- C) -
12n-1(C- C)
(C+ C)+(C- C) VREF
= C- C
2C 1 -22n VREF =
2n
2nC- C
2C 1 -22n VREF = 2n
C- C2C 1 -
22n LSBs
vOUT(1000...) - vOUT(0111...)
LSB -1 LSBs = 2nC+ C
2C -2nC- C
2C 1-22n -1 = (2n-1)
CC LSBs
Therefore, DNL = (2n - 1)C
C LSBs
Lecture 350 – Parallel DACs, Improved Resolution DACs and Serial DACs (3/28/10) Page 350-12
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 350-2 - DNL and INL of a Binary Weighted Capacitor Array DACIf the tolerance of the capacitors in an 8-bit, binary weighted, charge scaling DAC are
±0.5%, find the worst case INL and DNL.Solution
For the worst case INL, we get from above thatINL = (27)(±0.005) = ±0.64 LSBs
For the worst case DNL, we can write thatDNL = (28-1)(±0.005) = ±1.275 LSBs
Lecture 350 – Parallel DACs, Improved Resolution DACs and Serial DACs (3/28/10) Page 350-13
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 350-3 - Influence of Capacitor Ratio Accuracy on Number of BitsUse the data shown to estimate the number of
bits possible for a charge scaling DAC assuming aworst case approach for INL and that the worstconditions occur at the midscale (1 MSB).Solution
Assuming an INL of ±0.5 LSB, we can write that
INL = ±2N-1 C
C ±
1
2
C
C =
1
2N
Let us assume a unit capacitor of 50 μm by 50μm and a relative accuracy of approximately±0.1%. Solving for N in the above equation givesapproximately 10 bits. However, the ±0.1% figurecorresponds to ratios of 16:1 or 4 bits. In order toget a solution, we estimate the relative accuracy ofcapacitor ratios as
CC 0.001 + 0.0001N
Using this approximate relationship, a 9-bit digital-analog converter should berealizable.
Lecture 350 – Parallel DACs, Improved Resolution DACs and Serial DACs (3/28/10) Page 350-14
CMOS Analog Circuit Design © P.E. Allen - 2010
Binary Weighted, Charge Amplifier DAC
+
-b0
VREF
2N-1
CF = 2NC/K
+
-
vOUT
C2C
φ1
φ1
+
-
b0 b1φ1 b1 b2φ1 b2 bN-1φ1 bN-1
Fig. 10.2-12
C
bN-2φ1 bN-2
2N-2C 2N-3C
Attributes: • No floating nodes which implies insensitive to parasitics and fast • No terminating capacitor required
• With the above configuration, charge feedthrough will be Verror -(COL/2CN) V
• Can totally eliminate parasitics with parasitic-insensitive switched capacitor circuitrybut not the charge feedthrough
Lecture 350 – Parallel DACs, Improved Resolution DACs and Serial DACs (3/28/10) Page 350-15
CMOS Analog Circuit Design © P.E. Allen - 2010
EXTENDING THE RESOLUTION OF PARALLEL DIGITAL-ANALOGCONVERTERS
BackgroundTechnique:
Divide the total resolution N into k smaller sub-DACs each with a resolution of Nk .
Result:Smaller total area.More resolution because of reduced largest to smallest component spread.
Approaches:• Combination of similarly scaled subDACs
Divider approach (scale the analog output of the subDACs)Subranging approach (scale the reference voltage of the subDACs)
• Combination of differently scaled subDACs
Lecture 350 – Parallel DACs, Improved Resolution DACs and Serial DACs (3/28/10) Page 350-16
CMOS Analog Circuit Design © P.E. Allen - 2010
COMBINATION OF SIMILARLY SCALED SUBDACsAnalog Scaling - Divider ApproachExample of combining a m-bitand k-bit subDAC to form am+k-bit DAC.
vOUT = b02 +
b14 + ··· +
bm-12m VREF +
12m
bm2 +
bm+14 + ··· +
bm+k-12k VREF
vOUT = b02 +
b14 + ··· +
bm-12m +
bm2m+1 +
bm+12m+2 + ··· +
bm+k-12m+k VREF
m-MSBbits
k-LSBbits
m-bitMSBDAC
k-bitLSBDAC
÷ 2m
VREF
VREF
Σ++
vOUT
Fig. 10.3-1
Lecture 350 – Parallel DACs, Improved Resolution DACs and Serial DACs (3/28/10) Page 350-17
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 350-4 - Illustration of the Influence of the Scaling FactorAssume that m = 2 and k = 2 in Fig. 10.3-1 and find the transfer characteristic of this
DAC if the scaling factor for the LSB DAC is 3/8 instead of 1/4. Assume that VREF = 1VWhat is the ±INL and ±DNL for this DAC? Is this DAC monotonic or not?
Solution
The ideal DAC output is given as
vOUT = b02 +
b14 +
14
b22 +
b34 =
b02 +
b14 +
b28 +
b316 .
The actual DAC output can be written as
vOUT(act.) = b02 +
b14 +
3b216 +
3b332 =
16b032 +
8b132 +
6b232 +
3b332
The results are tabulated in the following table for this example.
Lecture 350 – Parallel DACs, Improved Resolution DACs and Serial DACs (3/28/10) Page 350-18
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 350-4 - Continued Ideal and Actual Analog Output for the DAC in Ex. 350-4,
The table contains all theinformation we are seekingAn LSB for this example is1/16 or 2/32. The fourthcolumn gives the +INL as1.5LSB and the -INL as0 L S B . The fifth columngives the +DNL as -0.5LSBand the -DNL as -1.5LSBBecause the -DNL is greaterthan -1LSB, this DAC is notmonotonic.
InputDigitalWord
vOUT(act.) vOUT vOUT(act.)- vOUT
Change invOUT(act) -
2/320000 0/32 0/32 0/32 -0001 3/32 2/32 1/32 1/320010 6/32 4/32 2/32 1/320011 9/32 6/32 3/32 1/320100 8/32 8/32 0/32 -3/320101 11/32 10/32 1/32 1/320110 14/32 12/32 2/32 1/320111 17/32 14/32 3/32 1/321000 16/32 16/32 0/32 -3/321001 19/32 18/32 1/32 1/321010 22/32 20/32 2/32 1/321011 25/32 22/32 3/32 1/321100 24/32 24/32 0/32 -3/321101 27/32 26/32 1/32 1/321110 30/32 28/32 2/32 1/32
1111 33/32 30/32 3/32 1/32
Lecture 350 – Parallel DACs, Improved Resolution DACs and Serial DACs (3/28/10) Page 350-19
CMOS Analog Circuit Design © P.E. Allen - 2010
Reference Scaling - Subranging ApproachExample of combining a m-bit and k-bit subDAC to form a m+k-bit DAC.
m-MSBbits
k-LSBbits
m-bitMSBDAC
k-bitLSBDAC
VREF
VREF/2m
Σ++
vOUT
Fig. 10.3-2
vOUT = b02 +
b14 + ··· +
bm-12m VREF +
bm2 +
bm+14 + ··· +
bm+k-12k
VREF2m
vOUT = b02 +
b14 + ··· +
bm-12m +
bm2m+1 +
bm+12m+2 + ··· +
bm+k-12m+k VREF
Accuracy considerations of this method are similar to the analog scaling approach.Advantage: There are no dynamic limitations associated with the scaling factor of 1/2m.
Lecture 350 – Parallel DACs, Improved Resolution DACs and Serial DACs (3/28/10) Page 350-20
CMOS Analog Circuit Design © P.E. Allen - 2010
Current Scaling Dac Using Two SubDACsImplementation:
+
-
I16
I8
I4
I2
I16
I8
I4
I2
15R
RLSB MSB
RF vOUTioi2i1
MSB subDACLSB subDAC
b0b1b2b3b4b5b6b7
CurrentDivider
Fig. 10.3-3
vOUT = RFI b02 +
b14 +
b28 +
b316 +
116
b42 +
b54 +
b68 +
b716
Lecture 350 – Parallel DACs, Improved Resolution DACs and Serial DACs (3/28/10) Page 350-21
CMOS Analog Circuit Design © P.E. Allen - 2010
Charge Scaling DAC Using Two SubDACsImplementation:
+
-
VREF
φ1
C2C
4C
φ2
b7
φ2 φ2 φ2 φ2
b6 b5 b1 b0
vOUT
C
φ2
b48
C8
φ2
b3
φ2
b2
C2C
4CC
8
Cs
Scal
ing
Cap
acito
r
LSB Array MSB ArrayTerminatingCapacitor
070515-01Circuit for LSB Thevenin Eq. Circuit for MSB Thevenin Eq.
Design of the scaling capacitor, Cs:
The series combination of Cs and the LSB array must terminate the MSB array orequal C/8. Therefore, we can write
C8 =
11Cs
+1
2C or
1Cs =
8C -
12C =
162C -
12C =
152C
Lecture 350 – Parallel DACs, Improved Resolution DACs and Serial DACs (3/28/10) Page 350-22
CMOS Analog Circuit Design © P.E. Allen - 2010
Equivalent Circuit of the Charge Scaling Dac Using Two SubDACsSimplified equivalent circuit:
where the Thevenin equivalent voltageof the MSB array is
V1 = 1
15/8 b0 +1/2
15/8 b1 +1/4
15/8 b2 +1/815/8 b3 VREF =
1615
b02 +
b14 +
b28 +
b316 VREF
and the Thevenin equivalent voltage of the LSB array is
V2 = 1/12 b4 +
1/22 b5 +
1/42 b6 +
1/82 b7 VREF =
b42 +
b54 +
b68 +
b816 VREF
Combining the elements of the simplified equivalent circuit above gives
vOUT=
12 +
152
12 +
152 +
815
V1+
815
12 +
152 +
815
V2= 15+15·15
15+15·15+16 V1+16
15+15·15+16 V2= 1516V1+
116V2
vOUT = b02 +
b14 +
b28 +
b316 +
b432 +
b564 +
b6128 +
b7256 VREF =
7
i=0 biVREF
2i+1
+
-
Cs = 2C/15
C + 7C/8 = 15C/8
V1V2
2CvOUT
070515-02
Lecture 350 – Parallel DACs, Improved Resolution DACs and Serial DACs (3/28/10) Page 350-23
CMOS Analog Circuit Design © P.E. Allen - 2010
Charge Amplifier DAC Using Two Binary Weighted Charge Amplifier SubDACsImplementation:
VREF
+
-
vOUT
+
-
C
b4 φ1
b4
C/2
b5 φ1
b5
b6 φ1
b6
b7 φ1
b7
C/4
C/8
+
-2C
φ1
VREF+
-
C
b0 φ1
b0
C/2
b1 φ1
b1
b2 φ1
b2
b3 φ1
b3
C/4
C/8
+
-2C
φ1
C/8
A1 A2
LSB Array MSB Array
vO1
Fig. 10.3-6
Attributes:• MSB subDAC is not dependent upon the accuracy of the scaling factor for the LSB
subDAC.• Insensitive to parasitics, fast• Limited to op amp dynamics (GB)• No ICMR problems with the op amp
Lecture 350 – Parallel DACs, Improved Resolution DACs and Serial DACs (3/28/10) Page 350-24
CMOS Analog Circuit Design © P.E. Allen - 2010
COMBINATION OF DIFFERENTLY SCALED SUBDACsVoltage Scaling MSB SubDAC And Charge Scaling LSB SubDACImplementation:
Ck =2k-1C
Sk-1,A
SF
SF
Bus A
Bus B
Sk,A
Sk,B
Ck-1 =2k-2C
Sk-1,B
C2
=2CC1
=CC
vOUT
S2A
S2B
S1A
S1B
m-to-2m Decoder A
m-to-2m Decoder BVREF
R1 R2 R3 R2m-2 R2m-1 R2m
m-MSB bits
m-MSB bits
m-bit, MSB voltagescaling subDAC
k-bit, LSB chargescaling subDAC
Fig. 10.3-7
Operation:1.) Switches SF and S1B through Sk,B discharge all capacitors.
2.) Decoders A and B connect Bus A and Bus B to the top and bottom, respectively, ofthe appropriate resistor as determined by the m-bits.3.) The charge scaling subDAC divides the voltage across this resistor by capacitivedivision determined by the k-bits.Attributes:
• MSB’s are monotonic but the accuracy is poor• Accuracy of LSBs is good
Lecture 350 – Parallel DACs, Improved Resolution DACs and Serial DACs (3/28/10) Page 350-25
CMOS Analog Circuit Design © P.E. Allen - 2010
Voltage Scaling MSB SubDAC And Charge Scaling LSB SubDAC - ContinuedEquivalent circuit of the voltage scaling (MSB) and charge scaling (LSB) DAC:
Ck =2k-1C
Sk-1,A
Bus A
Bus B
Sk,A
Sk,B
Ck-1 =2k-2C
Sk,B
C2
=2CC1
=CC
vOUTS2A
S2B
S1A
S1B
2-mVREF
V'REF
2-mVREF
V'REF
vOUT
Ceq.
2kC - Ceq.
Bus A
Bus B
v'OUT
Fig. 10.3-8
where,
V’REF = VREF b021 +
b122 + ··· +
bm-22m-1 +
bm-12m
and
v’OUT = VREF
2m bm2 +
bm+122 + ··· +
bm+k2k-1 +
bm+k-12k = VREF
bm2m+1 +
bm+12m+2 + ··· +
bm+k2m+k-1 +
bm+k-12m+k
Adding V’REF and v’OUT gives the DAC output voltage as
vOUT = V’REF + v’OUT = VREFb021+
b122+···+
bm-22m-1+
bm-12m +
bm2m+1+
bm+12m+2+···+
bm+k2m+k-1+
bm+k-12m+k
which is equivalent to an m+k bit DAC.
Lecture 350 – Parallel DACs, Improved Resolution DACs and Serial DACs (3/28/10) Page 350-26
CMOS Analog Circuit Design © P.E. Allen - 2010
Charge Scaling MSB SubDAC and Voltage Scaling LSB SubDAC
vOUT = b021+
b122+···+
bm-22m-1+
bm-12m VREF+
vk2m where vk =
bm21+
bm+122 +···+
bm+k2k-1 +
bm+k-12k VREF
vOUT =b021 +
b122 + ··· +
bm-22m-1 +
bm-12m +
bm2m+1 +
bm+12m+2 + ··· +
bm+k2m+k-1 +
bm+k-12m+k VREF
Attributes:• MSBs have good accuracy• LSBs are monotonic, have poor accuracy - require trimming for good accuracy
C1 =2mC
S2,AS1,A
S1,B
C2 =2m-1C
S2,B
Cm-1
=21CCm
=CCm=C
vOUTSm-2A
Sm-2B
Sm-1A
Sm-1BVREF
k-to-2k
Decoder
k-LSB bits
R1
R2
R3
R2k-2
R2k-1
R2k
VREF
m-bit, MSB charge scaling subDAC
k-bit,LSB
voltage scaling
subDAC
vk
Fig. 10.3-9A
Lecture 350 – Parallel DACs, Improved Resolution DACs and Serial DACs (3/28/10) Page 350-27
CMOS Analog Circuit Design © P.E. Allen - 2010
Tradeoffs in SubDAC Selection to Enhance Linearity PerformanceAssume a m-bit MSB subDAC and a k-bit LSB subDAC.
MSB Voltage Scaling SubDAC and LSB Charge Scaling SubDAC (n = m+k)INL and DNL of the m-bit MSB voltage-scaling subDAC:
INL(R) = 2m-12n
2m R
R = 2n-1 R
R LSBs and DNL(R) = ± R
R 2n
2m = 2k ± R
R LSBs
INL and DNL of the k-bit LSB charge-scaling subDAC:
INL(C) = 2k-1 C
C LSBs and DNL(C) = (2k-1) C
C LSBs
Combining these relationships:
INL = INL(R) + INL(C) = 2n-1R
R + 2k-1C
C LSBs
and DNL = DNL(R) + DNL(C) = 2kR
R + (2k-1)C
C LSBs
MSB Charge Scaling SubDAC and LSB Voltage Scaling SubDAC
INL = INL(R) + INL(C) = 2k-1R
R + 2n-1C
C LSBs
and DNL = DNL(R) + DNL(C) =R
R + (2n-1)C
C LSBs
Lecture 350 – Parallel DACs, Improved Resolution DACs and Serial DACs (3/28/10) Page 350-28
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 350-5 - Design of a DAC using Voltage Scaling for MBSs and ChargeScaling for LSBs
Consider a 12-bit DAC that uses voltage scaling for the MSBs charge scaling for theLSBs. To minimize the capacitor element spread and the number of resistors, choose m =5 and k = 7. Find the tolerances necessary for the resistors and capacitors to give an INLand DNL equal to or less than 2 LSB and 1 LSB, respectively.Solution
Substituting n = 12 and k = 7 into the previous equations gives
2 = 211 R
R + 26 C
C and 1 = 27 R
R + (27-1) C
C
Solving these two equations simultaneously givesC
C = 24-2
211 - 26 - 24 = 0.0071 C
C = 0.71%
RR =
28 - 26 -2218 - 213 - 211 = 0.0008
RR = 0.075%
We see that the capacitor tolerance will be easy to meet but that the resistor tolerancewill require resistor trimming to meet the 0.075% requirement. Because of the 2n-1multiplying R/R in the relationship, we are stuck with approximately 0.075%.Therefore, choose m = 2 (which makes the 0.075% easier to achieve) and let k = 10 whichgives R/R = 0.083% and C/C = 0.12%.
Lecture 350 – Parallel DACs, Improved Resolution DACs and Serial DACs (3/28/10) Page 350-29
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 350-6 - Design of a DAC using Charge Scaling for MBSs and VoltageScaling for LSBs
Consider a 12-bit DAC that uses charge scaling for the MSBs voltage scaling for theLSBs. To minimize the capacitor element spread and the number of resistors, choose m =7 and k = 5. Find the tolerances necessary for the resistors and capacitors to give an INLand DNL equal to or less than 2 LSB and 1 LSB, respectively.Solution
Substituting the values of this example into the relationships developed on a previousslide, we get
2 = 24 R
R + 211 C
C and 1 = R
R + (212-1) C
C
Solving these two equations simultaneously gives
C
C = 24-2
216-211-24 = 0.000221 C
C = 0.0221% and R
R 3
25-1 = 0.0968 R
R = 9.68%
For this example, the resistor tolerance is easy to meet but the capacitor tolerance willbe difficult. To achieve accurate capacitor tolerances, we should decrease the value of mand increase the value of k to achieve a smaller capacitor value spread and therebyenhance the tolerance of the capacitors. If we choose m = 4 and k = 8, the capacitortolerance is 0.049% and the resistor tolerance becomes 0.79% which is still reasonable.The largest to smallest capacitor ratio is 8 rather than 64 which helps to meet thecapacitor tolerance requirements.
Lecture 350 – Parallel DACs, Improved Resolution DACs and Serial DACs (3/28/10) Page 350-30
CMOS Analog Circuit Design © P.E. Allen - 2010
SERIAL DIGITAL-ANALOG CONVERTERSSerial DACs• Typically require one clock pulse to convert one bit• Types considered here are:
Charge-redistributionAlgorithmic
Charge Redistribution DACImplementation:
VREF
S2
S3
S1
S4C2C1 vC2
Fig. 10.4-1Operation:
Switch S1 is the redistribution switch that parallels C1 and C2 sharing their chargeSwitch S2 precharges C1 to VREF if the ith bit, bi, is a 1Switch S3 discharges C1 to zero if the ith bit, bi, is a 0Switch S4 is used at the beginning of the conversion process to initially discharge C2Conversion always begins with the LSB bit and goes to the MSB bit.
Lecture 350 – Parallel DACs, Improved Resolution DACs and Serial DACs (3/28/10) Page 350-31
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 350-7 - Operation of the Serial, Charge Redistribution DACAssume that C1 = C2 and that
the digital word to be convertedis given as b0 = 1, b1 = 1, b2 = 0,and b3 = 1. Follow through thesequence of events that result inthe conversion of this digitalinput word.Solution1.) S4 closes setting vC2 = 0.2.) b3 = 1, closes switch S2 causing vC1 = VREF.3.) Switch S1 is closed causing vC1 = vC2 = 0.5VREF.4.) b2 = 0, closes switch S3, causing vC1 = 0V.5.) S1 closes, the voltage across both C1 and C2 is 0.25VREF.6.) b1 = 1, closes switch S2 causing vC1 = VREF.7.) S1 closes, the voltage across both C1 and C2 is (1+0.25)/2VREF = 0.625VREF.8.) b0 = 1, closes switch S2 causing vC1 = VREF.9.) S1 closes, the voltage across both C1 and C2 is (0.625 + 1)/2VREF = 0.8125VREF =
(13/16)VREF.
0 1 2 3 4 5 6 7 8
1
3/4
1/2
1/4
0
t/T
v C1/
VR
EF
0 1 2 3 4 5 6 7 8
1
3/4
1/2
1/4
0
t/T
v C2/
VR
EF13/16 13/16
Fig. 10.4-2
Lecture 350 – Parallel DACs, Improved Resolution DACs and Serial DACs (3/28/10) Page 350-32
CMOS Analog Circuit Design © P.E. Allen - 2010
Pipeline DACThe pipeline DAC is simply an extension of the sub-DACs concept to the limit where thebits converted by each sub-DAC is 1.Implementation:
Σ z-11/2
bN-1 = ±1
Σ z-11/2
bN-2 = ±1
Σ z-11/2
b0 = ±1
0
VREF
vOUT
Fig. 10.4-3
Vout(z) = [b0z-1 + 2-1b1z-2 + ··· + 2-(N-2)bN-2z-(N-1) + bN-1z-N]VREF
where bi is either ±1 if the ith bit is high or low. The z-1 blocks represent a delay of oneclock period between the 1-bit sub-DACs.Attributes:• Takes N+1 clock cycles to convert the digital input to an analog output• However, a new analog output is converted every clock after the initial N+1 clocks
Lecture 350 – Parallel DACs, Improved Resolution DACs and Serial DACs (3/28/10) Page 350-33
CMOS Analog Circuit Design © P.E. Allen - 2010
Algorithmic (Iterative) DACImplementation:
ΣSample
andhold
+1
+1
12
+VREF A
B-VREF
vOUT
FIG. 10.4-4
Closed form of the previous series expression is,
Vout(z) = biz-1VREF1 - 0.5z-1
Operation:Switch A is closed when the ith bit is 1 and switch B is closed when the ith bit is 0.
Start with the LSB and work to the MSB.
Lecture 350 – Parallel DACs, Improved Resolution DACs and Serial DACs (3/28/10) Page 350-34
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 350-8 - Digital-Analog Conversion Using the Algorithmic MethodAssume that the digital word to be converted is 11001 in the order of LSB to MSB
Find the converted output voltage and sketch a plot of vOUT/VREF as a function of t/Twhere T is the period for one conversion.Solution1.) The conversion starts by zeroing the
output (not shown on Fig. 10.4-4).2.) The LSB = 1, switch A is closed and
VREF is summed with zero to give anoutput of +VREF.
3.) The next LSB = 0, switch B is closed andvOUT = -VREF+0.5VREF = -0.5VREF.
4.) The next LSB = 0, switch B is closed andvOUT = -VREF+0.5(-0.5VREF) = -1.25VREF.
5.) The next LSB = 1, switch A is closed and vOUT = VREF+0.5(-1.25VREF) = 0.375VREF.6.) The MSB = 1, switch A is closed and vOUT = VREF + 0.5(0.375VREF) = 1.1875VREF= (19/16)VREF. (Note that because the actual VREF of this example if ±VREF or 2VREF,the analog value of the digital word 11001 is 19/32 times 2VREF or (19/16)VREF.)
0 1 2 3 4 5
2.0
19/161.0
0
-1/2
3/8
-1.0-5/4
-2.0
vOUT/VREF
t
Fig. 10.4-5
Lecture 350 – Parallel DACs, Improved Resolution DACs and Serial DACs (3/28/10) Page 350-35
CMOS Analog Circuit Design © P.E. Allen - 2010
SUMMARY• Voltage scaling DACs are monotonic, use equal resistors but are sensitive to capacitve
parasitics• Charge scaling DACs are fast with good accuracy but have large element spread and are
nonmonotonic• DAC resolution can be increased by combining several subDACs with smaller
resolution• Methods of combining include scaling the output or the reference of the non-MSB
subDACs• SubDACs can use similar or different scaling methods• Tradeoffs in the number of bits per subDAC and the type of subDAC allow minimization
of the INL and DNL• Serial, charge redistribution DAC is simple and requires minimum area but is slow and
requires complex external circuitry• Serial, algorithmic DAC is simple and requires minimum area but is slow and requires
complex external circuitry
Lecture 360 – Characterization of ADCs and Sample and Hold Circuits (3/29/10) Page 360-1
CMOS Analog Circuit Design © P.E. Allen - 2010
LECTURE 360 – CHARACTERIZATION OF ADCS AND SAMPLEAND HOLD CIRCUITSLECTURE ORGANIZATION
Outline• Introduction to ADCs• Static characterization of ADCs• Dynamic characteristics of ADCs• Sample and hold circuits• Design of a sample and hold• SummaryCMOS Analog Circuit Design, 2nd Edition ReferencePages 652-665
Lecture 360 – Characterization of ADCs and Sample and Hold Circuits (3/29/10) Page 360-2
CMOS Analog Circuit Design © P.E. Allen - 2010
INTRODUCTIONGeneral Block Diagram of an Analog-Digital Converter
DigitalProcessor
Prefilter Sample/Hold Quantizer Encoder
x(t) y(kTN)
Fig.10.5-1
• Prefilter - Avoids the aliasing of high frequency signals back into the baseband of theADC
• Sample-and-hold - Maintains the input analog signal constant during conversion• Quantizer - Finds the subrange that corresponds to the sampled analog input• Encoder - Encoding of the digital bits corresponding to the subrange
Lecture 360 – Characterization of ADCs and Sample and Hold Circuits (3/29/10) Page 360-3
CMOS Analog Circuit Design © P.E. Allen - 2010
Nyquist Frequency Analog-Digital ConvertersThe sampled nature of the ADC places a practical limit on the bandwidth of the input
signal. If the sampling frequency is fS, and fB is the bandwidth of the input signal, thenfB < 0.5fS
which is simply the Nyquistrelationship which states thatto avoid aliasing, thesampling frequency must begreater than twice thehighest signal frequency.
fB-fB 0 f
fB-fB 0 fSfS-fB fS+fB 2fS2fS-fB 2fS+fBf
-fB 0 fS 2fSf
AntialiasingFilter
fS2
fB-fB 0f
fS2
fS2
fS
fS
Continuous time frequency response of the analog input signal.
Sampled data equivalent frequency response where fB < 0.5fS.
Case where fB > 0.5fS causing aliasing.
Use of an antialiasing filter to avoid aliasing.
Fig. 10.5-
Lecture 360 – Characterization of ADCs and Sample and Hold Circuits (3/29/10) Page 360-4
CMOS Analog Circuit Design © P.E. Allen - 2010
Classification of Analog-Digital ConvertersAnalog-digital converters can be classified by the relationship of fB and 0.5fS and by theirconversion rate.• Nyquist ADCs - ADCs that have fB as close to 0.5fS as possible.• Oversampling ADCs - ADCs that have fB much less than 0.5fS.
Classification of Analog-to-Digital Converter Architectures
ConversionRate Nyquist ADCs Oversampled ADCs
Slow Integrating (Serial) Very high resolution <14-16 bits
MediumSuccessive
Approximation1-bitPipeline Algorithmic
Moderate resolution <10-12 bits
FastFlash Multiple-bit
Pipeline Folding andinterpolating
Low resolution < 6-8 bits
Lecture 360 – Characterization of ADCs and Sample and Hold Circuits (3/29/10) Page 360-5
CMOS Analog Circuit Design © P.E. Allen - 2010
STATIC CHARACTERIZATION OF ANALOG-TO-DIGITAL CONVERTERSDigital Output Codes
Digital Output Codes used for ADCs
Decimal Binary Thermometer Gray Two’sComplement
0 000 0000000 000 0001 001 0000001 001 1112 010 0000011 011 1103 011 0000111 010 1014 100 0001111 110 1005 101 0011111 111 0116 110 0111111 101 0107 111 1111111 100 001
Lecture 360 – Characterization of ADCs and Sample and Hold Circuits (3/29/10) Page 360-6
CMOS Analog Circuit Design © P.E. Allen - 2010
Input-Output CharacteristicsIdeal input-output characteristics of a 3-bit ADC
Analog Input Value Normalized to VREF
000
001
010
011
100
101
110
111
Dig
ital O
utpu
t Cod
e
Ideal 3-bitCharacteristic
Figure 10.5-3 Ideal input-output characteristics of a 3-bit ADC.
Infinite ResolutionCharacteristic
1 LSB
18
28
38
48
58
68
08
78
1 LSB
vinVREF
0.5
1.0
0.0-0.5Q
uant
izat
ion
Noi
se L
SBs
88
Lecture 360 – Characterization of ADCs and Sample and Hold Circuits (3/29/10) Page 360-7
CMOS Analog Circuit Design © P.E. Allen - 2010
Definitions• The dynamic range, signal-to-noise ratio (SNR), and the effective number of bits
(ENOB) of the ADC are the same as for the DAC• Resolution of the ADC is the smallest analog change that distinguishable by an ADC.• Quantization Noise is the ±0.5LSB uncertainty between the infinite resolution
characteristic and the actual characteristic.• Offset Error is the difference between the ideal finite resolution characteristic and
actual finite resolution characteristic• Gain Error is the
difference betweenthe ideal finiteresolution charact-eristic and actualfinite resolutioncharacteristicmeasured at full-scale input. Thisdifference isproportional to theanalog inputvoltage.
000
001
010
011
100
101
110
111
vinVREF
Dig
ital O
utpu
t Cod
e
Offset = 1.5 LSBs
000
001
010
011
100
101
110
111
08
18
28
38
48
58
68
78
88
vinVREF
Dig
ital O
utpu
t Cod
e
Gain Error = 1.5LSBs
(a.) (b.)Figure 10.5-4 - (a.) Example of offset error for a 3-bit ADC. (b.) Example of gainerror for a 3-bit ADC.
IdealCharacteristic
IdealCharacteristic
08
18
28
38
48
58
68
78
88
ActualCharacteristic
Lecture 360 – Characterization of ADCs and Sample and Hold Circuits (3/29/10) Page 360-8
CMOS Analog Circuit Design © P.E. Allen - 2010
Integral and Differential NonlinearityThe integral and differential nonlinearity of the ADC are referenced to the vertical
(digital) axis of the transfer characteristic.• Integral Nonlinearity (INL) is the maximum difference between the actual finite
resolution characteristic and the ideal finite resolution characteristic measured vertically(% or LSB)
• Differential Nonlinearity (DNL) is a measure of the separation between adjacent levelsmeasured at each vertical step (% or LSB).
DNL = (Dcx - 1) LSBs
where Dcx is the size of the actual vertical step in LSBs.
Note that INL and DNL of an analog-digital converter will be in terms of integers incontrast to the INL and DNL of the digital-analog converter. As the resolution of theADC increases, this restriction becomes insignificant.
Lecture 360 – Characterization of ADCs and Sample and Hold Circuits (3/29/10) Page 360-9
CMOS Analog Circuit Design © P.E. Allen - 2010
Example of INL and DNL
000
001
010
011
100
101
110
111
08
18
28
38
48
58
68
78
88
vinVREF
Dig
ital O
utpu
t Cod
e
Example of INL and DNL for a 3-bit ADC.) Fig.10.5-5
IdealCharacteristic
ActualCharacteristic
INL =+1LSB
INL =-1LSB
DNL =+1LSB
DNL =0 LSB
Note that the DNL and INL errors can be specified over some range of the analog input.
Lecture 360 – Characterization of ADCs and Sample and Hold Circuits (3/29/10) Page 360-10
CMOS Analog Circuit Design © P.E. Allen - 2010
MonotonicityA monotonic ADC has all vertical jumps positive. Note that monotonicity can only bedetected by DNL.Example of a nonmonotonic ADC:
000
001
010
011
100
101
110
111
08
18
28
38
48
58
68
78
88
vinVREF
Dig
ital O
utpu
t Cod
e
DNL =-2 LSB
ActualCharacteristic
IdealCharacteristic
Fig. 10.5-6LIf a vertical jump is 2LSB or greater, missing output codes may result.If a vertical jump is -1LSB or less, the ADC is not monotonic.
Lecture 360 – Characterization of ADCs and Sample and Hold Circuits (3/29/10) Page 360-11
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 360-1 - INL and DNL of a 3-bit ADC
Find the INL and DNL for the 3-bit ADC shown on the previous slide.SolutionWith respect to the digital axis:1.) The largest value of INL for this 3-bit ADC occurs between 3/16 to 5/16 or 7/16 to
9/16 and is 1LSB. 2.) The smallest value of INL occurs
between 11/16 to 12/16 and is-2LSB.
3.) The largest value of DNL occurs at3/16 or 6/8 and is +1LSB.
4.) The smallest value of DNL occursat 9/16 and is -2LSB which iswhere the converter becomesnonmonotonic.
000
001
010
011
100
101
110
111
08
18
28
38
48
58
68
78
88
vinVREF
Dig
ital O
utpu
t Cod
e
DNL =-2 LSB
ActualCharacteristic
IdealCharacteristic
Fig. 10.5-6DL
INL =+1LSB
INL =-2LSB
DNL =+1 LSB
Lecture 360 – Characterization of ADCs and Sample and Hold Circuits (3/29/10) Page 360-12
CMOS Analog Circuit Design © P.E. Allen - 2010
DYNAMIC CHARACTERISTICS OF ADCsWhat are the Important Dynamic Characteristics for ADCs?
The dynamic characteristics of ADCs are influenced by:• Comparators
- Linear response- Slew response
• Sample-hold circuits• Circuit parasitics• Logic propagation delay
Lecture 360 – Characterization of ADCs and Sample and Hold Circuits (3/29/10) Page 360-13
CMOS Analog Circuit Design © P.E. Allen - 2010
ComparatorThe comparator is the quantizing unit of ADCs.
Open-loop model:
+
-Av(s)ViVi
VOS
Ri
RoVo
V1
V2Comparator Fig.10.5-7Nonideal aspects:• Input offset voltage, VOS (a static characteristic)
• Propagation time delay- Bandwidth (linear)
Av(s) = Av(0)s
c+ 1
= Av(0)
s c + 1
- Slew rate (nonlinear)
T = C· V
I (I constant) = V
Slew Rate
Lecture 360 – Characterization of ADCs and Sample and Hold Circuits (3/29/10) Page 360-14
CMOS Analog Circuit Design © P.E. Allen - 2010
SAMPLE AND HOLD CIRCUITSRequirements of a Sample and Hold CircuitThe objective of the sample and hold circuit is to sample the unknown analog signal andhold that sample while the ADC decodes the digital equivalent output.The sample and hold circuit must:
1.) Have the accuracy required for the ADC resolution, i.e. accuracy = 100%
2N
2.) The sample and hold circuit must be fast enough to work in a two-phase clock. For anADC with a 100 Megasample/second sample rate, this means that the sample and holdmust perform its function within 5 nanoseconds.3.) Precisely sample the analog signal at the same time for each clock. An advantage ofthe sample and hold circuit is that it removes the precise timing requirements from theADC itself.4.) The power dissipation of the sample and hold circuit must be small. Unfortunately,the above requirements for accuracy and speed will mean that the power must beincreased as the bits are increased and/or the clock period reduced.
Lecture 360 – Characterization of ADCs and Sample and Hold Circuits (3/29/10) Page 360-15
CMOS Analog Circuit Design © P.E. Allen - 2010
Sample-and-Hold CircuitWaveforms of a sample-and-holdcircuit:
Definitions:• Acquisition time (ta) = time requiredto acquire the analog voltage• Settling time (ts) = time required tosettle to the final held voltage to withinan accuracy tolerance
Tsample = ta + ts Maximum sample rate = fsample(max) = 1
Tsample
Other consideratons:• Aperture time= the time required for the sampling switch to open after the S/Hcommand is initiated• Aperture jitter = variation in the aperture time due to clock variations and noiseTypes of S/H circuits:• No feedback - faster, less accurate• Feedback - slower, more accurate
ta ts
Hold Sample HoldS/H Command
vin*(t)
vin*(t)vin(t)
vin(t)
Time
Am
plitu
de
Fig.10.5-9
Output of S/Hvalid for ADC
conversion
Lecture 360 – Characterization of ADCs and Sample and Hold Circuits (3/29/10) Page 360-16
CMOS Analog Circuit Design © P.E. Allen - 2010
Open-Loop, Buffered S/H CircuitCircuit:
+-
φvin(t)vout(t)
CHSwitchClosed
(sample)
SwitchOpen(hold)
SwitchClosed
(sample)
vin(t)vout(t)
vin(t), vout(t) vin(t), vout(t)
Time
Am
plitu
de
Fig.10.5-10
Attributes:• Fast, open-loop• Requires current from the input to charge CH
• DC voltage offset of the op amp and the charge feedthrough of the switch will create dcerrors
Lecture 360 – Characterization of ADCs and Sample and Hold Circuits (3/29/10) Page 360-17
CMOS Analog Circuit Design © P.E. Allen - 2010
Settling TimeAssume the op amp has a dominant pole at - a and a second pole at -GB.
The unity-gain response can be approximated as, A(s) GB2
s2 + GB·s + GB2
The resulting step response is, vout(t) = 1 - 43 e-0.5GB·t sin
34 GB·t +
Defining the error as the difference between the final normalized value and vout(t), gives,
Error(t) = = 1 - vout(t) = 43 e-0.5GB·t
In most ADCs, the error is equal to ±0.5LSB. Since the voltage is normalized,1
2N+1 = 43 e-0.5GB·ts e-0.5GB·ts =
43 2N
Solving for the time, ts, required to settle with ±0.5LSB from the above equation gives
ts = 2
GB ln43 2N =
1GB [1.3863N + 1.6740]
Thus as the resolution of the ADC increases, the settling time for any unity-gain bufferamplifiers will increase. For example, if we are using the open-loop, buffered S/H circuitin a 10 bit ADC, the amount of time required for the unity-gain buffer with a GB of 1MHzto settle to within 10 bit accuracy is 2.473μs.
Lecture 360 – Characterization of ADCs and Sample and Hold Circuits (3/29/10) Page 360-18
CMOS Analog Circuit Design © P.E. Allen - 2010
Open-Loop, Switched-Capacitor S/H CircuitCircuit:
+-
φ1dφ1φ2
vin(t) vout (t)C
+-
φ1dφ1φ2
vin(t) vout (t)
C
+-
C
φ2 φ1
φ1d
+
-
+
-
Fig.10.5-11
Switched capacitor S/H circuit. Differential switched-capacitor S/H
• Delayed clock used to remove input dependent feedthrough.• Differential version has lower PSRR, cancellation of even harmonics, and reduction of
charge injection and clock feedthrough
Lecture 360 – Characterization of ADCs and Sample and Hold Circuits (3/29/10) Page 360-19
CMOS Analog Circuit Design © P.E. Allen - 2010
Open-Loop, Diode Bridge S/H CircuitDiode bridge S/H circuit:
VDD
060927-01
vIN(t) vOUT(t)
CH
IBClock
IBClock
vIN(t) vOUT(t)
CH
rd rd
rd rdRON = rd
Sample phase - diodesforward biased.
vIN(t) vOUT(t)
CHROFF = ∞
Hold phase - diodesreversed biased.
D1 D2
D3 D4
Blowthru Capacitor
MOS diode bridge S/H circuit:VDD
060927-02
vIN(t) vOUT(t)
CH
IBClock
IBClock
vIN(t) vOUT(t)
CH
gm
RON = 1/gm
Sample phase - MOSdiodes forward biased.
vIN(t) vOUT(t)
CHROFF = ∞
Hold phase - MOSdiodes reversed biased.
1gm1
gm1
gm1
M1 M2 M3 M4
Blowthru Capacitor
Lecture 360 – Characterization of ADCs and Sample and Hold Circuits (3/29/10) Page 360-20
CMOS Analog Circuit Design © P.E. Allen - 2010
Practical Implementation of the Diode Bridge S/H Circuit
060927-03
IB IB
VDD
VSS
CH
vout(t)vin(t)
D1 D2
D3 D4 +-
2IB
D5
D6SampleHold
M1 M2
Practical implementation of the diode bridge sample and hold (sample mode).
IB IB
VDD
VSS
CH
vout(t)vin(t)
D1 D2
D3 D4 +-
2IB
D5
D6SampleHold
M1 M2
2IB
IB
IB
Hold mode.
IB2
IB2
During the hold mode, the diodes D5 and D6 become forward biased and clamp the upperand lower nodes of the sampling bridge to the sampled voltage.
Lecture 360 – Characterization of ADCs and Sample and Hold Circuits (3/29/10) Page 360-21
CMOS Analog Circuit Design © P.E. Allen - 2010
Closed-Loop S/H CircuitCircuit:
+-
+-
φ1
φ1
φ2
CH
vout(t)
vin(t)
+- +
-φ1
φ2
CH
vout(t)vin(t)
Fig.10.5-13
Closed-loop S/H circuit. φ1 is the sample phase and φ2 is the hold phase.
An improved version.
Attributes:• Accurate• First circuit has signal-dependent feedthrough• Slower because of the op amp feedback loop
Lecture 360 – Characterization of ADCs and Sample and Hold Circuits (3/29/10) Page 360-22
CMOS Analog Circuit Design © P.E. Allen - 2010
Closed-Loop, Switched Capacitor S/H CircuitsCircuit:
+- vout(t)vin(t) φ1d
φ1
φ2
CH +-
φ2
φ1 φ2dφ1d
φ2 φ1d
φ2d
φ1d
φ2d
φ1d φ2
φ1
φ2φ1
CH
CH
CH
CH
CH
CH
vout(t)vin(t)
+
-
+
-
φ1 φ2d
-+
070616-02
Switched capacitor S/H circuitwhich autozeroes the op ampinput offset voltage.
A differential version that avoids large changes at the op amp output
New charge (φ2)
Old charge (φ2)
New charge (φ2)
Old charge (φ2)
Attributes:• Accurate• Signal-dependent feedthrough eliminated by a delayed clock• Differential circuit keeps the output of the op amps constant during the 1 phase
avoiding slew rate limits
Lecture 360 – Characterization of ADCs and Sample and Hold Circuits (3/29/10) Page 360-23
CMOS Analog Circuit Design © P.E. Allen - 2010
Current-Mode S/H CircuitCircuit:
VDD
IB
CH
φ1φ1
φ2
iin iout
Fig.10.5-15Attributes:• Fast• Requires current in and out• Good for low voltage implementations
Lecture 360 – Characterization of ADCs and Sample and Hold Circuits (3/29/10) Page 360-24
CMOS Analog Circuit Design © P.E. Allen - 2010
Aperature Jitter in S/H CircuitsIllustration:
If we assume that vin(t) =Vpsin t, then themaximum slope is equal to
Vp.
Therefore, the value of Vis given as
V = dvindt t = Vp t .
The rms value of this noise is given as
V(rms) = dvindt t =
Vp t
2 .
The aperature jitter can lead to a limitation in the desired dynamic range of an ADC. Forexample, if the aperature jitter of the clock is 100ps, and the input signal is a full scalepeak-to-peak sinusoid at 1MHz, the rms value of noise due to this aperature jitter is111μV(rms) if the value of VREF = 1V.
Analog-DigitalConverter
Clock
AnalogInput
DigitalOutput ΔV
t
vin
Aperature Jitter = ΔtFigure10.5-14 - Illustration of aperature jitter in an ADC.
vin(to)
to
Lecture 360 – Characterization of ADCs and Sample and Hold Circuits (3/29/10) Page 360-25
CMOS Analog Circuit Design © P.E. Allen - 2010
DESIGN OF A SAMPLE AND HOLD AMPLIFIERSpecificationsAccuracy = 10 bitsClock frequency is 10 MHzPower dissipation 1mWSignal level is from 0 to 1VSlew rate 100V/μs with CL = 1pFUse 0.25μm CMOS
Technology Parameters (Cox = 60.6x10-4 F/m2):
Typical Parameter ValueParameter
SymbolParameter Description
N-Channel P-Channel
Units
VT0Threshold Voltage(VBS = 0)
0.5± 0.15 -0.5 ± 0.15 V
K' Transconductance Para-meter (insaturation)
120.0 ± 10% 25.0 ± 10% μA/V2
Bulk thresholdparameter
0.4 0.6 (V)1/2
Channel lengthmodulation parameter
0.32 (L=Lmin)0.06 (L 2Lmin)
0.56 (L=Lmin)0.08 (L 2Lmin)
(V)-1
2| F| Surface potential at strong inversion 0.7 0.8 V
Lecture 360 – Characterization of ADCs and Sample and Hold Circuits (3/29/10) Page 360-26
CMOS Analog Circuit Design © P.E. Allen - 2010
Op Amp DesignGain:
Gain error = 1
1+Loop Gain 0.5 LSB = 1
211
Therefore, the op amp gain 211 = 2048 V/VChoose the op amp gain as 5000 V/V
Gainbandwidth:For a dominant pole op amp with unity-gain feedback, the relationship between the
gain-bandwidth (GB), accuracy (N) and speed (ts) is
ts = N+1GB ln(2) = 0.693
N+1GB
Therefore, if ts 0.5 Tclock = 50 ns (choose ts = 10 ns). For N = 10, the gain-bandwidthis
GB = 0.762x109 = 120 MHzDominant pole is 24 kHz and with an output capacitance of 1pF this means the outputresistance of the op amp must be 6.6 M .
Lecture 360 – Characterization of ADCs and Sample and Hold Circuits (3/29/10) Page 360-27
CMOS Analog Circuit Design © P.E. Allen - 2010
Op Amp Design – ContinuedThe previous specifications suggest a
self-compensated op amp. The gain andoutput resistance should be easy to achievewith a cascaded output. A folded-cascodeop amp is proposed for the design. Inorder to have the 0-1V signal range, a p-channel, differential input is selected. Thiswill give the input 0-1V range. The outputwill effectively be 0-1V with the unity gainfeedback around the op amp.
Bias Currents:The 100V/μs slew rate requires I3 = 100μA. Setting I4 = I5 = 125μA gives a powerdissipation of 0.875mW with VDD = 2.5V.
061021-01
VNB1
M4 M5
I6
VPB2
I4 I5
VDD = 2.5V
I7M6 M7
VNB2
M8 M9
M10 M11
+
−vIN vOUT
VPB1
I1 I2
M1 M2
M3
I3
CL
Lecture 360 – Characterization of ADCs and Sample and Hold Circuits (3/29/10) Page 360-28
CMOS Analog Circuit Design © P.E. Allen - 2010
Op Amp Design – ContinuedTransistor sizes:Design M4-M7 to give a saturation voltage of 0.1V with 125μA.
W4L4 =
W5L5 =
W6L6 =
W7L7 =
2IDKn'·VDS(sat)2 =
2·125120·0.01 200
Since the upper swing is not as important, choose a saturation voltage of 0.25 for M8 –M11.
W8L8 =
W9L9 =
W10L10 =
W11L11 =
2IDKp'·VDS(sat)2 =
2·12525·0.0625 = 160
To get the GB of 120 MHz, this implies the gm of M1 and M2 is
gm = GB·CL = (120x106·2 )(10-12) = 762 μS
W1L1 =
W2L2 =
gm2
2IDKp' = 762·7622·25·50 = 232
Let the upper input common mode voltage be 1.5V which gives the W/L of M3 as,
1V = VSG1 + VSD3 = 0.631 + VSD3 VSD3 = 0.369V
W3L3 60
Lecture 360 – Characterization of ADCs and Sample and Hold Circuits (3/29/10) Page 360-29
CMOS Analog Circuit Design © P.E. Allen - 2010
Op Amp Design – ContinuedWe now need to check the output resistance and the gain to make sure the specificationsare satisfied. Let us choose twice minimum channel length to keep the capacitiveparasitics minimized and not have the output resistance too small. Therefore at quiescentconditions,
rds5 = 133k , rds7 = 222k , gm7 = 1.935mS and rds2 = 250k
Routdown (rds5||rds2)gm7rds7 = 37.29M
rds9 =rds11 = 167k , and gm11 = 1.697mS
Routup rds11gm9rds9 = 47.33M
Rout 20.86M
The low frequency gain is,Av gm1Rout
= 762μS·20.86M = 15,886 V/VThe frequency response will be as shown:
061023-02
log10f
15,886
Gain
5,000
24kHz 120MHz
7.55kHz1
Lecture 360 – Characterization of ADCs and Sample and Hold Circuits (3/29/10) Page 360-30
CMOS Analog Circuit Design © P.E. Allen - 2010
Op Amp Bias VoltagesWe also need to design the bias voltages VNB1, VNB2, VPB1 and VPB2. This can be doneusing the following circuit:Note, the W/L of M3, M4 and M7 will be 6 so thata current of 10μA gives 100μA in M3 of the opamp. Also, W/L of M1 and M5 will be 16 so acurrent of 10μA gives 125μA in M4 and M5 of theop amp.If M2 is 4 times larger than M1, which gives a W/Lof 64 for M2. Under these conditions,
I2 = I1 = 1
2ß1R2R =
106
2·120·16·10 = 5.1k
The extra 40 A brings the power dissipation to
0.975mW which is still in specification.
The W/L of M6 and M8 are designed as follows:
VGS8 = VT + 2VON VGS8 - VT = 0.2V = 2·10
120·(W8/L8) W8L8 = 4.167
VSG6 = |VT| + 2VON VSG6 - |VT| = 0.5V = 2·10
25·(W6/L6) W6L6 = 3.20
061021-02
VDD
VPB1
VPB2
VNB2
VNB1
M1 M2
M3 M4
M5
M6M7
M8
R
10µA 10µA10µA
10µA
Lecture 360 – Characterization of ADCs and Sample and Hold Circuits (3/29/10) Page 360-31
CMOS Analog Circuit Design © P.E. Allen - 2010
Switch and Hold Capacitor DesignSwitch:
Since the signal amplitude is from 0 to 1V, a single NMOS switch should besatisfactory. The resistance of a minimum size NMOS switch is,
RON(worst case) 1
Kn'(W/L)(VGS-VT) = 106
120(1)(1.5-0.5) = 8.33k
For a CH = 1pf, the time constant is 8 ns. This is too close to the 50 ns so let us increasethe switch size to 0.5μm/0.25μm which gives a time constant of 4ns.Therefore, the W/L ratio of the NMOS switch is 0.5μm/0.25μm and the hold capacitor is1pf.Check the error due to channel injection and clock feedthrough-If we assume the clock that rises and falls in 1ns, then a 0.5μm/0.25μm switch works inthe fast transition region. The channel/clock error can be calculated as:
Verror = -W·CGDO +
Cchannel
2CL
VHT -V
3HT
6U·CL -
W·CGDOCL
(VS+2VT -VL)
Lecture 360 – Characterization of ADCs and Sample and Hold Circuits (3/29/10) Page 360-32
CMOS Analog Circuit Design © P.E. Allen - 2010
Switch and Hold Capacitor Design – Continued
Assuming CGDO is 200x10-12 F/m we can calculate VHT as 0.8131V. Thus,Verror =
-100x10-18+0.5(7.57x10-16)
1x10-120.8131-
0.105x10-3
15x10-3 -
100x10-18
1x10-12(1+1-0) = -0.586mV
For a 1volt signal with 10 bit accuracy, the error must be less than 1LSB which is0.967mV. The channel/clock error is close to this value and one may have to considerusing a CMOS switch or a dummy switch to reduce the error.
Lecture 360 – Characterization of ADCs and Sample and Hold Circuits (3/29/10) Page 360-33
CMOS Analog Circuit Design © P.E. Allen - 2010
Design SummaryAt this point, the analog designer understands the weaknesses and strengths of thedesign. The next steps will not be done but are listed below:1.) Simulation to confirm and explore the hand-calculated performance2.) Layout of the op amp, hold capacitor and switch.3.) Verification of the layout4.) Extraction of the parasitics from the layout5.) Resimulation of the design.6.) Check for sensitivity to ESD and latchup.7.) Select package and include package parasitics in simulation.
Lecture 360 – Characterization of ADCs and Sample and Hold Circuits (3/29/10) Page 360-34
CMOS Analog Circuit Design © P.E. Allen - 2010
SUMMARY• An ADC is by nature a sampled data circuit (cannot continuously convert analog into
digital)• Two basic types of ADCs are:
- Nyquist – analog bandwidth is as close to the Nyquist frequency as possible- Oversampled – analog bandwidth is much smaller than the Nyquist frequency
• The active components in an ADC are the comparator and the sample and hold circuit
• A sample and hold circuit must have at least the accuracy of 100%/2N
• Sample and hold circuits are divided into two types:- Open loop which are fast but not as accurate- Close loop which are slower but more accurate
• An example of designing a sample and hold amplifier was given to illustrate theelectrical design process for CMOS analog circuits
Lecture 370 – Testing of ADCs and Moderate Speed Nyquist ADCs (3/29/10) Page 370-1
CMOS Analog Circuit Design © P.E. Allen - 2010
LECTURE 370 – TESTING OF ADCS AND MODERATE SPEEDNYQUIST ADCS
LECTURE ORGANIZATIONOutline• Introduction• Testing of ADCs• Serial ADCs• Successive approximation ADCs• Single-bit/stage pipeline ADCs• Iterative ADCs• Self calibration techniques• SummaryCMOS Analog Circuit Design, 2nd Edition ReferencePages 665-681
Lecture 370 – Testing of ADCs and Moderate Speed Nyquist ADCs (3/29/10) Page 370-2
CMOS Analog Circuit Design © P.E. Allen - 2010
TESTING OF ADCsInput-Output Test for an ADCTest Setup:
N-bitADCunder test
DAC withmore resolution
than ADC(N+2 bits)
DigitalWord
Output(N bits)
Fig.10.5-17
Vin Σ-
+
Vin'Qn =
Vin-Vin'
The ideal value of Qn should be within ±0.5LSB
Can measure:• Offset error = constant shift above or below the 0 LSB line• Gain error = contant increase or decrease of the sawtooth plot as Vin is increased
• INL and DNL (see following page)
Lecture 370 – Testing of ADCs and Moderate Speed Nyquist ADCs (3/29/10) Page 370-3
CMOS Analog Circuit Design © P.E. Allen - 2010
Illustration of the Input-Output Test for a 4-Bit ADC
016
116
216
316
416
516
616
716
816
916
1016
1116
1216
1316
1416
1516
1616
0.0 LSB
0.5 LSB
1.0 LSB
1.5 LSB
2.0 LSB
-0.5 LSB
-1.0 LSB
-1.5 LSB
-2.0 LSB
Qua
ntiz
atio
n N
oise
(L
SBs)
Analog Input Normalized to VREF
+2LSBDNL
-2LSBINL
+2LSBINL
-2LSBDNL
Fig.10.5-18
Lecture 370 – Testing of ADCs and Moderate Speed Nyquist ADCs (3/29/10) Page 370-4
CMOS Analog Circuit Design © P.E. Allen - 2010
Measurement of Nonlinearity Using a Pure SinusoidThis test applies a pure sinusoid to the input of the ADC. Any nonlinearity will
appear as harmonics of the sinusoid. Nonlinear errors will occur when the dynamic range(DR) is less than 6N dB where N = number of bits.
N-bitADCunder test
Harmonicfree
sinusoid
Clock
Distortionor
SpectrumAnalyzer
t
|Vout(jω)|
ωfsig
SpectralOutput
1000
0
1000
1
1001
1
1111
1
Noise floordue to non-linearities
VREF
Fig. 10.5-19A
DR
N-bitDAC
with N+2bits
resolution
Vout(DAC)
Vout(DAC)
tVREF
Vin
Vin
fsig
Comments:• Input sinusoid must have less distortion that the required dynamic range• DAC must have more accuracy than the ADC
Lecture 370 – Testing of ADCs and Moderate Speed Nyquist ADCs (3/29/10) Page 370-5
CMOS Analog Circuit Design © P.E. Allen - 2010
FFT Test for an ADCTest setup:
Analog-Digital
Converter
Fast RAM Buffer
FFTPost-
processor
PureSinusoidalInput, fin
Clockfc
FrequencySpectrum
Fig.10.5-19B
Comments:• Stores the digital output codes of the ADC in a RAM buffer• After the measurement, a postprocessor uses the FFT to analyze the quantization noise
and distortion components• Need to use a window to eliminate measurement errors (Raised Cosine or 4-term
Blackmann-Harris are often used)• Requires a spectrally pure sinusoid
Lecture 370 – Testing of ADCs and Moderate Speed Nyquist ADCs (3/29/10) Page 370-6
CMOS Analog Circuit Design © P.E. Allen - 2010
Histogram Test for an ADCThe number of occurences of each digital output code is plotted as a function of the digitaloutput code.Illustration:
Comments:• Emphasizesthe time spentat a given level and can show DNL and missing codes• DNL
DNL(i) = Width of the bin as a fraction of full scale
Ratio of the bin width to the ideal bin width -1 = H(i)/Nt
P(i) -1 where
H(i) = number of counts in the ith binNt = total number of samples
P(i) = ratio of the bin width to the ideal bin width• INL is found from the cumulative bin widths
0 MidScale
FullScale
Num
ber
of
Occ
uran
ces
Sinusoidal InputTriangular Input
OutputCode0
Fig.10.5-20
Lecture 370 – Testing of ADCs and Moderate Speed Nyquist ADCs (3/29/10) Page 370-7
CMOS Analog Circuit Design © P.E. Allen - 2010
Comparison of the Tests for Analog-Digital ConvertersOther Tests• Sinewave curve fitting (good for ENOB)• Beat frequency test (good for a qualitative measure of dynamic performance)Comparison
Test Error
Histogramor
Code TestFFT Test
SinewaveCurve
Fit Test
BeatFrequency
TestDNL Yes (spikes) Yes (Elevated
noise floor)Yes Yes
Missing Codes Yes (Bin counts withzero counts)
Yes (Elevatednoise floor)
Yes Yes
INL Yes (Triangle input givesINL directly)
Yes (Harmonics inthe baseband)
Yes Yes
AperatureUncertainty
No Yes (Elevatednoise floor)
Yes No
Noise No Yes (Elevatednoise floor)
Yes No
BandwidthErrors
No No No Yes (Measuresanalog bandwidth)
Gain Errors Yes (Peaks indistribution)
No No No
Offset Errors Yes (Offset of
distribution average)
No No No
Lecture 370 – Testing of ADCs and Moderate Speed Nyquist ADCs (3/29/10) Page 370-8
CMOS Analog Circuit Design © P.E. Allen - 2010
Bibliography on ADC Testing1.) D. H. Sheingold, Analog-Digital Conversion Handbook, Analog Devices, Inc.,
Norwood, MA 02062, 1972.2.) S.A. Tretter, Introduction to Discrete-Time Signal Processing, John Wiley & Sons
New York, 1976.3.) J. Doernberg, H.S. Lee, and D.A. Hodges, “Full-Speed Testing of A/D Converters,”
IEEE J. of Solid-State Circuits, Vol. SC-19, No. 6, December 1984, pp. 820-827.4.) “Dynamic performance testing of A to D converters,” Hewlett Packard Product Note
5180A-2.
Lecture 370 – Testing of ADCs and Moderate Speed Nyquist ADCs (3/29/10) Page 370-9
CMOS Analog Circuit Design © P.E. Allen - 2010
INTRODUCTION TO MODERATE SPEED ADCSModerate Speed ADC Topics
• Serial ADCs - require 2NT for conversion where T = period of the clockTypes:
- Single-slope- Dual-slope
• Successive approximation ADCs – require NT for conversion where T = the clockperiod
• 1-bit per stage, pipeline ADCs – require T for conversion after a delay of NT• Iterative ADCs – require NT for conversion• Self-calibration techniques
Lecture 370 – Testing of ADCs and Moderate Speed Nyquist ADCs (3/29/10) Page 370-10
CMOS Analog Circuit Design © P.E. Allen - 2010
SERIAL ANALOG-DIGITAL CONVERTERSSingle-Slope ADCBlock diagram:
RampGenerator vT
vT
vin*
vin*
nTt0
0
VREF
IntervalCounter
t
t
Clock
f =1/T
T
OutputCounter
nT
nT
Output
Reset
+-
Fig.10.6-1
n ≤ N
Attributes:• Simplicity of operation• Subject to error in the ramp generator• Long conversion time 2NT
Lecture 370 – Testing of ADCs and Moderate Speed Nyquist ADCs (3/29/10) Page 370-11
CMOS Analog Circuit Design © P.E. Allen - 2010
Dual-Slope ADCBlock diagram: Waveforms:
PositiveIntegrator
1
2
DigitalControl
Counter
vin*
-VREF
vint
Vth
CarryOutput Binary
Output
+-
Fig.10.6-2
Operation:1.) Initially vint = 0 and vin is sampled and held (vIN* > 0).2.) Reset the positive integrator by integrating a positive voltage until vint (0) = Vth.
3.) Integrate vin* for NREF clock cycles to get,
vint(t1) = K 0
NREFT
vin* dt + vint(0) = KNREFTvin* + Vth4.) After NREF counts, the carry output of the counter closes switch 2 and-VREF isapplied to the positive integrator. The output of the integrator at t = t1+t2 is,
vint(t1+t2) = vint(t1)+K t1
NoutT
( VREF)dt =Vth KNREFTvin*+Vth -KNoutTVREF = Vth
5.) Solving for Nout gives, Nout = NREF (vin*/VREF)
Comments: Conversion time 2(2N)T and the operation is independent of Vth and K.
vin
VREF+Vth
Vth0
0t
vin'''
vin''
vin'
Reset t0(start)
t1 = NREFT
t2' t2''t2'''
t2= NoutT
NREFT
Fig.10.6-3
vin''' > vin'' > vin'.
Lecture 370 – Testing of ADCs and Moderate Speed Nyquist ADCs (3/29/10) Page 370-12
CMOS Analog Circuit Design © P.E. Allen - 2010
SUCCESSIVE APPROXIMATION ANALOG-DIGITAL CONVERTERSIntroductionSuccessive Approximation Algorithm:1.) Start with the MSB bit and work toward the LSB bit.2.) Guess the MSB bit as 1.3.) Apply the digital word 10000.... to a DAC.4.) Compare the DAC output with the sampled analog input voltage.5.) If the DAC output is greater, keep the guess of 1. If the DAC output is less, change
the guess to 0.6.) Repeat for the next MSB.
vguessVREF
0.50VREF
00 1 2 3 4 5 6
tT
Fig.10.7-2
0.75VREF
0.25VREF
Lecture 370 – Testing of ADCs and Moderate Speed Nyquist ADCs (3/29/10) Page 370-13
CMOS Analog Circuit Design © P.E. Allen - 2010
Block Diagram of a Successive Approximation ADC†
OutputRegister
Digital-AnalogConverter
Conditional
ShiftRegister Clock
Output
VREF
Vin*+-
Comparator
Fig.10.7-1 Gates
† R. Hnatek, A User's Handbook of D/A and A/D Converters, John Wiley and Sons, Inc., New York, NY, 1976.
Lecture 370 – Testing of ADCs and Moderate Speed Nyquist ADCs (3/29/10) Page 370-14
CMOS Analog Circuit Design © P.E. Allen - 2010
5-Bit Successive Approximation ADC
AnalogSwitch
5
0 1FF5
R RD S
LSB
G5
AnalogSwitch
4
0 1FF4
R RD S
G4
VREF
LSB
AnalogSwitch
3
0 1FF3
R RD S
G3
AnalogSwitch
2
0 1FF2
R RD S
G2
AnalogSwitch
1
0 1FF1
R RD S
G1
MSB
5-bit Digital-Analog Converter
MSB
Shift Register
1SR5
1SR4SR3SR2SR1
111
Delay
-1
+ -
AnalogIn
Comp-arator
vIA vOA
Gate
Delay
Clock pulses
Start pulseThe delay allows for the circuit transients to settle before the comparator output is sampled. Fig.10.7-3
Lecture 370 – Testing of ADCs and Moderate Speed Nyquist ADCs (3/29/10) Page 370-15
CMOS Analog Circuit Design © P.E. Allen - 2010
m-Bit Voltage-Scaling, k-Bit Charge-Scaling Successive Approximation ADCOperation:1.) With the two SFswitches closed, allcapacitors are paralleledand connected to Vin*
which autozeros thecomparator offsetvoltage.2.) With all capacitorsstill in parallel, a suc-cessive approximationsearch is performed tofind the resistor segmentin which the analogsignal lies.3.) Finally, a successiveapproximation search is performed on charge scaling subDAC to establish the analogoutput voltage.
Ck =2k-1C
Sk-1,A
SBSF
Bus A
Bus B
Sk,A
Sk,B
Ck-1=2k-2C
Sk-1,B
C2=2C
C1=C
C
Vin*
S2A
S2B
S1A
S1B
m-to-2m Decoder A
m-to-2m Decoder BVREF
R1 R2 R3 R2m-2 R2m-1 R2m
m-MSB bits
m-MSB bits
m-bit, MSB voltagescaling subDAC
k-bit, LSB chargescaling subDAC
+-SF
m-MSB bits
ClockCapacitor Switches
(m+k) bit output of ADC Start
Successive approximationregister & switch control logic
Fig.10.7-4
Lecture 370 – Testing of ADCs and Moderate Speed Nyquist ADCs (3/29/10) Page 370-16
CMOS Analog Circuit Design © P.E. Allen - 2010
Voltage-Scaling, Charge-Scaling Successive Approximation ADC - ContinuedAutozero Step
Removes the influence of the offset voltage of thecomparator.
The voltage across the capacitor is given as,vC = Vin* - VOS
Successive Approximation Search on the Resistor StringThe voltage at the comparator input is
vcomp = VRi - Vin*
If vcomp > 0, then VRi > Vin*, if vcomp < 0, then VRi < Vin*
Successive Approximation Search on the Capacitor SubDACThe input to the comparator is written as,
vcomp = (VRi+1 - V *in)
Ceq2kC + (VRi - V *
in) 2kC-Ceq
2kCHowever, VRi+1 = VRi + 2-mVREFCombining gives,
vcomp = (VRi + 2-mVREF -V *IN)
Ceq2kC + (VRi-V *
IN) 2kC-Ceq
2kC
= VRi - V *IN + 2-mVREF Ceq2kC
+-
Vin*+
-VOS
+ -vC
2kC
VOS
Fig.10.7-5
+
-VRi=V'REF
vcomp
2kC
Busses A and B
V*in
+ -
Fig.10.
Fig.10.7-6
+
-
2-mVREF
VRi=V'REF
vcompCeq.
2kC - Ceq.
Bus A
Bus B
V*in
VRi+1
+ -
V*in
+ -+
-
Lecture 370 – Testing of ADCs and Moderate Speed Nyquist ADCs (3/29/10) Page 370-17
CMOS Analog Circuit Design © P.E. Allen - 2010
SINGLE-BIT/STAGE, PIPELINE ANALOG-DIGITAL CONVERTERSSingle-Bit/Stage Pipeline ADC Architecture
Operation:• Each stage multipliesits input by 2 and adds orsubtracts VREF dependingupon the sign of the input.• i-th stage,
Vi = 2Vi-1 - biVREF
where bi is given as
bi = +1 if Vi-1>0-1 if Vi-1<0
+ -
Σ z-12
±1Vin*
VREF
+ -
ΣVi-12
±1z-1
+ -
ΣVi2
±1z-1
+ -
i-th stage
MSB LSB
Fig.10.7-9Stage 1 Stage 2 Stage N
z-1
Vi/VREF1.0
-1.0
0 0.5 1.0-1.0 -0.50
bi+1=+1
bi+1=-1
bi = -1 bi = +1
Vi-1/VREF
[bi,bi+1] [0,0] [0,1] [1,0] [1,1] Fig.10.7-10
Implementation:
Lecture 370 – Testing of ADCs and Moderate Speed Nyquist ADCs (3/29/10) Page 370-18
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 370-1 - Illustration of the Operation of the Pipeline ADCAssume that the sampled analog input to a 4-bit pipeline analog-digital converter is 2.00V. If VREF is equal to 5 V, find the digital output word and the analog equivalent voltage.Solution
Stage No. Input to the ith stage, Vi-1 Vi-1 > 0? Bit i1 2V Yes 12 (2V·2) - 5 = -1V No 03 (-1V·2) + 5 = 3V Yes 14 (3V·2) - 5 = 1V Yes 1
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
Stag
e O
uput
s no
rmal
ized
to V
0.4
0.6
0.8
1
-1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1
RE
F
Stage 1
Stage 2
Stage 3
Stage 4
V in*/V REF
Illustration:
Vanalog = 512
14 +
18 +
116
= 5(0.4375) = 2.1875
where bi = +1 if the ith-bit is 1and bi = -1 if the ith bit is 0
Lecture 370 – Testing of ADCs and Moderate Speed Nyquist ADCs (3/29/10) Page 370-19
CMOS Analog Circuit Design © P.E. Allen - 2010
Achieving the High Speed Potential of the Pipeline ADCIf shift registers are used to store the output bits and align them in time, the pipeline ADCcan output a digital word at every clock cycle with a latency of NT.Illustration:
+ -
Σ z-12
±1Vin*
VREF
+ -
ΣVi-12
±1z-1
+ -
ΣVi2
±1z-1
+ -
i-th stage
MSB
LSB
Fig.10.7-9BStage 1 Stage 2 Stage N
z-1
SR
SR
SR
SR
i-th Bit
SR
SR
SR
MSB-1SR
Digital Ouput Word
Lecture 370 – Testing of ADCs and Moderate Speed Nyquist ADCs (3/29/10) Page 370-20
CMOS Analog Circuit Design © P.E. Allen - 2010
Errors in the Pipeline ADCTypes of errors:• Gain errors – x2 amplifier or summing junctions• Offset errors – comparators or summing junctionsIllustration of errors:
060927-04
2ΔAi
Vo/VREF
Vi/VREF2ΔAi
1
1
-1
-1
00
2VOSi
Vo/VREF
Vi/VREF1
1
-1
-1
00
System offset error, VOSi.
2VOSi
Vo/VREF
Vi/VREF1
1
-1
-1
00
Comparator offset error, VOCi.2VOCi
Gain error, Ai.
An error will occur if the output voltage of one stage exceeds ±VREF (saturates).
Lecture 370 – Testing of ADCs and Moderate Speed Nyquist ADCs (3/29/10) Page 370-21
CMOS Analog Circuit Design © P.E. Allen - 2010
Digital Error CorrectionIn the previous slide, we noted that if the analog output to the next stage exceeds ±VREFthat an error occurs. This error can be detected by adding one more bit to the followingstage for the purposes of detecting the error.Illustration (2nd bit not used for error correction):
060930-01
VREF
VREF
-VREF
-VREF
Vout(i)
Vin(i)
0 0 1 1VREF
VREF
-VREF
-VREF
Vout(i)
Vin(i)
[00] [01] [10] [11]
1
0
00 01 10 11
11
10
01
00
[0000][0001][0010][0011][0100][0101][0110][0111][1000][1001][1010][1011][1100][1101][1110][1111]
InputRange
for nextStage
InputRange
for nextStage
Input/output characteristics of a 1-bit stage Input/output characteristics of a 2-bit stage
Lecture 370 – Testing of ADCs and Moderate Speed Nyquist ADCs (3/29/10) Page 370-22
CMOS Analog Circuit Design © P.E. Allen - 2010
Digital Error Correction – ContinuedIf the gain of 4 amplifier is reduced back to 2, the input/output characteristics of the 2-bitstage become:
060930-02
VREF
VREF
-VREF
-VREF
Vout(i)
Vin(i)
00 01 10 11
10
01
[0001]
[0010]
[0101]
[0110]
[1001]
[1010]
[1101]
[1110]
InputRangefor nextStage
11
00
The output bits can be used to determine the error. If these bits are 00, then 0.5LSB mustbe added to get the correct digital output. If the bits are 11, then 0.5LSB must besubtracted to get the correct digital output.
Lecture 370 – Testing of ADCs and Moderate Speed Nyquist ADCs (3/29/10) Page 370-23
CMOS Analog Circuit Design © P.E. Allen - 2010
Modified Digital Error Correction (1.5 bits per stage)In the previous slide, it was necessary sometimes to perform digital subtraction which isnot easy to implement. To avoid this problem, a 0.5LSB shift has been added to theinput/output characteristic resulting in the following.
VREF
VREF
-VREF
-VREF
Vout(i)
Vin(i)
00 01 10 11
InputRangefor nextStage
060930-03
VREF
VREF
-VREF
-VREF
Vout(i)
Vin(i)
00 01 10
[0000]
[0001]
[0100][0101]
[1000][1001]
[1010]
[0010]
-VREF4
VREF4
00
01
1011
00
01
10
[0110]
[0000]
[0001]
[0100][0101]
[1000][1001][1010]
[0010]
[0110]
[1100][1101]
Movement of all comparator thresholdsto the right by 0.5LSB.
Removal of the comparator at 0.75LSB.
InputRangefor nextStage
To obtain code 11 out of the stage after correction, the correction logic must incrementthe output of the stage.To obtain code 00 from this stage after correction, the correction logic need do nothing.Therefore, only two comparators are needed to produce outputs of (00, 01, 10) as shownon the right-hand characteristic.
Lecture 370 – Testing of ADCs and Moderate Speed Nyquist ADCs (3/29/10) Page 370-24
CMOS Analog Circuit Design © P.E. Allen - 2010
How Does the 1.5 Bit Stage Correct Offset Errors?Consider a ±0.25VREF comparator offset shift in the input-output characteristics of the1.5 bit stage.
061001-01
VREF
Vout(i)
Vin(i)InputRangefor nextStage
VREF
10 14
24
341 3
424
14
----
1
0
0.5
-0.5
-1
Comparator shiftfrom 0.25VREFto 0VREF
VREF
Vout(i)
Vin(i)InputRangefor nextStage
VREF
10 14
24
341 3
424
14
----
1
0
0.5
-0.5
-1
Comparator shiftfrom 0.25VREFto 0.5VREF
When the shift is to the left, the comparator will not be in error until the shift is greaterthan 0.25 VREF. This is because the comparator thresholds were shifted to the right by0.5 VREF.
When the shift is to the right, the input to the next stage will be greater than 0.50VREF.This will cause the output code 10 which indicates that the digital word should beincremented by 1 bit.
The range of correction ±VREF /2B+1 where B is the number of bits per stage.
Lecture 370 – Testing of ADCs and Moderate Speed Nyquist ADCs (3/29/10) Page 370-25
CMOS Analog Circuit Design © P.E. Allen - 2010
Implementation of the 1.5 Bit Stage
061001-03
+
−
vin φ1
C
φ2
VREFφ1
C
φ24
φ1
+
−
vin φ1
C
φ2
VREFφ1
C
φ24
φ1
−
Sub-ADC
+
− φ2
φ1
φ1
φ1
φ2
VREF
VREF
MultiplyingSub-DAC
vout
C Cvin ≥ VREF
4+
vin < VREF
4−
1 if
1 if
φ1
The multiplying Sub-DAC must implement the following equation:
Vout =
2·vin - VREF2·vin2·vin + VREF
if vin > VREF/4if -VREF/4 vin VREF/4if vin < -VREF/4
Lecture 370 – Testing of ADCs and Moderate Speed Nyquist ADCs (3/29/10) Page 370-26
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 370-2 - Accuracy requirements for a 5-bit pipeline ADCShow that if Vin = VREF, that the pipeline ADC will have an error in the 5th bit if the gainof the first stage is 2-(1/8) =1.875 which corresponds to when an error will occur. Showthe influence of Vin on this result for Vin of 0.65VREF and 0.22VREF.
SolutionFor Vin = VREF, we get the results shown below. The input to the fifth stage is 0V
which means that the bit is uncertain. If A1 was slightly less than 1.875, the fifth bitwould be 0 which is in error. This result assumes that all stages but the first are ideal.
i Vi(ideal) Bit i (ideal) Vi(A1=1.875) Bit i (A1=1.875)1 1 1 1.000 12 1 1 0.875 13 1 1 0.750 14 1 1 0.500 15 1 1 0.000 ?
Now let us repeat the above results for Vin = 0.65VREF. The results are shown below.i Vi(ideal) Bit i (ideal) Vi(A1=1.875) Bit i (A1=1.875)1 +0.65 1 0.6500 12 +0.30 1 0.2188 13 -0.40 0 -0.5625 04 +0.20 1 -0.1250 05 -0.60 0 0.7500 1
Lecture 370 – Testing of ADCs and Moderate Speed Nyquist ADCs (3/29/10) Page 370-27
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 370-2 - ContinuedNext, we repeat for the results for Vin = 0.22VREF. The results are shown below. We
see that no errors occur.i Vi(ideal) Bit i (ideal) Vi(A1=1.875) Bit i (A1=1.875)1 +0.22 1 0.2200 12 -0.56 0 -0.5875 03 -0.12 0 -0.1750 04 +0.76 1 0.6500 15 +0.52 1 0.3000 1
Note the influence of Vin in the fact that an error occurs for A1= 1.875 for Vin =0.65VREF but not for Vin = 0.22VREF. Why? Note on the plot for the output of eachstage, that for Vin = 0.65VREF, the output of the fourth stage is close to 0V so any smallerror will cause problems. However, for Vin = 0.22VREF, the output of the fourth stage isat 0.65VREF which is further away from 0V and is less sensitive to errors.
The most robust values of Vin will be near -VREF , 0 and +VREF. or
when each stage output is furthest from the comparator threshold, 0V.
Lecture 370 – Testing of ADCs and Moderate Speed Nyquist ADCs (3/29/10) Page 370-28
CMOS Analog Circuit Design © P.E. Allen - 2010
ITERATIVE ANALOG-DIGITAL CONVERTERSIterative (Cyclic) Algorithmic Analog-Digital ConverterThe pipeline ADC can be reduced to a single stage that cycles the output back to theinput.Implementation:
+-
ΣSample
andHold
x2
+VREF
-VREF
Voi
+1 +1
+-
ΣSampleand
Hold
x2
VREF
Va
+1+1
S1
Vb
Vo
Vin*
-VREF
Vo ="1"
Vo ="0"
Iterative algorithm ADC Different version of iterative algorithm ADC implementationFig. 10.7-13
Operation:1.) Sample the input by connecting switch S1 to Vin*.2.) Multiply Vin* by 2.3.) If Va > VREF, set the corresponding bit = 1 and subtract VREF from Va. If Va < VREF, set the corresponding bit = 0 and add zero to Va.4.) Repeat until all N bits have been converted.
Lecture 370 – Testing of ADCs and Moderate Speed Nyquist ADCs (3/29/10) Page 370-29
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 370-3 - Conversion Process of an Iterative, Algorithmic Analog-DigitalConverter
The iterative, algorithmic analog-digital converter is to be used to convert an analogsignal of 0.8VREF. The figure below shows the waveforms for Va and Vb during theprocess. T is the time for one iteration cycle.1.) The analog input of 0.8VREF givesVa = 1.6VREF and Vb = 0.6VREF and the MSB as 1.2.) Vb is multiplied by two to give Va = 1.2VREF. The next bit is also 1 and Vb = 0.2VREF.3.) The third iteration givesVa = 0.4VREF, making the next bit is 0 and Vb = 0.4VREF .
4.) The fourth iteration gives Va = 0.8VREF, giving Vb = 0.8VREF and the fourth bit as 0.5.) The fifth iteration gives Va = 1.6VREF, Vb = 0.6VREF and the fifth bit as 1.The digital word after the fifth iteration is 11001 and is equivalent to an analog voltage of0.78125VREF.
������������
0.0
0.4
0.8
1.2
1.6
2.0
0 1 2 3 4 5t/T
Va/VREF
0.0
0.4
0.8
1.2
1.6
2.0
0 1 2 3 4 5t/T
Vb/VREF
������������
Fig. 10.7-14.
Lecture 370 – Testing of ADCs and Moderate Speed Nyquist ADCs (3/29/10) Page 370-30
CMOS Analog Circuit Design © P.E. Allen - 2010
SELF-CALIBRATION TECHNIQUESSelf-Calibrating Analog-Digital ConvertersSelf-calibration architecture for a m-bit charge scaling, k-bit voltage scaling successiveapproximation ADC
Comments:• Self-calibration can be
accomplished during acalibration cycle or at start-up
• In the above scheme, the LSB bits are not calibrated• Calibration can extend the resolution to 2-4 bits more that without calibration
+-
C1
VREF
C2 C3 Cm-1
Successive Approximation
Register
Cm
k-bits
m+k-bits
Cm
m-bit subDAC
k-bitsubDAC
m+2-bitCalibration
DAC
S1
ControlLogic
Register
Adder
Data Register
Vε1 Vε2
To SuccessiveApproximationRegister
Data Output
m control lines
Fig.10.7-15
Lecture 370 – Testing of ADCs and Moderate Speed Nyquist ADCs (3/29/10) Page 370-31
CMOS Analog Circuit Design © P.E. Allen - 2010
Self-Calibrating Analog-Digital Converters - ContinuedSelf-calibration procedure starting with the MSB bit:1.) Connect C1 to VREF and theremaining capacitors (C2+C3+···+Cm+Cm = C1 ) to ground and close SF.
2.) Next, connect C1 to ground andC1 to VREF.
3.) The result will be Vx1 = C1 -C1
C1 + C1 VREF. If C1 = C1 , then Vx1 = 0.
4.) If Vx1 0, then the comparator output will be either high or low. Depending on thecomparator output, the calibration circuitry makes a correction through the calibrationDAC until the comparator output changes. At this point the MSB is calibrated and theMSB correction voltage, V 1 is stored.
5.) Proceed to the next MSB with C1 out of the array and repeat for C2 and C2 . Storethe correction voltage, V 2, in the data register.6.) Repeat for C3 with C1 and C2 out of the array. Continue until all of the capacitors ofthe MSB DAC have been corrected.Note: For normal operation, the circuit adds the correct combined correction voltage.
C1
VREF C1
C1
VREF
C1
Vx1
Fig.10.7-16
+-
+-
VREF
Connection of C1 to VREF. Connection of C1 to VREF.
Lecture 370 – Testing of ADCs and Moderate Speed Nyquist ADCs (3/29/10) Page 370-32
CMOS Analog Circuit Design © P.E. Allen - 2010
SUMMARY• Tests for the ADC include:
- Input-output test- Spectral test- FFT test- Histogram test
• Moderate Speed ADCs:Type of ADC Advantage Disadvantage
Serial ADC High resolution SlowVoltage-scaling, charge-scalingsuccessive approximation ADC
High resolution Requiresconsiderable digitalcontrol circuitry
Successive approximationusing a serial DAC
Simple Slow
Pipeline ADC Fast after initiallatency of NT
Accuracy dependson input
Iterative algorithmic ADC Simple Requires otherdigital circuitry
• Successive approximation ADCs also can be calibrated extending their resolution 2-4bits more than without calibration.
Lecture 380 – High Speed Nyquist ADCs (3/29/10) Page 380-1
CMOS Analog Circuit Design © P.E. Allen - 2010
LECTURE 380 – HIGH SPEED NYQUIST ADCSLECTURE ORGANIZATION
Outline• Parallel/flash ADCs• Interpolating and averaging• Folding• High-speed, high-resolution ADCs• Time-interleaved ADCsCMOS Analog Circuit Design, 2nd Edition ReferencePages 682-697
Lecture 380 – High Speed Nyquist ADCs (3/29/10) Page 380-2
CMOS Analog Circuit Design © P.E. Allen - 2010
PARALLEL/FLASH ADCsParallel/Flash ADC Architecture
060928-01
VoltageScaling
Networkcreating
all possiblediscreteanalog voltages
VREF
V1V2V3V4
V2N-1
Sampleand HoldCircuit
vin(t)
vin*(t)
2N-1Compar
ators
d1d2d3d4
d2N-1
2N-1to N
Decoder
b1b2b3
bN
Phase 1 Phase 2
One Clock Period, T
AnalogInput
DigitalWordOutput
• The notation, vin*(t), means the signal is sampled and held.
• The sample and hold function can be incorporated into the comparators• The digital words designated as di form a thermometer code
Lecture 380 – High Speed Nyquist ADCs (3/29/10) Page 380-3
CMOS Analog Circuit Design © P.E. Allen - 2010
A 3-bit, parallel ADC
General Comments:• Fast, in the first phase of the clock the
analog input is sampled and applied to thecomparators. In the second phase, thedigital encoding network determines thecorrect output digital word.
• Number of comparators required is 2N-1which can become large if N is large
• The offset of the comparators must be lessthan ±VREF/2N+1
• Errors occur as “bubbles” in thethermometer code and can be correctedwith additional circuitry
• Typical sampling frequencies can be ashigh as 1000MHz for 6-bits in sub-micronCMOS technology.
1R+-
1R+-
0R+-
0R+-
0R+-
0R+-
0R+-
VREF Vin*=0.7VREF
R
2N-1to N
encoder
OutputDigitalWord101
0.875VREF
0.750VREF
0.625VREF
0.500VREF
0.375VREF
0.250VREF
0.125VREF
Fig.10.8-1
Lecture 380 – High Speed Nyquist ADCs (3/29/10) Page 380-4
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 380-1 - Comparator Bandwidth Limitations on the Flash ADCThe comparators of a 6-bit, flash ADC have a dominant pole at 104 radians/sec, a dc
gain of 104 a slew rate of 10V/μs, and a binary output voltage of 1V and 0V. Assume thatthe conversion time is the time required for the comparator to go from its initial state tohalfway to its final state. What is the maximum conversion rate of this ADC if VREF =1V? Assume the resistor ladder is ideal.Solution:
The output of the i-th comparator can be found by taking the inverse Laplacetransform of,
L -1 Vout(s) =
Ao(s/104) + 1 ·
Vin*-VRis vout(t) = Ao(1 - e-104t)(Vin* - VRi).
The worst case occurs whenVin*-VRi = 0.5VLSB = VREF/27 = 1/128
0.5V = 104(1 - e-104T)(1/128) 64x10-4 = 1- e-104T
or, e-104T = 1 - 64x10-4 = 0.9936 T = 10-4 ln(1.0064) = 0.6421μs
Maximum conversion rate = 1
0.6421μs = 1.557x106 samples/second
Checking the slew rate shows that it does not influence the maximum conversion rate.
SR = 10V/μs VT = 10V/μs V = 10V/μs(0.6421μs) = 6.421V > 1V
Lecture 380 – High Speed Nyquist ADCs (3/29/10) Page 380-5
CMOS Analog Circuit Design © P.E. Allen - 2010
Signal Delay in High Speed ConvertersAssume that clocked comparators are used in a 500MHz sampling frequency ADC
of 8-bits. If the input frequency is 250MHz with a peak-to-peak value of VREF, the clockaccuracy must be
t VVp =
VREF/2N+1
2 f(0.5VREF) = 1
29· ·f 2.5ps
Since electrical signals travel at approximately 50μm/ps for metal on an IC, each metalpath from the clock to each comparator must be equal to within 125μm to avoid LSBerrors due to clock skew. Therefore, must use careful layout to avoid ADC inaccuraciesat high frequencies.
An equal-delay clock distribution system for a 4-bit parallel ADC:
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
ClockGenerator
Fig.10.8-2BComparators
Lecture 380 – High Speed Nyquist ADCs (3/29/10) Page 380-6
CMOS Analog Circuit Design © P.E. Allen - 2010
Other Errors of the Parallel ADC• Resistor string error - if current is drawn from the taps to the resistor string this will
create a “bowing” effect on the voltage. This can be corrected by applying the correctvoltage to various points of the resistor string.
• Input common mode range of the comparators - the comparators at the top of the stringmust operate with the same performance as the comparators at the bottom of the string.
• Kickback or flashback - influence of rapid transition changes occurring at the input of acomparator. Can be solved by using a preamplifier or buffer in front of the comparator.
• Metastability - uncertainty of the comparator output causing the transition of thethermometer code to be undetermined.
Lecture 380 – High Speed Nyquist ADCs (3/29/10) Page 380-7
CMOS Analog Circuit Design © P.E. Allen - 2010
INTERPOLATING AND AVERAGINGIllustration of a 3-bit interpolating ADC using a factor of 4 interpolation
VDD
+-
V28R
+-
V2a7R
+-
V2b6R
+-
V2c5RV1 +
-4R+-
V1a3R
+-
V1b2R
+-
V1c1R
VREFVth
8 to 3encoder
Vin
R
R
VREF
2
3-bitdigitaloutput
+-VDD
+-A1
A2
Fig.10.8-3
Comments:• Capacitive loading at the input is reduced from 8 comparators to two amplifiers.• The comparators no longer need a large ICMR• V1 and V2, are interpolated through the resistor string and applied to the comparators.• Because of the amplification of the input amplifiers and a single threshold, the
comparators can be simple and are often replaced by a latch.• If the dots in Fig. 10.8-4 are not equally spaced, INL and DNL will result.
VDD
Vth
VREF0
0
V2a
V2
V2bV2c
V1aV1
V1b
V1c
0.5VREFVin
Volts
ComparatorThreshold
1 2 3 4 5 6 7 8
Fig.10.8-4
Lecture 380 – High Speed Nyquist ADCs (3/29/10) Page 380-8
CMOS Analog Circuit Design © P.E. Allen - 2010
A 3-Bit Interpolating ADC with Equalized Comparator DelaysOne of the problems in voltage (passive) interpolation is that the delay from the amplifieroutput to each comparator can be different due to different source resistance.Solution:
Lecture 380 – High Speed Nyquist ADCs (3/29/10) Page 380-9
CMOS Analog Circuit Design © P.E. Allen - 2010
Active InterpolationExample of a 3 level current interpolation:
060928-02
x4 x4x3x2x1 x3 x2 x1
I1 I14
2I14
3I14
I1
3I14
2I14
I14
x4 x4x3x2x1 x3 x2 x1
I2 I24
2I24
3I24
I2
3I24
2I24
I24
3I14 +
I24
2I14
+2I24
I14
+3I24
This type of interpolation works well with current processing, i.e., current comparators.
Lecture 380 – High Speed Nyquist ADCs (3/29/10) Page 380-10
CMOS Analog Circuit Design © P.E. Allen - 2010
Interpolation using Amplifiers
060928-03
+
-
+
-
+
-
+
-
+
-
+
-
+
-
+
-
+
-
+
-
VR,j+1
VR,j
Vin PreamplifiersInterpolating
Amplifiers
Aj+1
Aj
Vy
Vx Vo1
Vo3
Vo2
Vo3 = K(Vy – Vx) which is between Vy and Vx.
Lecture 380 – High Speed Nyquist ADCs (3/29/10) Page 380-11
CMOS Analog Circuit Design © P.E. Allen - 2010
Averaging†
In many cases, the comparatorsconsist of a number of pre-amplifiers followed by a latch.Averaging is the result ofinterconnecting the outputs ofeach stage of amplifiers so thatthe errors in one amplifier chainare balanced out by adjacentamplifier chains.
Result: The offsets are reducedallowing the transistors to bemade smaller and thereforereducing the parasiticsincreasing the speed of theADC.
† P.C.S. Scholtens and M. Vertregt, “A 6-b 1.6-Gsample/s Flash ADC in 0.18 μm CMOS Using Averaging Termination, IEEE J. of Solid-State
Circuits, vol. 37, no. 12, Dec. 2002, pp. 1599-1609.
VDD
TerminationResistors
TerminationResistors
A11
AN-2,1
A21
AN-1,1
VDD
TerminationResistors
TerminationResistors
A12
AN-2,2
A22
AN-1,2
VDD
TerminationResistors
TerminationResistors
A13
AN-2,3
A23
AN-1,3
060928-04
Lecture 380 – High Speed Nyquist ADCs (3/29/10) Page 380-12
CMOS Analog Circuit Design © P.E. Allen - 2010
Analog Front End of an ADC using Averaging
Lecture 380 – High Speed Nyquist ADCs (3/29/10) Page 380-13
CMOS Analog Circuit Design © P.E. Allen - 2010
FOLDINGFolding Analog-Digital ConvertersAllows the number of comparators to be reduced below the value of 2N-1.Architecture for a folded ADC:
PreprocessorCoarse
Quantizer
Folding Preprocessor
FineQuantizer
EncodingLogicVin
DigitalOutput
n1bits
n2bits
n1+n2bits
Fig.10.8-7
Operation:The input is split into two or more parallel paths.
• First path uses a coarse quantizer to quantize the signal into 2n1 values
• The second path maps all of the 2n1 subranges onto a single subrange and applies thisanalog signal to a fine quantizer of 2n2 subranges.
Thus, the total number of comparators is 2n1-1 + 2n2-1 compared with 2n1+n2-1 for aparallel ADC.I.e., if n1 = 2 and n2 = 4, the folding ADC requires 3 + 15 = 18 compared with 63comparators.
Lecture 380 – High Speed Nyquist ADCs (3/29/10) Page 380-14
CMOS Analog Circuit Design © P.E. Allen - 2010
Example of a Folding PreprocessorFolding characteristic for n1 = 2 and n2 = 3.
832
NoFolding
Folding
Analog Input
Aft
er A
nalo
gPr
epro
cess
ing
MSBs = 00 01 10 11
n1 = 2n2 = 3
VREF
VREF4
00 VREF
Fig.10.8-9
Problems:• The sharp discontinuities of the folder are difficult to implement at high speeds.• Fine quantizer must work at voltages ranging from 0 to VREF/4 (subranging).
• The actual frequency of the folding signal is F times the input frequency where F is thenumber of folds
Lecture 380 – High Speed Nyquist ADCs (3/29/10) Page 380-15
CMOS Analog Circuit Design © P.E. Allen - 2010
Modified Folding PreprocessorsThe discontinuity problem can be removed by the following folding preprocessors:
060928-04
Vin
Vout
Multiple folders shifted in voltage.
Vin
VoutVREF
80
-VREF8
VREF8
0-VREF
8
VREF
VREF
0
0
Folder that removes discontinuity problem.
In the second case, the reference voltage for all comparators is identical which removesany ICMR problems.
Lecture 380 – High Speed Nyquist ADCs (3/29/10) Page 380-16
CMOS Analog Circuit Design © P.E. Allen - 2010
A 5-Bit Folding ADC Using 1-Bit Quantizers (Comparators)Block diagram:
Comments:• Number of comparators is 7 for the fine quantizer and 3 for the course quantizer• The zero crossings of the folders must be equally spaced to avoid linearity errors• The number of folders can be reduced and the comparators simplified by use of
interpolation
CoarseMSBs(n1=2)
Folder 1
+-
Folder 2
+-
Folder 7
+-
Dec
oder
Vin
2 bits
3 bitsLSBs
Comparators
5-bitdigitaloutput
Fig.10.8-11
Lecture 380 – High Speed Nyquist ADCs (3/29/10) Page 380-17
CMOS Analog Circuit Design © P.E. Allen - 2010
Folding CircuitsImplementation ofa times 4 folder:
Comments:• Horizontal
shifting isachieved bymodifying thetopmost andbottom resistorsof the resistorstring
• Folding and interpolation ADCs offer the most resolution at high speeds ( 8 bits at500MHz)
060928-06
V1 V2 V8
VDD
FoldingOutputs
Vin
+VREF
V1
V2
V7
V8Vou-
+
Vout
V1 V2 V3 V4 V6V5 V7
V7
Vin
I I I I
RL RLR
R/4
0
+IRL
-IRL
VREF
I
V8
R/4R/4R/4R/4R/4R/4R/4
R/4R/4R/4R/4R/4R/4R/4R/4
Lecture 380 – High Speed Nyquist ADCs (3/29/10) Page 380-18
CMOS Analog Circuit Design © P.E. Allen - 2010
Use of a S/H in Front of the Folding ADCBenefit of a S/H:• With no S/H, the folding circuit acts as an amplitude-dependent frequency multiplier.
BW of ADC BW of Folding Circuit• With S/H, all inputs to the folding circuit arrive at the same time.
- The folding circuit is no longer an amplitude-dependent frequency multiplier - BW of the ADC is now limited by the BW of the S/H circuit - Settling time of the folding and interpolating preprocessor is critical
Single S/H versus Distributed S/H:• Single S/H requires high dynamic range for low THD• Dynamic range requirement for distributed S/H reduced by the number of S/H stages• If the coarse quantizer uses the same distributed S/H signals as the fine preprocessor,
the coarse/fine synchronization is automatic• The clock skew between the distributed S/H stages must be small. The clock jitter
will have a greater effect on the distributed S/H approach.
Lecture 380 – High Speed Nyquist ADCs (3/29/10) Page 380-19
CMOS Analog Circuit Design © P.E. Allen - 2010
Error Sources and Limitations of a Basic Folding ADCError Sources:• Offsets in reference voltages due to resistor mismatch• Preamp offset (reduced by large W /L for low VGS-VT, with common-centroid
geometry)• vin feedthrough to reference ladder via Cgs of input pairs places a maximum value on
ladder resistance which is dependent on the input frequency.• Folder current-source mismatches (gives signal-dependent error distortion)• Comparator kickback (driving nodes should be low impedance)• Comparator metastability condition (uncertainty of comparator output)• Misalignment between coarse and fine quantization outputs (large code errors possible)Sampling Speed Limitations:• Folding output settling time• Comparator settling time• Clock distribution and layout• Clock jitterInput Bandwidth Limitations:• Maximum folding signal frequency (F/2)·fin, unless a S/H is used• Distortion due to limited preamplifier linear range and frequency dependent delay• Distortion due to the limited linear range and frequency dependent delay of the folder• Parasitic capacitance of routing to comparators
Lecture 380 – High Speed Nyquist ADCs (3/29/10) Page 380-20
CMOS Analog Circuit Design © P.E. Allen - 2010
HIGH-SPEED, HIGH-RESOLUTION ADCsMultiple-Bit, Pipeline Analog-Digital ConvertersA compromise between speed and resolution is to use a pipeline ADC with multiplebits/stage.i-th stage of a k-bit per stage pipeline ADC with residue amplification:
061002-02
k-bitADC
k-bitDAC
k-bits
S/HVREF VREF
ΣAv =2k
+-
i-th stage
Vi-1
Clock
Vi
Residue
k-bitADC
k-bitDAC
k-bits
S/HVREF VREF
ΣAv =2k
+-
i+1-th stage
Clock
Vi+1
Residue
Residue voltage = Vi-1 - b02 +
b1
22 + ··· +bk-22k-1 +
bk-12k VREF
Potential specifications range from 100-300 Msps and 10 to 14 bits.
Lecture 380 – High Speed Nyquist ADCs (3/29/10) Page 380-21
CMOS Analog Circuit Design © P.E. Allen - 2010
A 3-Stage, 3-Bit Per Stage Pipeline ADCIllustration of the operation:
000001
011010
100101110111
000001
011010
100101110111
000001
011010
100101110111
Clock 1
Stage 1
Clock 2
Stage 2
Clock 3
Stage 3
Digital output = 011 111 001
MSB LSB Fig.10.8-14
VREF
VREF2
0 TimeV
olta
ge
Converted word is 011 111 001Comments:• Only 21 comparators are required for this 9-bit ADC• Conversion occurs in three clock cycles• The residue amplifier will cause a bandwidth limitation,
GB = 50MHz f-3dB = 50MHz
23 6MHz
Lecture 380 – High Speed Nyquist ADCs (3/29/10) Page 380-22
CMOS Analog Circuit Design © P.E. Allen - 2010
Multiple-Bit, Pipeline Analog-Digital Converters - Subranging
The amplification of Av = 2k for each stage places a bandwidth limitation on theconverter. The subranging technique shown below eliminates this problem.
061002-03
k-bitADC
k-bitDAC
k-bits
S/HVREF(i)=VREF(i-1)/2k Σ
+-
i-th stage
Vi-1
Clock
Vi
Residue
k-bitADC
k-bitDAC
k-bits
S/H Σ+-
i+1-th stage
Clock
Vi+1
Residue
VREF(i+1)=VREF(i)/2k
VREF(i)=VREF(i-1)/2k VREF(i+1)=VREF(i)/2k
Note: the reference voltage of the previous stage (i-1) is divided by 2k to get the referencevoltage for the present stage (i), VREF(i), and so forth.
Lecture 380 – High Speed Nyquist ADCs (3/29/10) Page 380-23
CMOS Analog Circuit Design © P.E. Allen - 2010
Subranging, Multiple-Bit, Pipeline ADCsIllustration of a 2-stage, 2-bits/stage pipeline ADC:
Comments:• Resolution of the
comparators for thefollowing stages increasesbut fortunately, thetolerance of each stagedecreases by 2k for everyadditional stage.
• Removes the frequencylimitation of the amplifier
00011011
11
VREF
0
Stage 2Stage 1
Time
Vol
tage
0.5000VREF
0.7500VREF
0.2500VREF
0.3750VREF0.3125VREF
0.4375VREF
Clock 1 Clock 2Digital output word = 01 10 Fig.10.8-15
00
10
01
Lecture 380 – High Speed Nyquist ADCs (3/29/10) Page 380-24
CMOS Analog Circuit Design © P.E. Allen - 2010
Implementation of the DAC in the Multiple-Bit, Pipeline ADCCircuit: Comments:
• A good compromise between area and speed• The ADC does not need to be a flash or
parallel if speed is not crucial• Typical performance is 10 bits at 50Msamples/sec+
-
+-
+-
+-
R
R
R
R 0
1
1
0
0
0
0
0
1
OFF
OFF
OFF
ON
AnalogOut VREF Vin*
Fig.10.8-16
Lecture 380 – High Speed Nyquist ADCs (3/29/10) Page 380-25
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 380-2 - Examination of error in subranging for a 2-stage, 2-bits/stagepipeline ADCThe stages of the 2-stage,2-bits/stage pipeline ADCshown below are ideal.However, the secondstage divides VREF by 2rather than 4. Find the±INL and ±DNL for this ADC.SolutionExamination of the first stage shows that its output, Vout(1) changes at
Vin(1)VREF
= 14,
24,
34, and
44 .
The output of the first stage will beVout(1)VREF
= b02 +
b14 .
The second stage changes atVin(2)VREF
= 18,
28,
38, and
48
whereVin(2) = Vin(1) - Vout(1).
The above relationships permit the information given in the following table.
2-bitADC
2-bitDAC Σ
VREF VREFb0 b1
Vin(1)
Vout(1)
2-bitADC
2-bitDAC
VREF VREFb2 b3
Vin(2)
Vout(2)
2 2 Fig.10.8-17
Lecture 380 – High Speed Nyquist ADCs (3/29/10) Page 380-26
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 380-2 - ContinuedOutput digital word for Ex. 380-2:
Vin(1)
VREF
b0 b1 Vout(1)
VREF
Vin(2)
VREF
b2 b3 Ideal Ouput
b0 b1 b2 b2
0 0 0 0 0 0 0 0 0 0 0
1/16 0 0 0 1/16 0 0 0 0 0 1
2/16 0 0 0 2/16 0 1 0 0 1 0
3/16 0 0 0 3/16 0 1 0 0 1 1
4/16 0 1 4/16 0 0 0 0 1 0 0
5/16 0 1 4/16 1/16 0 0 0 1 0 1
6/16 0 1 4/16 2/16 0 1 0 1 1 0
7/16 0 1 4/16 3/16 0 1 0 1 1 1
8/16 1 0 8/16 0 0 0 1 0 0 0
9/16 1 0 8/16 1/16 0 0 1 0 0 1
10/16 1 0 8/16 2/16 0 1 1 0 1 0
11/16 1 0 8/16 3/16 0 1 1 0 1 1
12/16 1 1 12/16 0 0 0 1 1 0 0
13/16 1 1 12/16 1/16 0 0 1 1 0 1
14/16 1 1 12/16 2/16 0 1 1 1 1 0
15/16 1 1 12/16 3/16 0 1 1 1 1 1
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1516 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16
Analog Input Voltage
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Dig
ital O
utpu
t Cod
e
Ideal Finite Characteristic
-INL=2LSB
+DNL=2LSB
INL=0LSB
-DNL=0LSB
Comparing the actual digital output word with the ideal output word gives the following:+INL = 0LSB, -INL = 0111-0101 = -2LSB, +DNL = (1000-0101) - 1LSB = +2LSB, and-DNL = (0101-0100) - 1LSB = 0LSB.
Lecture 380 – High Speed Nyquist ADCs (3/29/10) Page 380-27
CMOS Analog Circuit Design © P.E. Allen - 2010
Example of a Multiple-Bit, Pipeline ADCTwo-stages with 5-bits per stage resulting in a 10-bit ADC with a sampling rate of5Msamples/second.Architecture:
S/HMSBADC
DACIncrement
by 1
LSBADC
DAC
MSBs
LSBs
Vr1
Vr2
Vin Vin*
Fig.10.8-21
Features:• Requires only 2n/2-1 comparators• LSBs decoded using 31 preset charge redistribution capacitor arrays• Reference voltages used in the LSBs are generated by the MSB ADC• No op amps are used
Lecture 380 – High Speed Nyquist ADCs (3/29/10) Page 380-28
CMOS Analog Circuit Design © P.E. Allen - 2010
Example of a Multiple-Bit, Pipeline ADC - ContinuedMSB Conversion:
Operation:1.) Sample Vin* on
each 32Ccapacitanceautozeroing thecomparators
2.) Connect eachcomparator to a nodeof the resistor stringgenerating athermometer code.
+-
Vin*
+-
Vin*
VREF
R32
R31
+-
Vin*
+-
Vin*
LatchBankand
BinaryEncoder
32C
32C
32C
32C
Vin*+ -
Vin*+ -
Vin*+ -
Vin*+ -
R30
Ri
R2
R1
AnalogMUX
Vr2
Vr1VRi
VRi -Vin*
MSBOutpu
Fig.10.8-22MSBs
DAC
Lecture 380 – High Speed Nyquist ADCs (3/29/10) Page 380-29
CMOS Analog Circuit Design © P.E. Allen - 2010
Example of a Multiple-Bit, Pipeline ADC - ContinuedLSB Conversion: Operation:
1.) MSB comparators are preset to eachof the 31 possible digital codes.
2.) Vr1 and Vr2 are derived from theMSB conversion.
3.) Preset comparators will produce athermometer code to the encoder.
Comments:• Requires two full clock cycles• Reuses the comparators• Accuracy limited by resistor string
and its dynamic loading• Accuracy also limited by the capacitor
array• Comparator is a 3-stage, low-gain, wide-bandwidth, using internal autozeroing
LatchBankand
BinaryEncoder
LSBOutput
ADC set to Code 11111
Vr1
Vr2
Vin*
ADC set to Code 11110
Vr1
Vr2
Vin*
ADC set to Code 00010
Vr1
Vr2
Vin*
ADC set to Code 00001
Vr1
Vr2
Vin*
+-
2C C4C8C16C
Vr1
Vr2Switches
set to"Code" Fig.10.8-23
C
Lecture 380 – High Speed Nyquist ADCs (3/29/10) Page 380-30
CMOS Analog Circuit Design © P.E. Allen - 2010
Digital Error CorrectionLike many of the accuracy enhancing techniques, there are particular applications wherecertain correcting techniques are useful. In the pipeline, analog-digital converter, atechnique called digital error correction is used to remove the imperfections of thecomponents.Pipeline ADC:
Stage 1B bits
vIN* Stage 2B bits
Stage KB bits
KBbits
DigitalLogic
041007-11
Operation:1.) Stage 1 resolves the analog input signal to within one of B subranges which
determines the first B bits.2.) Stage 1 then creates the analog residue (analog input – quantized analog output) and
passes on to Stage 2 by either amplifying or subranging.3.) Stage 2 repeats this process which ends with Stage K.
Lecture 380 – High Speed Nyquist ADCs (3/29/10) Page 380-31
CMOS Analog Circuit Design © P.E. Allen - 2010
Comparator Error in a Pipeline ADCSubranging Pipeline ADC Example (B =2, K = 3):
Digital output word = 01 11
Stage 2Stage 1
Clock 1 Clock 2Time
VREF
0
00
Stage 3
Clock 3
Vin* = 0.45VREF
0.50VREF
0.75VREF
0.25VREF
041007-14Digital output word = 10 00
Stage 2Stage 1
Clock 1 Clock 2Time
VREF
0
00
Stage 3
Clock 3
Vin* = 0.45VREF
0.50VREF
0.75VREF
0.25VREF
First StageComparator
Error
Ideal ADC ADC with first stage erorr
Note that if the comparator in the first stage makes the wrong choice, the convertercannot recover as shown in the example on the right.
Lecture 380 – High Speed Nyquist ADCs (3/29/10) Page 380-32
CMOS Analog Circuit Design © P.E. Allen - 2010
Digital Error Correction – ContinuedDigital error correction uses one of the bits of each stage (except the first) to correct forany errors caused by the previous stage.Subranging Pipeline ADC Example (B =2, K = 3) using Digital Error Correction:
Digital output word = 01 00
Stage 2Stage 1
Clock 1 Clock 2Time
VREF
0
00
Stage 3
Clock 3
Vin* = 0.45VREF
0.50VREF
0.75VREF
0.25VREF
041007-15Digital output word = 10 -01
Stage 2Stage 1
Clock 1 Clock 2Time
VREF
0
00
Stage 3
Clock 3
Vin* = 0.45VREF
0.50VREF
0.75VREF
0.25VREF
First StageComparator
Error
ADC with Digital Error CorrectionADC with first stage erorr
00
01
10
11
100→10101→11
110→100111→101
00
01
10
11
00011011
00011011
000→-10001→-01010→00011→01
100→10101→11110→100111→101
000→-10001→-01010→00011→01
Corrected digital output word = 01 11 00
Comments:• Add a correcting bit to the following stage to correct for errors in the previous stage.• The subranging or amplification of the next stage does not include the correcting bit.• Correction can be done after all stages of the pipeline ADC have converted or after
each individual stage.
Lecture 380 – High Speed Nyquist ADCs (3/29/10) Page 380-33
CMOS Analog Circuit Design © P.E. Allen - 2010
12-Bit Pipeline ADC with Digital Error Correction & Self-Calibration†
Digital ErrorCorrection:• Avoids saturation
of the next stage• Reduces the
number ofmissing codes
• Relaxedspecifications forthe comparators
• Compensates forwrong decisionsin the coarsequantizers
Self-Calibration:• Can calibrate the effects of the DAC nonlinearity and gain error• Can be done by digital or analog methods or both
† J. Goes, et. al., CICC’96
DAC
ADC
S/Hvin
3 bits
DAC
ADC
3 bits
DAC
ADC
3 bits
DAC
ADC
3 bits
ADC
4 bits
12 bits
Digital Error Correction Logic
Clock
Fig. 11-30
Lecture 380 – High Speed Nyquist ADCs (3/29/10) Page 380-34
CMOS Analog Circuit Design © P.E. Allen - 2010
Digital Error Correction using B.5-Bit Pipeline StagesThe top and bottom comparators can be removed to achieve digital error correction moreefficiently.Input-output characteristics for different per-stage resolutions (B = 1, 2, and 3):
061002-01
vout
vin
VREF
VREF2
0
VREF2
−
VREF−VREF− VREF
2− 0 VREF
2VREF
Offset Correction
Range
B = 1
vout
vin
VREF− VREF2
− 0 VREF2
VREF
Offset Correction
Range
B = 2
vout
vin
VREF− VREF2
− 0 VREF2
VREF
Offset Correction
Range
B = 3
-116
116
-316
-516
-716
-916
-1116
-1316
316
516
716
916
1116
1316
18
38
58
-58
-38
-18
14
-14
If all else is ideal, the offset voltage correction range is equal to ±VREF
2B+1 .
Lecture 380 – High Speed Nyquist ADCs (3/29/10) Page 380-35
CMOS Analog Circuit Design © P.E. Allen - 2010
TIME-INTERLEAVED ADC CONVERTERSTime-Interleaved Analog-Digital ConvertersSlower ADCs are usedin parallel.Illustration:
Comments:• Can get the samethroughput with less chip area• If M = N, then a digital word is converted at every clock cycle• Multiplexer and timing become challenges at high speeds
S/H N-bit ADC No. 1
T1
S/H
T2
S/H
TM
Vin
Digitalwordout
T1 T2 TM T1+TCt
T2+TC TM+TC
N-bit ADC No. 2
N-bit ADC No. M
N-bit ADC No. 1N-bit ADC No. 2
N-bit ADC No. MT=TC
M
Fig.10.8-20
Lecture 380 – High Speed Nyquist ADCs (3/29/10) Page 380-36
CMOS Analog Circuit Design © P.E. Allen - 2010
SUMMARY
Type of ADC Primary Advantage Primary DisadvantageFlash or parallel Fast Area is large if N > 6Interpolating Fast Requires accurate
interpolationFolding Fast Bandwidth increases if
no S/H usedMultiple-Bit,Pipeline
Increased number of bits Slower than flash
Time-interleaved
Small area with largethroughput
Precise timing and fastmultiplexer
Typical Performance:• 6-8 bits• 500-2000 Msamples/sec.• The ENOB at the Nyquist frequency is typically 1-2 bits less that the ENOB at low
frequencies.• Power is approximately 0.3 to 1W
Lecture 390 – Oversampling ADCs – Part I (3/29/10) Page 390-1
CMOS Analog Circuit Design © P.E. Allen - 2010
LECTURE 390 – OVERSAMPLING ADCS – PART ILECTURE ORGANIZATION
Outline• Introduction• Delta-sigma modulators• SummaryCMOS Analog Circuit Design, 2nd Edition ReferencePages 698-705
Lecture 390 – Oversampling ADCs – Part I (3/29/10) Page 390-2
CMOS Analog Circuit Design © P.E. Allen - 2010
INTRODUCTIONWhat is an oversampling converter?An oversampling converter uses a noise-shaping modulator to reduce the in-bandquantization noise to achieve a high degree of resolution.• What is the range of oversampling?
The oversampling ratio, called M, is a ratio of the clock frequency to the Nyquistfrequency of the input signal. This oversampling ratio can vary from 8 to 256.- The resolution of the oversampled converter is proportional to the oversampled ratio.- The bandwidth of the input signal is inversely proportional to the oversampled ratio.
• What are the advantages of oversampling converters?Very compatible with VLSI technology because most of the converter is digitalHigh resolutionSingle-bit quantizers use a one-bit DAC which has no INL or DNL errorsProvide an excellent means of trading precision for speed (16-18 bits at 50ksps to 8-10bits at sampling rates of 5-10Msps).
• What are the disadvantages of oversampling converters?Difficult to model and simulateLimited in bandwidth to the clock frequency divided by the oversampling ratio
Lecture 390 – Oversampling ADCs – Part I (3/29/10) Page 390-3
CMOS Analog Circuit Design © P.E. Allen - 2010
Nyquist Versus Oversampled ADCsConventional Nyquist ADC Block Diagram:
Fig.10.9-01
DigitalProcessor
y(kTN)x(t)
Filtering Sampling Quantization Digital Coding
Oversampled ADC Block Diagram:
Fig.10.9-02
DecimationFilter
y(kTN)x(t)
Filtering Sampling Quantization Digital Coding
Modulator
Components:• Filter - Prevents possible aliasing of the following sampling step.• Sampling - Necessary for any analog-to-digital conversion.• Quantization - Decides the nearest analog voltage to the sampled voltage (determines
the resolution).• Digital Coding - Converts the quantizer information into a digital output signal.
Lecture 390 – Oversampling ADCs – Part I (3/29/10) Page 390-4
CMOS Analog Circuit Design © P.E. Allen - 2010
Frequency Spectrum of Nyquist and Oversampled ConvertersDefinitions:
fB = analog signal bandwidth
fN = Nyquist frequency (two times fB)
fS = sampling or clock frequency
M = fSfN =
fS2fB = oversampling ratio
Frequency prespective:
Fig.10.9-03
��
������
0.5fN = 0.5fSfB fS =fN0
0
Am
plitu
de
f
fB = 0.5fN
0.5fS fS =MfN0
0
Am
plitu
de
ffN
Anti-aliasing filter
Anti-aliasing filter
Signal Bandwidth
Signal Bandwidth
Transition band
Transition band
Conventional ADC with fB≈ 0.5fN=0.5fS.
Oversampled ADC with fB≈ 0.5fN<<fS.
Lecture 390 – Oversampling ADCs – Part I (3/29/10) Page 390-5
CMOS Analog Circuit Design © P.E. Allen - 2010
Quantization Noise of a Conventional (Nyquist) ADCMultilevel Quantizer:
The quantized signal y can be represented as,
y = Gx + ewhere
G = gain of the ADC, normally 1e = quantization error
The mean square value of the quantization error is
e 2rms = SQ =
1 - /2
/2e(x)2dx =
2
12
Fig.10.9-04
Output, y
Input, x
5
1
3
-1
-3
-5
2 4 6
-2-4-6
Ideal curve
Input, x
Quantization error, e1
-1
Δ
Δ
Lecture 390 – Oversampling ADCs – Part I (3/29/10) Page 390-6
CMOS Analog Circuit Design © P.E. Allen - 2010
Quantization Noise of a Conventional (Nyquist) ADC - ContinuedSpectral density of the sampled noise:
When a quantized signal is sampled at fS (= 1/ ), then all of its noise power folds intothe frequency band from 0 to 0.5fS. Assuming that the noise power is white, the spectraldensity of the sampled noise is,
E(f) = erms2fS = erms 2
where = 1/fS and fS = sampling frequency
The inband noise energy no is
no2 = 0
fBE2(f)df = e
2rms (2fB ) = e
2rms
2fBfS =
e2
rmsM no =
erms
M
What does all this mean? • One way to increase the resolution of an ADC is to make the bandwidth of the signal,
fB, less than the clock frequency, fS. In otherwords, give up bandwidth for precision.
• However, it is seen from the above that a doubling of the oversampling ratio M, onlygives a decrease of the inband noise, no, of 1/ 2 which corresponds to -3dB decreaseor an increase of resolution of 0.5 bits
As a result, increasing the oversampling ratio of a Nyquist analog-digital converteris not a very good method of increasing the resolution.
Lecture 390 – Oversampling ADCs – Part I (3/29/10) Page 390-7
CMOS Analog Circuit Design © P.E. Allen - 2010
Oversampled Analog-Digital ConvertersClassification of oversampled ADCs:1.) Straight-oversampling - The quantization noise is assumed to be equally distributed
over the entire frequency range of dc to 0.5fS. This type of converter is representedby the Nyquist ADC.
2.) Predictive oversampling - Uses noise shapingplus oversampling to reduce the inband noise toa much greater extent than the straight-oversampling ADC. Both the signal and noisequantization spectrums are shaped.
3.) Noise-shaping oversampling - Similar to thepredictive oversampling except that only thenoise quantization spectrum is shaped whilethe signal spectrum is preserved.
The noise-shaping oversampling ADCs are also known as delta-sigma ADCs. We willonly consider the delta-sigma type oversampling ADCs.
Lecture 390 – Oversampling ADCs – Part I (3/29/10) Page 390-8
CMOS Analog Circuit Design © P.E. Allen - 2010
DELTA-SIGMA MODULATORSGeneral block diagram of an oversampled ADC
Fig.10.9-07
ΔΣ Modulator(Analog)
Decimator(Digital)
Lowpass Filter(Digital)
fS fD<fS
AnalogInputx(t)
fB 2fB DigitalPCM
Components of the Oversampled ADC:1.) Modulator - Also called the noise shaper because it can shape the quantizationnoise and push the majority of the inband noise to higher frequencies. It modulates theanalog input signal to a simple digital code, normally a one-bit serial stream using asampling rate much higher than the Nyquist rate.2.) Decimator - Also called the down-sampler because it down samples the highfrequency modulator output into a low frequency output and does some pre-filtering onthe quantization noise.3.) Digital Lowpass Filter - Used to remove the high frequency quantization noise and topreserve the input signal.Note: Only the modulator is analog, the rest of the circuitry is digital.
Lecture 390 – Oversampling ADCs – Part I (3/29/10) Page 390-9
CMOS Analog Circuit Design © P.E. Allen - 2010
First-Order, Delta-Sigma ModulatorBlock diagram of a first-order, delta-sigmamodulator:
Components:• Integrator (continuous or discrete time)• Coarse quantizer (typically two levels)
- A/D which is a comparator for two levels- D/A which is a switch for two levels
First-order modulator output for a sinusoidal input:
Fig.10.9-09
-1.5
-1
-0.5
0
0.5
1
1.5
0 50 100 150 200 250
Vol
ts
Tme (Units of T, clock period)
Fig.10.9-08
-
+Integrator A/D
D/A
x
u
v y
Quantizer
fS
Lecture 390 – Oversampling ADCs – Part I (3/29/10) Page 390-10
CMOS Analog Circuit Design © P.E. Allen - 2010
Sampled-Data Model of a First-Order Modulator
Writing the following relationships,y[nTs] = q[nTs] +v[nTs]
v[nTs] = w[(n-1)Ts] + v[(n-1)Ts]
y[nTs] = q[nTs]+w[(n-1)Ts]+v[(n-1)Ts] = q[nTs]+{x[(n-1)Ts]-y[(n-1)Ts]}+v[(n-1)Ts]
But the first equation can be written asy[(n-1)Ts] = q[(n-1)Ts] +v[(n-1)Ts] q[(n-1)Ts] = y[(n-1)Ts]} - v[(n-1)Ts]
Substituting this relationship into the above gives,y[nTs] = x[(n-1)Ts] + q[nTs] - q[(n-1)Ts]
Converting this expression to the z-domain gives,
Y(z) = z-1X(z) + (1-z-1)Q(z)Definitions:
Signal Transfer Function = STF = Y(z)X(x) = z-1
Noise Transfer Function = NT F= Y(z)Q(x) = 1-z-1
+
+
-
+Delay
+Integrator
Quan-tizer
x[nTs] v[nTs]
q[nTs]
y[nTs]
Fig. 10.9-10
w[nTs]
Lecture 390 – Oversampling ADCs – Part I (3/29/10) Page 390-11
CMOS Analog Circuit Design © P.E. Allen - 2010
Higher-Order ModulatorsA second-order, modulator:
070917-01
+
+
-
+Delay
+Integrator 2
Quan-tizer
q[nTs]
y[nTs]x[nTs]
+
+
-
+Integrator 1
Delay
It can be shown that the z-domain output is,
Y(z) = z-1X(z) + (1-z-1)2Q(z)The general, L-th order modulator has the following form,
Y(z) = z-KX(z) + (1-z-1)LQ(z)Note that noise transfer function, NTF, has L-zeros at the origin resulting in a high-passtransfer function. K depends on the architecture where K L.This high-pass characteristic reduces the noise at low frequencies which is the key toextending the dynamic range within the bandwidth of the converter.
Lecture 390 – Oversampling ADCs – Part I (3/29/10) Page 390-12
CMOS Analog Circuit Design © P.E. Allen - 2010
Noise Transfer FunctionThe noise transfer function can be written as,
NTFQ (z) = (1-z-1)L
Evaluate (1-z-1) by replacing z by ej Ts to get
(1-z-1)= 1 - e-j Ts 2j2j
ej f/fs
ej f/fs = ej f/fs - e-j f/fs
2j 2j e-j f/fs = sin( fTs) 2j e-j f/fs
|1-z-1| = (2sin fTs) |NTFQ(f)| = (2sin fTs)L
Magnitude of the noise transferfunction,
Note: Single-loop modulatorshaving noise shaping charac-teristics of the form (1-z-1)Lare unstable for L>2 unless anL-bit quantizer is used.
Fig.10.9-12
LPF
����0
2
4
6
8
10
Mag
nitu
de o
f no
ise
shap
ing
func
tion
Frequency0
L = 1
L = 2
L = 3
fb fs/2
Lecture 390 – Oversampling ADCs – Part I (3/29/10) Page 390-13
CMOS Analog Circuit Design © P.E. Allen - 2010
In-Band Rms Noise of Single-Loop ModulatorAssuming noise power is white, the power spectral density of the modulator, SE(f), is
SE(f) = |NTFQ(f)|2 |SQ(f)|
fs
Next, integrate SE(f) over the signal band to get the inband noise power using SQ = 2
12
SB = 1fs
-fb
fb
(2sin fTs)2L2
12df 2L
2L+11
M2L+12
12 where sin fTs fTs for M>>1.
Therefore, the in-band, rms noise is given as
n0 = SB = L
2L+11
ML+0.5 12 = L
2L+11
ML+0.5 erms
Note that as the is a much more efficient way of achieving resolution by increasing M.
n0 erms
ML+0.5 Doubling of M leads to a 2L+0.5 decrease of in-band noise
resulting in an extra L+0.5 bits of resolution! The increase of the oversampling ratio is an excellent method of increasing the
resolution of a oversampling analog-digital converter.
Lecture 390 – Oversampling ADCs – Part I (3/29/10) Page 390-14
CMOS Analog Circuit Design © P.E. Allen - 2010
Illustration of RMS Noise Versus Oversampling Ratio for Single Loop ModulatorsPlotting n0/erms gives,
n0erms
= L
2L+11
ML+0.5
Lecture 390 – Oversampling ADCs – Part I (3/29/10) Page 390-15
CMOS Analog Circuit Design © P.E. Allen - 2010
Dynamic Range of Analog-Digital ConvertersOversampled Converter:The dynamic range, DR, for a 1 bit-quantizer with level spacing =VREF, is
DR2 = Maximum signal power
SB(f) = 2 2
2
2L
2L+11
M2L+12
12
= 32
2L+12L M2L+1
Nyquist Converter:The dynamic range of a N-bit Nyquist rate ADC is (now becomes VREF for large N),
DR2 = Maximum signal power
SQ =
(VREF/2 2)22/12 =
32 22N DR = 1.5 2N
Expressing DR in terms of dB (DRdB) and solving for N, gives
N = DRdB - 1.7609
6.0206 or DRdB = (6.0206N + 1.7609) dB
Example: A 16-bit ADC requires about 98dB of dynamic range. For a second-ordermodulator, M must be 153 or 256 since we must use powers of 2.Therefore, if the bandwidth is 20kHz, then the clock frequency must be 10.24MHz.
Lecture 390 – Oversampling ADCs – Part I (3/29/10) Page 390-16
CMOS Analog Circuit Design © P.E. Allen - 2010
Multibit QuantizersA single-bit quantizer:
= VREFAdvantage is that the DAC is inherently linear.
Multi-bit quantizer:Consists of an ADC and DAC of B-bits.
= VREF2B-1
Disadvantage is that theDAC is no longer perfectlylinear. To get largeresolution delta-sigmaADCs requires highlyprecise DACs.
Dynamic range of a multibit ADC:
DR2 = 32
2L+12L M2L+1 2B-1 2
+-
yv
uv<0
v>0
Fig. 10.9-13
VREF2
VREF2
Fig. 10.9-14
A/D
D/A
v
Quantizer
fS
u
yVREF Δ
Fig. 10.9-135
Lecture 390 – Oversampling ADCs – Part I (3/29/10) Page 390-17
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 390-1 - Tradeoff Between Signal Bandwidth and Accuracy of ADCs
Find the minimum oversampling ratio, M, for a 16-bit oversampled ADC which uses(a.) a 1-bit quantizer and third-order loop, (b.) a 2-bit quantizer and third-order loop, and(c.) a 3-bit quantizer and second-order loop. For each case, find the bandwidth of theADC if the clock frequency is 10MHz.
Solution
We see that 16-bit ADC corresponds to a dynamic range of approximately 98dB. (a.) Solving for M gives
M = 23
DR2
2L+12L
(2B-1)21/(2L+1)
Converting the dynamic range to 79,433 and substituting into the above equation gives aminimum oversampling ratio of M = 48.03 which would correspond to an oversamplingrate of 64. Using the definition of M as fc/2fB gives fB as 10MHz/2·64 = 78kHz.
(b.) and (c.) For part (b.) and (c.) we obtain a minimum oversampling rates of M = 32.53and 96.48, respectively. These values correspond to oversampling rates of 32 and 128,respectively. The bandwidth of the converters is 312kHz for (b.) and 78kHz for (c.).
Lecture 390 – Oversampling ADCs – Part I (3/29/10) Page 390-18
CMOS Analog Circuit Design © P.E. Allen - 2010
Z-Domain Equivalent CircuitsThe modulator structures are much easier to analyze and interpret in the z-domain.
Fig.10.9-16
+
+
-
+Delay
+Integrator
Quan-tizer
x[nTs] v[nTs]
q[nTs]
y[nTs]w[nTs]
+
+
-
+z-1 +
Integrator
Quan-tizer
X(z) V(z)
Q(z)
Y(z)W(z)
-
+ z-1 +X(z)
Q(z)
Y(z)
1-z-1
Y(z) = Q(z) + z-1
1-z-1 [X(z) - Y(z)] Y(z) 1
1-z-1 = Q(z) + z-1
1-z-1 X(z)
Y(z) = (1-z-1)Q(z) + z-1X(z) NTFQ (z) = (1-z-1) for L = 1
Lecture 390 – Oversampling ADCs – Part I (3/29/10) Page 390-19
CMOS Analog Circuit Design © P.E. Allen - 2010
Cascaded, Second-Order ModulatorSince the single-loop architecture with order higher than 2 are unstable, it is necessary tofind alternative architectures that allow stable higher order modulators.A cascaded, second-order structure:
Y1(z) = (1-z-1)Q1(z) + z-1X(z)
X2(z) = z-1
1-z-1 (X(z) -Y1(z)
= z-1
1-z-1 X(z) - z-1
1-z-1 [(1-z-1)Q1(z) + z-1X(z)]
Y2(z) = (1-z-1)Q2(z) + z-1X2(z) = (1-z-1)Q2(z) + z-2
1-z-1 X(z) - z-2Q1(z) - z-2
1-z-1 X(z)
= (1-z-1)Q2(z) - z-2Q1(z)Y(z) = Y2(z) - z-1Y2(z) + z-2Y1(z) = (1-z-1)Y2(z) + z-2Y1(z)= (1-z-1)2Q2(z) - (1-z-1)z-2Q1(z) + (1-z-1)z-2Q1(z) + z-3X(z) = (1-z-1)2Q2(z) + z-3X(z)
Y(z) = (1-z-1)2Q2(z) + z-3X(z)
Fig.10.9-17
-
+ z-1 +
Q1(z)
Y1(z)
1-z-1
-
+ z-1 +
X(z)
Q2(z)
Y(z)
1-z-1
z-1-
+ z-1 +
X2(z)
Y2(z)
+
Lecture 390 – Oversampling ADCs – Part I (3/29/10) Page 390-20
CMOS Analog Circuit Design © P.E. Allen - 2010
Third-Order, MASH ModulatorIt can be shown that
Y(z) = X(z) + (1-z-1)3Q3(z)
This results in a 3rd-order noise shaping and nodelay between the input and output.
Comments:• The above structures that eliminate the noise of all quantizers except the last are called
MASH or multistage architectures.• Digital error cancellation logic is used to remove the quantization noise of all stages,
except that of the last one.
1-z-11
z-1
X(z) +
-
Q1(z)
+ -
+ +
1-z-11
z-1
Q2(z)
+ -
+ +1-z-1
Y1(z)
Y2(z)
+- +
+
+
+
1-z-11
z-1
Q3(z)
+ +1-z-1
Y3(z)
+-
1-z-1
Y(z)
Fig. 10.9-17A
-Q1(z)
-Q2(z)
Lecture 390 – Oversampling ADCs – Part I (3/29/10) Page 390-21
CMOS Analog Circuit Design © P.E. Allen - 2010
A Fourth-Order, MASH-type Modulator using Scaling of Error Signals†
The signal is dividedby 1/C as it passesfrom the first 2nd-order modulator tothe second 2nd-ordermodulator. Thedigital output of thesecond 2nd-ordermodulator is thenmultiplied by theinverse factor of C.
The various transfer functions are (a1=1, a2=2, b1=1, b2=2, l1=2 and C = 4) :
† U.S. Patent 5,061,928, Oct. 29, 1991.
061207-01
a1
−+ z-1
1-z-1
a2
−+z-1
1-z-1
−
+Xin(z)
Q1(z)
b1
−
+ z-1
1-z-1
b2
−+z-1
1-z-1+
Q2(z)
+
1/C
D1(z)
D2(z)
z-1
1-z-11-z-1
z-1 +
C
Dout(z)
+
+
+
λ1
D1(z) = Xin(z) + (1-z-1)2 Q1(z)
D2(z) = (1/C)(-Q1(z)) + (1-z-1)2 Q2(z)
Dout(z) = Xin(z) + (1-z-1)4 Q2(z)
Lecture 390 – Oversampling ADCs – Part I (3/29/10) Page 390-22
CMOS Analog Circuit Design © P.E. Allen - 2010
Distributed Feedback Modulator - Fourth-Order
Fig.10.9-20
a1z-1
1-z-1-
+X a2z-1
1-z-1a3z-1
1-z-1a4z-1
1-z-1+
+ 1-bitA/D
1-bitD/A
Q
Y
++
++
Y1 Y2 Y3 Y4
Amplitude of integrator outputs:
0.00
0.25
0.50
0.75
1.00
1.25
1.50
am
plit
ude o
f in
tegra
tor
outp
ut
/ V
REF
-1.00 -0.60 -0.20 0.20 0.60 1.00
input signal amplitude / VREF
fourth order distributed feedback modulator
a1=0.1, a2=0.1, a3=0.4, a4=0.4
y1
y2
y3
y4
Lecture 390 – Oversampling ADCs – Part I (3/29/10) Page 390-23
CMOS Analog Circuit Design © P.E. Allen - 2010
0.00
0.25
0.50
0.75
1.00
1.25
1.50
-1.00
am
plit
ude o
f in
tegra
tor
outp
uts
-0.60 -0.20 0.20 0.60 1.00input signal amplitude / VREF
fourth order feedforward modulator
a1=0.5, a2=0.4, a3=0.1, a4=0.1
y1
y2
y3
y4
Distributed Feedback Modulator - Fourth-Order – Continued
Fig.10.9-20
a1z-1
1-z-1-
+X a2z-1
1-z-1a3z-1
1-z-1a4z-1
1-z-1+
+ 1-bitA/D
1-bitA/D
Q
Y
++
++
Y1 Y2 Y3 Y4
Amplitude of integrator outputs (Integrator constants have been optimized to minimizethe integrator outputs):
Lecture 390 – Oversampling ADCs – Part I (3/29/10) Page 390-24
CMOS Analog Circuit Design © P.E. Allen - 2010
Cascaded of a Second-Order Modulator with a First-Order Modulator
Fig.10.9-21
a1z-1
1-z-1-
+ a2z-1
1-z-1-
+
+
X +
α
a3z-1
1-z-1-
+ +β
q1
q2
+
+
Dig
ital e
rror
can
cella
tion
circ
uit
Y
Comments:• The stability is guaranteed for cascaded structures• The maximum input range is almost equal to the reference voltage level for the
cascaded structures• All structures are sensitive to the circuit imperfection of the first stages• The output of cascaded structures is multi-bit requiring a more complex digital
decimator
Lecture 390 – Oversampling ADCs – Part I (3/29/10) Page 390-25
CMOS Analog Circuit Design © P.E. Allen - 2010
Integrator Circuits for ModulatorsFundamental block of the modulator:
Fig.10.9-22+
+z-1
Vi(z) az-1
1-z-1
Vo(z) Vi(z) Vo(z)a
Fully-Differential, SwitchedCapacitor Implementation:
It can be shown (Chapter 9 of the text) that,Vout(z)Vin(z) =
CsCi
z-1
1-z-1
Vo
out(e j T)
Voin( e j T)
= C1
C2
e-j T/2
j2 sin( T/2) TT =
C1
j TC2
T/2sin( T/2) e-j T/2
V
oout(e j T)
Voin( e j T)
= (Ideal)x(Magnitude error)x(Phase error) where I = C1
TC2 Ideal =
I
j
Fig.10.9-23
+-+
-vin+
-vout+
-
φ2
φ2
φ2
φ2
φ1
φ1
φ1
φ1
Cs
φ1
Cs
Ci
Ci
Lecture 390 – Oversampling ADCs – Part I (3/29/10) Page 390-26
CMOS Analog Circuit Design © P.E. Allen - 2010
Power Dissipation versus Supply Voltage and Oversampling RatioThe following is based on the above switched-capacitor integrator:1.) Dynamic range:
The noise in the band [-fs,fs] is kT/C while the noise in the band [-fs/2M,fs/2M] iskT/MC. We must multiply this noise by 4; x2 for the sampling and integrating phasesand x2 for differential operation.
2.) Lower bound on the sampling capacitor, Cs:
3.) Static power dissipation of the integrator: Pint = IbVDD
4.) Settling time for a step input of Vo,max:
Ib = Ci Vo,maxTsettle
=Ci
Tsettle
CsCi
VDD = CsVDDTsettle
= CsVDD(2fs) = 2MfNCsVDD
Pint = 2MfNCsVDD2 = 16kT·DR·fNBecause of additional feedback to the first integrator, the maximum voltage can be 2VDD.
P1st-int = 32kT·DR·fN
DR = VDD2/24kT/MCs
= V
2DDMCs8kT
Cs = 8kT·DR
V2
DDM
Lecture 390 – Oversampling ADCs – Part I (3/29/10) Page 390-27
CMOS Analog Circuit Design © P.E. Allen - 2010
SUMMARY• Oversampled ADCs allow signal bandwidth to be efficiently traded for resolution• Noise shaping oversampled ADCs preserve the signal spectrum and shape the noise
quantization spectrum• The modulator shapes the noise quantization spectrum with a high pass filter• The quantizer can be single or multiple bit
- Single bit quantizers do not require linear DACs because a 1 bit DAC cannot benonlinear
- Multiple bit quantizers require ultra linear DACs• Modulators consist of combined integrators with the goal of high-pass shaping of the
noise spectrum and cancellation of all quantizer noise but the last quantizer
Lecture 400 – Oversampling ADCs – Part II (3/29/10) Page 400-1
CMOS Analog Circuit Design © P.E. Allen - 2010
LECTURE 400 – OVERSAMPLING ADCS – PART IILECTURE ORGANIZATION
Outline• Implementation of modulators• Decimation and filtering• Bandpass modulators• Digital-analog oversampling converters• SummaryCMOS Analog Circuit Design, 2nd Edition ReferencePages 705-715
Lecture 400 – Oversampling ADCs – Part II (3/29/10) Page 400-2
CMOS Analog Circuit Design © P.E. Allen - 2010
IMPLEMENTATION OF MODULATORS Modulators – The Analog Part of the Oversampling ADC
Most of today’s delta-sigma modulators use fully differential switched capacitor circuits.Advantages are:• Doubles the signal swing and increases the dynamic range by 6dB• Common-mode signals that may couple to the signal through the supply lines and
substrate are canceled• Charge injected by the switches are canceled to a first-orderExample:
First integratordissipates the mostpower and requires themost accuracy.
Fig.10.9-24
YB
Y
-
+ 0.5z-11 - z-1
-
+ 0.5z-11 - z-1
++X Y
Q1
+
-
VRef+
φ1dφ1d
Y YB
φ2φ2
VRef+ VRef
-
VRef-
2C
2C
C
Cφ1dφ1d
YYB
VRef+
Y YB
VRef-
φ1
φ1
VRef+ VRef
-
YYB
+
-φ2φ2
2C
2C
C
C
φ1
φ1
φ1
Lecture 400 – Oversampling ADCs – Part II (3/29/10) Page 400-3
CMOS Analog Circuit Design © P.E. Allen - 2010
1.5V, 1mW, 98db Analog-Digital Converter†
a1z - 1Σ
b1
Σ Σa2
z - 1
b2
a3z - 1
a4z - 1
Σ
1-bitA/D
1-bitD/A
α E
y4Y
y3y2y1
X
Fig. 10.10-06
where a1 = 1/3, a2 = 3/25, a3 = 1/10, a4 = 1/10, b1= 6/5, b2= 1 and = 1/6
Advantages: • The modulator combines the advantages of both DFB and DFF type modulators:
Only four op amps are required. The 1st integrator’s output swing is between ±VREFfor large input signal amplitudes (0.6VREF), even if the integrator gain is large (0.5).
• A local resonator is formed by the feedback around the last two integrators to furthersuppress the quantization noise.
• The modulator is fully pipelined for fast settling.
† A.L. Coban and P.E. Allen, “A 1.5V, 1mW Audio Modulator with 98dB Dynamic Range, “Proc. of 1999 Int. Solid-State Circuits Conf., Feb.
1999, pp. 50-51.
Lecture 400 – Oversampling ADCs – Part II (3/29/10) Page 400-4
CMOS Analog Circuit Design © P.E. Allen - 2010
1.5V, 1mW, 98dB Analog-Digital Converter - ContinuedIntegrator power dissipation vs. integrator gain
DR = 98 dBBW = 20 kHzCs = 5 pF0.5 μm CMOS
Lecture 400 – Oversampling ADCs – Part II (3/29/10) Page 400-5
CMOS Analog Circuit Design © P.E. Allen - 2010
1.5V, 1mW, 98db Analog-Digital Converter - ContinuedModulator power dissipation vs. oversampling ratio
SuppyVoltage (V)
DR = 98 dBBW = 20 kHzIntegrator gain = 1/30.5μm CMOS
OSR = 64
OSR = 32
OSR = 16 OSR = 8
Lecture 400 – Oversampling ADCs – Part II (3/29/10) Page 400-6
CMOS Analog Circuit Design © P.E. Allen - 2010
1.5V, 1mW, 98dB Analog-Digital Converter - ContinuedCircuit Implementation:
Capacitor ValuesCapacitor Integrator 1 Integrator 2 Integrator 3 Integrator 4
Cs 5.00pF 0.15pF 0.30pF 0.10pFCi 15.00pF 1.25pF 3.00pF 1.00pFCa - - 0.05pF -
Cb1 - - - 0.12pFCb2 - - - 0.10pF Fig.10.9-25
1
1d
2
2d
Lecture 400 – Oversampling ADCs – Part II (3/29/10) Page 400-7
CMOS Analog Circuit Design © P.E. Allen - 2010
1.5V, 1mW, 98dB Analog-Digital Converter - ContinuedMicrophotograph of the modulator.
Lecture 400 – Oversampling ADCs – Part II (3/29/10) Page 400-8
CMOS Analog Circuit Design © P.E. Allen - 2010
1.5V, 1mW, 98dB Analog-Digital Converter - ContinuedMeasured SNR and SNDR versus input level of the modulator.
Lecture 400 – Oversampling ADCs – Part II (3/29/10) Page 400-9
CMOS Analog Circuit Design © P.E. Allen - 2010
1.5V, 1mW, 98dB Analog-Digital Converter - ContinuedMeasured baseband spectrum for a -7.5dBr 1kHz input.
Lecture 400 – Oversampling ADCs – Part II (3/29/10) Page 400-10
CMOS Analog Circuit Design © P.E. Allen - 2010
1.5V, 1mW, 98dB Analog-Digital Converter - ContinuedMeasured baseband spectrum for a -80dBr 1kHz input.
-80 dBr, 1 kHz signalVREF = 1.5 V (diff.)2048-point FFT
frequency, (kHz)
Lecture 400 – Oversampling ADCs – Part II (3/29/10) Page 400-11
CMOS Analog Circuit Design © P.E. Allen - 2010
1.5V, 1mW, 98dB Analog-Digital Converter - ContinuedMeasured 4th-Order Modulator Characteristics:
Table 5.4
Measured fourth-order delta-sigma modulator characteristics
Technology : 0.5 μm triple-metal single-poly n-well CMOS process
Supply voltage 1.5 V
Die area 1.02 mm x 0.52 mm
Supply current 660 μA
analog part 630 μA
digital part 30 μA
Reference voltage 0.75V
Clock frequency 2.8224MHz
Oversampling ratio 64
Signal bandwidth 20kHz
Peak SNR 89 dB
Peak SNDR 87 dB
Peak S/D 101dB
HD @ -5dBv 2kHz input -105dBv
DR 98 dB
3
Lecture 400 – Oversampling ADCs – Part II (3/29/10) Page 400-12
CMOS Analog Circuit Design © P.E. Allen - 2010
DECIMATION AND FILTERINGDelta-Sigma ADC Block DiagramThe decimator and filterare implemented digitallyand consume most of thearea and the power.Function of the decimatorand filter are;
1.) To attenuate thequantization noise above the baseband
2.) Bandlimit the input signal3.) Suppress out-of-band spurious signals and circuit noise
Most of the ADC applications demand decimation filters with linear phasecharacteristics leading to the use of finite impulse response (FIR) filters.FIR filters:
For a specified ripple and attenuation,
Number of filter coefficients fsft
where fs is the input rate to the filter (clock frequency of the quantizer) and ft is thetransition bandwidth.
Fig.10.9-07
ΔΣ Modulator(Analog)
Decimator(Digital)
Lowpass Filter(Digital)
fS fD<fS
AnalogInputx(t)
fB 2fB DigitalPCM
Lecture 400 – Oversampling ADCs – Part II (3/29/10) Page 400-13
CMOS Analog Circuit Design © P.E. Allen - 2010
A Multi-Stage Decimation FilterTo reduce the number of stages, the decimation filters are implemented in several stages.Typical multi-stage decimation filter:
Fig.10.9-26
L+1-th order
fs fs/D 2fN fN
First-halfband filter
Second-halfband filter
fN
Droopcorrection
1.) For modulators with (1-z-1)L noise shaping comb filters are very efficient.• Comb filters are suitable for reducing the sampling rate to four times the Nyquist
rate.• Designed to supress the quantization noise that would otherwise alias into the
signal band upon sampling at an intermediate rate of fs1.
2.) The remaining filtering is performed by in stages by FIR or IIR filters.• Supresses out-of-band components of the signal
3.) Droop correction - may be required depending upon the ADC specifications
Lecture 400 – Oversampling ADCs – Part II (3/29/10) Page 400-14
CMOS Analog Circuit Design © P.E. Allen - 2010
Comb FiltersA comb filter that computes a running average of the last D input samples is given as
y[n] = 1D
i = 0
D - 1
x[n-i]
where D is the decimation factor given as
D = fsfs1
The corresponding z-domain expression is,
HD(z) = i = 1
D
z-i = 1D
1 - z-D
1 - z-1
The frequency response is obtained by evaluating HD(z) for z = ej2 fTs,
HD(f) = 1D
sin fDTssin fTs
e-j2 fTs/D
where Ts is the input sampling period (=1/fs). Note that the phase response is linear.
For an L-th order modulator with a noise shaping function of (1-z-1)L, the requirednumber of comb filter stages is L+1. The magnitude of such a filter is,
|HD(f)| = 1D
sin fDTssin fTs
K
Lecture 400 – Oversampling ADCs – Part II (3/29/10) Page 400-15
CMOS Analog Circuit Design © P.E. Allen - 2010
Magnitude Response of a Cascaded Comb FilterK = 1,2 and 3
Fig.10.9-27
-100
-80
-60
-40
-20
0
Frequency
K = 1
K= 2
0 fb4 fsD
3 fsD
2 fsD
fsD
K = 3
|HD
(f)|
dB
Lecture 400 – Oversampling ADCs – Part II (3/29/10) Page 400-16
CMOS Analog Circuit Design © P.E. Allen - 2010
Implementation of a Cascaded Comb FilterImplementation:
Fig.10.9-28
-
+z-1
-
+z-1
-
+z-1
fs/D
K = L +1 Integrators
Numerator Section
z-1
+
-z-1
+
-z-1
+
-
X
Y
K = L +1 Differentiators
Denominator Section
Comments:1.) The L+1 integrators operating at the sampling frequency, fs, realize the denominator
of HD(z).2.) The L+1 differentiators operating at the output rate of fs1 (= fs/D) realize the
numerator of HD(z).
3.) Placing the integrator delays in the feedforward path reduces the critical path fromL+1 adder delays to a single adder delay.
Lecture 400 – Oversampling ADCs – Part II (3/29/10) Page 400-17
CMOS Analog Circuit Design © P.E. Allen - 2010
Implementation of Digital Filters†
Digital filter structures:
Fig.10.9-29
x(n) h(0) y(n)
Input Output
z-1h(1)
z-1h(2)
z-1h(3)
z-1h(N-1)
x(n)h(0)y(n)
InputOutput
z-1h(1)
z-1h(2)
z-1h(3)
z-1h(N-1)
Direct-form structure for an FIR digital filter.
Transposed direct-form FIR filter structure.
† S.R. Norsworthy, R. Schreier, and G.C. Temes, Delta-Sigma Data Converters-Theory, Design, and Simulation, IEEE Press, NY, Chapter 13, 1997.
Lecture 400 – Oversampling ADCs – Part II (3/29/10) Page 400-18
CMOS Analog Circuit Design © P.E. Allen - 2010
Digital Lowpass FilterExample of a typical digital filter used in removal of the quantization noise at higherfrequencies
-110
-80
-50
-20
10
4000 Frequency (Hz)
Mag
nitu
de (
dB)
Lecture 400 – Oversampling ADCs – Part II (3/29/10) Page 400-19
CMOS Analog Circuit Design © P.E. Allen - 2010
Illustration of the Delta-Sigma ADC in Time and Frequency Domain
MODULATOR
DECIMATORLOW-PASS
FILTERanalog input
fDfS
2fB
digital PCM
fB
TimeTime
Frequency FrequencyFrequency
Lecture 400 – Oversampling ADCs – Part II (3/29/10) Page 400-20
CMOS Analog Circuit Design © P.E. Allen - 2010
BANDPASS DELTA-SIGMA MODULATORSBandpass ModulatorsBlock diagram of a bandpass modulator:
Components:• Resonator - a bandpass filter of order
2N, N= 1, 2,....• Coarse quantizer (1 bit or multi-bit)The noise-shaping of the bandpass oversampled ADC has the following interestingcharacteristics:
Center frequency = fs ·(2N-1)/4
Bandwidth = BW = fs /M
Illustration of the Frequency Spectrum(N=1):
Application of the bandpass ADC isfor systems with narrowband signals (IF frequencies)
Fig.10.9-27A
-
+Resonator A/D
D/A
x
u
v y
Quantizer
fS
Frequency3fs4
fs4
fs
BW BW
dB
Attenuation
0Fig. 11-32
Lecture 400 – Oversampling ADCs – Part II (3/29/10) Page 400-21
CMOS Analog Circuit Design © P.E. Allen - 2010
A First-Order Bandpass ModulatorBandpass Resonator:
V(z) = z-1 [X(z) - z-1V(z)] = z-1X(z) - z-2V(z)
V(z) (1+z-2) = z-1X(z)V(z)X(z) =
z-1
1+z-2
Modulator:
Y(z) = Q(z) + [X(z) - Y(z)] z-1
1+z-2
Y(z) = 1+z-2
1+ z-1-z-2Q(z) +
z-1
1+ z-1-z-2X(z)
NTFQ (z) = 1+z-2
1+ z-1-z-2
The NTFQ (z) has two zeros on the j axis.
z-1
z-1
ΣX(z) V(z)+
-
Fig. 10.9-27C
Fig.10.9-27B
-
+ z-1 +X(z)
Q(z)
Y(z)
1+z-2
Lecture 400 – Oversampling ADCs – Part II (3/29/10) Page 400-22
CMOS Analog Circuit Design © P.E. Allen - 2010
Resonator DesignResonators can be designed by applying a lowpass to bandpass transform as follows:
z-1ΣX(z) V(z)+
+
Fig. 10.9-27D
z-2ΣX(z) V(z)+
+
Replace z-1 by -z-2
1 - z-1z-1
1 + z-2-z-2
Result:• Simple way to design the resonator• Inherits the stability of a lowpass modulator• Center frequency located at fs/4
Lecture 400 – Oversampling ADCs – Part II (3/29/10) Page 400-23
CMOS Analog Circuit Design © P.E. Allen - 2010
Fourth-Order Bandpass ModulatorBlock diagram:
ΣX(z) Y(z)+
-
Fig. 10.9-27E
1 + z-2z-2
0.5 Σ+
+ 1 + z-2z-2
0.5
Comments:• Designed by applying a lowpass to bandpass transform to a second-order lowpass
modulator• The stabilty and SNR characteristics are the same as those of a second-order lowpass
modulator• The z-domain output is given as,
Y(z) = z-4X(z) + (1+z-2)2Q(z)• The zeros are located at z = ±j which corresponds to notches at fs/4.
Lecture 400 – Oversampling ADCs – Part II (3/29/10) Page 400-24
CMOS Analog Circuit Design © P.E. Allen - 2010
Resonator Circuit Implementation
Block diagram of z-2/(1+z-2):
z-1 z-1ΣX(z) V(z)+
+
Fig. 10.9-27FFully differential switch-capacitor implementation:
Lecture 400 – Oversampling ADCs – Part II (3/29/10) Page 400-25
CMOS Analog Circuit Design © P.E. Allen - 2010
Power Spectral Density of the Previous Fourth-Order Bandpass ModulatorSimulated result:
Lecture 400 – Oversampling ADCs – Part II (3/29/10) Page 400-26
CMOS Analog Circuit Design © P.E. Allen - 2010
DELTA-SIGMA DIGITAL-TO-ANALOG CONVERTERSPrinciplesThe principles of oversampling and noise shaping are also widely used in theimplementation of DACs.Simplified block diagram of a delta-sigma DAC:
Digitaldelta-sigmamodulator
Interpolat-ion filter
Analoglowpass
filterDAC
N-bit
MfN
N-bit
fN
1-bit
MfN MfN
Input
Digital Section Analog Section
Output
Fig10.9-29
Operation:1.) A digital signal with N-bits with a data rate of fN is sampled at a higher rate of MfN by
means of an interpolator.2.) Interpolation is achieved by inserting “0”s between each input word with a rate of
MfN and then filtering with a lowpass filter.
3.) The MSB of the digital filter is applied to a DAC which is applied to an analoglowpass filter to achieve the analog output.
Lecture 400 – Oversampling ADCs – Part II (3/29/10) Page 400-27
CMOS Analog Circuit Design © P.E. Allen - 2010
Block Diagram of a DAC
AnalogOutput-
+Interpol-ation
DigitalFilter
Digital Code Conversion
0→100000000000000 =-11→011111111111111 = 1
VRef
-VRef
DigitalInput
fN
fS=MfNfS
fS
fS
AnalogLowpass
Filter
MSB
DAC
fS fS
Fig10.9-31
y(k)
Operation:1.) Interpolate a digital word at the conversion rate of the converter (f
N) up to the sample
frequency, fs.2.) The word length is then reduced to one bit with a digital sigma-delta modulator.3.) The one bit PDM signal is converted to an analog signal by switching between two
reference voltages.4.) The high-frequency quantization noise is removed with an analog lowpass filter
yielding the required analog output signal.Sources of error: • Device mismatch (causes harmonic distortion rather than DNL or INL) • Component noise • Device nonlinearities • Clock jitter sensitivity • Inband quantization error from the - modulator
Lecture 400 – Oversampling ADCs – Part II (3/29/10) Page 400-28
CMOS Analog Circuit Design © P.E. Allen - 2010
Frequency Viewpoint of the DACFrequency spectra at different points of the delta-sigma ADC:
Frequency0Interpolationfilter output
Delta-sigmamodulator
output
Lowpassfilter
output
Input
Magnitude
Quantization noise after filtering
-0.5fN 0.5fN fN (M-1)fN MfN
FrequencyMfN0-0.5fN 0.5fN
FrequencyMfN0-0.5fN 0.5fN
FrequencyMfN0-0.5fN 0.5fNFig10.9-33
Lecture 400 – Oversampling ADCs – Part II (3/29/10) Page 400-29
CMOS Analog Circuit Design © P.E. Allen - 2010
A Third-Order, Modulator for a DACA digital equivalent of the third-order MASH modulator is shown below.
X
Y
X+Y
Latch
Σ
Over-flow
X+Y
Latch
Σ
Over-flow
X+Y
LatchOver-flow
z-1z-1
+ + ++
− −
Clk
Clk
Clk8-stateOutput
DigitalInputs
070521-01
The m-bit accumulators consist of an m-bit adder and m-bit latches.The 8-state digital output is converted to an analog through means of an analog filter.Spectral outputs:
Lecture 400 – Oversampling ADCs – Part II (3/29/10) Page 400-30
CMOS Analog Circuit Design © P.E. Allen - 2010
1-BitDAC for the Digital-to-Analog Converter - The Analog PartThe MSB output from the digital filter is used to drive a 1-bit DAC.Possible architectures:
-VRef
φ1y(k) φ2
y(k)
VRef
φ1y(k)
C R
Analog lowpass
filter with -3dB frequency of 0.5fN
AnalogOutputR
C
φ2
φ2y(k)
Analog lowpass
filter with -3dB
frequency of 0.5fN
AnalogOutput
IRef
-IRef
Voltage-driven DAC with apassive lowpass filter stage.
Current-driven DAC with apassive lowpass filter stage.
Fig10.9-32
A multi-bit output would consist of more parallel, controlled current sources and sinks.
Lecture 400 – Oversampling ADCs – Part II (3/29/10) Page 400-31
CMOS Analog Circuit Design © P.E. Allen - 2010
Switched-Capacitor DAC and FilterTypically, the DAC and the first stage of the lowpass filter are implemented usingswitched-capacitor techniques.
-VRef
φ1y(k)
VRef
φ1y(k)
φ2+-φ2
φ1
C1
C2
R
To analoglowpass
filter
Fig10.9-34
It is necessary to follow the switched-capacitor filter by a continuous time lowpass filterto provide the necessary attenuation of the quantization noise.
Lecture 400 – Oversampling ADCs – Part II (3/29/10) Page 400-32
CMOS Analog Circuit Design © P.E. Allen - 2010
SUMMARYComparison of the Various Types of ADCs
A/D Converter Type MaximumPractical Number
of Bits (±1)
Speed(Expressed in termsof T a clock period)
Area Dependenceon the number ofbits, N, or otherADC parameters
Dual Slope 12-14 bits 2(2NT) IndependentSuccessive Approximationwith self-correction
12-15 bits NT N
1-Bit Pipeline 10 bits T (After NT delay ) NAlgorithmic 12 bits NT IndependentFlash 6 bits T 2NTwo-step, flash 10-12 bits 2T 2N/2Mulitple-bit, M-pipe 12-14 bits MT 2N/M
- Oversampled (1-bit, Lloops and M= oversamplingratio = f clock/2fb) 15-17 bits MT L
Lecture 400 – Oversampling ADCs – Part II (3/29/10) Page 400-33
CMOS Analog Circuit Design © P.E. Allen - 2010
Comparison of Recent ADCsResolution versus conversion rate:
5
10
15
20
25
Out
put w
ord
leng
th
Conversion rate, (samples/sec.)1 102 104 106 108 1010
Figure 10.10-1
FlashPipelinedAlgorithmic
Dual-slopeDelta-sigma
Successive approximation
Folding/InterpolatingBandpass delta-sigma
Lecture 400 – Oversampling ADCs – Part II (3/29/10) Page 400-34
CMOS Analog Circuit Design © P.E. Allen - 2010
Comparison of Recent ADCs - ContinuedPower dissipation versus conversion rate:
Figure 10.10-2
0.01
0.1
1
10
100
1000
1 100 10 4 10 6 10 8 10 10
Pow
er D
issi
patio
n (m
W)
Conversion Rate (Samples/second)
FlashPipelined
Delta-sigmaSuccessive approximation
Folding/InterpolatingBandpass delta-sigma
Lecture 400 – Oversampling ADCs – Part II (3/29/10) Page 400-35
CMOS Analog Circuit Design © P.E. Allen - 2010
References for Previous Figures [1] A 12-b, 60-MSample/s Cascaded Folding and Interpolating ADC. Vorenkamp, P., IEEE J-SC, vol. 32, no. 12, Dec 97 1876
1886 [2] A 15-b, 5-Msample/s Low-Spurious CMOS ADC. Kwak, S. -U., IEEE J-SC, vol. 32, no. 12, Dec 97 1866-1875 [3] Error Suppressing Encode Logic of FCDL in a 6-b Flash A/D Converter. Ono, K., IEEE J-SC, vol. 32, no.9, Sep 97 1460-
1464 [4] A Cascaded Sigma-Delta Pipeline A/D Converter with 1.25 MHz Signal Bandwidth and 89 dB SNR. Brooks, T. L., IEEE
J-SC, vol.32, no.12, Dec 97 1896-1906 [5] A 10-b, 100 MS/s CMOS A/D Converter. Kwang Young Kim, IEEE J-SC, vol. 32, no. 3, Mar 97 302-311 [6] A 1.95-V, 0.34-mW, 12-b Sigma-Delta Modulator Stabilized by Local Feedback Loops. Au, S., IEEE J-SC, vol. 32, no. 3,
Mar 97 321-328 [7] A 250-mW, 8-b, 52Msamples/s Parallel-Pipelined A/D Converter with Reduced Number of Amplifiers. Nagaraj, K., IEEE J
SC, vol. 32, no. 3, Mar 97 312-320 [8] A DSP-Based Hearing Instrument IC. Neuteboom, H., IEEE J-SC, vol. 32, no. 11, Nov 97 1790-1806 [9] An Embedded 240-mW 10-b 50MS/s CMOS ADC in 1-mm2. Bult, K., IEEE J-SC, vol. 32, no. 12, Dec 97 1887-1895[10] Low-Voltage Double-Sampled Converters. Senderowicz, D., IEEE J-SC, vol. 32, no.12, Dec 97 1907-1919[11] Quadrature Bandpass Modulation for Digital Radio. Jantzi, S. A., IEEE J-SC, vol. 32, no. 12, Dec 97 1935-1950[12] A Two-Path Bandpass Modulator for Digital IF Extraction at 20 MHz. Ong, A. K., IEEE J-SC, vol. 32, no. 12, Dec 97
1920-1934[13] A 240-Mbps, 1-W CMOS EPRML Read-Channel LSI Chip Using an Interleaved Subranging Pipeline A/D Converter.
Matsuura, T., IEEE J-SC, vol. 33, no. 11, Nov 98 1840-1850[14] A 13-Bit, 1.4 MS/s Sigma-Delta Modulator for RF Baseband Channel Applications. Feldman, A. R., IEEE J-SC, vol. 33,
no. 10, Oct 98 1462-1469[15] Design and Implementation of an Untrimmed MOSFET-Only 10-Bit A/D Converter with –79-dB THD. Hammerschmied,
C. M., IEEE J-SC, vol. 33, no. 8, Aug 98 1148-1157[16] A 15-b Resolution 2-MHz Nyquist Rate ADC in a 1-μm CMOS Technology. Marques, A. M., IEEE J-SC, vol. 33, no.
7, Jul 98 1065-1075[17] A 950-MHz IF Second-Order Integrated LC Bandpass Delta-Sigma Modulator. Gao, W., IEEE J-SC, vol. 33, no. 5, May
98 723-732[18] A 200-MSPS 6-Bit Flash ADC in 0.6μm CMOS. Dalton, D., IEEE Transactions on Circuits and Systems II: Analog and
Digital Signal Processing, vol. 45, no. 11, Nov 98 1433-1444
Lecture 400 – Oversampling ADCs – Part II (3/29/10) Page 400-36
CMOS Analog Circuit Design © P.E. Allen - 2010
References - Continued[19] A 5-V Single-Chip Delta-Sigma Audio A/D Converter with 111 dB Dynamic Range. Fujimori, I., IEEE J-SC, vol. 32, no.
3, Mar 97 329-336[20] A 256 x 256 CMOS Imaging Array with Wide Dynamic Range Pixels and Column-Parallel Digital Output. Decker, S.,
IEEE J-SC, vol. 33, no.12, Dec 98 2081-2091[21] A 400 Msample/s, 6-b CMOS Folding and Interpolating ADC. Flynn, M., IEEE J-SC, vol. 33, no.12, Dec 98 1932-1938[22] An Analog Background Calibration Technique for Time-Interleaved Analog-to-Digital Converters. Dyer, K. C., IEEE J-SC,
vol. 33, no.12, Dec 98 1912-1919[23] A CMOS 6-b, 400-Msample/s ADC with Error Correction. Tsukamoto, S., IEEE J-SC, vol. 33, no.12, Dec 98 1939-1947[24] A Continuously Calibrated 12-b, 10-MS/s, 3.3-V ADC. Ingino, J. M., IEEE J-SC, vol. 33, no.12, Dec 98 1920-1931[25] A Delta-Sigma PLL for 14b, 50 ksamples/s Frequency-to-Digital Conversion of a 10 MHz FM Signal. Galton, I., IEEE J-
SC, vol. 33, no.12, Dec 98 2042-2053[26] A Digital Background Calibration Technique for Time-Interleaved Analog-to-Digital Converters. Fu, D., IEEE J-SC, vol. 33
no.12, Dec 98 1904-1911[27] An IEEE 1451 Standard Transducer Interface Chip with 12-b ADC, Two 12-b DAC’s, 10-kB Flash EEPROM, and 8-b
Microcontroller. Cummins, T., IEEE J-SC, vol. 33, no.12, Dec 98 2112-2120[28] A Single-Ended 12-bit 20 Msample/s Self-Calibrating Pipeline A/D Converter. Opris, I. E., IEEE J-SC, vol. 33, no.12, Dec
98 1898-1903[29] A 900-mV Low-Power A/D Converter with 77-dB Dynamic Range. Peluso, V., IEEE J-SC, vol. 33, no.12, Dec 98
1887-1897[30] Third-Order Modulator Using Second-Order Noise-Shaping Dynamic Element Matching. Yasuda, A., IEEE J-SC, vol.
33, no.12, Dec 98 1879-1886[31] R, G, B Acquisition Interface with Line-Locked Clock Generator for Flat Panel Display. Marie, H., IEEE J-SC, vol. 33,
no.7, Jul 98 1009-1013[32] A 25 MS/s 8-b - 10 MS/s 10-b CMOS Data Acquisition IC for Digital Storage Oscilloscopes. Kusayanagi, N., IEEE J-SC,
vol. 33, no.3, Mar 98 492-496[33] A Multimode Digital Detector Readout for Solid-State Medical Imaging Detectors. Boles, C. D., IEEE J-SC, vol. 33, no.5,
May 98 733-742[34] CMOS Charge-Transfer Preamplifier for Offset-Fluctuation Cancellation in Low Power A/D Converters. Kotani, K., IEEE J-
SC, vol. 33, no.5, May 98 762-769[35] Design Techniques for a Low-Power Low-Cost CMOS A/D Converter. Chang, Dong-Young, IEEE J-SC, vol. 33, no.8,
Aug 98 1244-1248
Lecture 400 – Oversampling ADCs – Part II (3/29/10) Page 400-37
CMOS Analog Circuit Design © P.E. Allen - 2010
CONCLUDING THOUGHTS• What is analog circuit design?
The complex process of creating circuit solutions using analog circuit techniques.• What is the analog integrated circuit design process?
The even more complex process of combining analog design with IC technologywhich includes electrical, physical and test design.
• What are the key principles, concepts and techniques for analog IC design?Key principles – Fundamental lawsKey concepts – Important relationships andideas
• How can the analog IC designer enhancecreativity and solve new problems in today’sindustrial environment?
Learn the key principles, concepts and techniques ofanalog circuit designLearn from mistakesLearn the technologyAlways try to understand the concept and operationof the circuit, never rely on a computer or someone else for this understanding
Technology changes but principles, concepts andtechniques remain the same.
Key techniques – Tools that allowsimplification or insight