Download - Project Mid Semester
Project Mid Semester Implementing a compressor in software
and decompression in hardware
Presents by - Schreiber Beeri
Yavich Alon
Guided by – Porian Moshe
11.1.2011
Reminder
142❤Compressed data
(Wireless)
Gym
132❤
170❤ 79❤
130❤ 127❤
Gym Control Room
Transmitter Compresses the dataReceiver extracts and displays
the data
Reminder (Cont.)
TOP ARCHITECTURE
VGA
Display
HostMatlab
UART RX
UART TX
Message
Decoder
RAM
MU
XMessage
Encoder
RAM DEC
Display Controlle
rRunLen Decoder
CRC
IS42S16400 SDRAM
SDRAM Controller
Arbiter
Mem Write
Mem Read
REGISTERS
Packet TX
Packet RX
Ext. Clk
PLL
ResetD’ bouncer
Ext. Reset
Sys.
ClkSys.
Rst
FPGA – Cyclone II
TXRX
VESA
115,200KBit/sec
800x600Done
Implemented,not
integratedUpdate
RequiredNot Implemented
MICRO ARCHITECTURE
DATA
Addr
DATA
COLOR
DATA
Data&Valid
Message Decoder
RAM
DEC
Mem Write
ArbiterSDRAM
Controller Mem Read
RunLen DecoderREGISTER
S
VGA Display
TX PACKPLLReset
Debouncer
Resets
SDARM
UART
Matlab
UART RXP
RAM Controlle
r
Display Controlle
r
FIFO(dual clock
)
UART TXP
REG Controlle
r
Addr REG
TYPE REG
CheckSum
Len REG
UART RXD
UART TXD from UART TX
VALID
DATA
REG CRC STATUS
CRC_ERR FROM MSG_DEC MP
REGS
RESE
T St
atus
REQ
VALIDCRC_ERR
DATA
WRE
N
WR_addr
RD_adress
Type
DATA
DATA
REQ
REQEN
EN
REQ
ACK
REQ
REQAdress
ACK VALI
D
DATA RX_R
DY to
M
EM R
EAD
RX_R
DY fr
om
MEM
REA
D
DATA
_RDY
to
MEM
REA
D
DATA
_RDY
from
M
EM R
EAD
REP
VALIDDATA
COLOR COL_
EN
DATA
RGB
UART TXD to UART TX
50MHZ
40MHZ (VESA)133MHZ (SDRAM)
1 bit8 bits
10 bits16 bits22 bits
Line legend
Data &
Control
Data &
Control
MSG_OK
Num Pixels
n_pi
x
40MHz
CheckSum & Valid
CRC Statu
s
FIFOFULL
EMPT
Y
DATA
&
Valid
REQ
Method of OperationProject Directory Structure
The work method established in the project was assisted with these tools:◦SVN◦Code review◦Coding Guidelines◦Excel assignment file
Excel assignment fileModel / IP / TB Assignments Responsibility Synthised
AlreadyStart Date Done Date / Expected Status
UART TX&RX Generator Beeri --- 16.11.2010 16.12.2010 DONE
UART RX
Delete HALFBIT_ST State, by counting until the middle of the bit Alon YES 17.11.2010 22.12.2010 DONE
Add '5' to sample_cnt at IDLE_ST Alon YES 6.1.2011 8.1.2011 Open
Fix drifting problem (2 stop bits are needed by Matlab to send correct value) Alon YES 22.12.2010 1.1.2011 Open
UART TX
Add 'data_valid' port from FIFO Alon
YES
24.12.2010 1.1.2011 DONE
Check if missing stop bit at special FIFO situation Beeri 6.1.2011 14.1.2011 Open
dout_i should be implemented using SR Alon 1.1.2011 20.10.2011 Open
Use ShiftRegister Alon 24.12.2010 1.1.2011 DONE
Use external FIFO Alon 27.11.2010 20.12.2010 DONE
UART TB Add many test to the regression Alon --- 27.11.2010 1.1.2011 Open
MessagePack Decoder
CRC - Change interface. WHEN waste too many logic Beeri
YES 19.11.2010
22.12.2010 DONE
Remove CRC output port Beeri 22.12.2010 DONE
Change blk_pos range to automatic function Beeri 1.1.2011 Open
init_sof_eof_proc : See how it looks like after synthesis, then consult about it with Moshe Beeri 22.12.2010 DONE
MessagePack Encoder
init_sof_eof_proc : See how it looks like after synthesis, then consult about it with Moshe Beeri
YES 27.11.2010
19.12.2010 DONE
Change blk_pos range to automatic function Beeri 1.1.2011 Open
Fix CRC Process Beeri 27.12.2011 DONE
Replace UART interface with FIFO interface Beeri 20.12.2010 DONE
UART&MP TB
Add Regresion to Macro File Beeri --- 20.12.2010 1.1.2011 OPEN
Re-run after UART and MP changes Beeri --- 20.11.2010 22.12.2010 Re-Opened
UART’s Test Bench
UART Generat
or
UART RX
Message Pack
Decoder
RAM
Message Pack
Encoder
CheckSum
UART TX
UART Comparat
or
FIFOCheckSum
This will be shown using Matlab and DE2 board
Maximum Current FrequencyAccording to Quartus Timing
Analyzer: 150MHz, in this implementation
Pin
Signal route through FPGA
Logic
Current Implemented IPsUART Rx, Tx
◦Noise-proof◦5-8 Data Bits◦Enable / Disable Parity Bit◦Odd / Even Parity Bit◦Parity & Stop bit Error◦System clock and UART transmission
clock is set by generic parameter
Start Bit
5-8 Data Bits
Stop Bit
Parity Bit (Optional
)
UART TX’s FSM
IDLE
TX
reset
fifo_empty p
os_c
nt =
dat
abits
+ p
arity
bit
+ 1
REGDATA
fifo_Din_Valid
not fifo_empty
1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 0 0 1 0 0 1 1 1 1 0 1 0 0 0 1 0 1 1 1 1 1 0 1 0 0 0 1 1 1 1 1 1 1 0 1 0 0 0 1 1 1 1 1 1 1 0 1 0 0 1 1 1 1 1 1 1 1 0 1 0 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Shift Register
Data – A2 Hexdout
Current Implemented IPsMessage Pack Encoder
◦Encodes a message from registers, RAM and CRC block
◦Generic block sizeMessage Pack Decoder
◦Decodes a message into registers, RAM, and compares CRC
◦Generic block size
Current Implemented IPsCheckSum Block
◦Calculates Signed / Unsigned Checksum
◦Generic input and output size◦Comfortable handshakedata_valid
reset_checksumreq_checksum
checksum_valid
Current Implemented IPsGeneric MUX
◦Generic input, selectorsGeneric Decoder
◦Generic selectors
Current Implemented IPsGeneric RAM
◦Generic input / output size (Under Development)
Generic FIFO◦Generic FIFO size, data width
SDRAM Controller◦IS42S16400 Model
Written in pure VHDL.Independent in the FPGA’s vendor
RAM – Different ImplementationsFirst Implementation:
Resources:8209 DFF8192 MUX
And more…
RAM – Different ImplementationsCurrent Implementation:
Resources:5 DFF4 MUX
1 Decoder2 Sync RAM
Din_validAddr_in
Addr_out_validAddr_out
Data_in
Dout_valid
Data_out
Current Implemented Simulation ModelsUART Generator
◦Generates UART transmission from text file
◦Generic UART parameters: Enable / Disable Parity bit Even / Odd parity bit Various transmission rates Generic delay between files transmission
UART Comparator◦Compares received UART transmission
to text file
Simulation MethodVarious Macro (DO) files, each
one execute the simulation with different generic parameter.
Validate wave against expected signals
Automatic software validation of actual data against expected data
UART Simulations:Pass/Fail
Description Test
Num
ODD/EVEN
PARITY
Deviation %
RX BAUD.
TX BAUD.
CLK MHz
Pass x x 0 115200 115200 133 1Pass x x 4 115200 110592 133 2Pass x x 5 115200 120960 133 3Fail x x 5 115200 109440 133 4Pass ODD V 0 115200 115200 133 5Pass ODD V 5 115200 109440 133 6Pass ODD V 5 115200 120960 133 7Pass EVEN V 0 115200 115200 133 8Pass EVEN V 4 115200 110592 133 9Pass EVEN V 5 115200 120960 133 10One Kbyte data transfer has been simulated
Pass/Fail
Description Test Num
ODD/EVEN
PARITY
Deviation %
RX BAUD.
TX BAUD.
CLK MHz
Pass x x 0 115200 115200
33 11
Pass x x 5 115200 109440
33 12
Pass x x 5 115200 120960
33 13
Fail x x 6 115200 108288
33 14
Pass ODD V 0 115200 115200
33 15
Pass ODD V 5 115200 109440
33 16
Pass ODD V 5 115200 120960
33 17
Pass EVEN V 0 115200 115200
33 18
Pass EVEN V 5 115200 109440
33 19
Pass EVEN V 5 115200 120960
33 20
UART Simulations (Cont.):
One Kbyte data transfer has been simulated
DocumentationsDone:
◦SDRAM Controller◦UART RX, TX
To do:◦MessagePack + Checksum◦RAM◦FIFO◦MUX◦Decoder
Schedule To do… Date Num.
Theoretical self-instruction 1.10 – 16.10 1
Run length algorithm implementation
17.10 – 23.10 2
SDRAM Controller implementation 24.10 – 30.10 3Architecture definition 31.10 – 15.11 4
Project Characterization presentation 16.11 5Full characterization of all blocks 17-1.12 6
Implement UART RX-MP & TB 2.12-8.12 7Implement UART TX-MP & TB 9-15.12 8
Prepare Mid. Presentation 16-27.12 9
Done
Done
Done
DoneDonePartia
lDoneDoneDone
Schedule To do… Date Num.
(1)Implement Display Controller & TB
(2)Update Debouncer
11.1-26.1 10
Exams!!! Prepare documentation to existing models, end of semester presentation, and final semester A
report
27.1-22.2 11
Present end of semester presentation
23.2 12