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CHAPTER 1
INTRODUCTION
1.1 Introduction
Now a days, RADAR system are widely used to detect obstacles. They are used to
detect enemy aircrafts; missiles, ships etc. and also they are used to determine the altitude of
planes and clouds from the ground, controlling of planes at airports, to record speed of the cars,
which exceed a specified limit, weather forecasts etc.
RADAR (Radio Detection And Ranging) is a way to detect and study far off targets by
transmitting a radio pulse in the direction of the target and observing the reflection of
the wave.
The idea is now to have this transmitted signal propagate to a target and receive the
scattered signal ,About the angle of target.
Its basically radio echo
Fig 1.1Basic concept of radar
In this system we are simulating the RADAR function with optical beam. We are
providing an IR transmitter and receiver in place of RF transmitter and receiver. If any object,
reflecting the IR rays back to receiver can be detected. This transmitter and receiver are placed
on rotating antenna to detect angle of the object.
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C program is used to receive the serial data and the object information on the
screen. Assembly program is used to control the micro controller.
1.2 BASIC BLOCK DIAGRAM
Fig 1.2 BLOCK DIAGRAM
1.3 CONCLUSION
A micro controller is used to supervise all these functions. All the peripherals like, stepper
motor, RS232, IR transmitter and receiver are interfaced to micro controller. Micro controller
rotates the stepper motor in specified angles and gets the feedback from IR receiver in that
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PC RS232
MICROCONTROLLER
ANTENA
IRTRANSMITER &RECEIVER
STEPPERDRIVE
STEPPERMOTOR
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position. This is sent to PC via serial port to indicate the object at that particular angle in the
monitor.
CHAPTER 2
FUNCTIONAL DESCRIPTION OF ROTATING ANTENNA
2.1 Introduction to Micro controller
Looking back into the history of microcomputers, one would first come across the
development of microprocessor that is the processing element, and later on the peripheral
devices. The three basic elements-the CPU, I/O devices and memory-have developed in
distinct directions. While the CPU has been the proprietary item, the memory devices fall into
general-purpose category and the I/O devices may be grouped somewhere in-etween.Micro controllers:
Fig 2.1: Block diagram of micro controller
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ALUTimer/Counter
I/OPort
I/OPort
InternalROM
Clockcircuit
Interruptcircuits
Register(s)
ccumulator
InternalRAM
Stack Pointer
Program Counter
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Figure shows the block diagram of a typical micro controller, which is a true
computer on a chip. The design incorporates all of the features in a microprocessor CPU
ALU, PC, SP, and registers. It also has added the other features needed to make a complete
computer. ROM, RAM, parallel I/O, serial I/O, counters and a clock circuit.
Like the microprocessor, the micro controller is a general purpose device that is
meant to read data, program limited calculations. The prime use of a micro controller is to
control the operation of a machine using a fixed program that is stored in ROM and that does
not change over the lifetime of the system.
The micro controller design uses a much more limited set of single and
double byte instructions, which are used to move code and data from internal memory to the
ALU. Many instructions are coupled with pins on the integrated circuit package; the pins are
programmable that is, capable of having several different functions depending on the wishes
of the programmer.
The micro controller is concerned with getting data from and to its own pins;
the architecture and instructions set are optimized to handle data in bit and byte size
2.2 Introduction about AT89C51
The 8051 Micro controller generic part number actually include a whole family of
micro controller that have numbers ranging from 8031 to 8751 and are available in
N-channel metal oxide silicon (NMOS) and complementary metal oxide silicon (CMOS)constructions in a variety of package types. The most popular micro controller is the 8031-core
manufacture by Intel. The 8031 contain to 16 bit timer /counters. The 8052 chips can be
substituted if a third timer /counter is needed. There are five interrupts available; two for timer
control, other for the serial port and two general purposes interrupt pins.
The AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4K
bytes of Flash erasable programmable read only memory (FLASH EPROM). The device is
manufactured using Atmels high-density nonvolatile memory technology and is compatible
with the industry-standard MCS-51 instruction set and pin out. The on-chip Flash allows the
program memory to be reprogrammed in-system or by a conventional nonvolatile memory
programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel
AT89C51 is a powerful microcomputer, which provides a highly flexible and cost-effective
solution to many embedded control applications.
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The AT89C51 provides 4k EPROM/ROM, 128 byte RAM and 32 I/O lines. It also
includes a universal asynchronous receiver-transmitter (UART) device, two 16-bit
timer/counters and elaborates interrupt logic. Lack of multiply and divide instructions which
had been always felt in 8-bit microprocessors/micro controllers, has also been taken care of in
the 89C51- Thus the 89C51 may be called nearly equivalent of the following devices on a
single chip: 8085 + 8255 + 8251 + 8253 + 2764 + 6116.
The AT89C51 has the following on-chip facilities:
4K bytes ROM (EPROM on 8751).
8-bit program counter (PC), data pointer (DPTR), program status word (PSW) and
stack pointer (SP).
Internal ROM or EPROM of 0 to 4K.
Internal RAM of 128 bytes.
Four register banks each containing 8 registers.
16-bytes, which may be addressed at bit level.
32 input-output port lines.
Two 16-bit timer/counters.
A full duplex serial data receiver/transmitter
Control registers: TCON, TMOD, SCON, PCON, IP and IE.
On-chip clock oscillator and power on reset circuitry.
In addition, the AT89C51 is designed with static logic for operation
down to zero frequency and supports to software selectable power saving modes.
The idle mode stops the CPU while allowing the RAM, timer/counters, serial port and
interrupts system to continue functioning. The power down mode saves the RAM contents but
freezes the oscillator disabling all other chip functions until the next hardware reset.
The 89C51 micro controller contains 34 general purposes or working
register. Two of these registers A and B hold the results of many instructions, particularly
mathematical and logical operations. The A register is used for many operations including
addition, subtraction, integer multiplication, division and Boolean bit manipulations. It is also
used for all data transfers between the micro controller and any external memory.
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Internal Block diagram
Fig 2.2 AT89C51 internal block diagram
The 89C51 can be configured to bypass, the internal 4k ROM and run solely with
external program memory. For this its external access (EA) pin has to be grounded, which
makes it equivalent to 8031. The program store enable (PSEN) signal acts as read pulse for
program memory. The data memory is external only and a separate RD* signal is available for
reading its contents.
Use of external memory requires that three of its 8-bit ports (out of four) are configured
to provide data/address multiplexed bus, high address bus and control signals related to
external memory use. The RXD (receive data) and TXD (transmit data) ports of UART also
appear on pins 10 and 11 of 8051 and 8031 respectively. One 8-bit port, which is bit
addressable are extremely used for control applications.
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The UART utilizes one of the internal timers for generation of baud rate. The crystal
used for generation of CPU clock has therefore to be chosen carefully. The 11.0596 MHz
crystals; available abundantly, can provide a baud rate of 9600.
These internal RAM utilizes the 256-byte address space and special function registers
(SFRs) array, which is separate from external data RAM space of 64k. The 00-7F space is
occupied by the RAM and the 80 - FF space by the SFRs. The 128 byte internal RAM has
been utilized in the following fashion:
00-IF: Used for four banks of eight registers of 8-bit each. The four banks may be selected by
software at any time during the program.
20-2F: The 16 bytes may be used as 128 bits of individually addressable locations.
These are extremely useful for bit-oriented programs.
30- 7F: This area is used for temporary storage, pointers and stack. On reset, the
stack starts at 08 and gets incremented during use.
The list of special function registers along with their hex addresses is given
Below
(I)AT89C51
Address
register
Address Port/Register
80 P0 (Port 0)
81 SP (stack pointer)
82 DPH (data pointer High)
83 DPL (data pointer Low)
88 TCON (timer control)
89 TMOD (timer mode)
8A TLO (timer 0 low byte)
8B TL1 (timer 1 low byte)
8C TH0 (timer 0 high byte)
8D TH1 (timer 1 high byte)90 P1 (port 1)
98 SCON (serial control)
99 SBUF (serial buffer)
A0 P2 (port 2)
A8 Interrupt enable (IE)
B0 P3 (port 3)
B8 Interrupt priority (IP)
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D0 Processor status word (PSW)
E0 Accumulator (ACC)
F0 B register
Table 2.2.1-AT89C51 Special function register(SFR)
Hardware details :
The on chip oscillator of 89C51 can be used to generate system clock. Depending upon
version of the device, crystals from 3.5 to 12 MHz may be used for this purpose. The system
clock is internally divided into 6 and the resultant time period becomes one processor cycle.
The instructions take mostly one or two processor cycles to execute, and very occasionally
three processor cycles. The ALE (address latch enable) pulse rate is 16th of the system clock,
except during access of internal program memory, and thus can be used for timing purposes.
AT89C51 Serial port pins
PIN ALTERNATE USE SFR
P3.ORXD Serial data input SBUF
P3.ITXD Serial data output SBUF
P3.2INTO External interrupt 0 TCON-1
P3.3INT1 External interrupt 1 TCON- 2
P3.4TO External timer 0 input TMOD
P3.5T1 External timer 1 input TMODP3.6WR External memory write pulse ---------
P3.7RD External memory read pulse ---- Table 2.2.2 AT89C51 serial port pinsThe two internal timers are wired to the system clock and pre scaling factor is decided
by the software, apart from the count stored in the two bytes of the timer control registers.
The reset input is normally low and taking it high resets the micro controller. In the
present hardware, a separate CMOS circuit has been used for generation of reset signal so that
it could be used to drive external devices as well.Writing the software
The 89C51 have been specifically developed for control applications. Out of 128 bytes
of internal RAM, 16 bytes have been organized in such a way that all the 128 bits associated
with this group may be accessed bit wise to facilitate their use for bit set/reset/test applications.
These are therefore extremely useful for programs involving individual logical operations.
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The 89C51 have instructions for bit manipulation and testing. Apart from these, it has
8-bit multiply and divide instructions, which may be used with advantage. The 89C51 has short
branch instructions for 'within page' and conditional jumps, short jumps and calls within 2k
memory space which are very convenient, and as such the controller seems to favor programs
which are less than 2k byte long. Some versions of 8751 EPROM devices have a security bit
which can be programmed to lock the device and then the contents of internal program
EPROM cannot be read.
Program counter and data pointer:
The micro controller contains two 16 bit registers, program counter (PC) and data
pointer (DPTR). Each is used to hold address of a byte in memory. Program instruction bytes
are fetched from location in memory that is addressed by the PC. The PC is automatically
incremented after every instruction is fetched. PC is the only register that does not have
internal address. The DPTR registers made up of two 8-bit register named DPH and DPI.The
DPTR is under the control of program instruction and can be specified by its 16- bit name
DPTR or by each individual byte name DPH and DPI.
Flags and program status word:
Flags are bit wise registers provided to store the results of certain program
instructions. Other instructions can test the conditions of the flag and make decisions
based on the flag states. The flags are grouped inside the PSW and the power control
(PCON) registers. The 89C51 has 4 mathematical flags which include carry (CF),
Auxiliary carry (AC),Over flow(OF) and Parity(P) and three general purpose user flags
which can be set to one or cleared to zero by the programmer.
Stack and stack pointer:
The stack refers to an area of internal RAM that is used in conjunction with certain
opcodes to store and retrieve data quickly. The 8-bit stack pointer (SP) register is used by
micro controller to hold an internal RAM address, that is called the top of the stack..
Central Processing Unit:
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By adding 3 more memory locations to a specific block that will have a built in
capability to multiply, divide, subtract, and move its contents from one memory location onto
another. The part, which is added in it, is called central processing unit (CPU). Its memory
locations are called registers.
Registers are therefore memory locations whose role is to help with performing various
mathematical operations or any other operations with data wherever data can be found. Look at
the current situation. We have two independent entities (memory and CPU), which are
interconnected, and thus any exchange of data is hindered, as well as its unctionality. If, for
example, we wish to add the contents of two memory locations and return the result again back
to memory, we would need a connection between memory and CPU. Simply stated, we must
have some way through data goes from one block to another.
Input-output pin The 32 Input/Output pins are arranged as four ports P0-P3 each
having eight pins.
2.3 Pin diagram of 89C51
2.3 Pin Description(89c51)
VCC
Supply voltage.
GND
Ground.
Port 0
Port 0 is an 8-bit open-drain bi-directional I/O port. As an output port, each pin can
sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high
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impedance inputs. Port 0 may also be configured to be the multiplexed low order address/data
bus during accesses to external program and data memory. In this mode P0 has internal pull-
ups. Port 0 also receives the code bytes during Flash programming, and outputs the code bytes
during program verification. External pull-ups are required during program verification.
Port 1
Port 1 is an 8-bit bi-directional I/O port with internal pull-ups The Port 1 output buffers
can sink/source four TTL inputs. When 1s are written to Port 1 pins they are pulled high by the
internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being
pulled low will source current (IIL) because of the internal pull-ups. Port 1 also receives the
low-order address bytes during Flash programming and verification.
Port 2Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 2 output
buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins they are pulled
high by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are
externally being pulled low will source current (IIL) because of the internal pull-ups. Port 2
emits the high-order address byte during fetches from external program memory and during
accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this
application, it uses strong internal pull-ups when emitting 1s. During accesses to external data
memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special
Function Register. Port 2 also receives the high-order address bits and some control signals
during Flash programming and verification.
Port 3
Port 3 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 3 output
buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins they are pulled
high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are
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externally being pulled low will source current (IIL) because of the pull-ups. Port 3 also serves
the functions of various special features of the AT89C51 as listed below: Port 3 also receives
some control signals for Flash programming and verification.
Table 2.3.:Reset port pins and alternate functions
RESET
Reset input. A high on this pin for two machine cycles while the oscillator is running resets thedevice.An internal diffused resistor to VSS permits a power-on reset using only an externalcapacitor to VCC.ALE/PROG
Address Latch Enable (ALE) output pulse for latching the low byte of the address during
accesses to external memory. This pin is also the program pulse input (PROG) during Flash
Programming. In normal operation ALE is emitted at a constant rate of 1/6the oscillator
frequency, and may be used for external timing or clocking purposes. Note, however, that one
pulse is skipped during each access to external Data Memory. If desired, ALE operation can be
disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a
MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-
disable bit has noEffect if the micro controller is in external execution mode.
PSEN
Program Store Enable (PSEN) is the read strobe to external program memory. When the
AT89C51 is executing code from external program memory, PSEN is activated twice each
machine cycle, except that two PSEN activations are skipped during each access to external
data memory.
EA/VPP
External Access Enable. EA must be strapped to GND in order to enable the device to fetch
code from external program memory locations starting at 0000H up to FFFFH. Note, however,
that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped
to VCC for internal program executions. This pin also receives the 12-volt programming
enable voltage
(VPP) during Flash programming, for parts that require 12-volt VPP.
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XTAL1
Input to the inverting oscillator amplifier and input to the internal clock operating circuit.
XTAL2
Output from the inverting oscillator amplifier.
Oscillator and clock circuit:
The heart of the micro controller is the crystal oscillator that generates the clock
pulses by which all internal operations are synchronized. Pins XTAL1 and XTAL2 are
provided for connection of the resonant network to form an oscillator.
The clock frequency F, establishes the smallest internal time within the micro
controller called the pulse time. The smallest internal time to accomplish any simple
instruction, or the part of complex instruction be the machine cycle.The time to execute the
instruction is obtained by
T inst = No of cycles x12d
Crystal frequency
Oscillator Characteristics
XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier,
which can be configured for use as an on-chip oscillator, as shown in Figure 1. Either a quartz
crystal or ceramic resonator may be used. To drive the device from an external clock source,
XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2. There are no
requirements on the duty cycle of the external clock signal, since the input to the internal
clocking circuitry
is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time
specifications must be observed.
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Fig 2.3.2:Specifying Quartz Crystals
This article explains in detail the specifications and characteristics of crystals and crystal
oscillators. It is extremely useful as an aid in specifying crystals and working with crystal
vendors. It covers every significant performance characteristics of crystals such as resonance
frequency, resonance mode, load capacitance, series resistance, holder capacitance, motional
Inductance and capacitance, and drive level.
Quartz crystals are available in a myriad of shapes and sizes, and can range widely in
performance specifications. These specifications include resonance frequency, resonance
mode, load capacitance, series resistance, holder capacitance, motional inductance and
capacitance, and drive level. Understanding these parameters and how they relate to the
crystal's performance will allow you to successfully specify crystals for your circuit
application.
A quartz crystal can be modeled as a series LRC circuit in parallel with a shunt capacitor.
Figure 1 shows this generic circuit model.
Now let's look at each key performance specification in detail.
Resonance Frequency
Crystals below 30MHz are often specified at the fundamental frequency, but above 30MHz
they are typically specified as 3rd, 5th, or even 7th overtone (overtones occur only at odd
multiples). It's important to know whether the oscillator is operating in fundamental or
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overtone mode. An overtone is similar in concept to a harmonic, with the exception that crystal
oscillation overtones are not exact integer multiples of the fundamental. Selection of overtone
is based upon using the lowest possible overtone that will result in a crystal fundamental
frequency below 30MHz. The vendor calibrates a 3rd overtone crystal at the 3rd overtone, not
the fundamental. For example, most crystal vendors will automatically give you a 3rd overtone
50MHz crystal if you don't specify fundamental mode or an overtone mode. If you plug a
50MHz 3rd overtone crystal into an oscillator that expects a fundamental-mode crystal, you are
likely to have an oscillator running at 50/3 or 16.666MHz! If you don't know the frequency
mode of your crystal, contact the designer or the manufacturer of the oscillator circuit.
The reason crystal vendors provide overtone crystals are that the quartz material becomes
thinner and thinner as frequency increases. Starting at about 30MHz, the quartz becomes sothin that it is hard to handle during the manufacturing process, and crystal vendors don't like to
deal with thin crystals. One recent innovation in this area is the invention of inverted mesa
crystals. Inverted mesa crystals can be manufactured with a thinner structure and thus can be
reliably manufactured at higher fundamental-mode frequencies. This makes for less complex
high-frequency oscillator designs and reduces component count by avoiding the need for
external inductors/capacitors to induce the proper overtone oscillation mode from the crystal.
Not all crystal vendors can provide inverted mesa technology; but, for the ones that can, they
will be able to specify fundamental-mode crystals considerably higher than 30MHz. Remember
that an overtone-mode crystalcannot be used in a fundamental-mode oscillator, and vice versa.
It may oscillate but not at the correct frequency.
Resonance Mode
Crystals have two modes of resonance:paralleland series. All crystals exhibit both resonance
modes. The oscillator circuit is calibrated for one or the other, but not both. For applications
requiring no tighter than 100ppm frequency accuracy, this spec is usually not an issue.
However, if you are attempting to control frequency (or time) to within 100ppm, the
resonance-mode specification becomes important. The difference to the crystal vendor is in
which mode the crystal is calibrated during manufacturing. The crystal vendor sets up an
oscillator circuit with the crystal in a customer-specified series resonance or parallel resonance
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and calibrates the crystal. Figure 2 shows crystal impedance behavior versus frequency as well
as the relative location of each resonance mode.
Counters and Timers:
Two 16 bit microprocessor counters named T0 and T1 are provided for the
general use of the programmer. Each counter may be programmed to count internal clock
pulses acting as a timer or programmed to count external pulses as counter. The counters are
divided into two 8-bit registers called the timer low (TL0, TL1) and high (TH0, TH1) bytes.
All counter action is controlled by bit states in the time mode control register (TMOD), the
timer/counter control register (TCON) and certain program instructions.
TMOD is dedicated solely to the two timers and can be considered to be two
duplicate four bit registers each of which controls the action of one of the TCON has control
bits and flags for timers in upper nibble and for timers external interrupts in lower nibble.
Serial data Input/Output:
Onecost effective way to communicate with other computers is to send and receive data bits
serially. The 89C51 has a serial data communication circuit but uses register SBUF to hold
data. Register SCON controls data communication and register PCON controls data rates and
pins RXD (P3.0) and TXD(P3.1) connect to the serial data network. SBUF is physically two
registers. One is write only and used to hold data to be transmitted out of the micro controller
using TXD. The other is read only and hold- receive data from external sources using RXD.
Interrupt
Interrupts may be generated by the internal chip operations or provided by external
sources. Five interrupts are provided in the 89C51.Internal operations timer flag0, timer flag1
and the serial port generate three of these automatically interrupt (R1 or T1). Two interrupts are
triggered by external signals provided by circuitry which are connected to pins INT0 and INT1.
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2.4PowerSupply
Fig 2.4 power
supply
Power supply unit provides 5V regulates power supply to the systems. It
consists of two parts namely,
1. Rectifier
2. Monolithic voltage regulator
Rectifier
Here the step down transformer 230-0v/12-0-12V gives the secondary current up to
500mA, to the Rectifier. The secondary Transformer is provided with a center tap. Hence the
voltage V1 and V2 are equal and are having a phase difference of 180 0. So it is anode of Diode
D1 which is positive with respect to the center tap, the anode of the other diode d2 will be
negative with respect to the center tap. During the positive half cycle of the supply D1
conducts and current flows through the center tap D1 and load. During this period D2 will not
conduct as its anode is at negative potential. During the negative half cycle of the supply
voltage, the voltage on the diode D2 will be positive and hence D2 conducts. The current
flows through the transformer winding, Diode D2 and load. It is to be noted that the current i1
and i2 are flowing in the same direction in load.
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The average of the two current i1 and i2 flows through the load producing a voltage
drop, which is the D.C. output voltage of the rectifier. Using monolithic IC voltage regulators,
voltage can be regulated.
Monolithic IC voltage regulator:
A voltage regulator is a circuit that supplies a constant voltage regardless of changes in
load currents. Although voltage regulators can be designed using op-amps, it is quicker and
easier to use IC voltage regulators. Furthermore, IC voltage regulators are versatile and
relatively inexpensive and are available with features such as programmable output,
current/voltage boosting, internal short-circuit current limiting, thermal shutdown and floating
operation for high voltage applications
Here 7800 series voltage regulators are used. The 7800 series consists of 3-terminal
positive voltage regulators with seven voltage options. These ICs are designed as fixed voltage
regulators and with adequate heat sinking can deliver output currents in excess of 1A.
Although these devices do not require external components, such components can be used to
obtain adjustable voltages and currents. For proper operation a common ground between input
and output voltages is required. In addition, the difference between input and output voltages
(Vi Vo) called drop out voltage, must be typically 1.5V even during the low point as the
input ripple voltage. The capacitor Ci is required if the regulator is located at an appreciable
distance from a power supply filter. Even though Co is not needed, it may be used to improve
the transient response of the regulator.
Typical performance parameters for voltage regulators are line regulation, load
regulation, temperature stability and ripple rejection. Line regulation is defined as the change
in output voltage for a change in the input voltage and is usually expressed in milli volts or as a
percentage of Vo. Temperature stability or average temperature coefficient of output voltage
(TCVo) is the change in output voltage per unit change in temperature and is expressed in
either milli volts/C or parts per million (PPM/C). Ripple rejection is the measure of a
regulators ability to reject ripple voltage. It is usually expressed in decibels. The smaller the
values of line regulation, load regulation and temperature stability, gives better regulation.
2.5 Optical Transducer
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fig 2.5 IR Tx&Rx
IR transmitter:
IR transmitter is an optical transducer which converts electrical signals into IR rays.
This IR rays are transmitted into the space(in all directions) for sensing the presence of target.
IR receiver:
IR receiver is an optical transducer which converts IR rays into electrical signals. When
a target is intersected by emitted rays of the IR transmitter (RADAR antenna), a portion of
intersected rays are reflected back which is collected by IR receiver. This information is sent to
micro controller 89C51.Thus ensuring the presence of target in space.
2.6 Conclusion
In this chapter we explained working of microcontroller in this project and
their brief explaniation. Here also explained how we are giving power supply to this project
PCB layout and also explained brief story of power supply .the main pcb layout in this project
that is ir transmitter ir receiver how it tx & rx from a object.
CHAPTER 3
FUNCTIONAL DESCRIPTION OF MONITORING UNIT AT
SUBSTATION
3.1 PC interface section
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Fig 3.1 RS-232 Connecter diagram
The above shown connector known as 9-pin, D-type male connector is used for RS232
connections. The pin description is given in the following table.
Pin number CommonName
RS232name
Description Signaldirection
1 /CD CF Received line signal detector IN
2 RXD BB Received data IN
3 TXD BA Transmitted data OUT
4 /DTR CD Data terminal ready OUT
5 GND AB Signal ground --
6 /DSR CC Data set ready IN
7 /RTS CA Request to send OUT
8 /CTS CB Clear to send IN
9 -- CE Ring indicator INTable 3.1 RS-232 pin details
We cannot simply connect our system to this terminal with out providing proper hand
shaking signal. For communicating with RS-232 type equipment, the /RTS of the connector is
simply looped into the /CTS, so /CTS will automatically be asserted when /RTS is asserted
internally. Similarly the /DTR is looped into /DSR and /CD, so when PC asserts its /DTR
output the /DSR and /CD inputs are automatically be asserted. These connections do not
provide for any hardware hand shaking. They are necessary to get the PC and our system talk
each other. The connection diagram is shown below.
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12345
6789
Tx 3Rx 2
/CTS 8/RTS 7/DSR 6/DTR 4/CT 1
GND 5
2 Rx3 Tx
5 GND
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Fig 3.1 RS-232 Interface diagram
3.2 RS 232 serial interface
The MAX232 I.C convert input TTL level into RS-232C standard level and connected to
PC through 9-pin D-type connector. Now discuss about standards of RS232 and Serial
communication through RS232
MAX232 circuit diagram
Fig 3..2 RS-232 Circuit diagram
RS-232 logic levels are indicated by positive and negative voltages, rather than by the
positive-only signals of 5V TTL and CMOS logic. At an RS-232 data output (TD), a logic 0 is
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defined as equal to or more positive than +5V, and a logic 1 is defined as equal to or more
negative than 5V. In other words, the signals use negative logic, where the more negative
voltage is logic 1.
The control signals use the same voltages, but with positive logic. A positive voltage
indicates that the function is on, or asserted, and a negative voltage indicates that the function
is off, or not asserted.
RS-232 interface chips invert the signals. On a UARTs output pin, a logic-1 data bit or
an off control signal is near 5V, which results in a negative voltage at the RS-232 interface.
Logic 0 data bit or on control signal is near 0V, resulting in a positive voltage at the RS-232
interface. Because an RS-232 receiver may be at the end of a long cable, by the time the signal
reaches the receiver, its voltage may have attenuated or have noise riding on it. To allow for
this, the minimum required voltages at the receiver are less than at the driver. An input more
positive than +3V is a logic 0 at RD, or On at a control input. An input more negative than 3V
is a logic 1 at RD, or Off at a control input. According to the standard, the logic level of an
input between 3V and +3V is undefined.
The noise margin, or voltage margin, is the difference between the output and input
voltages. RS-232s large voltage swings result in a much wider noise margin than 5V TTL
logic. For example, even if an RS-232 drivers output is the minimum +5V, it can attenuate or
have noise spikes as large as 2V at the receiver and still be a valid logic 0. Many RS-232
outputs have much wider voltage swings: 9 and 12V are common. These in turn give much
wider noise margin. The maximum allowed voltage swing is 15V, though receivers must
handle voltages as high as 25V without damage.
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Two other terms used in relation to RS-232 are Mark and Space. Space is logic 0, and
Mark is logic 2. These refer to the physical marks and spaces made by the mechanical
recorders used years ago to log binary data.
TIA/EIA-232 includes both minimum and maximum timing specifications. All of the
many RS-232 interface chips meet these specifications. The specified slew rate limits the
maximum bit rate of the interface. Slew rate is a measure of how fast the voltage changes when
the output switches and describes an outputs instantaneous rate of voltage change. The slew
rate of an RS-232 driver must be 30 Volts per microsecond or less. The advantage of limiting
slew rate is that it improves signal quality by virtually eliminating problems due to voltage
reflections that occur on long links that carry signals. With fast rise and fall times. But the slew
rate also limits a links maximum speed. At 30 V/s, an output requires 0.3 microsecond to
switch from +5V to 5V. RS-232s specified maximum bit rate is 20 kbps, which translates to
a bit width of 50 microseconds, or 166 times the switching time at the fastest allowed slew rate.
In reality, because UARTs read inputs near the middle of the bit, and because most
timing references are very accurate, you can often safely use bit widths as short as 5 to 10
times the switching time. Taking these into account, some interface chips allow bit rates of 115
kbps and higher, even though this violates the standards recommendations. Besides having a
maximum switching speed, RS-232 drivers must also meet minimum standards to ensure that
signals dont linger in the undefined region between logic states. For the control signals and
other signals of 40 bps and lower, the line must spend no more than 1 millisecond in the
transition region between a valid logic 0 and logic 1. For other data and timing signals, the
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limit is 4% of a bit width, or 2 microseconds at 20 kbps. The signals rise and fall times should
also be as nearly equal as possible.
3.3 IRF540:
Main features of IRF540
Advanced Process Technology
Dynamic dv/dt Rating
175C Operating Temperature
Fast Switching
Fully Avalanche Rated
Fig 3.3 IRF540 symbol
Fifth Generation HEXFETs from International Rectifier utilize advanced
processing techniques to achieve the lowest possible on-resistance per silicon area. This
benefit, combined with the fast switching speed and rugged zed device design that HEXFET
Power MOSFETs are well known for, provides the designer with an extremely efficient device
for use in a wide variety of applications. The TO-220 package is universally preferred for all
commercial-industrial applications at power dissipation levels to approximately 50 watts. The
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low thermal resistance and low package cost of the TO-220 contribute to its wide acceptance
throughout the industry.
3.4 BC548:
This device is designed for use as general purpose amplifiers and switches requiring collector
currents to 300 mA. Sourced from Process 10.
. fig 3.4 transistor BC548
3.5 STEPPER MOTAR
3.5.1 Stepper motor drive circuit
Fig 3.5.1(i) STEPPER MOTOR DRIVE CIRCUIT
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When the output of the controller is high, the base current I flows in to base of the
transistor, thus providing voltage drop more then 0.7V across the Ve junction, thus the
transistor goes in to saturation mode. So the Ic is maximum and the voltage drop across the
Vce junction is zero. I.e. the input to MOSFET is zero. So the MOSFET will not conduct and
stepper motor coil will not energize.
If the output of the controller is low, the base current I is zero, thus providing voltage
drop less then 0.1V across the Ve junction, thus the transistor goes in to cut-off mode. So the
Ic is minimum and the voltage drop across the Vce junction is maximum. I.e. the input to
MOSFET is almost Vcc. So the MOSFET will conduct and stepper motor coil get energized.
is For driving of motor coils, we used IRF540 MOSFET, which are having low on-state
resistance so that the dissipation is less, fast switching and low thermal resistance. This
MOSFET is driven by BC548 transistor. For each motor four MOSFET sections are required.
CONNECTION FOR STEPPER MOTOR DRIVER:
For every output line we need one driver as shown in the below figure. These four
drivers are connected to the coils of the stepper motor .
3.5.2 INTRODUCTION TOSTEPPER MOTOR
Introduction
Stepper Motors have several features which distinguish them from AC Motors, and
DC Servo Motors.
Brushless
Steppers are brush less Motors with contact brushes create sparks, undesirable in
certain environments. (Space missions, for example.)
Holding Torque - Steppers have very good low speed and holding torque. Steppers are usually
rated in terms of their holding force (oz/in) and can even hold a position (to a lesser degree)
without power applied, using magnetic 'detent' torque.
Open loop positioning
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Perhaps the most valuable and interesting feature of a stepper is the ability to
position the shaft in fine predictable increments, without need to query the motor as to its
position. Steppers can run 'open-loop' without the need for any kind of encoder to determine
the shaft position. Closed loop systems- systems that feed back position information, are
known asservo systems. Compared to servos, steppers are very easy to control, the position of
the shaft is guaranteed as long as the torque of the motor is sufficient for the load, under all its
operating conditions.
Load Independent
The rotation speed of a stepper is independent of load, provided it has sufficient
torque to overcome slipping. The higher rpm a stepper motor is driven, the more torque it
needs, so all steppers eventually poop out at some rpm and start slipping. Slipping is usually a
disaster for steppers, because the position of the shaft becomes unknown. For this reason,
software usually keeps the stepping rate within a maximum top rate. In applications where a
known RPM is needed under a varying load, steppers can be very handy.
Types of steppers
Stepper Motors come in a variety of sizes, and strengths, from tiny floppy disk
motors, to huge machinery steppers rated over 1000 oz in. There are two basic types of
steppers-- bipolar and unipolar. The bipolar stepper has 4 wires. Unipolar steppers have 5,6 or
8 wires. This document will discuss control of Unipolar Steppers.
Motor Basics
The Unipolar Stepper motor has 2 coils, simple lengths of wound
wire. The coils are identical and are not electrically connected. Each coil has a center tap - a
wire coming out from the coil that is midway in length between its two terminals. You can
identify the separate coils by touching the terminal wires together-- If the terminals of a coil are
connected, the shaft becomes harder to turn. Because of the long length of the wound wire, it
has a significant resistance (and inductance). You can identify the center tap by measuring
resistance with a suitable ohm-meter (capable of measuring low resistance
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ohms/phase'indicates the resistance from center tap to either terminal of a coil. The resistance
from terminal to terminal should be 10 ohms.
Fig 3.5.2(ii)stepper motor coil diagram
Motor Control Circuitry
Fig 3.5.2(iii)magnetic field diagram
Current flowing through a coil produces a magnet field which attracts a
permanent magnet rotor which is connected to the shaft of the motor. The basic principle of
stepper control is to reverse the direction of current through the 2 coils of a stepper motor, in
sequence, in order to influence the rotor. Since there are 2 coils and 2 directions, that gives us
a possible 4-phase sequence. All we need to do is get the sequencing right and the motor will
turn continuously. You may wonder how the stepper can achieve such fine stepping increments
with only a 4-phase sequence. The internal arrangement of the motor is quite complex- the
winding and core repeating around the perimeter of the motor many times. The rotor is
advanced only a small angle, either forward or reverse, and the 4-phase sequence is repeated
many times before a complete revolution occurs.
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Fig 3.5.2(iv) stepper motor basic control diagram
Let us return to the 4-phase sequence of reversing the current though the 2
coils. A Bipolar stepper controller achieves the current reversal by reversing the polarity at the
two terminals of a coil. The Unipolar controller takes advantage of the center tap to achieve
the current reversal with a clever trick -- The Center tap is tied to the positive supply, and one
of the 2 terminals is grounded to get the current flowing one direction. The other terminal is
grounded to reverse the current. Current can thus flow in both directions, but only half coils
are energized at a time. Both terminals are never grounded at the same time, which would
energize both coils, achieving nothing but a waste of power.
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Conceptual Model of Unipolar Stepper Motor
Fig 3.5.2(v) conceptual model of unipolar stepper motor
With center taps of the windings wired to the positive supply, the terminals of
each winding are grounded, in sequence, to attract the rotor, which is indicated by the arrow in
the picture. (Remember that a current through a coil produces a magnetic field.) This
conceptual diagram depicts a 90-degree step per phase.
In a basic "Wave Drive" clockwise sequence, winding 1a is de-activated and winding 2a
activated to advance to the next phase. The rotor is guided in this manner from one winding to
the next, producing a continuous cycle. Note that if two adjacent windings are activated, the
rotor is attracted mid-way between the two windings.
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The following table describes 3 useful stepping sequences and their relative merits. The
sequence pattern is represented with 4 bits, a '1' indicates an energized winding. After the last
step in each sequence the sequence repeats. Stepping backwards through the sequence reverses
the direction of the motor.
Table of Stepping Sequences
Sequence Name Description
0001
0010
0100
1000
Wave
Drive,
One-Phase
Consumes the least power. Only one phase is energized at
a time. Assures positional accuracy regardless of any
winding imbalance in the motor.
0011
0110
1100
1001
Hi-
Torque,
Two-
Phase
Hi Torque - This sequence energizes two adjacent phases,
which offers an improved torque-speed product and
greater holding torque.
0001
0011
0010
0110
0100
1100
1000
1001
Half-Step Half Step - Effectively doubles the stepping resolution of
the motor, but the torque is not uniform for each step.
(Since we are effectively switching between Wave Drive
and Hi-Torque with each step, torque alternates each
step.) This sequence reduces motor resonance, which can
sometimes cause a motor to stall at a particular resonant
frequency. Note that this sequence is 8 steps.
Table3.5 Table of stepping sequences
Identifying Stepper Motors
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Fig 3.5.2(vi) stepper motor identification diagram
Stepper motors have numerous wires, 4, 5, 6, or 8. When you turn the shaft you will
usually feel a "notched" movement. Motors with 4 wires are probably bipolar motors and will
not work with a Unipolar control circuit. The most common configurations are pictured
above. You can use an ohm-meter to find the center tap - the resistance between the center anda leg is 1/2 that from leg to leg. Measuring from one coil to the other will show an open
circuit, since the 2 coils are not connected. (Notice that if you touch all the wires together,
with power off, the shaft is difficult to turn!)
Shortcut for finding the proper wiring sequence
Connect the center tap(s) to the power source (or current-Limiting resistor.) Connect
the remaining 4 wires in any pattern. If it doesn't work, you only need try these 2 swaps...
1 2 4 8 - (arbitrary first wiring order)
1 2 8 4 - switch end pair
1 8 2 4 - switch middle pair
You're finished when the motor turns smoothly in either direction. If the motor turns in the
opposite direction from desired, reverse the wires so that ABCD would become DCBA.
Heat Considerations
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Over-heating can be an early indicator of a problem or need for additional heat
sinking. This is true of both the controller and motors. Components can be warm to the touch,
but not so hot that you can't leave your finger on them for a few seconds.
Motors are designed to be mounted in such a way that, heat is drawn away from the motors.
This is usually accomplished with a metal mounting bracket. Motors that are not yet mounted
may require some type of temporary heat sinking. Motors heat more running at the LOW
speeds or in Hold Mode.
If a component or motor is running too hot, try using the Wave Drive stepping mode only, if it
still runs too hot, try heat sinking, and/or a fan. If it still runs too hot, something is wrong.
Above diagram indicate the connections for over all receiver block diagram. All
four driver will connect the four coils of stepper motor . Stepper motor coils will energized
depend upon the output bits which are coming out of the microcontroller . If bit is high the
coils will be energized other wise coils are not energized . Depend upon the bits , stepper
motor will rotate clockwise or anticlockwise direction.
3.6 Conclusion
In this chapter we explained about the transfer information what is detect object
from ir rx it can appear in pc we used rs232 i.e max 232 ic explanation and working in thisproject. And how the ir tx& rx cover the 360 degrees that means around place by controlling
the stepper motor with their stepper driver circuits here we explained all about stepper motor
working in this project which components are efficiently used for construction or controlling
stepper motor its also explained.
CHAPTER .4
SOURCE CODE
4.1Assembling Language Programming Description
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TITLE : RADAR SIMILATION WITH OPTICAL SENSOR
TARGET : AT89S51
VERSION : VER-01
STARTED : 05-06-2009
------------------------------------------------------------------------------------------------------------
;> INCLUDES :
$MOD51
;-----------------------------------------------------------------------------------------------------------
;> HARD WARE DETAILS :
;> MOTOR CONTROL - P0.0 TO P0.3
;> COMMUNICATION O.K. IND - P1.7
COK BIT P1.7
;> I.R.FEED BACK - P3.2
IRF BIT P3.2
;> SLOT SENSOR FEEDBACK - P1.0
SFB BIT P1.0
;----------------------------------------------------------------------------------------------------------
;> FLAGS :
SEND_ANG BIT 00H
MOT_DIR BIT 02H
;-----------------------------------------------------------------------------------------------------------
;> VARIABLES :
STEP_CNT DATA 30H
ANGL_CNT DATA 31H
MOT_FB DATA 32H
ROT_CNT1 DATA 33H
ROT_CNT2 DATA 34H
;----------------------------------------------------------------------------------------------------------
;> VECTOR ADDRESESS:
ORG 0000H
ljmp INITIALISATION
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ORG 000BH
reti
ORG 0023H ; serial interrupt
push ACC
push PSW
jbc RI, RECEIVE_DATA
ajmp SKIP_CHKS
RECEIVE_DATA:
mov MOT_FB, SBUF
setb SEND_ANG
SKIP_CHKS:
pop PSW
pop ACC
reti
;-----------------------------------------------------------------------------------------------------------
INITIALISATION:
mov P0, #0FFH
mov P1, #0FFH
mov P2, #0FFH
mov P3, #0FFH
mov SP, #65H
mov DPTR, #0400H
mov TMOD, #21Hanl pcon, #7fh ; set smod
mov th1, #0fdh ; set TH1 for 9600 rate.
mov scon, #050h ; set MODE 3, REN, TB8, TI. Clr SM2.
mov IE, #90H
setb TR1
mov STEP_CNT, #00h
lcall BRING_HOME
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mov ANGL_CNT, #00H
mov SBUF, #0AAH
CHAN0: jnb TI, CHAN0
clr TI
;-----------------------------------------------------------------------------------------------------------
MAIN:
jb IRF, ON_IR_IND
clr P1.6
ON_IR_IND:
jnb IRF, OFF_IR_IND
setb P1.6
OFF_IR_IND:
inc ROT_CNT1
mov A, ROT_CNT1
cjne A, #00H, SKIP_CY_CNT
inc ROT_CNT2
mov A, ROT_CNT2
SKIP_CY_CNT:
mov A, ROT_CNT2
cjne A, #01H, CP_REV_CNT1
mov A, ROT_CNT1
cjne A, #8FH, CP_REV_CNT1
CP_REV_CNT1:
jc CP_REV_CNT
jnb MOT_DIR, CP_REV_CNT2
lcall BRING_HOME
CP_REV_CNT2:
cpl MOT_DIR
mov ROT_CNT2, #00H
mov ROT_CNT1, #00H
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CP_REV_CNT:
jb MOT_DIR, MOVE_MOT_FD
lcall MOVE_FRWD
lcall DLY2
MOVE_MOT_FD:
jnb MOT_DIR, MOVE_MOT_BD
lcall MOVE_REV
lcall DLY2
MOVE_MOT_BD:
xrl P1, #08H
jnb IRF, SEND_NO_INT
mov A, #05H
mov C, MOT_DIR
mov ACC.7, C
mov SBUF, A
CHAN1: jnb TI, CHAN1
clr TI
SEND_NO_INT:
jb IRF, SEND_INT
mov A, #0AH
mov C, MOT_DIR
mov ACC.7, C
mov SBUF, A
CHAN2: jnb TI, CHAN2
clr TI
SEND_INT:
DONT_SEND_INF:
ljmp MAIN
;-----------------------------------------------------------------------------------------------------------
; software delay loops
DLY1:
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mov r6, #00h
IN1: djnz r6, IN1
ret
;-----------------------------------------------------------------------------------------------------------
MOVE_FRWD:
mov A, STEP_CNT
movc A, @A+dptr
mov P2, A
inc STEP_CNT
mov A, STEP_CNT
cjne A, #08h, NOTCH1
mov STEP_CNT, #00h
NOTCH1:
ret
;-----------------------------------------------------------------------------------------------------------
MOVE_REV:
mov A, STEP_CNT
movc A, @A+dptr
mov P2, A
dec STEP_CNT
mov A, STEP_CNT
cjne A, #0FFh, NOTCH4
mov STEP_CNT, #07h
NOTCH4:
ret
;-----------------------------------------------------------------------------------------------------------
BRING_HOME:
lcall MOVE_REV
lcall DLY2
jnb SFB, BRING_HOME
ret
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;-----------------------------------------------------------------------------------------------------------
DLY2:
mov r4, #05h
GONE2: mov r5, #06h
OUT2: mov r6, #00h
IN2: djnz r6, IN2
djnz r5, OUT2
djnz r4, GONE2
RET
;-----------------------------------------------------------------------------------------------------------
ORG 0400H
STEP_RUN:
db 09H
db 01H
db 05H
db 04H
db 06H
db 02H
db 0AH
db 08H
5. CONCLUSION
Radar (radio detection and ranging) is something that is in use all around us,
although it is normally invisible. Air traffic control uses radar to track planes both on the
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ground and in the air, and also to guide planes in for smooth landing. Police use radar to detect
the speed of passing motorists. NASA uses radar to map the Earth and other plants, to track
satellite and space debris and to help with things like docking and maneuvering. The military
uses it to detect the enemy and to guide weapons. Meteorologist use radar to track storms,
hurricanes and tornadoes. You even see a form of radar at many grocery stores when the doors
open automatically! Obviously, radar is an extremely useful technology.
6. BIBLIOGRAPHY
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[1] Introduction to Radar Systems Merrill I. Skolnik, SECOND EDITION, McGraw-Hill,
1981.
[2] Introduction to Radar Systems Merrill I. Skolnik, THIRD EDITION, Tata McGraw-Hill,
2001.
[3] The 8051 Microcontroller and Embedded Systems Mazidi and Mazidi, PHI, 2000.
[4] Micro Controllers Deshmukh, Tata McGraw Hill Edition.
Web Reference:
[1] hibp.ecse.rpi.edu/connor/
[2] http://courses.ece.ubc.ca/[3] www.electronicsforyou.com
[4] www.sodoityourself.com
[5] http://en.wikipedia.org/wiki/Rs232
[6] www.Wikipedia.com
[7] www.electronicsforyou.com
[8] www.google.co.in/searches
[9] www.electronicstutorials.com etc
THE END
http://courses.ece.ubc.ca/http://www.electronicsforyou.com/http://www.sodoityourself.com/http://en.wikipedia.org/wiki/Rs232http://www.wikipedia.com/http://www.electronicsforyou.com/http://www.google.co.in/searcheshttp://www.electronicstutorials.com/http://courses.ece.ubc.ca/http://www.electronicsforyou.com/http://www.sodoityourself.com/http://en.wikipedia.org/wiki/Rs232http://www.wikipedia.com/http://www.electronicsforyou.com/http://www.google.co.in/searcheshttp://www.electronicstutorials.com/