1

RCU to FECs

CONNECTORS

BUS

TRANSCEIVERS

FPGA

XILINX Virtex-II Pro

FINAL RCU (FECs side)

FPGA MAIN FUNCTION

• Power-on Procedure

• FEE Initialization

• Dataflow Control

• FEE Safety Control

Reconfiguration Auxiliary Devices

- FLASH Memory

- FLASH FPGA (ProASIC+)

Readout Control Unit 1/3

FPGA for final RCU • Real-time readback of configuration data for verification

• Partial reconfiguration while running

2

Power Regulators

FINAL RCU (links side)

Readout Control Unit 2/3

DCS CARD

SIU CARD

3

Characterization of Sector A09

Sector A09 equipped with • backplanes • cooling circuit• LV power rods• LV PS + cables (4 x 40m)

Sector A09 equipped with • backplanes • cooling circuit• LV power rods• LV PS + cables (4 x 40m)