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reVieWreVieW
Combinational & Sequential Logic Combinational & Sequential Logic CircuitCircuit
EKT 221 / 4EKT 221 / 4DIGITAL DIGITAL
ELECTRONICS IIELECTRONICS II
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Numbering SystemNumbering System
BinaryBinary DecimalDecimal OctalOctal HexadecimalHexadecimal
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Refresh…Refresh…
1011101122 + 1100 + 110022 = ___________ = ___________ FFFF + 1 = ___________FFFF + 1 = ___________
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ConversionConversion
Binary to decimalBinary to decimal
Octal to decimalOctal to decimal
Hexa to decimalHexa to decimal
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ConversionConversion
Binary to decimalBinary to decimal
Octal to decimalOctal to decimal Convert 653Convert 65388 to its decimal equivalent to its decimal equivalent
Hexa to decimalHexa to decimalConvert 3B4FConvert 3B4F1616 to its decimal equivalent to its decimal equivalent
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Octal to Decimal Octal to Decimal ConversionConversion
Convert 653Convert 65388 to its decimal equivalent: to its decimal equivalent:
6 5 3xxx
82 81 80
384 + 40 + 3
42710
Positional Values
Products
Octal Digits
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Hexadecimal to Decimal Hexadecimal to Decimal ConversionConversion
Convert 3B4FConvert 3B4F1616 to its decimal equivalent: to its decimal equivalent:
Hex DigitsHex Digits 3 B 4 Fxxx
163 162 161 160
12288 +2816 + 64 +15
15,18310
Positional Values
Products
x
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ConversionConversion
Decimal to binaryDecimal to binary
Decimal to octalDecimal to octal Convert 427Convert 4271010 to its octal equivalent to its octal equivalent
Decimal to hexadecimalDecimal to hexadecimal Convert 830Convert 8301010 to its hexadecimal to its hexadecimal
equivalentequivalent
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Decimal to Octal ConversionDecimal to Octal Conversion
Convert 427Convert 4271010 to its octal equivalent: to its octal equivalent:
427 / 8 = 53 R3427 / 8 = 53 R3 Divide by 8; R is LSDDivide by 8; R is LSD
53 / 8 = 6 R553 / 8 = 6 R5 Divide Q by 8; R is next Divide Q by 8; R is next digitdigit
6 / 8 = 0 R66 / 8 = 0 R6 Repeat until Q = 0Repeat until Q = 0
6538
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Decimal to Hexadecimal Decimal to Hexadecimal ConversionConversion
Convert 830Convert 8301010 to its hexadecimal equivalent: to its hexadecimal equivalent:
830 / 16 = 51 R14830 / 16 = 51 R14
51 / 16 = 3 R351 / 16 = 3 R3
3 / 16 = 0 R33 / 16 = 0 R3
33E16
= E in Hex
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Binary ArithmeticBinary Arithmetic
AdditionAddition SubtractionSubtraction MultiplicationMultiplication DivisionDivision 1’s complement1’s complement 2’s complement2’s complement
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Basic Logic GatesBasic Logic Gates
Page 31 in Page 31 in Mano & Kime.Mano & Kime.
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Basic Logic GatesBasic Logic Gates
Page 32 in Page 32 in Mano & Kime.Mano & Kime.
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Basic Identities of Boolean Basic Identities of Boolean AlgebraAlgebra
Page 35 in Page 35 in Mano & Kime.Mano & Kime.
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Gates to implement Gates to implement Boolean functionBoolean function
Page 38 in Page 38 in Mano & Kime.Mano & Kime.
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Karnaugh MapKarnaugh Map
Page 49, 53, 64 in Page 49, 53, 64 in Mano & Mano & Kime.Kime.
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Combinational Arithmetic Combinational Arithmetic CircuitsCircuits
Addition:Addition:– Half Adder (HA).Half Adder (HA).– Full Adder (FA).Full Adder (FA).– Carry Ripple Adders.Carry Ripple Adders.
Subtraction:Subtraction:– Half Subtractor.Half Subtractor.– Full Subtractor.Full Subtractor.– Borrow Ripple Subtractors.Borrow Ripple Subtractors.– Subtraction using adders.Subtraction using adders.
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Half AdderHalf Adder
X0011
Y0101
S0110
C-out 0 0 0 1
Half Adder Truth Table:
Inputs Outputs
S = X Y
C-out = XY
X
YSum S
C-out HalfAdder
X
Y
SC-OUT
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Full AdderFull Adder
X00001111
Y00110011
S01101001
C-out 0 0 0 1 0 1 1 1
C-in 0 1 0 1 0 1 0 1
Full Adder Truth Table
S(X,Y, C-in) = (1,2,4,7)C-out(x, y, C-in) = (3,5,6,7)
Inputs Outputs S = X Y (C-in)
C-out = XY + X(C-in) + Y(C-in)
Full Adder
X Y
S
C-inC-out
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Full Adder
X1 Y1
S1
C-inC-out Full Adder
X0 Y0
S0
C-inC-out C0 =0 Full Adder
X2 Y2
S2
C-inC-out Full Adder
X3 Y3
S3
C-inC-outC1C2C3C4
Data inputs to be added
Sum output
4-bit Carry Ripple Adder4-bit Carry Ripple Adder
4-bit Adder
X3X2X1X0
S3 S2 S1 S0
C-inC-outC4
Y3Y2Y1Y0
C0 =0
Inputs to be added
Sum Output
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4-bit Subtractor Using 4-bit 4-bit Subtractor Using 4-bit AdderAdder
4-bit Adder
X3 X2 X1 X0
D3 D2 D1 D0
C-inC-outC4
Y3 Y2 Y1 Y0
C0 = 1
Inputs to be subtracted
Difference Output
S3 S2 S1 S0
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EncoderEncoder Encoder converts information
such as decimal number or an alphabetical character into some binary coded form
Example: 8-to-3 Binary Encoder
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DecoderDecoderExample: 3 to 8 Binary Decoder
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DecoderDecoder
Example:Example: Seven Segment Decoder Seven Segment Decoder
A seven segment decoderA seven segment decoder
has 4-bit BCD input and has 4-bit BCD input and
the seven segment display the seven segment display
code as its output:code as its output: In minimizing the circuits In minimizing the circuits
for the segment outputs all for the segment outputs all
non-decimal input combinations non-decimal input combinations
(1010, 1011, 1100,1101, 1110,(1010, 1011, 1100,1101, 1110,
1111) are taken as don’t-cares1111) are taken as don’t-cares
/Bl D C B A a b c d e f g 0 x x x x 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 1 1 0 1 0 0 0 1 0 1 1 0 0 0 0 1 0 0 1 0 1 1 0 1 1 0 1 1 0 0 1 1 1 1 1 1 0 0 1 1 0 1 0 0 0 1 1 0 0 1 1 1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 0 0 1 1 1 1 1 1 0 1 1 1 1 1 1 0 0 0 0 1 1 0 0 0 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 0 0 1 1 1 1 0 1 0 0 0 0 1 1 0 1 1 1 0 1 1 0 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 0 1 1 1 1 1 0 1 1 0 0 1 0 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0
-- d
on’t
car
e in
pu
ts -
-
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MultiplexerMultiplexer
A 4 input multiplexer
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DemultiplexerDemultiplexerExample: 1- to -4 Demultiplexer
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seQuenTial loGicseQuenTial loGic
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Latches:Latches:– S-R LatchS-R Latch– Gate S-R Latch Gate S-R Latch – Gate D-LatchGate D-Latch
Flip-Flops:Flip-Flops:– Edge-Triggered Flip-Flop (S-R, J-K, D)Edge-Triggered Flip-Flop (S-R, J-K, D)– Asynchronous InputsAsynchronous Inputs– Master-Slave Flip-FlopMaster-Slave Flip-Flop– Flip-Flop Operating CharacteristicsFlip-Flop Operating Characteristics– Flip-Flop ApplicationsFlip-Flop Applications– One-shots & The 555 TimerOne-shots & The 555 Timer
Latches & Flip Flop
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Latches & Flip Flop
Truth Table for each FFTruth Table for each FF +ve / -ve edge triggered+ve / -ve edge triggered WaveformWaveform
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Basic shift register functionBasic shift register function Serial in / serial out shift registersSerial in / serial out shift registers Serial in / parallel out shift registersSerial in / parallel out shift registers Parallel in / serial out shift registersParallel in / serial out shift registers Parallel in / parallel out shift Parallel in / parallel out shift
registersregisters Bidirectional shift registersBidirectional shift registers Shift register applicationsShift register applications
Shift Register
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Serial In, Serial Out Shift RegisterSerial In, Serial Out Shift Register(SISO)(SISO)
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Serial In, Parallel Out Shift registerSerial In, Parallel Out Shift register (SIPO) (SIPO)
• Data bits entered serially (right-most bit first)
• Difference from SISO is the way data bits are taken
out of the register – in parallel.
• Output of each stage is available
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Parallel In, Parallel Out Shift Register Parallel In, Parallel Out Shift Register (PIPO)(PIPO)
Immediately following simultaneous entry of all data bits,it appear on parallel output.
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ASYNCHRONOUS COUNTER:
A 2-bit asynchronous binary counter.
•Don’t have fixed time relationship with each other.
•Don’t occur at the same time.
•Don’t have a common clock pulse
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SYNCHRONOUS COUNTER OPERATION A 2-bit synchronous binary counter.
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UP/DOWN SYNCHRONOUS COUNTER
A basic 3-bit up/down synchronous counter.