Download - Role of Op-Amps
![Page 1: Role of Op-Amps](https://reader035.vdocument.in/reader035/viewer/2022062316/56815f8f550346895dce9072/html5/thumbnails/1.jpg)
1Analog and Mixed-Signal VLSI Design Center
IOWA STATE UNIVERSITY
Role of Op-Amps
• widely used building blocks for analog circuits
• widely used in communication circuits• Widely used in analog signal processing
– critical block for data-converters• Widely Used in High Volume ICs
– memory read out– Disk-driver reading-writing
![Page 2: Role of Op-Amps](https://reader035.vdocument.in/reader035/viewer/2022062316/56815f8f550346895dce9072/html5/thumbnails/2.jpg)
2Analog and Mixed-Signal VLSI Design Center
IOWA STATE UNIVERSITY
New challenges in Analog Design
• Decreased Supply Voltage• Increased Digital/Analog Interference• Reduced Testability• Increased Parametric Variations
![Page 3: Role of Op-Amps](https://reader035.vdocument.in/reader035/viewer/2022062316/56815f8f550346895dce9072/html5/thumbnails/3.jpg)
3Analog and Mixed-Signal VLSI Design Center
IOWA STATE UNIVERSITY
Critical Specifications for Op-Amps
• High DC Gain• High Speed/Large Gain-Bandwidth • Sufficient Output Swing• High power efficiency
Desirable: digital built-in-self-test and self-calibration
![Page 4: Role of Op-Amps](https://reader035.vdocument.in/reader035/viewer/2022062316/56815f8f550346895dce9072/html5/thumbnails/4.jpg)
4Analog and Mixed-Signal VLSI Design Center
IOWA STATE UNIVERSITY
Existing structures & Limitations
Cascode AmplifierDC Gain: Modest
Speed: Excellent
Output Swing: Small
Power Efficiency: Good
Vi2
M4
Mb
M1 M1
M3 M3
Vi1
M2 M2
M4
bias1
bias2
bias3
cmfb
Frequency Response: Good
![Page 5: Role of Op-Amps](https://reader035.vdocument.in/reader035/viewer/2022062316/56815f8f550346895dce9072/html5/thumbnails/5.jpg)
5Analog and Mixed-Signal VLSI Design Center
IOWA STATE UNIVERSITY
Existing structures & Limitations
Cascaded AmplifierDC Gain: High
Output Swings: Large
Speed: Poor
CP1
CP2
in outA1 A2 A3
Frequency Response: Poor
![Page 6: Role of Op-Amps](https://reader035.vdocument.in/reader035/viewer/2022062316/56815f8f550346895dce9072/html5/thumbnails/6.jpg)
6Analog and Mixed-Signal VLSI Design Center
IOWA STATE UNIVERSITY
Existing structures & Limitations
Positive Feedback AmplifierDC Gain: Large
Output Swing: Good
Speed: High
Low Yield
Frequency Response: Good
Vi1 Vi2
Vbn
Vbp Vbp
Vo1 Vo2
![Page 7: Role of Op-Amps](https://reader035.vdocument.in/reader035/viewer/2022062316/56815f8f550346895dce9072/html5/thumbnails/7.jpg)
7Analog and Mixed-Signal VLSI Design Center
IOWA STATE UNIVERSITY
Our Objective
• Low Voltage Compatible• High DC Gain• High Speed• Good Output Swing• High Yield• Standard Digital Process Compatible• Good Power Efficiency
![Page 8: Role of Op-Amps](https://reader035.vdocument.in/reader035/viewer/2022062316/56815f8f550346895dce9072/html5/thumbnails/8.jpg)
8Analog and Mixed-Signal VLSI Design Center
IOWA STATE UNIVERSITY
Our Approach
• Find new amplifier architectures• Rely on digital logic to enhance
performance• Use simple digital circuit sensing amplifier
performance• Integrate controllability• Use adaptive feedback control
![Page 9: Role of Op-Amps](https://reader035.vdocument.in/reader035/viewer/2022062316/56815f8f550346895dce9072/html5/thumbnails/9.jpg)
9Analog and Mixed-Signal VLSI Design Center
IOWA STATE UNIVERSITY
Positive Feedback Gain-Boosting
• Can operate at very low voltages• Can achieve very high DC gain• No compromise in bandwidth• No appreciable power increase• Conventional wisdom has two concerns
– positive feedback leads to RHP poles– gain boosting is limited if requiring robustness w.r.t.
process variations
![Page 10: Role of Op-Amps](https://reader035.vdocument.in/reader035/viewer/2022062316/56815f8f550346895dce9072/html5/thumbnails/10.jpg)
10Analog and Mixed-Signal VLSI Design Center
IOWA STATE UNIVERSITY
Our response to the concerns
• positive feedback causes RHP open-loop poles, but do not necessarily cause RHP closed-loop poles!
• RHP open-loop poles can actually improve performance of closed-loop amplifiers!
• F16/F18 fighter jets have open-loop RHP poles, they play critical role in achieving their superior closed-loop performance
• no need for robustness across process variations• use positive feedback pole control after fabrication
![Page 11: Role of Op-Amps](https://reader035.vdocument.in/reader035/viewer/2022062316/56815f8f550346895dce9072/html5/thumbnails/11.jpg)
11Analog and Mixed-Signal VLSI Design Center
IOWA STATE UNIVERSITY
Positive Feedback Operational Amplifiers
A(s)
-
+Vin
-
+Vd VoutA(s)
-
+Vin
-
+Vd Vout
Open loop transfer function ps
GBps
pAA(s)
0
Closed-loop transfer function βGBps
GBβA(s)A(s)(s)Af
1
Open-loop pole: Closed-loop pole: βGBppf p
![Page 12: Role of Op-Amps](https://reader035.vdocument.in/reader035/viewer/2022062316/56815f8f550346895dce9072/html5/thumbnails/12.jpg)
12Analog and Mixed-Signal VLSI Design Center
IOWA STATE UNIVERSITY
Positive Feedback Amplifier Architecture Exploration
• Some positive feedback amplifier architectures have a dc gain that is much more sensitive to the feedback control variable than others
• Although architecture optimality may be difficult to determine, synthesis techniques may yield better structures than those already considered
• Comparative study of several structures with existing positive feedback structures
![Page 13: Role of Op-Amps](https://reader035.vdocument.in/reader035/viewer/2022062316/56815f8f550346895dce9072/html5/thumbnails/13.jpg)
13Analog and Mixed-Signal VLSI Design Center
IOWA STATE UNIVERSITY
A)(1gggsCg(s)A
dsnds2ds1L
m1v
Vdd
Vi
Vbias1 Vo
M1
M2
AVxx
CL
Mn
AVo
ADC = gm1
gds1+gds2- (A-1)gdsn
As (A-1)gdsn → gds1+gds2,
ADC → ∞ !
Negative Output Conductance Op Amp
![Page 14: Role of Op-Amps](https://reader035.vdocument.in/reader035/viewer/2022062316/56815f8f550346895dce9072/html5/thumbnails/14.jpg)
14Analog and Mixed-Signal VLSI Design Center
IOWA STATE UNIVERSITY
Implementation Block Diagram
Bias Generator
CMFB
Vip
Vin Von
VopBasic Amp
2nd stage
Negative Conductance GeneratorVi-
Vi+
2nd stage
First Stage
![Page 15: Role of Op-Amps](https://reader035.vdocument.in/reader035/viewer/2022062316/56815f8f550346895dce9072/html5/thumbnails/15.jpg)
15Analog and Mixed-Signal VLSI Design Center
IOWA STATE UNIVERSITY
Basic Amplifier and the Second Stage
Basic amplifier Second stage
VBP
Vin
VCMVBN
Vip
Von Vop
M1
M5
M4M3
M2
M6Vin
M8M9
M7
Vout
![Page 16: Role of Op-Amps](https://reader035.vdocument.in/reader035/viewer/2022062316/56815f8f550346895dce9072/html5/thumbnails/16.jpg)
16Analog and Mixed-Signal VLSI Design Center
IOWA STATE UNIVERSITY
Negative Conductance Generator
Vdd
M1
VopVon
Vctrl
AM5
Mg1Mn1
M4
M3 M2
Mn2
M8
M7M6
Mg2
Vi+ Vi-
Vctrl
VXX VXX
![Page 17: Role of Op-Amps](https://reader035.vdocument.in/reader035/viewer/2022062316/56815f8f550346895dce9072/html5/thumbnails/17.jpg)
17Analog and Mixed-Signal VLSI Design Center
IOWA STATE UNIVERSITY
Low Gain Stage A
Vin
VBN
Vip
VopMa1
Ma3
Ma2Von
Ma4
Ma8
Ma5
Ma6
Ma7
Ma9
![Page 18: Role of Op-Amps](https://reader035.vdocument.in/reader035/viewer/2022062316/56815f8f550346895dce9072/html5/thumbnails/18.jpg)
18Analog and Mixed-Signal VLSI Design Center
IOWA STATE UNIVERSITY
Positive Feedback Amplifier Architecture Exploration
VOUT
VIN
M1
M2
M3
M4
VA
VB
f1(-θ1VA-θ2VB-θ3VOUT)
f2(-θ4VA-θ5VB-θ6VOUT)
f3(-θ7VA-θ8VB-θ9VOUT)
Overhead for realizing this structure can be very small
![Page 19: Role of Op-Amps](https://reader035.vdocument.in/reader035/viewer/2022062316/56815f8f550346895dce9072/html5/thumbnails/19.jpg)
19Analog and Mixed-Signal VLSI Design Center
IOWA STATE UNIVERSITY 43212122
433343
2221 )(
omoooombm
oombmoo
ombmm
gkggggggggggggg
ggggA
Mb
M1 M1
M3 M3
k
Vi1 Vi2
M2 M2
M4 M4
bias1
bias2
Example positive feedback amp1:
43
212122
433343
om
oooombm
oombmoo
gg
gggggggggggg
k
Gain = infinity
![Page 20: Role of Op-Amps](https://reader035.vdocument.in/reader035/viewer/2022062316/56815f8f550346895dce9072/html5/thumbnails/20.jpg)
20Analog and Mixed-Signal VLSI Design Center
IOWA STATE UNIVERSITY 2122
12
2122
21
4333
43
2122
2221
oombm
om
oombm
oo
oombm
oo
oombm
ombmm
i
o
gggggkg
gggggg
gggggg
gggggggg
vv
Example positive feedback amp2:
Mb
M1 M1
M3 M3
k
Vi1 Vi2
M2 M2
M4 M4
bias1
bias2
Vo1 Vo2
2122
12
2122
21
4333
43
oombm
om
oombm
oo
oombm
oo
gggggg
gggggg
gggggg
k
Gain = infinity
![Page 21: Role of Op-Amps](https://reader035.vdocument.in/reader035/viewer/2022062316/56815f8f550346895dce9072/html5/thumbnails/21.jpg)
21Analog and Mixed-Signal VLSI Design Center
IOWA STATE UNIVERSITY
M4
Mb
M1 M1
M3 M3
k
Vi1 Vi2
M2 M2
M4
bias1
bias2
422122
321
2122
433343
2221 )(
oooombm
moo
oombm
oombmoo
ombmm
gggggg
gkgggggggggggg
ggggA
Example positive feedback amp3:
2122
423
212122
433343
oombm
oom
oooombm
oombmoo
ggggggg
gggggggggggg
k
Gain = infinity
![Page 22: Role of Op-Amps](https://reader035.vdocument.in/reader035/viewer/2022062316/56815f8f550346895dce9072/html5/thumbnails/22.jpg)
22Analog and Mixed-Signal VLSI Design Center
IOWA STATE UNIVERSITY
M2
M1
M4
Mb
M1
M3 M3
k
Vi1 Vi2
M2
M4
bias1
bias2
314333
243
4333
212221
2221 )(
oooombm
moo
oombm
oombmoo
ombmm
gggggg
gkgggggggggggg
ggggA
Example positive feedback amp4:
314333
2
434333
212221
oooombm
m
oooombm
oombmoo
gggggg
g
gggggggggg
ggk
Gain = infinity
![Page 23: Role of Op-Amps](https://reader035.vdocument.in/reader035/viewer/2022062316/56815f8f550346895dce9072/html5/thumbnails/23.jpg)
23Analog and Mixed-Signal VLSI Design Center
IOWA STATE UNIVERSITY
DC Sweep of amp1 in 0.1um process
-6 -4 -2 0 2 4 6x 10-3
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
differential input(V)
diffe
rent
ial o
utpu
t(V)
A High Gain Positive Feedback Amplifier in 0.1um Process
![Page 24: Role of Op-Amps](https://reader035.vdocument.in/reader035/viewer/2022062316/56815f8f550346895dce9072/html5/thumbnails/24.jpg)
24Analog and Mixed-Signal VLSI Design Center
IOWA STATE UNIVERSITY
Preliminary Results: DBISTSC PFAmp
A Digital Programmable Amplifier
Bifurcation in Positive Feedback Amplifier
Simulation and Measurement Results
![Page 25: Role of Op-Amps](https://reader035.vdocument.in/reader035/viewer/2022062316/56815f8f550346895dce9072/html5/thumbnails/25.jpg)
25Analog and Mixed-Signal VLSI Design Center
IOWA STATE UNIVERSITY
A digital controllable Amplifier•Low-Voltage Compatible
3 transistors from VDD to VSS
•High GainAttenuator provides positive feedbacknegative-conductance compensation
•High SpeedSingle Stage
M2 M2
Vi1
Vi2
Vbn
Vo1 Vo2 CL CL
VDD
VSS
![Page 26: Role of Op-Amps](https://reader035.vdocument.in/reader035/viewer/2022062316/56815f8f550346895dce9072/html5/thumbnails/26.jpg)
26Analog and Mixed-Signal VLSI Design Center
IOWA STATE UNIVERSITY
Small Signal Linear Equivalence
21 ii VVx
21 oo VVy gopgongmnx
y
xsCL-gmpy
0A=0
opon
mp
ggg
0mpoponL
mn
gggsCgA
![Page 27: Role of Op-Amps](https://reader035.vdocument.in/reader035/viewer/2022062316/56815f8f550346895dce9072/html5/thumbnails/27.jpg)
27Analog and Mixed-Signal VLSI Design Center
IOWA STATE UNIVERSITY
Nonlinear Dynamic
04})](1[)(4{ 232 xgyxVVgggy mnSOCMnnnmponoppp
xCgy
CxVVy
Cy
Cggg
yL
mn
L
SOCMnnn
L
pp
L
mponop
4
)](1[4
23
2
Dynamic equation
Equilibrium manifold (DC Transfer)
![Page 28: Role of Op-Amps](https://reader035.vdocument.in/reader035/viewer/2022062316/56815f8f550346895dce9072/html5/thumbnails/28.jpg)
28Analog and Mixed-Signal VLSI Design Center
IOWA STATE UNIVERSITY
Amplifier’s DC Characteristics
x
y
0
0.020.021
0.03
![Page 29: Role of Op-Amps](https://reader035.vdocument.in/reader035/viewer/2022062316/56815f8f550346895dce9072/html5/thumbnails/29.jpg)
29Analog and Mixed-Signal VLSI Design Center
IOWA STATE UNIVERSITY
y
-0.1 -0.05 0 0.05 0.1-1.5
-1
-0.5
0
0.5
1
1.5
x
y
0=0.02=0
=0.021
=0.03
L
Amplifier’s DC Characteristics
![Page 30: Role of Op-Amps](https://reader035.vdocument.in/reader035/viewer/2022062316/56815f8f550346895dce9072/html5/thumbnails/30.jpg)
30Analog and Mixed-Signal VLSI Design Center
IOWA STATE UNIVERSITY
0
>0 Hysteresis
No Hysteresis
Decrease L Gain
Hysteresis
Observations
![Page 31: Role of Op-Amps](https://reader035.vdocument.in/reader035/viewer/2022062316/56815f8f550346895dce9072/html5/thumbnails/31.jpg)
31Analog and Mixed-Signal VLSI Design Center
IOWA STATE UNIVERSITY
Phase Diagram in Y- Plane
0.017 0.018 0.019 0.02 0.021 0.022 0.023-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
0
unstable
stable
stable
stable
yx=0
![Page 32: Role of Op-Amps](https://reader035.vdocument.in/reader035/viewer/2022062316/56815f8f550346895dce9072/html5/thumbnails/32.jpg)
32Analog and Mixed-Signal VLSI Design Center
IOWA STATE UNIVERSITY
Phase Diagram in Y- Plane
0.018 0.019 0.02 0.021 0.022 0.023 0.024-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
y
y
*x=-0.001
![Page 33: Role of Op-Amps](https://reader035.vdocument.in/reader035/viewer/2022062316/56815f8f550346895dce9072/html5/thumbnails/33.jpg)
33Analog and Mixed-Signal VLSI Design Center
IOWA STATE UNIVERSITY
Phase Diagram in Y- Plane
0.018 0.019 0.02 0.021 0.022 0.023 0.024-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
yy
*x=0.001
![Page 34: Role of Op-Amps](https://reader035.vdocument.in/reader035/viewer/2022062316/56815f8f550346895dce9072/html5/thumbnails/34.jpg)
34Analog and Mixed-Signal VLSI Design Center
IOWA STATE UNIVERSITY
Observations
>0 Bifurcation
For some given x, 3 solutions for y2 stable and 1 unstableFor some given x, one unique solution for y
0 No Bifurcation
For a given x, one unique solution for y
![Page 35: Role of Op-Amps](https://reader035.vdocument.in/reader035/viewer/2022062316/56815f8f550346895dce9072/html5/thumbnails/35.jpg)
35Analog and Mixed-Signal VLSI Design Center
IOWA STATE UNIVERSITY
Pull up/Pull down Circuit
-0.5 0 0.5-1.5
-1
-0.5
0
0.5
1
1.5
x
yDiscontinouity
Stable
Unstable
Stable
pullup pulldown
![Page 36: Role of Op-Amps](https://reader035.vdocument.in/reader035/viewer/2022062316/56815f8f550346895dce9072/html5/thumbnails/36.jpg)
36Analog and Mixed-Signal VLSI Design Center
IOWA STATE UNIVERSITY
-0.5 0 0.5-1.5
-1
-0.5
0
0.5
1
1.5
x
yDiscontinouity
Stable
Unstable
Stable
x
Pull down, stay low
OHOL=10
y
Pull up/Pull Down
Pull up, stay high
![Page 37: Role of Op-Amps](https://reader035.vdocument.in/reader035/viewer/2022062316/56815f8f550346895dce9072/html5/thumbnails/37.jpg)
37Analog and Mixed-Signal VLSI Design Center
IOWA STATE UNIVERSITY
-0.5 0 0.5-1.5
-1
-0.5
0
0.5
1
1.5
x
yDiscontinouity
Stable
Unstable
Stable
x
Pull down, return high
OHOL=11
y
Pull up/Pull Down
Pull up, stay high
![Page 38: Role of Op-Amps](https://reader035.vdocument.in/reader035/viewer/2022062316/56815f8f550346895dce9072/html5/thumbnails/38.jpg)
38Analog and Mixed-Signal VLSI Design Center
IOWA STATE UNIVERSITY
-0.5 0 0.5-1.5
-1
-0.5
0
0.5
1
1.5
x
yDiscontinouity
Stable
Unstable
Stable
x
Pull down, stay low
OHOL=00
y
Pull up/Pull Down
Pull up, return low
![Page 39: Role of Op-Amps](https://reader035.vdocument.in/reader035/viewer/2022062316/56815f8f550346895dce9072/html5/thumbnails/39.jpg)
39Analog and Mixed-Signal VLSI Design Center
IOWA STATE UNIVERSITY
Sensing Processpull up
release
record OH
pull down
release
record OL
OHOL=?
no bifurcation bifurcation detected
11/00 10
![Page 40: Role of Op-Amps](https://reader035.vdocument.in/reader035/viewer/2022062316/56815f8f550346895dce9072/html5/thumbnails/40.jpg)
40Analog and Mixed-Signal VLSI Design Center
IOWA STATE UNIVERSITY
Linear MOS Attenuator
111 k1.
3. controlled by Aspect Ratio Vo
M2
M1
Vi
W2/L2
W1/L1
2211
221 //
/LWLW
LW
2.
4. k controlled by Aspect Ratio
5. Infinite input impedance at DC
![Page 41: Role of Op-Amps](https://reader035.vdocument.in/reader035/viewer/2022062316/56815f8f550346895dce9072/html5/thumbnails/41.jpg)
41Analog and Mixed-Signal VLSI Design Center
IOWA STATE UNIVERSITY
Adaptively Controllable Attenuator
M2
M1
M4
M3
M6
M5
d6 d0
1.Quiescent-voltage shifting
)11( 132 kk2.
3.Decreased Sensitivity to transistor size change
m4.
: input code <d6…d0>
![Page 42: Role of Op-Amps](https://reader035.vdocument.in/reader035/viewer/2022062316/56815f8f550346895dce9072/html5/thumbnails/42.jpg)
42Analog and Mixed-Signal VLSI Design Center
IOWA STATE UNIVERSITY
Programmable Attenuation
0 20 40 60 80 100 120 1400.016
0.017
0.018
0.019
0.02
0.021
0.022
input
atte
nuat
ion
![Page 43: Role of Op-Amps](https://reader035.vdocument.in/reader035/viewer/2022062316/56815f8f550346895dce9072/html5/thumbnails/43.jpg)
43Analog and Mixed-Signal VLSI Design Center
IOWA STATE UNIVERSITY
Gain Enhancement Requirement
mpm
mng
gA)]([ 0
||1
A
Gain is related to controllable Attenuator
Required Attenuator Control Code
Achievable Gain Lower Bound
mm or 02
01 ,
![Page 44: Role of Op-Amps](https://reader035.vdocument.in/reader035/viewer/2022062316/56815f8f550346895dce9072/html5/thumbnails/44.jpg)
44Analog and Mixed-Signal VLSI Design Center
IOWA STATE UNIVERSITY
Design Specification for Attenuator DAC
1. Sufficient Coverage)2()0( 1
max0min0N
2. Fine Resolution
specAN
1)}()1({max120 1
3. DAC Size
min0max012 N
![Page 45: Role of Op-Amps](https://reader035.vdocument.in/reader035/viewer/2022062316/56815f8f550346895dce9072/html5/thumbnails/45.jpg)
45Analog and Mixed-Signal VLSI Design Center
IOWA STATE UNIVERSITY
Effect of Offset on Sensing
-0.1 -0.05 0 0.05 0.1-1.5
-1
-0.5
0
0.5
1
1.5
x
y
offset
O
![Page 46: Role of Op-Amps](https://reader035.vdocument.in/reader035/viewer/2022062316/56815f8f550346895dce9072/html5/thumbnails/46.jpg)
46Analog and Mixed-Signal VLSI Design Center
IOWA STATE UNIVERSITY
Offset Compensated Sensing Circuit
pull up pull down
VICM
DACcomparator O
![Page 47: Role of Op-Amps](https://reader035.vdocument.in/reader035/viewer/2022062316/56815f8f550346895dce9072/html5/thumbnails/47.jpg)
47Analog and Mixed-Signal VLSI Design Center
IOWA STATE UNIVERSITY
Design Specifications for input DAC
1. Sufficient Coverage)2()0( 2
maxminNOffsetOffset
2. Fine Resolution
specLN
)}()1({max120 2
3. DAC Size
spec
NL
OffsetOffset minmax22
![Page 48: Role of Op-Amps](https://reader035.vdocument.in/reader035/viewer/2022062316/56815f8f550346895dce9072/html5/thumbnails/48.jpg)
48Analog and Mixed-Signal VLSI Design Center
IOWA STATE UNIVERSITY
Design Specifications
y
-0.1 -0.05 0 0.05 0.1-1.5
-1
-0.5
0
0.5
1
1.5
x
y
=0.021
Lspec
Aspec:80dB
Lspec:20V
N2 12
:0.0001
offset variation:50mV
0variation:0.006N16
![Page 49: Role of Op-Amps](https://reader035.vdocument.in/reader035/viewer/2022062316/56815f8f550346895dce9072/html5/thumbnails/49.jpg)
49Analog and Mixed-Signal VLSI Design Center
IOWA STATE UNIVERSITY
Combined Sensing and Control Logic
• Implement with inexpensive digital logic• Time-efficient processing• Accomplish offset compensation• Realize optimal control code searching• Adaptive feedback control
![Page 50: Role of Op-Amps](https://reader035.vdocument.in/reader035/viewer/2022062316/56815f8f550346895dce9072/html5/thumbnails/50.jpg)
50Analog and Mixed-Signal VLSI Design Center
IOWA STATE UNIVERSITY
Functional Block Diagram
pull up pull down
VICM
ComparatorO
branching parameter controland offset cancellation
DAC
cal/un
![Page 51: Role of Op-Amps](https://reader035.vdocument.in/reader035/viewer/2022062316/56815f8f550346895dce9072/html5/thumbnails/51.jpg)
51Analog and Mixed-Signal VLSI Design Center
IOWA STATE UNIVERSITY
Nested attenuation/bifurcation control
initialize
=(L+H)/2
bifurcation detection
Bifurcation?
L=H=
no
: Attenuator DAC input
yes no
step=N1?yes
finish searching
inner loop
![Page 52: Role of Op-Amps](https://reader035.vdocument.in/reader035/viewer/2022062316/56815f8f550346895dce9072/html5/thumbnails/52.jpg)
52Analog and Mixed-Signal VLSI Design Center
IOWA STATE UNIVERSITY
Bifurcation Detection Algorithm
initialize
=(L+H)/2
Pull-up/Down
OHOL=? bifurcationdetected
H=
: Input of offset compensation DAC
00 10
break L= 11
no2N2+1input codes
step=N2?yes
break withoutbifurcation
![Page 53: Role of Op-Amps](https://reader035.vdocument.in/reader035/viewer/2022062316/56815f8f550346895dce9072/html5/thumbnails/53.jpg)
53Analog and Mixed-Signal VLSI Design Center
IOWA STATE UNIVERSITY
Convergence Proof
Conditions on offset-DAC range guarantee initial conditions:
H
()
x
offset
L
at step 01.When =L=0, OHOL=112.When =H=2N2,
OHOL=003. (L)< offset (H)4. H-L=2N2
![Page 54: Role of Op-Amps](https://reader035.vdocument.in/reader035/viewer/2022062316/56815f8f550346895dce9072/html5/thumbnails/54.jpg)
54Analog and Mixed-Signal VLSI Design Center
IOWA STATE UNIVERSITY
Convergence Proof (Continue)• at step k+1,
=(L+ H)/2, pull up/down
– if OHOL=10, bifurcation is detected, break
– if OHOL=11, ()<offset, let L=
– if OHOL=00, ()offset, let H= – if bifurcation is not detected, continue.
• then (L)< offset (H) H - L=2N2-(k+1)
– At L, OHOL=11; at H ,OHOL=00• This iteration ends either with ‘bifurcation detected’ or ‘step=N2’
without bifurcation.
![Page 55: Role of Op-Amps](https://reader035.vdocument.in/reader035/viewer/2022062316/56815f8f550346895dce9072/html5/thumbnails/55.jpg)
55Analog and Mixed-Signal VLSI Design Center
IOWA STATE UNIVERSITY
Convergence Proof (Continue)• If step=N2, H-L=1 (L)< offset (H)
• when =L, OHOL=11, (L)< lower bound of hysteresis
• when =H, OHOL=00, (H)> up bound of hysteresis
• Lhys>(H)- (L)offset
(L) (H)
potential
hysteresis width
x
lower bound up boundLhys
![Page 56: Role of Op-Amps](https://reader035.vdocument.in/reader035/viewer/2022062316/56815f8f550346895dce9072/html5/thumbnails/56.jpg)
56Analog and Mixed-Signal VLSI Design Center
IOWA STATE UNIVERSITY
Convergence Proof (Attenuator)
L
H
0 128
control code
Converge tobifurcation
nobifurcation
0
L L+1
Conditions on -DAC range guarantee initial conditions:at step 01.When = L=0, no bifurcation
2.When = H=2N1, bifurcation
3. (L)0< (H)4. H- L=2N1
![Page 57: Role of Op-Amps](https://reader035.vdocument.in/reader035/viewer/2022062316/56815f8f550346895dce9072/html5/thumbnails/57.jpg)
57Analog and Mixed-Signal VLSI Design Center
IOWA STATE UNIVERSITY
Convergence Proof (Attenuator)•step k+1: (L)0< (H), H- L=2N2-k •let =(L+ H)/2, do ‘bifurcation detection’•if bifurcation is detected, ()> 0 ,let H= •else let L= •at both situations, (L)0< (H), H- L=2N1-k-1
![Page 58: Role of Op-Amps](https://reader035.vdocument.in/reader035/viewer/2022062316/56815f8f550346895dce9072/html5/thumbnails/58.jpg)
58Analog and Mixed-Signal VLSI Design Center
IOWA STATE UNIVERSITY
Convergence Proof (Attenuator)
• This iteration ends with no bifurcation and finds an optimal control code L
spec
Lachieved
AN
1)}()1({max
)(
120
0
1
• Aachieved Aspec
(L) (H)
0
![Page 59: Role of Op-Amps](https://reader035.vdocument.in/reader035/viewer/2022062316/56815f8f550346895dce9072/html5/thumbnails/59.jpg)
59Analog and Mixed-Signal VLSI Design Center
IOWA STATE UNIVERSITY
Simulation Environment• Ami 0.5um CMOS (most)• Cadence
– Spectre (simulator)– Hspice (simulator)– SpectreVerilog (simulator)– Analog Artist– Schematic– Virtuoso (layout tool)– SEDSM (Floor-plan /Route )
• Synopsys
![Page 60: Role of Op-Amps](https://reader035.vdocument.in/reader035/viewer/2022062316/56815f8f550346895dce9072/html5/thumbnails/60.jpg)
60Analog and Mixed-Signal VLSI Design Center
IOWA STATE UNIVERSITY
Simulation Results
0 50 100 150 200 2500
0.02
0.04
0.06
0.08
0.1
0.12
0.14
0.16
0.18
0.2
DAC input (MSB)
Volta
ge
Offset Compensation DAC Characteristics
16-b R-1.8R DAC=5V<Lspe
c
![Page 61: Role of Op-Amps](https://reader035.vdocument.in/reader035/viewer/2022062316/56815f8f550346895dce9072/html5/thumbnails/61.jpg)
61Analog and Mixed-Signal VLSI Design Center
IOWA STATE UNIVERSITY
M2
M1
M4
M3
M6
M5
d6 d0
![Page 62: Role of Op-Amps](https://reader035.vdocument.in/reader035/viewer/2022062316/56815f8f550346895dce9072/html5/thumbnails/62.jpg)
62Analog and Mixed-Signal VLSI Design Center
IOWA STATE UNIVERSITY
Digitally controlled PF Amplifier
+ -
cmfb
- +
VDD
VSS
+
-
-
+
A1
+ -
cmfb
- +
VDD
VSS
Vbp
+
-
-
+A2
![Page 63: Role of Op-Amps](https://reader035.vdocument.in/reader035/viewer/2022062316/56815f8f550346895dce9072/html5/thumbnails/63.jpg)
63Analog and Mixed-Signal VLSI Design Center
IOWA STATE UNIVERSITY
Two Stage Amplifier
PU PDA1 A2
vi1
vi2
vop
von
vo1
vo2
vi1
vi2
PU
PD
vo1
vo2
vop
von
Amp
![Page 64: Role of Op-Amps](https://reader035.vdocument.in/reader035/viewer/2022062316/56815f8f550346895dce9072/html5/thumbnails/64.jpg)
64Analog and Mixed-Signal VLSI Design Center
IOWA STATE UNIVERSITY
R-2R DAC
DAC
R-2R
ground
reference
2R 2R 2R 2R 2R 1.9R
R R 0.94R
Matched 2R-R
For K LSBDesigned 2R-xR
For N-K MSB
X<1LSB MSB
0 1 N-2 N-1
ground
reference
2R 2R 2R 2R 2R 1.9R
R R 0.94R
Matched 2R-R
For K LSBDesigned 2R-xR
For N-K MSB
X<1
ground
reference
2R 2R 2R 2R 2R 1.9R
R R 0.94R
ground
reference
2R 2R 2R 2R 2R 1.9R
R R 0.94R
Matched 2R-R
For K LSBDesigned 2R-xR
For N-K MSB
X<1
output
LSBLSB MSBMSB
0 1 N-2 N-1
![Page 65: Role of Op-Amps](https://reader035.vdocument.in/reader035/viewer/2022062316/56815f8f550346895dce9072/html5/thumbnails/65.jpg)
65Analog and Mixed-Signal VLSI Design Center
IOWA STATE UNIVERSITY
Two way switch
00
VHVL
VoVo
VH
VL
![Page 66: Role of Op-Amps](https://reader035.vdocument.in/reader035/viewer/2022062316/56815f8f550346895dce9072/html5/thumbnails/66.jpg)
66Analog and Mixed-Signal VLSI Design Center
IOWA STATE UNIVERSITY
Comparator
Vin+ Vin-
latch
M1 M2Vin+ Vin-
latch
Vin+ Vin-
latch
M1 M2
Vout Comparator
![Page 67: Role of Op-Amps](https://reader035.vdocument.in/reader035/viewer/2022062316/56815f8f550346895dce9072/html5/thumbnails/67.jpg)
67Analog and Mixed-Signal VLSI Design Center
IOWA STATE UNIVERSITY
Self-Calibrated High Gain Amplifier
vi1
vi2
PU
PD
vo1
vo2
vop
von
DACcode
calibr
PU
PD
vcm
DS
CLK
RN
controller Amp Comparator
16-bit R-2R
![Page 68: Role of Op-Amps](https://reader035.vdocument.in/reader035/viewer/2022062316/56815f8f550346895dce9072/html5/thumbnails/68.jpg)
68Analog and Mixed-Signal VLSI Design Center
IOWA STATE UNIVERSITY
Algorithm for Controller
• Step 1: Initialize • Step 2: Sweep input• Step 3: Use pull-up/down method to detect hysteresis• Step 4: if hysteresis exists, decrease ; else increase • Step 5: if is very close to 0, finish; else goto step 2
![Page 69: Role of Op-Amps](https://reader035.vdocument.in/reader035/viewer/2022062316/56815f8f550346895dce9072/html5/thumbnails/69.jpg)
69Analog and Mixed-Signal VLSI Design Center
IOWA STATE UNIVERSITY
Offset Compensation DAC
Attenuator Control DAC
32768 16384 24576 16384 28672 25578 24577
No Bifurcation
64 32 48 52 50 49 48
yesbifurcation: no no yes yes yesMax searching time: 7x16 cycles
Searching Process
![Page 70: Role of Op-Amps](https://reader035.vdocument.in/reader035/viewer/2022062316/56815f8f550346895dce9072/html5/thumbnails/70.jpg)
70Analog and Mixed-Signal VLSI Design Center
IOWA STATE UNIVERSITY
Bifurcation Simulation
pull up
OH=1
pull down
OL=0
x=0
![Page 71: Role of Op-Amps](https://reader035.vdocument.in/reader035/viewer/2022062316/56815f8f550346895dce9072/html5/thumbnails/71.jpg)
71Analog and Mixed-Signal VLSI Design Center
IOWA STATE UNIVERSITY
Pull-up/Pull Down
pull up
OH=1
pull down
OL=1
x=-0.1mV
![Page 72: Role of Op-Amps](https://reader035.vdocument.in/reader035/viewer/2022062316/56815f8f550346895dce9072/html5/thumbnails/72.jpg)
72Analog and Mixed-Signal VLSI Design Center
IOWA STATE UNIVERSITY
AC Response
50dB gain enhancement
![Page 73: Role of Op-Amps](https://reader035.vdocument.in/reader035/viewer/2022062316/56815f8f550346895dce9072/html5/thumbnails/73.jpg)
73Analog and Mixed-Signal VLSI Design Center
IOWA STATE UNIVERSITY
Step Response
1.8 2 2.2 2.4 2.6 2.8x 10-7
-0.1
-0.05
0
0.05
0.1
time
outp
ut(V
)
before calibrationafter calibration
![Page 74: Role of Op-Amps](https://reader035.vdocument.in/reader035/viewer/2022062316/56815f8f550346895dce9072/html5/thumbnails/74.jpg)
74Analog and Mixed-Signal VLSI Design Center
IOWA STATE UNIVERSITY
Step Response
2.28 2.3 2.32 2.34 2.36 2.38x 10-7
0.0988
0.099
0.0992
0.0994
0.0996
0.0998
0.1
time
outp
ut(V
)
before calibrationafter calibration
Significant Settling
accuracy Improvement
![Page 75: Role of Op-Amps](https://reader035.vdocument.in/reader035/viewer/2022062316/56815f8f550346895dce9072/html5/thumbnails/75.jpg)
75Analog and Mixed-Signal VLSI Design Center
IOWA STATE UNIVERSITY
Robustness Over Temperature
-40 -20 0 20 40 60 80 10050
60
70
80
90
100
110
temperature(C)
DC
Gai
ns (d
B)
No temperature compesation
With Temperature Compensation
![Page 76: Role of Op-Amps](https://reader035.vdocument.in/reader035/viewer/2022062316/56815f8f550346895dce9072/html5/thumbnails/76.jpg)
76Analog and Mixed-Signal VLSI Design Center
IOWA STATE UNIVERSITY
Simulated Performance in 90nm CMOS
Easy Migration
![Page 77: Role of Op-Amps](https://reader035.vdocument.in/reader035/viewer/2022062316/56815f8f550346895dce9072/html5/thumbnails/77.jpg)
77Analog and Mixed-Signal VLSI Design Center
IOWA STATE UNIVERSITY
One Fabricated Amplifier’s Performance
Tab. 1 Simulated DC gain over wide temperature range
Gain (dB)
SS SF FS FF NN
0°C 84 85 72 92 103
27°C 82.2
89 84 85 110
80°C 70.4
84.5
83.7
89 88
AMI 0.5um CMOS
Tab. 2 Measured DC gain of fabricated chipsChip #
1#2 #3 #4 #5
Gain (dB)
90 87.6
89.3
84.5
86.5
manual tuning
![Page 78: Role of Op-Amps](https://reader035.vdocument.in/reader035/viewer/2022062316/56815f8f550346895dce9072/html5/thumbnails/78.jpg)
78Analog and Mixed-Signal VLSI Design Center
IOWA STATE UNIVERSITY
Two-Stage to enhance linearity
Mb
M1 M1
M3 M3
k
Vi1 Vi2
M2 M2
M4 M4
bias1
bias2
CMFB1
CMFB2
![Page 79: Role of Op-Amps](https://reader035.vdocument.in/reader035/viewer/2022062316/56815f8f550346895dce9072/html5/thumbnails/79.jpg)
79Analog and Mixed-Signal VLSI Design Center
IOWA STATE UNIVERSITY
Two stage amp DC Sweep
-2 -1 0 1 2x 10-4
-1
-0.5
0
0.5
1
differential inputs(V)
diffe
rent
ial o
utpu
ts(V
)
![Page 80: Role of Op-Amps](https://reader035.vdocument.in/reader035/viewer/2022062316/56815f8f550346895dce9072/html5/thumbnails/80.jpg)
80Analog and Mixed-Signal VLSI Design Center
IOWA STATE UNIVERSITY
Two stage Gain vs Vout
-1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1110
120
130
140
150
160
170
180
differential outputs(V)
Gai
n(dB
)
Equivalent Gain Plot
>130dBover +- 0.75V
![Page 81: Role of Op-Amps](https://reader035.vdocument.in/reader035/viewer/2022062316/56815f8f550346895dce9072/html5/thumbnails/81.jpg)
81Analog and Mixed-Signal VLSI Design Center
IOWA STATE UNIVERSITY
Amplifier performance summary
• Berkeley projected 90nm process• power supply voltage Vdd=1.1 • two stage total current Itot=18ma• Total power consumption Ptot=20mw• Capacitive load CL=4p • Unity gain frequency UGF = 1.35GHz• Phase margin at UGF = 39 deg• Frequency at gain 2: G2F = 804MHz • Phase margin at G2F = 65 deg
![Page 82: Role of Op-Amps](https://reader035.vdocument.in/reader035/viewer/2022062316/56815f8f550346895dce9072/html5/thumbnails/82.jpg)
82Analog and Mixed-Signal VLSI Design Center
IOWA STATE UNIVERSITY
Switched-Capacitor Amplifier
Vout
S1C1
C2
S2
S3
S4
S1
C1
S2
S5Vin
S4
S3
pos
neg
Vicm
Vicm
C3
Precision Multiply-by-Two Circuit
![Page 83: Role of Op-Amps](https://reader035.vdocument.in/reader035/viewer/2022062316/56815f8f550346895dce9072/html5/thumbnails/83.jpg)
83Analog and Mixed-Signal VLSI Design Center
IOWA STATE UNIVERSITY
100 MS/s
60% swing:0.3Vdiff
Settlingaccuracy:8.9e-4=10.1 bits
Transient Simulation Results
![Page 84: Role of Op-Amps](https://reader035.vdocument.in/reader035/viewer/2022062316/56815f8f550346895dce9072/html5/thumbnails/84.jpg)
84Analog and Mixed-Signal VLSI Design Center
IOWA STATE UNIVERSITY
100 MS/s
full swing0.5Vdiff
Settlingaccuracy:0.0013=9.6 bits
Transient Simulation Results
![Page 85: Role of Op-Amps](https://reader035.vdocument.in/reader035/viewer/2022062316/56815f8f550346895dce9072/html5/thumbnails/85.jpg)
85Analog and Mixed-Signal VLSI Design Center
IOWA STATE UNIVERSITY
80 MS/s
60% swing0.3Vdiff
Settlingaccuracy:2.1e-4=12.24 bits
Transient Simulation Results
![Page 86: Role of Op-Amps](https://reader035.vdocument.in/reader035/viewer/2022062316/56815f8f550346895dce9072/html5/thumbnails/86.jpg)
86Analog and Mixed-Signal VLSI Design Center
IOWA STATE UNIVERSITY
Transient Simulation Results
input=0.25V
output=0.499969V
40 MS/s
Settling accuracy:3.1e-5/0.5=6.2e-5=14.0 bits
![Page 87: Role of Op-Amps](https://reader035.vdocument.in/reader035/viewer/2022062316/56815f8f550346895dce9072/html5/thumbnails/87.jpg)
87Analog and Mixed-Signal VLSI Design Center
IOWA STATE UNIVERSITY
Transient Simulation Results
input=0.25V
output=0.499994V
10 MS/s
Settling accuracy:6e-6/0.5=1.2e-5=16.3 bits