-
8/13/2019 Split Gate Transsistor & Quantam Cell Autumata
1/14
CENTRE OF NANOTECHNOLOGYRTU,KOTA
NANOELECTRONICS
SHOBI BAGGA SIR
CNT,RTU,KOTA
MAHENDRA SINGH YADAV
M.TECH,CNT,RTU,KOTA
-
8/13/2019 Split Gate Transsistor & Quantam Cell Autumata
2/14
2
Split Gate Transistor & Quantu Cell Autoata
Silicon on insulator
T!e a"#anta$es o% SO te'!nolo$( 'oe %ro its )urie" o*i"e +O-. la(er/
0it! t!e re"u'tion o% t!e parasiti' 'apa'itan'es, ostl( as a result o% t!e
re"u'e" "rain1sour'e un'tion 'apa'itan'es/
SO "e#i'es (iel" ipro#e" s3it'!in$ spee" an" re"u'e" po3er 'onsuption/
T!e operatin$ spee" is also ipro#e" sin'e t!e isolate" '!annel %ro
su)strate )ias pre#ents t!e in'rease in a t!res!ol" #olta$e o% sta'4e" SO
transistors/
n a""ition, t!e per%e't lateral an" #erti'al isolation %ro su)strate pro#i"eslat'!5up an" inter5"e#i'e lea4a$e %ree
C6OS te'!nolo$(, re"u'tion in #arious inter%eren'es, an" )etter so%t error
iunit(/
6oreo#er, SO te'!nolo$( o%%ers ti$!ter transistor pa'4in$ "ensit( an"
sipli%ie" pro'essin$
2
-
8/13/2019 Split Gate Transsistor & Quantam Cell Autumata
3/14
7
SO transistors are 'lassi%ie" into t3o t(pes8 9partiall( "eplete" +:;. SO,< i%
t!e sili'on %il +t(pi'all( =>> n or ore. on t!e O- la(er is t!i'4er t!an
t!e "epletion re$ion "ept! )eneat! t!e $ate o*i"e, an" 9%ull( "eplete" +F;.
SO,< i% t!e )o"( +sili'on %il. t!i'4ness is t!in enou$! +t(pi'all( ?> n or
less. or t!e "opin$ 'on'entration o% t!e )o"( is lo3 enou$! to )e %ull(
"eplete"
F; SO transistors !a#e superior a"#anta$es o#er :; SO transistors in ters
o% e*treel( lo3 su)5t!res!ol" s3in$ +@? B1"e'a"e., no %loatin$5)o"(
e%%e'ts, an" lo3 t!res!ol" #olta$e #ariation 3it! teperature +257 ties less.
Ho3e#er, sin'e F; SO transistors are e#en ore sensiti#e to pro'ess
#ariation su'! as t!e sili'on %il la(er #ariation resultin$ in t!res!ol" #olta$e
%lu'tuation, :; SO "e#i'es 3ere 'oer'iall( intro"u'e" %irst/ 0it! 'are%ul"e#i'e "esi$n an" a"#an'e" pro'ess te'!niues, %ull( "eplete" ultrat!in5
)o"( SO +F; UT SO. "e#i'es are 'onsi"ere" as one o% t!e )est s'alin$
options
7
-
8/13/2019 Split Gate Transsistor & Quantam Cell Autumata
4/14
D
0!( ;ou)le5$ate Transistors
10 nm
Feature size
32 nm
;G5FETs 'an )e use" to %ill t!is $ap
;G5FETs are e*tensions o% C6OS
6anu%a'turin$ pro'esses siilar to C6OS
Ke( liitations o% C6OS s'alin$ a""resse" t!rou$!
etter 'ontrol o% '!annel %ro transistor $ates
Re"u'e" s!ort5'!annel e%%e'ts
etter on1o%%
pro#e" su)5t!res!ol" slope
No "is'rete "opant %lu'tuations
:lanar transistors, in 3!i'! t!e $ates an" t!e '!annel are !oriontal,
Fin FETs, in 3!i'! t!e '!annel is #erti'al an" t!e 'on"u'tion is parallel to t!e
3a%er sur%a'e
Berti'al transistors, in 3!i'! t!e 'on"u'tion "ire'tion is #erti'al/
;i%%erent T(pes o% ;G5FETs
D
-
8/13/2019 Split Gate Transsistor & Quantam Cell Autumata
5/14
?
First FinFET 5 ;ELTA +;Eplete" Lean5'!annel
TrAnsistor.
?
-
8/13/2019 Split Gate Transsistor & Quantam Cell Autumata
6/14
;esi$n 5 Geoetr(
H%in T%in
Top $ate o*i"e t!i'4ness si"e3all o*i"e t!i'4ness
-
8/13/2019 Split Gate Transsistor & Quantam Cell Autumata
7/14
E%%e'ti#e '!annel len$t! Le%% I L$ate J 2Le*t
E%%e'ti#e '!annel 3i"t! 0 I T%in J 2H%in
T!e '!annel 'an )e le%t un "ope", t!e t!res!ol" #olta$e )ein$ a"uste" )(
'!oosin$ t!e appropriate etal %or t!e $ate aterial
T!e !ei$!t o% t!is %in 3ill )e at t!e en" t!e ele'tri'al 3i"t! o% t!e "e#i'e/
n"ee", 'ontrar( to planar "e#i'es, t!e 'on"u'tion ta4es pla'e on t!e #erti'al
si"e3alls o% t!e %in/
T!e 'on"u'tion 3i"t! is t!us t3i'e t!e %in !ei$!t +!%in./ As t!e %in !ei$!t is
liite" to t(pi'all( ?>=>> n, FinFETs are usuall( "esi$ne" as ulti%in$ertransistors, 3it! a 'on"u'tion 3i"t! uanti%ie" )( 2!%in/
T!e ipa't o% t!is 3i"t! uantiation on t!e 'ir'uit "esi$n %le*i)ilit( !as to )e
a''ounte" %or/
Furt!erore, in or"er to rea'! !i$! la(out "ensit(, t!e ratio )et3een t!e %in
!ei$!t an" a'!ie#a)le pit'! )et3een t3o su''essi#e %ins !as to )e
a*iie"/
n parti'ular, t!e %in !ei$!t !as to )e !i$!er t!an t!e pit'! )et3een t!e
%in$ers in or"er to o)tain t!e sae "ri#e 'urrent per sili'on area as planar
"ou)le $ate transistors
Tri $ate Transistor
-
8/13/2019 Split Gate Transsistor & Quantam Cell Autumata
8/14
M
In that case, the channel is controlled by the gate on three sides. This device,
called Tri gate has a conduction width given by twice the fin height plus the
fin width.
Tri gate is still a multi finger device, and the pitch between fins has to be
lower than hfin +wfin/2 to obtain higher drive currents per silicon area thanwith planar devices.
This limit is far more strict for Tri gate than for Fin FET, since the fin height
must be as low as the fin width in order to operate in tri gate mode, and
comparable to the gate length to benefit from a good electrostatic channel
control.
To further improve the electrostatic control of the channel, the buried oide
can be slightly etched during the fin patterning. In that case, the gate
material is also deposited below the bottom face of the channel and the
electrostatic control of this bac! interface can be improved
These devices are called "#$ate transistors or %#FETs when the buried oide
is undercut
%#FET and "#$ate architectures are very similar to Trigate, but their channel
control is close to that of a &uadruple#gate device.
M
-
8/13/2019 Split Gate Transsistor & Quantam Cell Autumata
9/14
;esi$n 5 ;epen"en'e o% Bt! an" S S3in$ on H%in
-
8/13/2019 Split Gate Transsistor & Quantam Cell Autumata
10/14
=>
T!e saturation o% Bt! roll5o%% an" S is o)ser#e" 3!en H%in is in'rease" %ro
2> n to > n
T!e 'riti'al H%in nee"e" %or saturation is "epen"ent on T%in
For lar$er T%in, t!e 'riti'al H%in is 'orrespon"in$l( lar$er
;esi$n 5 ;epen"en'e o% Bt! an" S S3in$ on T%in
=>
-
8/13/2019 Split Gate Transsistor & Quantam Cell Autumata
11/14
==
Bt! roll5o%% an" S '!an$e ore an" ore rapi"l( as T%in '!an$in$
%ro => n to > n, an" slo3 "o3n a%ter t!at
Fin t!i'4ness re"u'e 'an suppress s!ort '!annel e%%e'ts, )ut t!e
#ariation 3ill '!an$e t!e per%oran'e o% t!e "e#i'e a lot
On t!e ot!er !an" t!ere is a si$ni%i'ant "ra3)a'4 in SO te'!nolo$(/ Sin'e
t!e O-, 3!i'! !as appro*iatel( =>> ties lo3er t!eral 'on"u'ti#it( t!an
t!at o% sili'on,pre#ents t!eral 'on"u'tion pat! %ro SO transistors to t!e
su)strate, SO transistors are easil( a%%e'te" )( t!e t!eral !eatin$
$enerate" in t!e '!annel, 3!i'! is 'alle" 9Sel%5Heatin$ E%%e'ts/