Stabiliti™ Modbus Programming Guide
Product Models: 30C & 30C3
Purpose and Scope This document describes the Modbus communication protocol and register set used by the Ideal Power 30
kW Stabiliti™ Series Power Conversion Systems. Included in this document is information pertaining to
all control and status registers, accessible via Modbus RTU and Modbus TCP communication protocols.
This document shall be used as a reference manual for the command control and status read-back of Ideal
Power (“IPWR”) 30 kW Stabiliti™ Series Power Conversion Systems (“PCS”). Brief descriptions of each
Modbus register, including format, access level, data-type, range, and functionality are included. This
document should be used in conjunction with other product documentation provided by IPWR, which is
referenced throughout this document.
Revision Date Rev Author Notes
1/23/2017 A Chris Perez Initial draft DOC-00038
Stabiliti™ Modbus Programming Guide DOC-00038 Rev A 2 of 64 Copyright © 2017 Ideal Power Inc. All rights reserved.
Table of Contents Purpose and Scope ........................................................................................................................................... 1
Revision ............................................................................................................................................................ 1
1. Document information ................................................................................................................................. 4
Product and Firmware ................................................................................................................................. 4
Target Group ................................................................................................................................................ 4
Usage ............................................................................................................................................................ 4
2. Modbus Communication Interface ............................................................................................................... 4
2.1 Baud Rate ............................................................................................................................................... 4
2.2 Data Format ........................................................................................................................................... 4
2.3 Device Address ........................................................................................................................................ 5
2.4 Supported Function Codes ..................................................................................................................... 5
3. Message Format ........................................................................................................................................... 5
3.1 Modbus Read Status Query and Response (Function Code 0x03) ........................................................ 5
3.2 Modbus Write Control Query and Response (Function Code 0x06) ...................................................... 6
3.3 Exception Response ................................................................................................................................ 6
3.4 Supported Exception Codes .................................................................................................................... 6
4. PCS Control and Status Registers ............................................................................................................... 7
4.1 Specific Fault Registers (0x0000 – 0x0009) ........................................................................................... 7
4.2 Global Fault Registers (0x000A – 0x003F) .......................................................................................... 10
4.3 Port AC1 Control Registers (0x0040 – 0x005F) ................................................................................... 13
4.4 Port AC1 Status Registers (0x0060 – 0x007F) .................................................................................... 17
4.5 Port DC2 Control Registers (0x0080 – 0x009F) ................................................................................... 22
4.6 Port DC2 Status Registers (0x00A0 – 0x00BF) ................................................................................... 27
4.7 Port DC3 Control Registers (0x00C0 – 0x00DF) ................................................................................. 29
4.8 Port DC3 Status Registers (0x00E0 – 0x00FF) ................................................................................... 34
4.9 System Operation Control Registers (0x0100 – 0x011F) ..................................................................... 36
4.10 System Operation Status Registers (0x0120 – 0x013F) .................................................................... 41
4.11 Thermal Status Registers (0x0160 – 0x017F) .................................................................................... 46
4.12 Diagnostic Control and Status Registers (0x0180 – 0x01BF) ........................................................... 47
5. Interconnection Standards Control and Status Registers ........................................................................ 50
5.1 Low Voltage (LV) Disconnect Control Registers (0x0240 – 0x025F) ................................................... 50
5.2 High Voltage (HV) Disconnect Control Registers (0x0260 – 0x027F) ................................................. 53
5.3 Low Frequency (LF) Disconnect Control Registers (0x0280 – 0x029F) .............................................. 55
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5.4 High Frequency (HF) Disconnect Control Registers (0x02A0 – 0x02BF) ........................................... 58
6. System Communication Control ................................................................................................................ 60
6.1 Modbus RTU Control Registers ........................................................................................................... 60
6.2 Modbus TCP Control Registers ............................................................................................................ 61
6.3 System Load-Save Command, Timezone Update, and ID Readback ................................................. 63
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1. Document information
Product and Firmware This document is valid and applicable for all Stabiliti™ Series 30 kW PCS released with the following
firmware revision:
Firmware 3.1 Build 658
Target Group This document is intended for qualified installation and operating personnel with the following skills:
• Knowledge of Modbus specifications
• Knowledge of distributed grid resource management
• Knowledge of all safety information pertaining to Ideal Power PCS systems, PV systems, energy
storage systems, and the grid
This document assumes familiarity with the network layout and the physical PCS communication
connectivity.
Usage The Modbus interface and the associated register profile are designed for industrial use and remote
control of the PCS. The Modbus interface can be used via TCP (over Ethernet) as well as via RTU (over
the RS485 serial port).
2. Modbus Communication Interface The Modbus protocol is an industrial control communication protocol used by many in the solar and
energy storage industry. This protocol defines a message structure independent of the type of network
over which communication takes place. This protocol describes how a controller (or Modbus server)
requests command control information or status information from a device (or Modbus client), how the
device responds to the request, and how errors are detected and reported. The following sections describe
information pertaining to the Modbus RTU communication interface.
2.1 Baud Rate The supported baud rates for all Modbus RTU communications with the PCS are as follows:
1. 9600 bps
2. 19200 bps
3. 38400 bps
4. 57600 bps
5. 115200 bps
See section 6.1 for information related to Modbus RTU baud rate update over Modbus communications.
2.2 Data Format The supported data formats for all Modbus RTU communications with the PCS are as follows:
1. 8 data bits + 1 even parity bit + 1 stop bit (8-E-1)
2. 8 data bits + 1 odd parity bit + 1 stop bit (8-O-1)
3. 8 data bits + 1 stop bit (8-N-1)
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See section 6.1 for information related to Modbus RTU data format update over Modbus RTU
communications.
2.3 Device Address The PCS supports Modbus device addresses in range of 1 – 247. The default Modbus device address for
Ideal Power PCS systems is set to 240.
See section 6.1 for information related to Modbus device address update over Modbus communications.
2.4 Supported Function Codes The PCS Modbus protocol implementation supports the following standard function codes for
communication with external instruments:
1. Function Code 0x03 (Read Holding Registers) for reading single or multiple registers
2. Function Code 0x06 (Write Single Holding Register) for writing a single register
3. Message Format This section describes the message formatting details for the PCS Modbus communication protocol.
3.1 Modbus Read Status Query and Response (Function Code 0x03) The format for a Modbus read status query message is shown below.
Byte Content Value/Range Description
1 Device Address 0x00-0xF7 (0-247) IPWR 30C or 30C3 PCS Address
2 Function Code 0x03 Read Holding Registers
3 Starting Address Hi 0x00-0xFF (0-255) MSByte of register address
4 Starting Address Lo 0x00-0xFF (0-255) LSByte of register address
5 Quantity of Registers Hi 0x00-0xFF (0-255) MSByte of number of registers
6 Quantity of Registers Lo 0x00-0xFF (0-255) LSByte of number of registers
7 CRC Hi 0x00-0xFF (0-255) MSByte of CRC
8 CRC Lo 0x00-0xFF (0-255) LSByte of CRC
The format for a Modbus read status response message is shown below.
Byte Content Value/Range Description
1 Device Address 0x00-0xF7 (0-247) IPWR 30C or 30C3 PCS Address
2 Function Code 0x03 Read Holding Registers
3 Byte Count 0x00-0xFF (0-255) Num bytes (N) in response
4 Data 1 0x00-0xFF (0-255) Data byte 1 (MSByte of reg 1)
5 Data 2 0x00-0xFF (0-255) Data byte 2 (LSByte of reg 1)
… … … …
N+2 Data N-1 0x00-0xFF (0-255) Data byte N-1 (MSByte of reg N/2)
N+3 Data N 0x00-0xFF (0-255) Data byte N (LSByte of reg N/2)
N+4 CRC Hi 0x00-0xFF (0-255) MSByte of CRC
N+5 CRC Lo 0x00-0xFF (0-255) LSByte of CRC
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3.2 Modbus Write Control Query and Response (Function Code 0x06) The format for a Modbus write control query message is shown below.
Byte Content Value/Range Description
1 Device Address 0x00-0xF7 (0-247) IPWR 30C or 30C3 PCS Address
2 Function Code 0x06 Write Single Holding Register
3 Register Address Hi 0x00-0xFF (0-255) MSByte of register address
4 Register Address Lo 0x00-0xFF (0-255) LSByte of register address
5 Data to Write Hi 0x00-0xFF (0-255) MSByte of data to write
6 Data to Write Lo 0x00-0xFF (0-255) LSByte of data to write
7 CRC Hi 0x00-0xFF (0-255) MSByte of CRC
8 CRC Lo 0x00-0xFF (0-255) LSByte of CRC
The format for a Modbus write control response message is shown below.
Byte Content Value/Range Description
1 Device Address 0x00-0xF7 (0-247) IPWR 30C or 30C3 PCS Address
2 Function Code 0x06 Write Single Holding Register
3 Register Address Hi 0x00-0xFF (0-255) MSByte of register address
4 Register Address Lo 0x00-0xFF (0-255) LSByte of register address
5 Data to Write Hi 0x00-0xFF (0-255) MSByte of data to write
6 Data to Write Lo 0x00-0xFF (0-255) LSByte of data to write
7 CRC Hi 0x00-0xFF (0-255) MSByte of CRC
8 CRC Lo 0x00-0xFF (0-255) LSByte of CRC
3.3 Exception Response The format for a Modbus exception response message is shown below.
Byte Content Value/Range Description
1 Device Address 0x00-0xF7 (0-247) IPWR 30C or 30C3 PCS Address
2 Function Code 0x83 or 0x86 MSB set in Function Code
3 Exception Code 0x00-0x04 Supported Exception Code
7 CRC Hi 0x00-0xFF (0-255) MSByte of CRC
8 CRC Lo 0x00-0xFF (0-255) LSByte of CRC
3.4 Supported Exception Codes The PCS Modbus implementation supports the following exception codes:
1. Exception code 0x01 – Illegal function
2. Exception code 0x02 – Illegal data address
3. Exception code 0x03 – Illegal data value
4. Exception code 0x04 – Slave device failure
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4. 30C and 30C3 PCS Control and Status Registers This section provides detailed descriptions of the PCS Modbus control and status registers, including
register type, format, range, default value, access level, and functionality. Each register description listed
here will include the following information:
1. Address – Hexadecimal 16-bit value representing Modbus register address
2. Access – RW (read-write) or R (read only)
3. Data-type – Format of 16-bit value to write or read. IPWR PCS data-types are defined as:
a. U16 – Unsigned 16-bit integer (0 – 65535)
b. S16 – Signed 16-bit integer (-32768 – 32767)
c. HEX – Hexadecimal 16-bit value (may indicate bit-specific functionality, or a bit-map)
d. POWER – Signed 16-bit integer representing active power in units of 10W
e. VAR – Signed 16-bit integer representing reactive power in units of 10VAR
f. VA – Signed 16-bit integer representing apparent power in units of 10VA
g. PF – Signed 16-bit integer representing signed power factor in units of 0.01
h. CURRENT – Signed 16-bit integer representing current in units of 0.1A
i. VOLTAGE – Signed 16-bit integer representing voltage in units of 1V
j. FREQ – Unsigned 16-bit integer representing frequency in units of 0.001Hz
k. TEMP – Signed 16-bit integer representing temperature in units of 0.1 °C
l. RPM – Unsigned 16-bit integer representing fan speed in units of 1RPM
m. MINUTES – Unsigned 16-bit integer representing time-of-day via elapsed minutes from
00:00 (midnight at start of day), e.g. 425 represents 07:05.
n. BAUD – Unsigned 16-bit integer representing baud rate in units of 100 bps
o. STRING – 16-bit value representing 2-character ASCII string (consecutive registers of type
STRING represent concatenated characters of a string)
4. Range – Allowable data range for write access
5. Default – Default 16-bit value read back
4.1 Specific Fault Registers (0x0000 – 0x0009) The following register set provides details pertaining to a single specific PCS fault.
4.1.1 fault_index Address: 0x0000 (0)
Access: RW
Data-type: U16
Range: 0 – 63
Default: NA
The fault_index register controls the fault pointer. The value of this pointer register is the fault number
for which status information will be populated in fault-specific status registers in address range 0x0001 –
0x0009. This register can select fault number 0 thru fault number 63 for fault-specific status read-back.
4.1.2 fault_limit Address: 0x0001 (1)
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Access: R
Data-type: U16
Range: NA
Default: NA
The fault_limit register reads the limit used in determining if the fault pointed to is active.
4.1.3 fault_value Address: 0x0002 (2)
Access: R
Data-type: U16
Range: NA
Default: NA
The fault_value register reads the offending value used in determining if the fault pointed to by
fault_index is active.
4.1.4 fault_count Address: 0x0003 (3)
Access: R
Data-type: U16
Range: NA
Default: NA
The fault_count register reads a count of the number of times the fault pointed to has occurred.
4.1.5 fault_utime_0 Address: 0x0004 (4)
Access: R
Data-type: U16
Range: NA
Default: NA
The fault_utime_0 register reads the lower 16-bit word of the UNIX timestamp of the last occurrence of
the fault pointed to.
4.1.6 fault_utime_1 Address: 0x0005 (5)
Access: R
Data-type: U16
Range: NA
Default: NA
The fault_utime_1 register reads the upper 16-bit word of the UNIX timestamp of the last occurrence of
the fault pointed to.
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4.1.7 fault_selector Address: 0x0008 (8)
Access: R
Data-type: HEX
Range: NA
Default: NA
The register reads back a bit-map value useful for IPWR diagnosis of the fault pointed to. In several fault
instances, there may be multiple sources. This register identifies the source for such faults. Refer to
IPWRPCS Fault documentation to interpret the 2-bit value represented by fault_selector.
Bit 7 6 5 4 3 2 1 0
Description Reserved Fault selector [1:0]
Bit 15 14 13 12 11 10 9 8
Description Reserved
4.1.8 fault_status Address: 0x0009 (9)
Access: R
Data-type: HEX
Range: NA
Default: NA
The register reads back the current status of the fault pointed to.
fault_status[4:3] –
00 – Fault disabled
01 – Fault is not active and has not occurred since last power-up
10 – Fault is active
11 – Fault is not active and has occurred since last power-up
fault_status[2:0] –
000 – INFO: internal informational event
001 – ALERT: fault counter incremented only, operation continues
010 – ALARM: fault is logged in PCS black-box, operation continues
011 – ABORT-0: fault is logged in PCS black-box, operation stops
100 – ABORT-1: fault is logged in PCS black-box, operation stops
101 – ABORT-2: fault is logged in PCS black-box, operation stops
110 – LOCKDOWN: fault is logged in PCS black-box, operation stops, and PCS requires a reset
111 – Reserved
Bit 7 6 5 4 3 2 1 0
Description Reserved Fault status Fault severity
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Bit 15 14 13 12 11 10 9 8
Description Reserved
4.2 Global Fault Registers (0x000A – 0x003F) The following register set provides IPWR PCS global fault status, watchdog control, and fault clearing
control.
4.2.1 fault_global_control Address: 0x000C (12)
Access: RW
Data-type: HEX
Range: 0 – 1
Default: 0
The fault_global_control register allows user to reset all faults, including all fault counters and
timestamps. This register is self-clearing.
Bit 7 6 5 4 3 2 1 0
Description Reserved Fault reset
Bit 15 14 13 12 11 10 9 8
Description Reserved
4.2.2 fault_active_0 Address: 0x0010 (16)
Access: R
Data-type: HEX
Range: NA
Default: NA
The fault_active_0 register indicates the active state of faults 15 – 0.
Bit 7 6 5 4 3 2 1 0
Description Fault 7
active
Fault 6
active
Fault 5
active
Fault 4
active
Fault 3
active
Fault 2
active
Fault 1
active
Fault 0
active
Bit 15 14 13 12 11 10 9 8
Description Fault 15
active
Fault 14
active
Fault 13
active
Fault 12
active
Fault 11
active
Fault 10
active
Fault 9
active
Fault 8
active
4.2.3 fault_active_1 Address: 0x0011 (17)
Access: R
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Data-type: HEX
Range: NA
Default: NA
The fault_active_1 register indicates the active state of faults 31 – 16.
Bit 7 6 5 4 3 2 1 0
Description Fault 23
active
Fault 22
active
Fault 21
active
Fault 20
active
Fault 19
active
Fault 18
active
Fault 17
active
Fault 16
active
Bit 15 14 13 12 11 10 9 8
Description Fault 31
active
Fault 30
active
Fault 29
active
Fault 28
active
Fault 27
active
Fault 26
active
Fault 25
active
Fault 24
active
4.2.4 fault_active_2 Address: 0x0012 (18)
Access: R
Data-type: HEX
Range: NA
Default: NA
The fault_active_2 register indicates the active state of faults 47 – 32.
Bit 7 6 5 4 3 2 1 0
Description Fault 39
active
Fault 38
active
Fault 37
active
Fault 36
active
Fault 35
active
Fault 34
active
Fault 33
active
Fault 32
active
Bit 15 14 13 12 11 10 9 8
Description Fault 47
active
Fault 46
active
Fault 45
active
Fault 44
active
Fault 43
active
Fault 42
active
Fault 41
active
Fault 40
active
4.2.5 fault_active_3 Address: 0x0013 (19)
Access: R
Data-type: HEX
Range: NA
Default: NA
The fault_active_3 register indicates the active state of faults 63 – 48.
Bit 7 6 5 4 3 2 1 0
Description Fault 55
active
Fault 54
active
Fault 53
active
Fault 52
active
Fault 51
active
Fault 50
active
Fault 49
active
Fault 48
active
Bit 15 14 13 12 11 10 9 8
Description Fault 63
active
Fault 62
active
Fault 61
active
Fault 60
active
Fault 59
active
Fault 58
active
Fault 57
active
Fault 56
active
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4.2.6 fault_occurred_0 Address: 0x0018 (24)
Access: R
Data-type: HEX
Range: NA
Default: NA
The fault_occurred_0 register indicates the occurred state of faults 15 – 0.
Bit 7 6 5 4 3 2 1 0
Description Fault 7
occurred
Fault 6
occurred
Fault 5
occurred
Fault 4
occurred
Fault 3
occurred
Fault 2
occurred
Fault 1
occurred
Fault 0
occurred
Bit 15 14 13 12 11 10 9 8
Description Fault 15
occurred
Fault 14
occurred
Fault 13
occurred
Fault 12
occurred
Fault 11
occurred
Fault 10
occurred
Fault 9
occurred
Fault 8
occurred
4.2.7 fault_occurred_1 Address: 0x0019 (25)
Access: R
Data-type: HEX
Range: NA
Default: NA
The fault_occurred_1 register indicates the occurred state of faults 31 – 16.
Bit 7 6 5 4 3 2 1 0
Description Fault 23
occurred
Fault 22
occurred
Fault 21
occurred
Fault 20
occurred
Fault 19
occurred
Fault 18
occurred
Fault 17
occurred
Fault 16
occurred
Bit 15 14 13 12 11 10 9 8
Description Fault 31
occurred
Fault 30
occurred
Fault 29
occurred
Fault 28
occurred
Fault 27
occurred
Fault 26
occurred
Fault 25
occurred
Fault 24
occurred
4.2.8 fault_occurred_2 Address: 0x001A (26)
Access: R
Data-type: HEX
Range: NA
Default: NA
The fault_occurred_2 register indicates the occurred state of faults 47 – 32.
Bit 7 6 5 4 3 2 1 0
Description Fault 39
occurred
Fault 38
occurred
Fault 37
occurred
Fault 36
occurred
Fault 35
occurred
Fault 34
occurred
Fault 33
occurred
Fault 32
occurred
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Bit 15 14 13 12 11 10 9 8
Description Fault 47
occurred
Fault 46
occurred
Fault 45
occurred
Fault 44
occurred
Fault 43
occurred
Fault 42
occurred
Fault 41
occurred
Fault 40
occurred
4.2.9 fault_occurred_3 Address: 0x001B (27)
Access: R
Data-type: HEX
Range: NA
Default: NA
The fault_occurred_3 register indicates the occurred state of faults 63 – 48.
Bit 7 6 5 4 3 2 1 0
Description Fault 55
occurred
Fault 54
occurred
Fault 53
occurred
Fault 52
occurred
Fault 51
occurred
Fault 50
occurred
Fault 49
occurred
Fault 48
occurred
Bit 15 14 13 12 11 10 9 8
Description Fault 63
occurred
Fault 62
occurred
Fault 61
occurred
Fault 60
occurred
Fault 59
occurred
Fault 58
occurred
Fault 57
occurred
Fault 56
occurred
4.2.10 watchdog Address: 0x0028 (40)
Access: RW
Data-type: S16
Range: 0 – 32767
Default: 0
The user watchdog register is disabled when 0 is written, and enabled when a value in range 1 – 32767 is
written. Once enabled, the watchdog register decrements by 1 every second, until expiring at the
transition from 0 to -1. Once expired, the PCS issues an ABORT-2 fault which halts power conversion and
logs all fault information.
4.3 Port AC1 Control Registers (0x0040 – 0x005F) The following register set provides command control for the PCS port AC1.
4.3.1 p1_control_method Address: 0x0041 (65)
Access: RW
Data-type: HEX
Range: NA
Default: 0x0000
The p1_control_method register defines the AC1 port power conversion method. Allowable values for this
port are:
1. 0x0000 – IDLE: AC1 port is off
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2. 0x0001 – NET: AC1 port set as NET port (maintains energy conservation for system). Used only
in AC grid-following application.
3. 0x0402 – GPWR: AC1 port set for constant real power control. Used only in AC grid-following
application.
4. 0x0502 – FPWR: AC1 port set for facility power. Used for microgrid/off-grid applications, as well
as applications requiring seamless transition from off-grid to grid-following applications.
4.3.2 p1_power_ramp_rate Address: 0x0042 (66)
Access: RW
Data-type: POWER
Range: 1 – 8000 (10W/sec – 80kW/sec)
Default: 250 (2.5kW/sec)
The p1_power_ramp_rate register defines the normal-operations power ramp rate used in GPWR
constant real power control and in NET control. This register is set in units of 10W/sec, e.g. a setting of
500 results in GPWR control ramping real power to the specified setpoint at a rate of 5kW/sec. This ramp
rate is used for both normal power transitions (going from one setpoint to another), as well as for startup
ramp-up.
4.3.3 p1_throttle_port Address: 0x0043 (67)
Access: RW
Data-type: HEX
Range: 0 – 1
Default: 0x0000
The p1_throttle_port register defines the port to throttle back power on once the soft-power or soft-current
limit is reached on the AC1 port in NET control.
p1_throttle_port[0] –
0 – Throttle back on DC3 port if DC3 is active; if DC3 is inactive, throttle back on DC2 port.
1 – Throttle back on DC2 port if DC2 is active; if DC2 is inactive, throttle back on DC3 port.
Bit 7 6 5 4 3 2 1 0
Description Reserved Throttle
port
Bit 15 14 13 12 11 10 9 8
Description Reserved
4.3.4 p1_real_pwr_setpt Address: 0x0044 (68)
Access: RW
Data-type: POWER
Range: -3200 – 3200 (-32kW – 32kW)
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Default: 0
The p1_real_pwr_setpt defines the real power setpoint when AC1 is set for the following power control
methods:
1. FPWR1
2. GPWR
This register is ignored if AC1 is set for NET power control. The register is set in units of 10W.
4.3.5 p1_react_pwr_setpt Address: 0x0045 (69)
Access: RW
Data-type: VAR
Range: -2150 – 2150 (-21.5kVAR – 21.5kVAR)
Default: 0
The p1_react_pwr_setpt defines the reactive power setpoint when AC1 is set for the following power
control methods:
1. FPWR1
2. GPWR
This register is ignored if AC1 is set for NET power control. The register is set in units of 10VAR.
4.3.6 p1_power_factor_setpt Address: 0x0046 (70)
Access: RW
Data-type: S16
Range: 50 – 150
Default: 100
The p1_power_factor_setpt defines the power factor setpoint when AC1 is set to be the NET power control
port. The register is set in units of 0.01. The value entered in this register determines the effective signed
power factor to control by the following equation:
𝑝𝑓(𝑥) = 𝑥 − 200, 150 > 𝑥 > 100
𝑥, 50 < 𝑥 < 100
For example, if p1_power_factor_setpt is set to 125, the PCS will set the observed power factor to -0.75. If
the p1_power_factor register is set to 80, the PCS will set the observed power factor +0.80.
4.3.7 p1_voltage_setpt Address: 0x0047 (71)
Access: RW
Data-type: VOLTAGE
Range: 0 - 532
Default: 480
1 If AC1 is set to FPWR control, registers p1_real_pwr_setpt and p1_react_pwr_setpt will take effect on utility grid presence.
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The p1_voltage_setpt defines the microgrid RMS voltage (line-line) setpoint when AC1 is set to FPWR
control. This register is ignored if AC1 is set to NET control or GPWR control, or if the utility grid is
present when in FPWR control. The register is set in units of 1V.
4.3.8 p1_frequency_setpt Address: 0x0048 (72)
Access: RW
Data-type: FREQ
Range: 45000 - 65000
Default: 60000
The p1_frequency_setpt defines the microgrid frequency setpoint when AC1 is set to FPWR control. This
register is ignored if AC1 is set to NET control or GPWR control, or if the utility grid is present when in
FPWR control. The register is set in units of 0.001Hz.
4.3.9 p1_reactive_ctrl Address: 0x004A (74)
Access: RW
Data-type: HEX
Range: 0 – 1
Default: 0
The p1_reactive_ctrl register enables or disables AC1 reactive power control.
p1_reactive_ctrl[0] –
0 – Reactive power control is disabled.
1 – Reactive power control is enabled (GPWR control of constant reactive power, or NET control of
power factor)
Bit 7 6 5 4 3 2 1 0
Description Reserved
Reactive
control
enabled
Bit 15 14 13 12 11 10 9 8
Description Reserved
4.3.10 p1_react_power_limit Address: 0x0058 (88)
Access: RW
Data-type: VAR
Range: 0 – 2150 (0 – 21.5kVAR)
Default: 1500 (15kVAR)
The p1_react_power_limit defines the reactive power soft limit for the AC1 port. The register defines the
limit for reactive power generation or absorption at the AC1 port during power conversion. The register is
set in units of 10VAR.
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4.3.11 p1_real_power_limit Address: 0x0059 (89)
Access: RW
Data-type: POWER
Range: 0 – 3200 (0 – 32kW)
Default: 3200 (32kW)
The p1_real_power_limit defines the real power soft limit for the AC1 port. The register defines the limit
for real power generation or loading at the AC1 port during power conversion. The register is set in units
of 10W.
4.3.12 p1_current_limit Address: 0x005A (90)
Access: RW
Data-type: CURRENT
Range: 0 – 440 (0 – 44A)
Default: 400 (40A)
The p1_current_limit defines the current soft limit for the AC1 port. The register defines the limit for the
AC line currents at the AC1 port during power conversion. The register is set in units of 0.1A.
4.4 Port AC1 Status Registers (0x0060 – 0x007F) The following register set provides status read-back for the PCS port AC1.
4.4.1 p1_port_status Address: 0x0060 (96)
Access: R
Data-type: HEX
Range: NA
Default: NA
The p1_port_status register reads back the status of the AC1 port.
p1_port_status[0] – AC1 port is real power soft-limiting
p1_port_status[1] – AC1 port is current soft-limiting
p1_port_status[2] – AC1 port is reactive power soft-limiting
p1_port_status[3] – AC1 port is power derated (limited) due to high temperature
p1_port_status[4] – Reserved
p1_port_status[5] – AC1 port is throttling back on port DC2 due to soft-limiting
p1_port_status[6] – Reserved
p1_port_status[7] – AC1 port is throttling back on port DC3 due to soft-limiting
p1_port_status[8] – AC1 port has the seamless transfer feature enabled when in FPWR control
p1_port_status[9] – The PCS SEL-547 interface transfer switch HW is indicating the PCS is islanded
(islanding contactor is commanded to open). If enabled, the PCS is able to form a
microgrid in FPWR control.
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p1_port_status[10] – The PCS SEL-547 interface transfer switch HW is indicating the PCS is islanded
(islanding contactor has successfully opened). If enabled, the PCS is able to form a
microgrid in FPWR control.
Bit 7 6 5 4 3 2 1 0
Description Throttling
DC3 Reserved
Throttling
DC2 Reserved
Power
derating for
thermal
Reactive
power
limiting
Current
limiting
Real power
limiting
Bit 15 14 13 12 11 10 9 8
Description Reserved
PCS
islanded
(ACK)
PCS
islanded
Seamless
enabled
4.4.2 p1_real_pwr_ramped Address: 0x0064 (100)
Access: R
Data-type: POWER
Range: NA
Default: NA
The p1_real_pwr_ramped reads back the ramping control point for real power when the PCS is
performing power conversion and the AC1 port is set for GPWR or FPWR2 control. The register is read
back in units of 10W.
4.4.3 p1_reactive_pwr_ramped Address: 0x0065 (101)
Access: R
Data-type: VAR
Range: NA
Default: NA
The p1_reactive_pwr_ramped reads back the ramping control point for reactive power when the PCS is
performing power conversion and the AC1 port is set for GPWR or FPWR2. The register is read back in
units of 10VAR.
4.4.4 p1_frequency Address: 0x0069 (105)
Access: R
Data-type: FREQ
Range: NA
Default: NA
The p1_frequency register reads back the AC1 port frequency. This register is read back in units of
0.001Hz.
2 Constant real power control enabled for FPWR only when PCS is grid-following (AC grid is present).
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4.4.5 p1_v_ab_rms Address: 0x006D (109)
Access: R
Data-type: VOLTAGE
Range: NA
Default: NA
The p1_v_ab_rms register reads back the AC1 port phase A-phase B (line-line) RMS voltage. This register
is read back in units of 1V.
4.4.6 p1_v_bc_rms Address: 0x006E (110)
Access: R
Data-type: VOLTAGE
Range: NA
Default: NA
The p1_v_bc_rms register reads back the AC1 port phase B-phase C (line-line) RMS voltage. This register
is read back in units of 1V.
4.4.7 p1_v_ca_rms Address: 0x006F (111)
Access: R
Data-type: VOLTAGE
Range: NA
Default: NA
The p1_v_ca_rms register reads back the AC1 port phase C-phase A (line-line) RMS voltage. This register
is read back in units of 1V.
4.4.8 p1_v_an_rms Address: 0x0070 (112)
Access: R
Data-type: VOLTAGE
Range: NA
Default: NA
The p1_v_an_rms register reads back the AC1 port phase A (line-neutral) RMS voltage. This register is
read back in units of 1V.
4.4.9 p1_v_bn_rms Address: 0x0071 (113)
Access: R
Data-type: VOLTAGE
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Range: NA
Default: NA
The p1_v_bn_rms register reads back the AC1 port phase B (line-neutral) RMS voltage. This register is
read back in units of 1V.
4.4.10 p1_v_cn_rms Address: 0x0072 (114)
Access: R
Data-type: VOLTAGE
Range: NA
Default: NA
The p1_v_cn_rms register reads back the AC1 port phase C (line-neutral) RMS voltage. This register is
read back in units of 1V.
4.4.11 p1_power_factor Address: 0x0076 (118)
Access: R
Data-type: PF
Range: NA
Default: NA
The p1_power_factor register reads back the AC1 port power factor. This register is read back in units of
0.01, and will read back a value in the range -99 to +100, corresponding to -0.99 to +1.00.
4.4.12 p1_real_power Address: 0x0077 (119)
Access: R
Data-type: POWER
Range: NA
Default: NA
The p1_real_power register reads back the AC1 port real power. This register is read back in units of
10W. For this register, a positive value read-back indicates AC1 port is generating (sourcing) real power,
while a negative value read-back indicates AC1 port is loading (sinking) real power.
4.4.13 p1_reactive_power Address: 0x0078 (120)
Access: R
Data-type: VAR
Range: NA
Default: NA
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The p1_reactive_power register reads back the AC1 port reactive power. This register is read back in
units of 10VAR. For this register, a positive value read-back indicates AC1 port is generating (sourcing)
reactive power, while a negative value read-back indicates AC1 port is absorbing (sinking) reactive power.
4.4.14 p1_apparent_power Address: 0x0079 (121)
Access: R
Data-type: VA
Range: NA
Default: NA
The p1_apparent_power register reads back the AC1 port apparent power. This register is read back in
units of 10VA. This register is signed internally to match the direction of real power flow, i.e. shown as a
positive number if exporting real power, and shown as a negative number if importing real power.
4.4.15 p1_i_a_int_rms Address: 0x007A (122)
Access: R
Data-type: CURRENT
Range: NA
Default: NA
The p1_i_a_int_rms register reads back the AC1 port phase A RMS current internal to the PCS. This
current does not include the contribution from the AC1 port line capacitance. This register is read back in
units of 0.1A.
4.4.16 p1_i_b_int_rms Address: 0x007B (123)
Access: R
Data-type: CURRENT
Range: NA
Default: NA
The p1_i_b_int_rms register reads back the AC1 port phase B RMS current internal to the PCS. This
current does not include the contribution from the AC1 port line capacitance. This register is read back in
units of 0.1A.
4.4.17 p1_i_c_int_rms Address: 0x007C (124)
Access: R
Data-type: CURRENT
Range: NA
Default: NA
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The p1_i_c_int_rms register reads back the AC1 port phase C RMS current internal to the PCS. This
current does not include the contribution from the AC1 port line capacitance. This register is read back in
units of 0.1A.
4.4.18 p1_i_a_ext_rms Address: 0x007D (125)
Access: R
Data-type: CURRENT
Range: NA
Default: NA
The p1_i_a_ext_rms register reads back the AC1 port phase A RMS current. This is the RMS current
observed at the AC connect terminals. This register is read back in units of 0.1A.
4.4.19 p1_i_b_ext_rms Address: 0x007E (126)
Access: R
Data-type: CURRENT
Range: NA
Default: NA
The p1_i_b_ext_rms register reads back the AC1 port phase B RMS current. This is the RMS current
observed at the AC connect terminals. This register is read back in units of 0.1A.
4.4.20 p1_i_c_ext_rms Address: 0x007F (127)
Access: R
Data-type: CURRENT
Range: NA
Default: NA
The p1_i_c_ext_rms register reads back the AC1 port phase C RMS current. This is the RMS current
observed at the AC connect terminals. This register is read back in units of 0.1A.
4.5 Port DC2 Control Registers (0x0080 – 0x009F) The following register set provides command control for the PCS port DC2.
4.5.1 p2_control_method Address: 0x0081 (129)
Access: RW
Data-type: HEX
Range: NA
Default: 0x0000
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The p2_control_method register defines the DC2 port power conversion method. Allowable values for this
port are:
1. 0x0000 – IDLE: DC2 port is off
2. 0x0001 – NET: DC2 port set as NET port (maintains energy conservation for system).
3. 0x0002 – PV/MPPT: DC2 port set for MPPT control for PV applications.
4. 0x0301 – CURR: DC2 port set for constant current control.
5. 0x0401 – PWR: DC2 port set for constant power control.
6. 0x0501 – VOLT: DC2 port set for constant voltage control.
4.5.2 p2_throttle_port Address: 0x0083 (131)
Access: RW
Data-type: HEX
Range: 0 – 1
Default: 0x0000
The p2_throttle_port register defines the port to throttle back power on once the soft-power or soft-current
limit is reached on the DC2 port in NET control.
p2_throttle_port[0] –
0 – Throttle back on DC3 port if DC3 is active; if DC3 is inactive, throttle back on AC1 port.
1 – Throttle back on AC1 port if AC1 is active; if AC1 is inactive, throttle back on DC3 port.
Bit 7 6 5 4 3 2 1 0
Description Reserved Throttle
port
Bit 15 14 13 12 11 10 9 8
Description Reserved
4.5.3 p2_current_setpt Address: 0x0084 (132)
Access: RW
Data-type: CURRENT
Range: -620 – 620 (-62A – 62A)
Default: 0
The p2_current_setpt register defines the DC2 current setpoint when DC2 is set for constant current
control. This register is ignored if DC2 is set for any other control method. The register is set in units of
0.1A.
4.5.4 p2_power_setpt Address: 0x0085 (133)
Access: RW
Data-type: POWER
Range: -3200 – 3200 (-32kW – 32kW)
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Default: 0
The p2_power_setpt register defines the DC2 power setpoint when DC2 is set for constant power control.
The register is set in units of 10W.
4.5.5 p2_voltage_setpt Address: 0x0086 (134)
Access: RW
Data-type: VOLTAGE
Range: 0 – 1000
Default: 0
The p2_voltage_setpt register defines the voltage setpoint when DC2 is set for constant voltage control.
The register is set in units of 1V.
4.5.6 p2_pv_start_tod_setpt Address: 0x0087 (135)
Access: RW
Data-type: MINUTES
Range: 0 – 1440 (00:00 – 24:00)
Default: 0
The p2_pv_start_tod_setpt register defines the time-of-day to start power conversion operations for DC2 if
the DC2 control method is set for PV/MPPT. If the PCS is set for auto-control mode, and DC2 is set for
PV/MPPT, the PCS will attempt to start tracking to the PV maximum power point at the time-of-day
specified by register p2_pv_start_tod_setpt. The register is in units of elapsed minutes from 00:00, or
midnight start-of-day.
4.5.7 p2_pv_stop_tod_setpt Address: 0x0088 (136)
Access: RW
Data-type: MINUTES
Range: 0 – 1440 (00:00 – 24:00)
Default: 1440
The p2_pv_stop_tod_setpt register defines the time-of-day to stop power conversion operations for DC2 if
the DC2 control method is set for PV/MPPT. If the PCS is set for auto-control mode, and DC2 is set for
PV/MPPT, the PCS will stop tracking to the PV maximum power point at the time-of-day specified by
register p2_pv_stop_tod_setpt. The register is in units of elapsed minutes from 00:00, or midnight start-
of-day.
4.5.8 p2_pv_restart_setpt Address: 0x0089 (137)
Access: RW
Data-type: U16
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Range: 10 – 1800
Default: 20
The p2_pv_restart_setpt register defines the setting for the PV/MPPT restart counter in seconds. The
function of this restart counter is to hold off power conversion re-start for a specified duration if the PV
voltage drops below the limit set by register p2_pv_min_v_setpt. The register is in units of seconds.
4.5.9 p2_pv_min_v_setpt Address: 0x008A (138)
Access: RW
Data-type: VOLTAGE
Range: 0 – 1000
Default: 100
The p2_pv_min_v_setpt register defines the lower limit for the PV/MPPT voltage. If the DC2 PV voltage
drops below this limit, the restart function stops PV power conversion for the specified duration set by
register p2_pv_restart_setpt. When the restart counter expires, the DC2 PV port will attempt to restart
power conversion if the voltage is above register p2_pv_min_v_setpt. The register is in units of 1V.
4.5.10 p2_v_pn_max_limit Address: 0x008D (141)
Access: RW
Data-type: VOLTAGE
Range: -20 – 1050
Default: 1050
The p2_v_pn_max_limit voltage register defines the upper limit for the DC2 port. If the DC2 voltage rises
above this limit, the DC over-voltage fault is set, the PCS stops power conversion. The register is set in
units of 1V.
4.5.11 p2_v_pn_min_limit Address: 0x008E (142)
Access: RW
Data-type: VOLTAGE
Range: -20 – 1050
Default: 100
The p2_v_pn_min_limit voltage register defines the lower limit for the DC2 port. If the DC2 voltage drops
below this limit, the DC under-voltage fault is set, the PCS stops power conversion. The register is set in
units of 1V.
4.5.12 p2_current_ramp_rate Address: 0x008F (143)
Access: RW
Data-type: CURRENT
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Range: 1 – 25000 (0.1A/sec – 2500A/sec)
Default: 50 (5A/sec)
The p2_current_ramp_rate register defines the current ramp rate used for DC2 constant current control.
This register is set in units of 0.1A/sec, e.g. a setting of 500 results in DC2 controls ramping current up or
down to the specified setpoint at a rate of 50A/sec.
4.5.13 p2_power_ramp_rate Address: 0x0090 (144)
Access: RW
Data-type: POWER
Range: 1 – 25000 (10W/sec – 250kW/sec)
Default: 250 (2.5kW/sec)
The p2_power_ramp_rate register defines the power ramp rate used for DC2 constant power control. This
register is set in units of 10W/sec, e.g. a setting of 500 results in DC2 controls ramping power up or down
to the specified setpoint at a rate of 5kW/sec.
4.5.14 p2_voltage_ramp_rate Address: 0x0091 (145)
Access: RW
Data-type: VOLTAGE
Range: 1 – 1000 (1V/sec – 1000V/sec)
Default: 50 (50V/sec)
The p2_voltage_ramp_rate register defines the voltage ramp rate used for DC2 constant voltage control.
This register is set in units of 1V/sec, e.g. a setting of 200 results in DC2 controls ramping voltage up or
down to the specified setpoint at a rate of 200V/sec.
4.5.15 p2_power_limit Address: 0x0099 (153)
Access: RW
Data-type: POWER
Range: 0 – 3200 (0 – 32kW)
Default: 3200 (32kW)
The p2_power_limit defines the power soft limit for the DC2 port. The register defines the limit for power
generation or loading at the DC2 port during power conversion. The register is set in units of 10W.
4.5.16 p2_current_limit Address: 0x009A (154)
Access: RW
Data-type: CURRENT
Range: 0 – 640 (0 – 64A)
Default: 600 (60A)
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The p2_current_limit defines the current soft limit for the DC2 port. The register defines the limit for the
DC current at the DC2 port during power conversion. The register is set in units of 0.1A.
4.6 Port DC2 Status Registers (0x00A0 – 0x00BF) The following register set provides status read-back for the PCS port DC2.
4.6.1 p2_port_status Address: 0x00A0 (160)
Access: R
Data-type: HEX
Range: NA
Default: NA
The p2_port_status register reads back the status of the DC2 port.
p2_port_status[0] – DC2 port is power soft-limiting
p2_port_status[1] – DC2 port is current soft-limiting
p2_port_status[2] – Reserved
p2_port_status[3] – DC2 port is power derated (limited) due to high temperature
p2_port_status[4] – Reserved
p2_port_status[5] – DC2 port is throttling back on port AC1 due to soft-limiting
p2_port_status[6] – Reserved
p2_port_status[7] – DC2 port is throttling back on port DC3 due to soft-limiting
Bit 7 6 5 4 3 2 1 0
Description Throttling
DC3 Reserved
Throttling
AC1 Reserved
Power
derating for
thermal
Reserved Current
limiting
Power
limiting
Bit 15 14 13 12 11 10 9 8
Description Reserved
4.6.2 p2_current_ramped Address: 0x00A4 (164)
Access: R
Data-type: CURRENT
Range: NA
Default: NA
The p2_current_ramped reads back the ramping control point for current when the PCS is performing
power conversion and the DC2 port is set for constant current control. The register is read back in units of
0.1A.
4.6.3 p2_power_ramped Address: 0x00A5 (165)
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Access: R
Data-type: POWER
Range: NA
Default: NA
The p2_power_ramped reads back the ramping control point for power when the PCS is performing power
conversion and the DC2 port is set for constant power control. The register is read back in units of 10W.
4.6.4 p2_voltage_ramped Address: 0x00A6 (166)
Access: R
Data-type: VOLTAGE
Range: NA
Default: NA
The p2_voltage_ramped register reads back the ramping control point for voltage when the PCS is
performing power conversion and the DC2 port is set for constant voltage control. This register is read
back in units of 1V.
4.6.5 pv_tod_stat Address: 0x00A7 (167)
Access: R
Data-type: MINUTES
Range: NA
Default: NA
The pv_tod_stat register reads back the current time-of-day represented in elapsed minutes from 00:00
(midnight start-of-day).
4.6.6 p2_pv_restart_stat Address: 0x00A8 (168)
Access: R
Data-type: U16
Range: NA
Default: NA
The p2_pv_restart_stat register reads back the current value of the restart counter when the restart
function is in use for PV/MPPT operation at the DC2 port. This register is in units of 1 second.
4.6.7 p2_v_pn Address: 0x00AD (173)
Access: R
Data-type: VOLTAGE
Range: NA
Default: NA
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The p2_v_pn register reads back the DC2 port voltage. This register is read back in units of 1V.
4.6.8 p2_v_pg Address: 0x00B0 (176)
Access: R
Data-type: VOLTAGE
Range: NA
Default: NA
The p2_v_pg register reads back the DC2 port terminal voltage with respect to earth ground. This
register is read back in units of 1V.
4.6.9 dc_com_voltage Address: 0x00B1 (177)
Access: R
Data-type: VOLTAGE
Range: NA
Default: NA
The dc_com_voltage register reads back the DC-COM terminal voltage with respect to earth ground. This
register is read back in units of 1V.
4.6.10 p2_power Address: 0x00B9 (185)
Access: R
Data-type: POWER
Range: NA
Default: NA
The p2_power register reads back the DC2 port power. This register is read back in units of 10W.
4.6.11 p2_current Address: 0x00BA (186)
Access: R
Data-type: CURRENT
Range: NA
Default: NA
The p2_current register reads back the DC2 port current. This register is read back in units of 0.1A.
4.7 Port DC3 Control Registers (0x00C0 – 0x00DF) The following register set provides command control for the PCS port DC3.
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4.7.1 p3_control_method Address: 0x00C1 (193)
Access: RW
Data-type: HEX
Range: NA
Default: 0x0000
The p3_control_method register defines the DC3 port power conversion method. Allowable values for this
port are:
1. 0x0000 – IDLE: DC3 port is off
2. 0x0001 – NET: DC3 port set as NET port (maintains energy conservation for system).
3. 0x0002 – PV/MPPT: DC3 port set for MPPT control for PV applications.
4. 0x0301 – CURR: DC3 port set for constant current control.
5. 0x0401 – PWR: DC3 port set for constant power control.
6. 0x0501 – VOLT: DC3 port set for constant voltage control.
4.7.2 p3_throttle_port Address: 0x00C3 (195)
Access: RW
Data-type: HEX
Range: 0 – 1
Default: 0x0000
The p3_throttle_port register defines the port to throttle back power on once the soft-power or soft-current
limit is reached on the DC3 port in NET control.
p3_throttle_port[0] –
0 – Throttle back on DC2 port if DC2 is active; if DC2 is inactive, throttle back on AC1 port.
1 – Throttle back on AC1 port if AC1 is active; if AC1 is inactive, throttle back on DC2 port.
Bit 7 6 5 4 3 2 1 0
Description Reserved Throttle
port
Bit 15 14 13 12 11 10 9 8
Description Reserved
4.7.3 p3_current_setpt Address: 0x00C4 (196)
Access: RW
Data-type: CURRENT
Range: -620 – 620 (-62A – 62A)
Default: 0
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The p3_current_setpt register defines the DC3 current setpoint when DC3 is set for constant current
control. This register is ignored if DC3 is set for any other control method. The register is set in units of
0.1A.
4.7.4 p3_power_setpt Address: 0x00C5 (197)
Access: RW
Data-type: POWER
Range: -3200 – 3200 (-32kW – 32kW)
Default: 0
The p3_power_setpt register defines the DC3 power setpoint when DC3 is set for constant power control.
The register is set in units of 10W.
4.7.5 p3_voltage_setpt Address: 0x00C6 (198)
Access: RW
Data-type: VOLTAGE
Range: 0 – 1000
Default: 0
The p3_voltage_setpt register defines the voltage setpoint when DC3 is set for constant voltage control.
The register is set in units of 1V.
4.7.6 p3_pv_start_tod_setpt Address: 0x00C7 (199)
Access: RW
Data-type: MINUTES
Range: 0 – 1440 (00:00 – 24:00)
Default: 0
The p3_pv_start_tod_setpt register defines the time-of-day to start power conversion operations for DC3 if
the DC3 control method is set for PV/MPPT. If the PCS is set for auto-control mode, and DC3 is set for
PV/MPPT, the PCS will attempt to start tracking to the PV maximum power point at the time-of-day
specified by register p3_pv_start_tod_setpt. The register is in units of elapsed minutes from 00:00, or
midnight start-of-day.
4.7.7 p3_pv_stop_tod_setpt Address: 0x00C8 (200)
Access: RW
Data-type: MINUTES
Range: 0 – 1440 (00:00 – 24:00)
Default: 1440
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The p3_pv_stop_tod_setpt register defines the time-of-day to stop power conversion operations for DC3 if
the DC3 control method is set for PV/MPPT. If the PCS is set for auto-control mode, and DC3 is set for
PV/MPPT, the PCS will stop tracking to the PV maximum power point at the time-of-day specified by
register p3_pv_stop_tod_setpt. The register is in units of elapsed minutes from 00:00, or midnight start-
of-day.
4.7.8 p3_pv_restart_setpt Address: 0x00C9 (201)
Access: RW
Data-type: U16
Range: 10 – 1800
Default: 20
The p3_pv_restart_setpt register defines the setting for the PV/MPPT restart counter in seconds. The
function of this restart counter is to hold off power conversion re-start for a specified duration if the PV
voltage drops below the limit set by register p3_pv_min_v_setpt. The register is in units of seconds.
4.7.9 p3_pv_min_v_setpt Address: 0x00CA (202)
Access: RW
Data-type: VOLTAGE
Range: 0 – 1000
Default: 100
The p3_pv_min_v_setpt register defines the lower limit for the PV/MPPT voltage. If the DC3 PV voltage
drops below this limit, the restart function stops PV power conversion for the specified duration set by
register p3_pv_restart_setpt. When the restart counter expires, the DC3 PV port will attempt to restart
power conversion if the voltage is above register p3_pv_min_v_setpt. The register is in units of 1V.
4.7.10 p3_v_pn_max_limit Address: 0x00CD (205)
Access: RW
Data-type: VOLTAGE
Range: -20 – 1050
Default: 1050
The p3_v_pn_max_limit voltage register defines the upper limit for the DC3 port. If the DC3 voltage rises
above this limit, the DC over-voltage fault is set, the PCS stops power conversion. The register is set in
units of 1V.
4.7.11 p3_v_pn_min_limit Address: 0x00CE (206)
Access: RW
Data-type: VOLTAGE
Range: -20 – 1050
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Default: 100
The p3_v_pn_min_limit voltage register defines the lower limit for the DC3 port. If the DC3 voltage drops
below this limit, the DC under-voltage fault is set, the PCS stops power conversion. The register is set in
units of 1V.
4.7.12 p3_current_ramp_rate Address: 0x00CF (207)
Access: RW
Data-type: CURRENT
Range: 1 – 25000 (0.1A/sec – 2500A/sec)
Default: 50 (5A/sec)
The p3_current_ramp_rate register defines the current ramp rate used for DC3 constant current control.
This register is set in units of 0.1A/sec, e.g. a setting of 500 results in DC3 controls ramping current up or
down to the specified setpoint at a rate of 50A/sec.
4.7.13 p3_power_ramp_rate Address: 0x00D0 (208)
Access: RW
Data-type: POWER
Range: 1 – 25000 (10W/sec – 250kW/sec)
Default: 250 (2.5kW/sec)
The p3_power_ramp_rate register defines the power ramp rate used for DC3 constant power control. This
register is set in units of 10W/sec, e.g. a setting of 500 results in DC3 controls ramping power up or down
to the specified setpoint at a rate of 5kW/sec.
4.7.14 p3_voltage_ramp_rate Address: 0x00D1 (209)
Access: RW
Data-type: VOLTAGE
Range: 1 – 1000 (1V/sec – 1000V/sec)
Default: 50 (50V/sec)
The p3_voltage_ramp_rate register defines the voltage ramp rate used for DC3 constant voltage control.
This register is set in units of 1V/sec, e.g. a setting of 200 results in DC3 controls ramping voltage up or
down to the specified setpoint at a rate of 200V/sec.
4.7.15 p3_power_limit Address: 0x00D9 (217)
Access: RW
Data-type: POWER
Range: 0 – 3200 (0 – 32kW)
Default: 3200 (32kW)
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The p3_power_limit defines the power soft limit for the DC3 port. The register defines the limit for power
generation or loading at the DC3 port during power conversion. The register is set in units of 10W.
4.7.16 p3_current_limit Address: 0x00DA (218)
Access: RW
Data-type: CURRENT
Range: 0 – 640 (0 – 64A)
Default: 600 (60A)
The p3_current_limit defines the current soft limit for the DC3 port. The register defines the limit for the
DC current at the DC3 port during power conversion. The register is set in units of 0.1A.
4.8 Port DC3 Status Registers (0x00E0 – 0x00FF) The following register set provides status read-back for the PCS port DC3.
4.8.1 p3_port_status Address: 0x00E0 (224)
Access: R
Data-type: HEX
Range: NA
Default: NA
The p3_port_status register reads back the status of the DC3 port.
p3_port_status[0] – DC3 port is power soft-limiting
p3_port_status[1] – DC3 port is current soft-limiting
p3_port_status[2] – Reserved
p3_port_status[3] – DC3 port is power derated (limited) due to high temperature
p3_port_status[4] – Reserved
p3_port_status[5] – DC3 port is throttling back on port AC1 due to soft-limiting
p3_port_status[6] – Reserved
p3_port_status[7] – DC3 port is throttling back on port DC2 due to soft-limiting
Bit 7 6 5 4 3 2 1 0
Description Throttling
DC2 Reserved
Throttling
AC1 Reserved
Power
derating for
thermal
Reserved Current
limiting
Power
limiting
Bit 15 14 13 12 11 10 9 8
Description Reserved
4.8.2 p3_current_ramped Address: 0x00E4 (228)
Access: R
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Data-type: CURRENT
Range: NA
Default: NA
The p3_current_ramped reads back the ramping control point for current when the PCS is performing
power conversion and the DC3 port is set for constant current control. The register is read back in units of
0.1A.
4.8.3 p3_power_ramped Address: 0x00E5 (229)
Access: R
Data-type: POWER
Range: NA
Default: NA
The p3_power_ramped reads back the ramping control point for power when the PCS is performing power
conversion and the DC3 port is set for constant power control. The register is read back in units of 10W.
4.8.4 p3_voltage_ramped Address: 0x00E6 (230)
Access: R
Data-type: VOLTAGE
Range: NA
Default: NA
The p3_voltage_ramped register reads back the ramping control point for voltage when the PCS is
performing power conversion and the DC3 port is set for constant voltage control. This register is read
back in units of 1V.
4.8.5 p3_pv_restart_stat Address: 0x00E8 (232)
Access: R
Data-type: U16
Range: NA
Default: NA
The p3_pv_restart_stat register reads back the current value of the restart counter when the restart
function is in use for PV/MPPT operation at the DC3 port. This register is in units of 1 second.
4.8.6 p3_v_pn Address: 0x00ED (237)
Access: R
Data-type: VOLTAGE
Range: NA
Default: NA
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The p3_v_pn register reads back the DC3 port voltage. This register is read back in units of 1V.
4.8.7 p3_v_pg Address: 0x00F0 (240)
Access: R
Data-type: VOLTAGE
Range: NA
Default: NA
The p3_v_pg register reads back the DC3 port terminal voltage with respect to earth ground. This
register is read back in units of 1V.
4.8.8 p3_power Address: 0x00F9 (249)
Access: R
Data-type: POWER
Range: NA
Default: NA
The p3_power register reads back the DC3 port power. This register is read back in units of 10W.
4.8.9 p3_current Address: 0x00FA (250)
Access: R
Data-type: CURRENT
Range: NA
Default: NA
The p3_current register reads back the DC3 port current. This register is read back in units of 0.1A.
4.9 System Operation Control Registers (0x0100 – 0x011F) The following register set provides system operational control for the PCS.
4.9.1 reconnect_timer_set_0 Address: 0x0100 (256)
Access: RW
Data-type: U16
Range: NA
Default: 320
The reconnect_timer_set_0 register defines soft reconnect time after a disconnect triggered by a fault of
severity level ABORT-0. This soft reconnect time is only used when the PCS in auto-control mode
following an ABORT-0 fault clearance. This register is in units of 1 second.
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4.9.2 reconnect_timer_set_1 Address: 0x0101 (257)
Access: RW
Data-type: U16
Range: NA
Default: 20
The reconnect_timer_set_1 register defines soft reconnect time after a disconnect triggered by a fault of
severity level ABORT-1. This soft reconnect time is only used when the PCS in auto-control mode
following an ABORT-1 fault clearance. This register is in units of 1 second.
4.9.3 reconnect_timer_set_2 Address: 0x0102 (258)
Access: RW
Data-type: U16
Range: NA
Default: 20
The reconnect_timer_set_2 register defines soft reconnect time after a disconnect triggered by a fault of
severity level ABORT-2. This soft reconnect time is only used when the PCS in auto-control mode
following an ABORT-2 fault clearance.
4.9.4 timestamp_sec_set_0 Address: 0x0104 (260)
Access: RW
Data-type: HEX4
Range: NA
Default: 0x0000
The timestamp_sec_set_0 register sets the lower 16-bits of the UNIX timestamp to be set for the PCS
system. This timestamp will not take effect until register timestamp_update at address 0x0106 (262) is
set.
4.9.5 timestamp_sec_set_1 Address: 0x0105 (261)
Access: RW
Data-type: HEX4
Range: NA
Default: 0x0000
The timestamp_sec_set_1 register sets the upper 16-bits of the UNIX timestamp to be set for the PCS
system. This timestamp will not take effect until register timestamp_update at address 0x0106 (262) is
set.
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4.9.6 timestamp_update Address: 0x0106 (262)
Access: RW
Data-type: HEX4
Range: NA
Default: 0x0000
The timestamp_update register latches the current settings for timestamp_sec_set_1 and
timestamp_sec_set_0, representing a 32-bit UNIX timestamp to be programmed into the PCS, and
programs the PCS system time to this timestamp. This register is self-clearing.
timestamp_update[0] –
1 – Set new timestamp
Bit 7 6 5 4 3 2 1 0
Description Reserved Update
timestamp
Bit 15 14 13 12 11 10 9 8
Description Reserved
4.9.7 user_start Address: 0x0107 (263)
Access: RW
Data-type: HEX4
Range: NA
Default: 0x0000
The user_start register starts power conversion when set. This register is used when the PCS is set for
manual-mode system operation, and is ignored in auto-mode operations. This register is self-clearing.
user_start[0] –
1 – Start power conversion
Bit 7 6 5 4 3 2 1 0
Description Reserved Start power
conversion
Bit 15 14 13 12 11 10 9 8
Description Reserved
4.9.8 user_stop Address: 0x0108 (264)
Access: RW
Data-type: HEX4
Range: NA
Default: 0x0000
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The user_stop register stops power conversion when set. This register is used when the PCS is set for
manual-mode system operation, and is ignored in auto-mode operations. This register is self-clearing.
user_stop[0] –
1 – Stop power conversion
Bit 7 6 5 4 3 2 1 0
Description Reserved Stop power
conversion
Bit 15 14 13 12 11 10 9 8
Description Reserved
4.9.9 remote_reset Address: 0x010A (266)
Access: RW
Data-type: HEX4
Range: NA
Default: 0x0000
The remote_reset register performs a PCS system reset when set. System power-up or reset put the PCS
system through the following steps:
1. Boot of PCS communications processor
2. Communications initialization
3. Boot of PCS power control processor
4. Load of PCS power control register set
5. Power-up self-test routines
This register is used in both manual-mode and auto-mode operations. This register is self-clearing.
remote_reset[15] –
1 – Perform system reset
Bit 7 6 5 4 3 2 1 0
Description Reserved
Bit 15 14 13 12 11 10 9 8
Description Perform
remote reset Reserved
4.9.10 system_op_mode Address: 0x010B (267)
Access: RW
Data-type: HEX4
Range: NA
Default: 0x0000
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The system_op_mode register sets the PCS system mode of operation.
system_op_mode[0] –
0 – Manual mode (Require setting user_start after control setup to initiate power conversion)
1 – Auto mode (Power conversion starts and re-connects automatically after control setup)
Bit 7 6 5 4 3 2 1 0
Description Reserved Enable auto-
mode
Bit 15 14 13 12 11 10 9 8
Description Reserved
4.9.10 ac_disconnect Address: 0x010C (268)
Access: RW
Data-type: HEX4
Range: NA
Default: 0x0000
The ac_disconnect register controls the external AC disconnect, if present.
ac_disconnect[0] –
0 – Close external AC disconnect (circuit is closed)
1 – Open external AC disconnect (circuit is opened)
Bit 7 6 5 4 3 2 1 0
Description Reserved
Ext AC
Disconnect
Control
Bit 15 14 13 12 11 10 9 8
Description Reserved
4.9.11 precharge_control Address: 0x0113 (275)
Access: RW
Data-type: HEX4
Range: NA
Default: 0x0000
The precharge_control register provides control of the PCS DC port pre-charge function. This function is
reserved for the DC2 port only, and does not support pre-charge of the DC3 port. Once the pre-charge
operation is started, the operation will run indefinitely until the function is stopped. This register is self-
clearing.
precharge_control[0] –
1 – Start DC2 port pre-charge operation
precharge_control[1] –
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1 – Stop DC2 port pre-charge operation
Bit 7 6 5 4 3 2 1 0
Description Reserved Stop DC2
pre-charge
Start DC2
pre-charge
Bit 15 14 13 12 11 10 9 8
Description Reserved
4.9.12 precharge_hi_lim Address: 0x0114 (276)
Access: RW
Data-type: VOLTAGE
Range: 0 – 1000
Default: 800
The precharge_hi_lim register controls the high-limit for the DC2 pre-charge voltage setpoint. This
register is set in units of 1V. The PCS DC2 pre-charge logic will charge the DC2 port line capacitance to
be no greater than this voltage setpoint.
4.9.13 precharge_lo_lim Address: 0x0115 (277)
Access: RW
Data-type: VOLTAGE
Range: 0 – 1000
Default: 790
The precharge_lo_lim register controls the low-limit for the DC2 pre-charge voltage setpoint. This register
is set in units of 1V. The PCS DC2 pre-charge logic will charge the DC2 port line capacitance to be no less
than this voltage setpoint.
4.10 System Operation Status Registers (0x0120 – 0x013F) The following register set provides system status read-back for the PCS.
4.10.1 reconnect_timer_stat_0 Address: 0x0120 (288)
Access: R
Data-type: U16
Range: NA
Default: NA
The reconnect_timer_stat_0 register reads back the current state of the reconnect_timer_0 timer in the
PCS. This reconnect timer is used to hold off reconnect after disconnects triggered by faults of severity
level ABORT-0. This soft reconnect time is only valid when the PCS in auto-control mode following an
ABORT-0 fault clearance. This register is in units of 1 second.
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4.10.2 reconnect_timer_stat_1 Address: 0x0121 (289)
Access: R
Data-type: U16
Range: NA
Default: NA
The reconnect_timer_stat_1 register reads back the current state of the reconnect_timer_1 timer in the
PCS. This reconnect timer is used to hold off reconnect after disconnects triggered by faults of severity
level ABORT-1. This soft reconnect time is only valid when the PCS in auto-control mode following an
ABORT-1 fault clearance. This register is in units of 1 second.
4.10.3 reconnect_timer_stat_2 Address: 0x0122 (290)
Access: R
Data-type: U16
Range: NA
Default: NA
The reconnect_timer_stat_2 register reads back the current state of the reconnect_timer_2 timer in the
PCS. This reconnect timer is used to hold off reconnect after disconnects triggered by faults of severity
level ABORT-2. This soft reconnect time is only valid when the PCS in auto-control mode following an
ABORT-2 fault clearance. This register is in units of 1 second.
4.10.4 timestamp_sec_0 Address: 0x0124 (292)
Access: R
Data-type: HEX4
Range: NA
Default: NA
The timestamp_sec_0 register reads back the lower 16-bits of the UNIX timestamp of the PCS system.
This timestamp represents the current time for the PCS.
4.10.5 timestamp_sec_1 Address: 0x0125 (293)
Access: R
Data-type: HEX4
Range: NA
Default: NA
The timestamp_sec_1 register reads back the upper 16-bits of the UNIX timestamp of the PCS system.
This timestamp represents the current time for the PCS.
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4.10.6 firmware_version Address: 0x0128 (296)
Access: R
Data-type: HEX4
Range: NA
Default: NA
The firmware_version register reads back installed firmware version identifier for the PCS system.
4.10.7 build_version Address: 0x0129 (297)
Access: R
Data-type: U16
Range: NA
Default: NA
The build_version register reads back installed build version identifier for the PCS system.
4.10.8 system_status Address: 0x012A (298)
Access: R
Data-type: HEX4
Range: NA
Default: NA
The system_status register reads back the system status for the PCS system.
system_status[0] – PCS in self-test mode
system_status[1] – PCS reconnect timer 0 counting down from last disconnect due to ABORT-0 fault
system_status[2] – PCS reconnect timer 1 counting down from last disconnect due to ABORT-1 fault
system_status[3] – PCS reconnect timer 2 counting down from last disconnect due to ABORT-2 fault
system_status[4] – PCS DC2 port pre-charge operation is active
system_status[5] – Invalid control method programmed in PCS
system_status[6] – AC rotation indication
0 – AC1 port wired as A-B-C
1 – AC1 port wired as C-B-A
system_status[7] – PV/MPPT low-voltage indication
0 – PV/MPPT is disabled due to low voltage at port
1 – PV/MPPT is enabled with voltage above minimum PV/MPPT limit set for port
system_status[8] – PV/MPPT time-of-day indication
0 – System time-of-day outside PV/MPPT operational range
1 – System time-of-day satisfies start-time and stop-time limits set for PV/MPPT port, PV/MPPT
port allowed to convert power
system_status[9] – PCS power conversion is active
system_status[10] – PCS hardware shutdown function is active (power conversion disabled)
system_status[11] – PCS lockdown active due to GFDI fault, IMI fault, or fan fault
system_status[12] – PCS fault of severity level ABORT-0 active
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system_status[13] – PCS fault of severity level ABORT-1 active
system_status[14] – PCS fault of severity level ABORT-2 active
system_status[15] – PCS GFDI fault or IMI fault detected
Bit 7 6 5 4 3 2 1 0
Description PV above
min voltage
AC1
rotation
Invalid
control
method
DC2
precharge
active
Recon-2
counting
down
Recon-1
counting
down
Recon-0
counting
down
Self-test
mode ON
Bit 15 14 13 12 11 10 9 8
Description GFDI/IMI
fault
PCS fault-2
active
PCS fault-1
active
PCS fault-0
active
PCS
lockdown
active
PCS HW
shutdown
active
PCS
conversion
active
PV time-of-
day valid
4.10.9 la_fsm_code Address: 0x012B (299)
Access: R
Data-type: HEX4
Range: NA
Default: NA
The la_fsm_code register reads back the code identifier for the current state of the state machine
controlling the PCS energy link. The state mapping is as follows:
0x0000 – PCS_INIT
0x0001 – PCS_SELF_TEST
0x0002 – PCS_IDLE
0x0003-0x0006 – PCS power conversion startup
0x0008-0x000F – PCS power conversion active
0x0010 – PCS_FAULT
4.10.10 system_power Address: 0x012C (300)
Access: R
Data-type: POWER
Range: NA
Default: NA
The system_power register reads back the max port power being converted by the PCS. This register is
represented in units of 10W.
4.10.11 la_v_peak Address: 0x012E (302)
Access: R
Data-type: VOLTAGE
Range: NA
Default: NA
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The la_v_peak register reads back the PCS energy link peak voltage. This register is represented in units
of 1V.
4.10.12 la_i_peak Address: 0x012F (303)
Access: R
Data-type: CURRENT
Range: NA
Default: NA
The la_v_peak register reads back the PCS energy link peak voltage. This register is represented in units
of 0.1A.
4.10.13 gfdi_header Address: 0x013C (316)
Access: R
Data-type: HEX4
Range: NA
Default: NA
The gfdi_header register reads back the installed firmware version identifier for the GFDI/IMI fault
detection PCS sub-system.
4.10.14 imi_data Address: 0x013E (318)
Access: R
Data-type: U16
Range: NA
Default: NA
The imi_data register reads back the computed impedance detected between the DC-COM node and earth
ground. This impedance is calculated once every 30 secs. If the computed impedance is below a built-in
threshold of 4kΩ, the PCS system asserts an IMI fault.
4.10.15 gfdi_data Address: 0x013F (319)
Access: R
Data-type: U16
Range: NA
Default: NA
The gfdi_data register reads back a non-zero value if the PCS ground fault fuse is intact, or closed. If the
fuse opens due to a PCS system ground fault, the GFDI/IMI fault detection sub-system shall write a value
of 0 to the gfdi_data register indicating detection of the ground fault.
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4.11 Thermal Status Registers (0x0160 – 0x017F) The following register set provides status read-back of the thermal control system for the PCS.
4.11.1 avg_temp_filt Address: 0x0160 (352)
Access: R
Data-type: TEMP
Range: NA
Default: NA
The avg_temp_filt register reads back the average of the DC-side and AC-side temperatures of the PCS
internal thermal control sub-system. This register is represented in units of 0.1 °C.
4.11.2 ac_temp_filt Address: 0x0161 (353)
Access: R
Data-type: TEMP
Range: NA
Default: NA
The ac_temp_filt register reads back the AC-side temperature of the PCS internal thermal control sub-
system. This register is represented in units of 0.1 °C.
4.11.3 dc_temp_filt Address: 0x0162 (354)
Access: R
Data-type: TEMP
Range: NA
Default: NA
The dc_temp_filt register reads back the DC-side temperature of the PCS internal thermal control sub-
system. This register is represented in units of 0.1 °C.
4.11.4 ob_temp_filt Address: 0x0163 (355)
Access: R
Data-type: TEMP
Range: NA
Default: NA
The ob_temp_filt register reads back the ambient temperature of the PCS internal thermal control sub-
system. This register is represented in units of 0.1 °C.
4.11.5 fan_status Address: 0x0171 (369)
Access: R
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Data-type: HEX4
Range: NA
Default: NA
The fan_status register reads back status of the internal fan controller.
fan_status[0] – Fan is locked based on observation of tach read-back
fan_status[8] – Fan is enabled and PWM-controlled
Bit 7 6 5 4 3 2 1 0
Description Reserved Fan locked
Bit 15 14 13 12 11 10 9 8
Description Reserved Fan ON and
controlled
4.11.6 fan_pwm Address: 0x0175 (373)
Access: R
Data-type: U16
Range: NA
Default: NA
The fan_pwm register reads back the PWM control-point set by the internal fan controller. The fan_pwm
value may read between 1-1920, depending on fan speed control; the fan power varies linearly with the
PWM control-point.
4.11.7 fan_tach Address: 0x017C (380)
Access: R
Data-type: RPM
Range: NA
Default: NA
The fan_tach register reads back the computed fan speed based on the observed tach signal from the fan.
This register is represented in units of 1RPM.
4.12 Diagnostic Control and Status Registers (0x0180 – 0x01BF) The following register set provides system diagnostic control and status for the PCS system.
4.12.1 fault_diag_0 Address: 0x0180 (384)
Access: RW
Data-type: HEX4
Range: NA
Default: 0x0000
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The fault_diag_0 register controls various fault simulation functions embedded in the system to allow
testing of fault responses.
fault_diag_0[0] – Emulate PCS system GFDI fault detection
fault_diag_0[1] – Emulate PCS system IMI fault detection
fault_diag_0[2] – Emulate PCS power module under-temperature or over-temperature fault
fault_diag_0[3] – Emulate PCS ambient under-temperature or over-temperature fault
fault_diag_0[4] – Emulate PCS system under-voltage fault for internal 24V power supply
fault_diag_0[5] – Emulate PCS fan locked fault
fault_diag_0[6] – Emulate PCS DC over-voltage fault
fault_diag_0[7] – Emulate PCS DC under-voltage fault
fault_diag_0[8] – Emulate PCS energy link over-voltage fault
fault_diag_0[9] – Emulate PCS energy link starved fault
fault_diag_0[10] – Emulate PCS energy link over-current fault
fault_diag_0[14] – Emulate PCS surge detected fault
fault_diag_0[15] – Emulate PCS island detected fault
Bit 7 6 5 4 3 2 1 0
Description Sim DC UV
fault
Sim DC OV
fault
Sim fan
locked fault
Sim system
UV fault
Sim ambient
temp fault
Sim power
module
temp fault
Sim IMI
fault
Sim GFDI
fault
Bit 15 14 13 12 11 10 9 8
Description Sim island
detected
fault
Sim surge
detected
fault
Reserved Sim link OI
fault
Sim energy
starved
fault
Sim link OV
fault
4.12.2 fault_diag_1 Address: 0x0181 (385)
Access: RW
Data-type: HEX4
Range: NA
Default: 0x0000
The fault_diag_1 register controls various fault simulation functions embedded in the system to allow
testing of fault responses.
fault_diag_1[0] – Emulate PCS AC1 LV1 (under-voltage 1) disconnect fault
fault_diag_1[1] – Emulate PCS AC1 LV2 (under-voltage 2) disconnect fault
fault_diag_1[2] – Emulate PCS AC1 LV3 (under-voltage 3) disconnect fault
fault_diag_1[3] – Emulate PCS AC1 LV4 (under-voltage 4) disconnect fault
fault_diag_1[4] – Emulate PCS AC1 HV1 (over-voltage 1) disconnect fault
fault_diag_1[5] – Emulate PCS AC1 HV2 (over-voltage 2) disconnect fault
fault_diag_1[6] – Emulate PCS AC1 HV3 (over-voltage 3) disconnect fault
fault_diag_1[7] – Emulate PCS AC1 HV4 (over-voltage 4) disconnect fault
fault_diag_1[8] – Emulate PCS AC1 LF1 (under-frequency 1) disconnect fault
fault_diag_1[9] – Emulate PCS AC1 LF2 (under-frequency 2) disconnect fault
fault_diag_1[10] – Emulate PCS AC1 HF1 (over-frequency 1) disconnect fault
fault_diag_1[11] – Emulate PCS AC1 HF2 (over-frequency 2) disconnect fault
fault_diag_1[12] – Emulate PCS watchdog fault
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fault_diag_1[13] – Emulate PCS E-Stop fault
fault_diag_1[14] – Emulate PCS Arc fault detection
fault_diag_1[15] – Test PCS system 24V under-voltage detection function
Bit 7 6 5 4 3 2 1 0
Description Sim AC
HV4 fault
Sim AC
HV3 fault
Sim AC
HV2 fault
Sim AC
HV1 fault
Sim AC LV4
fault
Sim AC LV3
fault
Sim AC LV2
fault
Sim AC LV1
fault
Bit 15 14 13 12 11 10 9 8
Description Test 24V
UV fault
Sim Arc
fault
Sim E-stop
fault
Sim
watchdog
fault
Sim AC HF2
fault
Sim AC HF1
fault
Sim AC LF2
fault
Sim AC LF1
fault
4.12.3 dc_voltage_fault_holdoff Address: 0x0196 (406)
Access: RW
Data-type: U16
Range: NA
Default: 2000
The dc_voltage_fault_holdoff register controls the hold-off time between consecutive DC voltage faults.
For example, once a DC2 over-voltage fault occurs, another DC2 over-voltage fault cannot occur for
another duration specified by this register. This register is in units of 1 msec. The default value is 2 secs.
4.12.4 la_free_res_duration Address: 0x01A0 (416)
Access: R
Data-type: U16
Range: NA
Default: NA
The la_free_res_duration register reads back the free-resonance duration for the energy link, a useful
metric for diagnosis of problems related to energy management. This register is in units of internal clock
cycles.
4.12.5 la_pwr_cycle_duration Address: 0x01AE (430)
Access: R
Data-type: U16
Range: NA
Default: NA
The la_pwr_cycle_duration register reads back the current duration for the energy link power cycles, a
useful metric for diagnosis of problems related to energy management. This register is in units of internal
clock cycles.
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4.12.6 system_diag_info Address: 0x01B6 (438)
Access: R
Data-type: HEX4
Range: NA
Default: NA
The system_diag_info register reads back diagnostic information pertaining to fault diagnosis and general
system operational control and status.
system_diag_info[0] – AC1 rotation indication
0 – AC1 port wired as A-B-C
1 – AC1 port wired as C-B-A
system_diag_info[1] – Arc fault active
system_diag_info[2] – GFDI fault detected
system_diag_info[3] – Fan fault detected
system_diag_info[4] – Communications processor fault detected, driving HW shutdown
system_diag_info[5] – PCS HW shutdown active
system_diag_info[6] – PCS internal PLL locked indication
0 – PCS internal PLL not locked
1 – PCS internal PLL locked
system_diag_info[7] – PCS system has some fault active
system_diag_info[8] – PCS DC conduction power switches ON
system_diag_info[9] – PCS link forming a conduction
system_diag_info[10] – PCS link converting power
system_diag_info[11] – PCS DC link anchoring power switch ON
system_diag_info[12] – PCS AC conduction power switches ON
system_diag_info[13] – PCS AC link anchoring power switch ON
system_diag_info[14] – E-stop fault detected, driving HW shutdown
system_diag_info[15] – System under-voltage fault detected, driving HW shutdown
Bit 7 6 5 4 3 2 1 0
Description Fault active PLL locked HW
shutdown
Comms Proc
shutdown
Fan fault
detected
GFDI fault
detected
Arc fault
active
AC1
rotation
Bit 15 14 13 12 11 10 9 8
Description System UV
shutdown
E-stop
shutdown
AC anchor
ON
AC conduct
ON
DC anchor
ON
Link
converting
power
Link
conducting
DC conduct
ON
5. Interconnection Standards Control and Status Registers The following sections describe the control and status registers used by thePCS logic functions in
compliance with the IEEE 1547 series of standards for distributed resources interconnection with the
grid.
5.1 Low Voltage (LV) Disconnect Control Registers (0x0240 – 0x025F) The following registers support the low voltage ride-through and disconnect functions of the PCS system.
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5.1.1 uv_1_trip_level Address: 0x0240 (576)
Access: RW
Data-type: VOLTAGE
Range: 0 – 332
Default: 244
The uv_1_trip_level register defines the LV1 under-voltage region threshold limit as part of the UL-
1741/IEEE-1547 grid-safety checks. If the grid RMS voltage drops below this level for the duration set by
register uv_1_trip_time, then the PCS will issue an ABORT-0 fault, stop power conversion, and
disconnect from the AC1 port. This register is specified in units of 1V. If this register is set to 0, the LV1
region and its associated checks are disabled. This register defaults to a setting of 88% of the nominal AC
voltage, 277VAC.
5.1.2 uv_1_trip_time Address: 0x0242 (578)
Access: RW
Data-type: U16
Range: NA
Default: 157
The uv_1_trip_time register defines the LV1 under-voltage region ride-through duration as part of the
UL-1741/IEEE-1547 grid-safety checks. If the grid RMS voltage drops below the LV1 threshold for the
duration set by this register, then the PCS will issue an ABORT-0 fault, stop power conversion, and
disconnect from the AC1 port. This register is specified in units of 10msec, e.g. the default setting of 157
specifies a duration of 1.57s.
5.1.3 uv_2_trip_level Address: 0x0244 (580)
Access: RW
Data-type: VOLTAGE
Range: 0 – 332
Default: 139
The uv_2_trip_level register defines the LV2 under-voltage region threshold limit as part of the UL-
1741/IEEE-1547 grid-safety checks. If the grid RMS voltage drops below this level for the duration set by
register uv_2_trip_time, then the PCS will issue an ABORT-0 fault, stop power conversion, and
disconnect from the AC1 port. This register is specified in units of 1V. If this register is set to 0, the LV2
region and its associated checks are disabled. This register defaults to a setting of 50% of the nominal AC
voltage, 277VAC.
5.1.4 uv_2_trip_time Address: 0x0246 (582)
Access: RW
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Data-type: U16
Range: NA
Default: 13
The uv_2_trip_time register defines the LV2 under-voltage region ride-through duration as part of the
UL-1741/IEEE-1547 grid-safety checks. If the grid RMS voltage drops below the LV2 threshold for the
duration set by this register, then the PCS will issue an ABORT-0 fault, stop power conversion, and
disconnect from the AC1 port. This register is specified in units of 10msec, e.g. the default setting of 13
specifies a duration of 0.13s.
5.1.5 uv_3_trip_level Address: 0x0248 (584)
Access: RW
Data-type: VOLTAGE
Range: 0 – 332
Default: 0
The uv_3_trip_level register defines the LV3 under-voltage region threshold limit as part of the UL-
1741/IEEE-1547 grid-safety checks. If the grid RMS voltage drops below this level for the duration set by
register uv_3_trip_time, then the PCS will issue an ABORT-0 fault, stop power conversion, and
disconnect from the AC1 port. This register is specified in units of 1V. If this register is set to 0, the LV3
region and its associated checks are disabled.
5.1.6 uv_3_trip_time Address: 0x024A (586)
Access: RW
Data-type: U16
Range: NA
Default: 0
The uv_3_trip_time register defines the LV3 under-voltage region ride-through duration as part of the
UL-1741/IEEE-1547 grid-safety checks. If the grid RMS voltage drops below the LV3 threshold for the
duration set by this register, then the PCS will issue an ABORT-0 fault, stop power conversion, and
disconnect from the AC1 port. This register is specified in units of 10msec.
5.1.7 uv_4_trip_level Address: 0x024C (588)
Access: RW
Data-type: VOLTAGE
Range: 0 – 332
Default: 0
The uv_4_trip_level register defines the LV4 under-voltage region threshold limit as part of the UL-
1741/IEEE-1547 grid-safety checks. If the grid RMS voltage drops below this level for the duration set by
register uv_4_trip_time, then the PCS will issue an ABORT-0 fault, stop power conversion, and
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disconnect from the AC1 port. This register is specified in units of 1V. If this register is set to 0, the LV4
region and its associated checks are disabled.
5.1.8 uv_4_trip_time Address: 0x024E (590)
Access: RW
Data-type: U16
Range: NA
Default: 0
The uv_4_trip_time register defines the LV4 under-voltage region ride-through duration as part of the
UL-1741/IEEE-1547 grid-safety checks. If the grid RMS voltage drops below the LV4 threshold for the
duration set by this register, then the PCS will issue an ABORT-0 fault, stop power conversion, and
disconnect from the AC1 port. This register is specified in units of 10msec.
5.2 High Voltage (HV) Disconnect Control Registers (0x0260 – 0x027F) The following registers support the high voltage ride-through and disconnect functions of the PCS system.
5.2.1 ov_1_trip_level Address: 0x0260 (608)
Access: RW
Data-type: VOLTAGE
Range: 0 – 332
Default: 305
The ov_1_trip_level register defines the HV1 over-voltage region threshold limit as part of the UL-
1741/IEEE-1547 grid-safety checks. If the grid RMS voltage rises above this level for the duration set by
register ov_1_trip_time, then the PCS will issue an ABORT-0 fault, stop power conversion, and disconnect
from the AC1 port. This register is specified in units of 1V. If this register is set to 0, the HV1 region and
its associated checks are disabled. This register defaults to a setting of 110% of the nominal AC voltage,
277VAC.
5.2.2 ov_1_trip_time Address: 0x0262 (610)
Access: RW
Data-type: U16
Range: NA
Default: 77
The ov_1_trip_time register defines the HV1 over-voltage region ride-through duration as part of the UL-
1741/IEEE-1547 grid-safety checks. If the grid RMS voltage rises above the HV1 threshold for the
duration set by this register, then the PCS will issue an ABORT-0 fault, stop power conversion, and
disconnect from the AC1 port. This register is specified in units of 10msec, e.g. the default setting of 77
specifies a duration of 0.77s.
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5.2.3 ov_2_trip_level Address: 0x0264 (612)
Access: RW
Data-type: VOLTAGE
Range: 0 – 332
Default: 332
The ov_2_trip_level register defines the HV2 over-voltage region threshold limit as part of the UL-
1741/IEEE-1547 grid-safety checks. If the grid RMS voltage rises above this level for the duration set by
register ov_2_trip_time, then the PCS will issue an ABORT-0 fault, stop power conversion, and disconnect
from the AC1 port. This register is specified in units of 1V. If this register is set to 0, the HV2 region and
its associated checks are disabled. This register defaults to a setting of 120% of the nominal AC voltage,
277VAC.
5.2.4 ov_2_trip_time Address: 0x0266 (614)
Access: RW
Data-type: U16
Range: NA
Default: 13
The ov_2_trip_time register defines the HV2 over-voltage region ride-through duration as part of the UL-
1741/IEEE-1547 grid-safety checks. If the grid RMS voltage rises above the HV2 threshold for the
duration set by this register, then the PCS will issue an ABORT-0 fault, stop power conversion, and
disconnect from the AC1 port. This register is specified in units of 10msec, e.g. the default setting of 13
specifies a duration of 0.13s.
5.2.5 ov_3_trip_level Address: 0x0268 (616)
Access: RW
Data-type: VOLTAGE
Range: 0 – 332
Default: 0
The ov_3_trip_level register defines the HV3 over-voltage region threshold limit as part of the UL-
1741/IEEE-1547 grid-safety checks. If the grid RMS voltage rises above this level for the duration set by
register ov_3_trip_time, then the PCS will issue an ABORT-0 fault, stop power conversion, and disconnect
from the AC1 port. This register is specified in units of 1V. If this register is set to 0, the HV3 region and
its associated checks are disabled.
5.2.6 ov_3_trip_time Address: 0x026A (618)
Access: RW
Data-type: U16
Range: NA
Default: 0
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The ov_3_trip_time register defines the HV3 over-voltage region ride-through duration as part of the UL-
1741/IEEE-1547 grid-safety checks. If the grid RMS voltage rises above the HV3 threshold for the
duration set by this register, then the PCS will issue an ABORT-0 fault, stop power conversion, and
disconnect from the AC1 port. This register is specified in units of 10msec.
5.2.7 ov_4_trip_level Address: 0x026C (620)
Access: RW
Data-type: VOLTAGE
Range: 0 – 332
Default: 0
The ov_4_trip_level register defines the HV4 over-voltage region threshold limit as part of the UL-
1741/IEEE-1547 grid-safety checks. If the grid RMS voltage rises above this level for the duration set by
register ov_4_trip_time, then the PCS will issue an ABORT-0 fault, stop power conversion, and disconnect
from the AC1 port. This register is specified in units of 1V. If this register is set to 0, the HV4 region and
its associated checks are disabled.
5.2.8 ov_4_trip_time Address: 0x026E (622)
Access: RW
Data-type: U16
Range: NA
Default: 0
The ov_4_trip_time register defines the HV4 over-voltage region ride-through duration as part of the UL-
1741/IEEE-1547 grid-safety checks. If the grid RMS voltage rises above the HV4 threshold for the
duration set by this register, then the PCS will issue an ABORT-0 fault, stop power conversion, and
disconnect from the AC1 port. This register is specified in units of 10msec.
5.3 Low Frequency (LF) Disconnect Control Registers (0x0280 – 0x029F) The following registers support the low frequency ride-through and disconnect functions of the PCS
system.
5.3.1 uf_1_trip_level Address: 0x0280 (640)
Access: RW
Data-type: FREQ
Range: 0 - 65000
Default: 59300
The uf_1_trip_level register defines the LF1 under-frequency region threshold limit as part of the UL-
1741/IEEE-1547 grid-safety checks. If the grid frequency drops below this level for the duration set by
register uf_1_trip_time, then the PCS will issue an ABORT-0 fault, stop power conversion, and disconnect
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from the AC1 port. This register is specified in units of 0.001Hz. If this register is set to 0, the LF1 region
and its associated checks are disabled. This register defaults to a setting of 59.3Hz.
5.3.2 uf_1_trip_time Address: 0x0282 (642)
Access: RW
Data-type: U16
Range: NA
Default: 97
The uf_1_trip_time register defines the LF1 under-frequency region ride-through duration as part of the
UL-1741/IEEE-1547 grid-safety checks. If the grid frequency drops below the LF1 threshold for the
duration set by this register, then the PCS will issue an ABORT-0 fault, stop power conversion, and
disconnect from the AC1 port. This register is specified in units of 10msec, e.g. the default setting of 97
specifies a duration of 0.97s.
5.3.3 uf_2_trip_level Address: 0x0284 (644)
Access: RW
Data-type: FREQ
Range: 0 – 65000
Default: 57000
The uf_2_trip_level register defines the LF2 under-frequency region threshold limit as part of the UL-
1741/IEEE-1547 grid-safety checks. If the grid frequency drops below this level for the duration set by
register uf_2_trip_time, then the PCS will issue an ABORT-0 fault, stop power conversion, and disconnect
from the AC1 port. This register is specified in units of 0.001Hz. If this register is set to 0, the LF2 region
and its associated checks are disabled. This register defaults to a setting of 57.0Hz.
5.3.4 uf_2_trip_time Address: 0x0286 (646)
Access: RW
Data-type: U16
Range: NA
Default: 13
The uf_2_trip_time register defines the LF2 under-frequency region ride-through duration as part of the
UL-1741/IEEE-1547 grid-safety checks. If the grid frequency drops below the LF2 threshold for the
duration set by this register, then the PCS will issue an ABORT-0 fault, stop power conversion, and
disconnect from the AC1 port. This register is specified in units of 10msec, e.g. the default setting of 13
specifies a duration of 0.13s.
5.3.5 uf_3_trip_level Address: 0x0288 (648)
Access: RW
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Data-type: FREQ
Range: 0 – 65000
Default: 0
The uf_3_trip_level register defines the LF3 under-frequency region threshold limit as part of the UL-
1741/IEEE-1547 grid-safety checks. If the grid frequency drops below this level for the duration set by
register uf_3_trip_time, then the PCS will issue an ABORT-0 fault, stop power conversion, and disconnect
from the AC1 port. This register is specified in units of 0.001Hz. If this register is set to 0, the LF3 region
and its associated checks are disabled.
5.3.6 uf_3_trip_time Address: 0x028A (650)
Access: RW
Data-type: U16
Range: NA
Default: 0
The uf_3_trip_time register defines the LF3 under-frequency region ride-through duration as part of the
UL-1741/IEEE-1547 grid-safety checks. If the grid frequency drops below the LF3 threshold for the
duration set by this register, then the PCS will issue an ABORT-0 fault, stop power conversion, and
disconnect from the AC1 port. This register is specified in units of 10msec.
5.3.7 uf_4_trip_level Address: 0x028C (652)
Access: RW
Data-type: FREQ
Range: 0 – 65000
Default: 0
The uf_4_trip_level register defines the LF4 under-frequency region threshold limit as part of the UL-
1741/IEEE-1547 grid-safety checks. If the grid frequency drops below this level for the duration set by
register uf_4_trip_time, then the PCS will issue an ABORT-0 fault, stop power conversion, and disconnect
from the AC1 port. This register is specified in units of 0.001Hz. If this register is set to 0, the LF4 region
and its associated checks are disabled.
5.3.8 uf_4_trip_time Address: 0x028E (654)
Access: RW
Data-type: U16
Range: NA
Default: 0
The uf_4_trip_time register defines the LF4 under-frequency region ride-through duration as part of the
UL-1741/IEEE-1547 grid-safety checks. If the grid frequency drops below the LF4 threshold for the
duration set by this register, then the PCS will issue an ABORT-0 fault, stop power conversion, and
disconnect from the AC1 port. This register is specified in units of 10msec.
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5.4 High Frequency (HF) Disconnect Control Registers (0x02A0 – 0x02BF) The following registers support the high frequency ride-through and disconnect functions of the PCS
system.
5.4.1 of_1_trip_level Address: 0x02A0 (672)
Access: RW
Data-type: FREQ
Range: 0 - 65000
Default: 60500
The of_1_trip_level register defines the HF1 over-frequency region threshold limit as part of the UL-
1741/IEEE-1547 grid-safety checks. If the grid frequency increases above this level for the duration set by
register of_1_trip_time, then the PCS will issue an ABORT-0 fault, stop power conversion, and disconnect
from the AC1 port. This register is specified in units of 0.001Hz. If this register is set to 0, the HF1 region
and its associated checks are disabled. This register defaults to a setting of 60.5Hz.
5.4.2 of_1_trip_time Address: 0x02A2 (674)
Access: RW
Data-type: U16
Range: NA
Default: 13
The of_1_trip_time register defines the HF1 over-frequency region ride-through duration as part of the
UL-1741/IEEE-1547 grid-safety checks. If the grid frequency increases above the HF1 threshold for the
duration set by this register, then the PCS will issue an ABORT-0 fault, stop power conversion, and
disconnect from the AC1 port. This register is specified in units of 10msec, e.g. the default setting of 13
specifies a duration of 0.13s.
5.4.3 of_2_trip_level Address: 0x0284 (644)
Access: RW
Data-type: FREQ
Range: 0 – 65000
Default: 0
The of_2_trip_level register defines the HF2 over-frequency region threshold limit as part of the UL-
1741/IEEE-1547 grid-safety checks. If the grid frequency increases above this level for the duration set by
register of_2_trip_time, then the PCS will issue an ABORT-0 fault, stop power conversion, and disconnect
from the AC1 port. This register is specified in units of 0.001Hz. If this register is set to 0, the HF2 region
and its associated checks are disabled.
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5.4.4 of_2_trip_time Address: 0x0286 (646)
Access: RW
Data-type: U16
Range: NA
Default: 0
The of_2_trip_time register defines the HF2 over-frequency region ride-through duration as part of the
UL-1741/IEEE-1547 grid-safety checks. If the grid frequency increases above the HF2 threshold for the
duration set by this register, then the PCS will issue an ABORT-0 fault, stop power conversion, and
disconnect from the AC1 port. This register is specified in units of 10msec.
5.4.5 of_3_trip_level Address: 0x0288 (648)
Access: RW
Data-type: FREQ
Range: 0 – 65000
Default: 0
The of_3_trip_level register defines the HF3 over-frequency region threshold limit as part of the UL-
1741/IEEE-1547 grid-safety checks. If the grid frequency increases above this level for the duration set by
register of_3_trip_time, then the PCS will issue an ABORT-0 fault, stop power conversion, and disconnect
from the AC1 port. This register is specified in units of 0.001Hz. If this register is set to 0, the HF3 region
and its associated checks are disabled.
5.4.6 of_3_trip_time Address: 0x028A (650)
Access: RW
Data-type: U16
Range: NA
Default: 0
The of_3_trip_time register defines the HF3 over-frequency region ride-through duration as part of the
UL-1741/IEEE-1547 grid-safety checks. If the grid frequency increases above the HF3 threshold for the
duration set by this register, then the PCS will issue an ABORT-0 fault, stop power conversion, and
disconnect from the AC1 port. This register is specified in units of 10msec.
5.4.7 of_4_trip_level Address: 0x028C (652)
Access: RW
Data-type: FREQ
Range: 0 – 65000
Default: 0
The of_4_trip_level register defines the HF4 over-frequency region threshold limit as part of the UL-
1741/IEEE-1547 grid-safety checks. If the grid frequency increases above this level for the duration set by
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register of_4_trip_time, then the PCS will issue an ABORT-0 fault, stop power conversion, and disconnect
from the AC1 port. This register is specified in units of 0.001Hz. If this register is set to 0, the HF4 region
and its associated checks are disabled.
5.4.8 of_4_trip_time Address: 0x028E (654)
Access: RW
Data-type: U16
Range: NA
Default: 0
The of_4_trip_time register defines the HF4 over-frequency region ride-through duration as part of the
UL-1741/IEEE-1547 grid-safety checks. If the grid frequency increases above the HF4 threshold for the
duration set by this register, then the PCS will issue an ABORT-0 fault, stop power conversion, and
disconnect from the AC1 port. This register is specified in units of 10msec.
6. System Communication Control The following sections describe the PCS registers controlling communication parameters.
6.1 Modbus RTU Control Registers The following registers control the behavior of Modbus RTU communications for the PCS.
6.1.1 mb_adr_rtu Address: 0x07EA (2026)
Access: RW
Data-type: U16
Range: 1 – 250
Default: 240
The mb_adr_rtu register sets the Modbus RTU device address. Any new setting for this register takes
effect immediately (for all future Modbus RTU communications until the PCS is powered down or re-
booted). To have this setting persist beyond a system power-down or re-boot, the operator must also issue
a ‘save-settings’ command, described in section 6.3.
6.1.2 mb_adr_tcp Address: 0x07EB (2027)
Access: RW
Data-type: U16
Range: 1 – 250
Default: 240
The mb_adr_tcp register sets the Modbus TCP device address. Any new setting for this register takes
effect immediately (for all future Modbus TCP communications until the PCS is powered down or re-
booted). To have this setting persist beyond a system power-down or re-boot, the operator must also issue
a ‘save-settings’ command, described in section 6.3.
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6.1.3 mb_baud Address: 0x07EC (2028)
Access: RW
Data-type: BAUD
Range: 96 – 1152
Default: 192
The mb_baud register sets the Modbus RTU communication baud rate. This register is in units of 100
bps, e.g. a setting of 192 sets the baud rate to 19200 bps. The PCS only supports baud rate settings of:
1. 9600 bps
2. 19200 bps
3. 38400 bps
4. 57600 bps
5. 115200 bps
If this register is updated with a setting not on the above list (and thus not supported by the PCS), the
PCS will ignore the setting and continue Modbus RTU communications with the previous valid setting.
Any new setting for this register will take effect only after issuing a ‘save-settings command (described in
section 6.3) and re-booting the PCS system.
6.1.4 mb_parity Address: 0x07ED (2029)
Access: RW
Data-type: U16
Range: 0 – 2
Default: 2
The mb_parity register sets the Modbus RTU communication data format and parity-bit type. The
Modbus data format and parity-bit type are set by the following mapping:
0 : 8 data bits + 1 odd parity bit + 1 stop bit (8-O-1)
1 : 8 data bits + 1 even parity bit + 1 stop bit (8-E-1)
2 : 8 data bits + 1 stop bit (8-N-1)
Any new setting for this register will take effect only after issuing a ‘save-settings command (described in
section 6.3) and re-booting the PCS system.
6.2 Modbus TCP Control Registers The following registers control the behavior of Modbus TCP communications for the PCS system. This
section describes all registers associated with setup for the TCP/IP network configuration of the PCS.
6.2.1 eth_address Address: 0x07EE-0x07F5 (2030-2037)
Access: RW
Data-type: STRING
Range: NA
Default: NA
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The eth_address register sets the IP address for the PCS network configuration. Any new setting for this
register will take effect only after issuing a ‘save-settings command (described in section 6.3) and re-
booting the PCS. Set this register to 0.0.0.0 to enable DHCP for the PCS network configuration. This
register should specify the PCS IP address in dotted-decimal notation.
6.2.2 eth_mask Address: 0x07F6-0x07FD (2038-2045)
Access: RW
Data-type: STRING
Range: NA
Default: NA
The eth_mask register sets the subnet mask address for the PCS network configuration. Any new setting
for this register will take effect only after issuing a ‘save-settings command (described in section 6.3) and
re-booting the PCS system. This register should specify the subnet mask address in dotted-decimal
notation.
6.2.3 eth_gateway Address: 0x07FE-0x0805 (2046-2053)
Access: RW
Data-type: STRING
Range: NA
Default: NA
The eth_gateway register sets the default gateway address for the PCS network configuration. Any new
setting for this register will take effect only after issuing a ‘save-settings command (described in section
6.3) and re-booting the PCS. This register should specify the default gateway address in dotted-decimal
notation.
6.2.4 eth_dns Address: 0x0806-0x080D (2054-2061)
Access: RW
Data-type: STRING
Range: NA
Default: NA
The eth_dns register sets the DNS server IP address to be used with the PCS. Any new setting for this
register will take effect only after issuing a ‘save-settings command (described in section 6.3) and re-
booting the PCS. This register should specify the default DNS server address in dotted-decimal notation.
6.2.5 eth_ntp Address: 0x080E-0x0815 (2062-2069)
Access: RW
Data-type: STRING
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Range: NA
Default: NA
The eth_ntp register sets the NTP server IP address to be used with the PCS. Any new setting for this
register will take effect only after issuing a ‘save-settings command (described in section 6.3) and re-
booting the PCS. This register should specify the default NTP server address in dotted-decimal notation.
6.3 System Load-Save Command, Timezone Update, and ID Readback This section describes the system load and save functions, as well as the system timezone update function
and the system serial number identifier for the PCS.
6.3.1 command Address: 0x07D0 (2000)
Access: RW
Data-type: U16
Range: NA
Default: 0
The command register for the PCS system performs the following functions:
• Setting = 1 – Load of system control registers from last saved register set (performed
automatically at PCS power-up)
• Setting = 2 – Save of system control registers (to persist beyond power-down or re-boot)
• Setting = 6 – Save system timezone and communication settings (to persist beyond power-down or
re-boot)
All other settings to this register are reserved and should not be used unless given instructions from
IPWR.
6.3.2 timezone Address: 0x07E9 (2025)
Access: RW
Data-type: S16
Range: -12 – 12
Default: -6
The timezone register for the PCS sets the system timezone. This register sets the time offset from UTC.
6.3.3 serial Address: 0x07D1-0x07D8 (2001-2008)
Access: R
Data-type: STRING
Range: NA
Default: NA
The serial register allows read-back of the 8-character string representing the PCS system serial number.
This register is read-only and cannot be modified.
Stabiliti™ Modbus Programming Guide DOC-00038 Rev A 64 of 64 Copyright © 2017 Ideal Power Inc. All rights reserved.
End of Document.