STEREO electronics back-end overview
O. Bourrion J. L. Bouly J. Bouvier C. Li N. PonchantD. Tourres C. Vescovi
CNRS-IN2P3-LPSC Grenoble
June 19th, 2015
O. Bourrion STEREO electronics (journee reseau DAQ) 1 / 23
Table of Contents
1 OverviewGeneral requirementsElectronics overviewRequired first level triggering and processing
2 Front-end descriptionSpecificationsHardwareFirmwareSerial link FE8 ↔ trigger mezz. board
3 Trigger and readout descriptionHardwareFirmware
4 LED boardHardwareFirmware
5 Summary
O. Bourrion STEREO electronics (journee reseau DAQ) 2 / 23
Table of Contents
1 OverviewGeneral requirementsElectronics overviewRequired first level triggering and processing
2 Front-end descriptionSpecificationsHardwareFirmwareSerial link FE8 ↔ trigger mezz. board
3 Trigger and readout descriptionHardwareFirmware
4 LED boardHardwareFirmware
5 Summary
O. Bourrion STEREO electronics (journee reseau DAQ) 3 / 23
General requirements
STEREO experiment is a search for a sterileneutrino (dimension: 3m × 1m × 1.5m)
Measures the anti-neutrino energy spectrumas a function of the distance from the source(ILL nuclear reactor).
Monitor 68 channels required in 3 classes (for triggering)
24 PMT for Gamma catcher24 PMT for target (gadolinium-loaded liquid scintillator)20 PMT for muon veto (Cerenkov detector)
Withstand a mean first level trigger rate of 1 kHz
Have no dead-time (pile-up excepted)
Manage various trigger schemes and conditions (coincidence andanti-coincidence)
Process signals on board: compute Qtot and Qtail for Pulse Shapediscrimination (PSD)
O. Bourrion STEREO electronics (journee reseau DAQ) 4 / 23
Electronics overview
Trigger board used for: triggering, FE readout and LED control
Communication FE ↔ Trig Board with custom protocol
Readout and slow control via IPBus (Secured UDP from CERN)
O. Bourrion STEREO electronics (journee reseau DAQ) 5 / 23
Required first level triggering and processing
1 FE emits a trigger when at least one PMT signal > trig threshold
2 Confirmed trigger (by trig board) reception initiate PSD processing
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Beginning of signal is to be found with a Constant FractionDiscriminator (CFD) having its own threshold (above noise)
Adjustable parameter defined prior to run
Ntot represents typical pulse duration
Nsample time window for analysis and samples to record in debugmode
O. Bourrion STEREO electronics (journee reseau DAQ) 6 / 23
Table of Contents
1 OverviewGeneral requirementsElectronics overviewRequired first level triggering and processing
2 Front-end descriptionSpecificationsHardwareFirmwareSerial link FE8 ↔ trigger mezz. board
3 Trigger and readout descriptionHardwareFirmware
4 LED boardHardwareFirmware
5 Summary
O. Bourrion STEREO electronics (journee reseau DAQ) 7 / 23
Front-end 8 (FE8) specifications
8 channels board (13 bit ADC @250 MSPS, dynamic range 1.0 V)
Readout by custom serial protocol, slow control by IPBus
Preamplifier + amplifier with 2 selectable gains, e.g x1 and x20
The ADC input feature anti-aliasing filter (80 MHz)
First level trigger on amplitude OR charge, selectable by mask :
Individual channelsum of first 4 channelssum of last 4 channelssum of 8 channels
Trigger bit inserted in the data flow
Each channel has a high pass IIR to suppress pedestal
Scalers for individual PMT monitoring
CFD and PSD for each channel. Qtot and Qtail computed on board
Transfer of Qtot × 8, Qtail × 8, zero crossing ×8
Optional debug mode to readout the Nsamples used to compute CFDand PSD
O. Bourrion STEREO electronics (journee reseau DAQ) 8 / 23
FE8 hardware
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Main FPGA: XC7K70-2TFBG676,
ADC: Texas Instrument ADS42LB49 (AC coupled, fc >30 kHz)
O. Bourrion STEREO electronics (journee reseau DAQ) 9 / 23
FE8 firmware overview
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Parameters are in red
Pipelined processing: 1st CFD, then PSD, then data concentratedand finally serialized
O. Bourrion STEREO electronics (journee reseau DAQ) 10 / 23
CFD description
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Fraction can be tuned with a high resolution (steps of 1/65536)
Output data are delayed to be in phase with zero crossing result
Zero crossing (N ZC) searched on computed signal
To keep scaling, cfd thres is searched on delayed original signal
N ZC is the sample count of the 1st data after sign inversion (Y1always < 0 and Y2 always > 0) validated by cfd thres crossing.
Sub sampling resolution can be reached off-line by interpolation withY1 and Y2
O. Bourrion STEREO electronics (journee reseau DAQ) 11 / 23
PSD description
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NZC (produced by CFD) used to start Riemann integration of Qtot
Nstarttail = Ntot −Ntail used to start Riemann integration of Qtail
Daq mode selects between normal or debug mode
If tail not finished when N samples is reached, Qtot isunderestimated.
Param. word inserted in data flow (over-range, Σ4 trig., Σ8 trig.)
O. Bourrion STEREO electronics (journee reseau DAQ) 12 / 23
Serial link FE8 ↔ trigger mezz. board
For the prototype the serial link was emulated, 5 signals:
SDATA : OUT (FE), IN (Trig board)SEN : OUT (FE), IN (Trig board)SCLK : OUT (FE), IN (Trig board)CANDIDATE TRIG : OUT (FE), IN (Trig board)CONFIRMED TRIG : IN (FE), OUT (Trig board)
Serial link operated at 125 Mbit/s, typical frame content:
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In normal mode, rate limited at 125MHz/(4x32x8)=122 kHz.
In debug mode, rate limited at 13.5 kHz (worst case, 64 samples).
Triggering path at 250 MHz (to be sample accurate)
⇒ Delay from candidate trigger to confirmed trigger, a circular bufferis required in the front-end (about 120 ns or 30 samples)
O. Bourrion STEREO electronics (journee reseau DAQ) 13 / 23
Table of Contents
1 OverviewGeneral requirementsElectronics overviewRequired first level triggering and processing
2 Front-end descriptionSpecificationsHardwareFirmwareSerial link FE8 ↔ trigger mezz. board
3 Trigger and readout descriptionHardwareFirmware
4 LED boardHardwareFirmware
5 Summary
O. Bourrion STEREO electronics (journee reseau DAQ) 14 / 23
Trigger and readout hardware
NAT-MCH and extensions (2 boards)
T1: NAT-MCH featuring an Ethernet switch
T2: Clock trees (FCLKA, TCLKA), clock reception (TCLKB)
T3: Main board with FPGA (XC6SLX45T-FGG484), power,Ethernet (GTP and spare phy)
T4: Fast SMA inputs, RJ45 (spare Ethernet, LED box control)
O. Bourrion STEREO electronics (journee reseau DAQ) 15 / 23
Ports allocation for slot 1-10 (containing FE8)
Port 0: for IPbus (Ethernet)
Port 5-7, trigger and acq serial protocol :
Port 5: unidirectional serial data FE8→MCH (125 Mbps)Port 6: unidirectional serial enable FE8→MCHPort 7: bidir, candidate trigger FE8→MCH, confirmed trigger toMCH→FE8 (4 ns pulses)
TCLKB: used as serial link reference clock to MCH.
TCLKA: system reference clock
Ports allocation for slot 11-12 (containing LED board)
Port 0: for IPbus (Ethernet)
Port 5-7:
Port 5: unidirectional serial data MCH→LED board (125 Mbps)Port 6: unidirectional serial enable MCH→LED boardPort 7: unidirectional LED pulse MCH→LED board (4 ns pulses)
FCLKB: used as LED serial link reference clock to LED boards
TCLKA: system reference clock
O. Bourrion STEREO electronics (journee reseau DAQ) 16 / 23
Trigger and readout firmware
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MEB is implemented: up to 84 (normal)/6 (debug) consecutivetriggers can be accepted (if separated by N samples x 4 ns)
Low level and high level trig function(s) can evolve.
In calibration mode (LED) several pattern sequences are possible.
O. Bourrion STEREO electronics (journee reseau DAQ) 17 / 23
Table of Contents
1 OverviewGeneral requirementsElectronics overviewRequired first level triggering and processing
2 Front-end descriptionSpecificationsHardwareFirmwareSerial link FE8 ↔ trigger mezz. board
3 Trigger and readout descriptionHardwareFirmware
4 LED boardHardwareFirmware
5 Summary
O. Bourrion STEREO electronics (journee reseau DAQ) 18 / 23
LED board hardware
Slow control by IPBus (for LED voltage level and BPI programming)
LED pattern and timing are selected and driven by the trigger board.
O. Bourrion STEREO electronics (journee reseau DAQ) 19 / 23
LED box driver and led box
15 LED box driver from LED board
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Each LED box contains 6 LED and a discrete LED driver.
LED light driver supplied and driven via a single coax cable:1 LED light level set by mean voltage (DAC setting via IPBus)2 Square pulse > 2V fires the LED (generated by FPGA)
O. Bourrion STEREO electronics (journee reseau DAQ) 20 / 23
LED board firmware
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1 Use IPBus to configure DAC and select the LED box to driven.
2 Serial data frame is used to set the required pattern (for instanceincremental pattern).
3 After each serial frame, a led pulse trigger is send by the triggerboard for activating the LED pattern.
O. Bourrion STEREO electronics (journee reseau DAQ) 21 / 23
Table of Contents
1 OverviewGeneral requirementsElectronics overviewRequired first level triggering and processing
2 Front-end descriptionSpecificationsHardwareFirmwareSerial link FE8 ↔ trigger mezz. board
3 Trigger and readout descriptionHardwareFirmware
4 LED boardHardwareFirmware
5 Summary
O. Bourrion STEREO electronics (journee reseau DAQ) 22 / 23
Summary
TRB and LED board validated on prototype experiment
Final validations of FE8 design in progress
Cabling of 11 remaining FE8 board to be done this summer.
Data-taking at ILL starts in December.
Shareable items
IPBus:
Rewritten IPbus firmware (LPSC flavour) and software (QT4 based)working fine.DHCP capability was addedNTP feature implemented (to be improved)
micro-TCA plateform at LPSC :
IPBusMMC software spin-off from CPPM/CERN currently used on 5different designsFlash programmer for in-situ upgrades (IPBus slave + C++ driver)Encapsulated openHPI driver for reading crate sensors.
O. Bourrion STEREO electronics (journee reseau DAQ) 23 / 23