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System Design Verification andSystem Design, Verification and Optimization of Modern Memory
Interfaces (DDR3)Interfaces (DDR3)
Santa Clara, Aug 23rd 2011Robert Myoung
© 2011 ANSYS, Inc. August 25, 20111
Robert MyoungSr. Application Engineer
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Agenda
IntroductionIntroduction
ECAD Geometry Translation
SI/PI DDR3 Channel Extraction
i i d h i iDesign Automation and Schematic Creation
DDR3 Transient Simulation Results
© 2011 ANSYS, Inc. August 25, 20112
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ANSYS for DDR3 Designs
ProblemProblemNeed for automated and accurate extraction of channel components and system verification for meeting strict DDR3 electrical standards and design specifications
SolutionAutomatic physical extraction and system compliance verification for memory interface design using ANSYSverification for memory interface design using ANSYS Electromagnetics tools
ResultDetailed and accurate system simulation enables engineers to explorer pre‐ and post‐layout verification for optimal memory interface design.
© 2011 ANSYS, Inc. August 25, 20113 Pictures source: www.istockphoto.com
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DDR2/3 Overview
• DDR3 speed is 800‐1600MBps which is 2x DDR2– Tighter noise margins and need for less SSN
– DDR3 uses less voltage (1.5V from 1.2V)
• DDR3 has less SSN than DDR2 due to its fly‐by terminationy y
© 2011 ANSYS, Inc. August 25, 20114 Information source: JEDEC 2007 DDR Workshop and HP DDR3 Application Note
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DDR2/3 Timing Specifications
• Setup Margin & Hold Margin• It’s included timing margin and noise (voltage) margin
DQ DQSJitter
V IH(DC)
VREF
V IH(AC)
V V IL(DC)
SetupTime
HoldTime
V IL(AC)IL(DC)
• DIMMs require tighter specifications than down device memory in the case of
Setup Margin Hold Margin
© 2011 ANSYS, Inc. August 25, 20115
DIMMs require tighter specifications than down device memory, in the case of applying and input voltage value, DIMMs require both an AC & DC value.
• Down Device DDR2/3 memory generally requires only the DC input voltage value.
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ANSYS Solution
Electrical
DesignerSI, SIwave, HFSS
Fluid DynamicMechanical
© 2011 ANSYS, Inc. August 25, 20116
Dynamic
Images and models courtesy of the Xilinx, Micron Technology, TE Connectivity.
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Virtual System Prototyping
Layout
3D CAD
Layout
Virtual Prototype ElectromagneticExtraction
Mechanical andThermal
Vendor SpecificDriver/Receiver Models
Vendor SpecificElectronics Virtual
SystemVendor Specific
VRM Models
Virtual Compliance
© 2011 ANSYS, Inc. August 25, 20117
p
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Virtual System Prototyping
Layout
3D CAD
Layout
Virtual Prototype
© 2011 ANSYS, Inc. August 25, 20118
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Xilinx ML605 Board
© 2011 ANSYS, Inc. August 25, 20119 Courtesy of:
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Layout Translation from Cadence Allegro
© 2011 ANSYS, Inc. August 25, 201110 Courtesy of:
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SODIMM board, Connector and Main Board
© 2011 ANSYS, Inc. August 25, 201111 Courtesy of: Xilinx and http://www.jedec.org/
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Virtual System Prototyping
Layout
3D CAD
ElectromagneticExtraction
Layout
Virtual Prototype
Mechanical andThermal
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Complex Multiple PCB Power Domains
P S d Si kP S d Si kPower Sources and SinksPower Sources and Sinks•1.5V Memory and FPGA•1V8•2V5•2V5 FPGA3V3
© 2011 ANSYS, Inc. August 25, 201113
•3V3•5V•12_P•12_P_IN
Courtesy of:
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SIwave DC IR solver
• SIwave has the ability to examine the full current path as well as each individual segment.
• Current/voltage/power levels set at each stage
• Power Supply StabilityCapacitor Library Browser PI Advisor‐ Capacitor Library Browser, PI Advisor
• Hot spots/bottlenecks that may cause reliability and excessive heating can be detected via current density and DC simulation results can be coupled to a th l / i fl i l ti i ANSYS I P kTMthermal / airflow simulation using ANSYS IcePakTM.
onal
Link Bi‐directional Coupling
Bidirectio
Thermal
SIwave Icepak
Power and Thermal Mapping
p g
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SIwave Design
• DDR3 1.5V Power Delivery Network with real VRM model
1 5V VRMVRM
© 2011 ANSYS, Inc. August 25, 201115
1.5V1.5V +/- 5%
VRM VRM
Courtesy of:
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SIwave SYZ Parameter extraction
• Extraction example of mixed‐mode s‐parameters– Power Rail and Signal Nets, DC and ACPower Rail and Signal Nets, DC and AC
• Vertex V6 to DDR3 SODIMM Memory–ML605 PCB
– DDR3 204PIN SODIMM Connector– Power/Ground separate referencing
– Some of the signal reference to Power plane– Some of the signal reference to Power plane
– DDR3 204 SODIMM PCB
• Real VRM modelReal VRM model
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S‐parameter Extraction & Analysis
Signal Integrity• Insertion/Return Loss parameters
• Power/Ground Isolation effect in Frequency and Time Domain
Main board with connector
Main board only
Main board with connector and SODIMM board
Main board only
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Virtual System Prototyping
Layout
3D CAD
ElectromagneticExtraction
Layout
Virtual Prototype
Mechanical andThermal
Vendor SpecificDriver/Receiver Models
Vendor SpecificElectronics
Vendor SpecificVRM Models
© 2011 ANSYS, Inc. August 25, 201118
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VRM(PTD08A010W) model from TIFusion Digital Power designer from TI• Generate real VRM model
© 2011 ANSYS, Inc. August 25, 201119Information source: http://focus.ti.com/docs/toolsw/folders/print/fusion_digital_power_designer.html
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DDR3 PDN model• DDR3 1.5V Power Delivery Network with real VRM model
• Multiple probing points displayed
• Top and bottom DDR3 package, FPGA and VRM
U8U18
© 2011 ANSYS, Inc. August 25, 201120 Courtesy of:
VRM
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VRM Current Signature Profile• Probe Point : VRM Output(Blue), FPGA Power(Brown) and DDR3 (Red).
1. VRM Output2 DDR3 package2. DDR3 package
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Virtual System Prototyping
Layout
3D CAD
ElectromagneticExtraction
Layout
Virtual Prototype
Mechanical andThermal
VirtualSystem
Vendor SpecificDriver/Receiver Models
Vendor SpecificElectronics
Virtual Compliance
Vendor SpecificVRM Models
© 2011 ANSYS, Inc. August 25, 201122
p
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System Level Signal and Power integrity AnalysisAnalysis
• While extraction and analysis are important steps of a design methodology, a system level analysis gives the engineer the ability to best balance and trade off design choices for the given performance and cost requirements
…generally there are multiple “lanes” of l d d b d h
choices for the given performance and cost requirements.
+ + Rcv+ + Rcv
+ + Rcv
Tx +Tx +
Tx +
serial data running side by side; these can CROSSTALK with each other.
- -- -
+
-
+
-
Rcv+
-
+
-
Rcv-
-+
-Tx +
-
…Power/Ground Bounce and Coupling to Signal Nets
• Design Automation is essential;• Automatic Schematic generation and Simulation
© 2011 ANSYS, Inc. August 25, 201123
g
• Data analysis compare to Standard
• Deal with Various different data set.
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Network Data Explorer
Network Data Explorer (nD Explorer in Designer)• 3 Stage Dynamic Link Design
• 36port model with mixed reference impedance– Supports Touchstone 2.0
• Bandwidth : DC to 20GHz Spice model
• Passivity and Causality enforcement
36port model of DDR3 channel
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Automatic Schematic Creation
– SSN analysis
– DQS Zero Crossing and Eye Margins
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DDR3 Channel Eye Diagrams
Without Connector
• Connector Effects on DQS line Zero CrossingWith ConnectorWithout Connector With Connector
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DDR3 Channel Eye Diagrams and Regular Plot
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DDR3 Channel Derating tables, slew rate
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SODIMM board, Connector and Main Board
SIwave, DesignerSI SIwave, DesignerSI
HFSSHFSS
SIwave, DesignerSI and HFSSSIwave, DesignerSI and HFSS
© 2011 ANSYS, Inc. August 25, 201129
HFSSHFSS
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ANSYS Tools Overview
• DDR3 Solution for Electrical Simulations– ECAD Geometry Translationy
• ECAD Translators and AnsoftLinks
– SI/PI DDR3 Channel Extraction• HFSS, SIwave
– Design Automation and Schematic Creation• DesignerSI and SIwaveDesignerSI and SIwave
– DDR3 Transient Simulation Results• DesignerSI, UDO’s
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Thank You
© 2011 ANSYS, Inc. August 25, 201131