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Technology Mapping of Timed Asynchronous
Circuits
Curtis A. Nelson
University of Utah
August 26, 2004
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Technology Mapping
Process of implementing a synthesized design. Utilizes technology-specific libraries.Combines the steps of: Partitioning Decomposition Matching Covering
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Synchronous Design Flow
Decomposition
Partitioning
Matching/Covering
Physical Design
Cost Factors
Layout
Library
Specifications
Logic SynthesisMapping
Technology
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Asynchronous Design Flow
HazardVerification Decomposition
Partitioning
Matching/Covering
Physical Design
Cost Factors
Layout
Library
Specifications
Logic SynthesisMapping
Technology
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Timed Asynchronous Circuits
Timed circuits are a class of asynchronous circuits that use explicit timing information.Can potentially reduce required circuitry as compared with speed-independent circuits.Used in Intel RAPPID design which was 3 times faster than synchronous design.As in all asynchronous circuits, timed circuit design is complicated by hazards.
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Hazards
Conditions that may manifest as glitches. Caused by structure or timing of the circuit.May result in incorrect behavior.Must be detected and eliminated.Two types of hazards: Acknowledgment. Monotonicity.
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Acknowledgement Hazard
0
1
1
3 [2,4]
Occurs when inputs to a gate change evaluation before the output stabilizes.
0
0
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Acknowledgement Hazard
1
1
[2,4]
Occurs when inputs to a gate change evaluation before the output stabilizes.
0
0
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Acknowledgement Hazard
1
1
[2,4]
Occurs when inputs to a gate change evaluation before the output stabilizes.
0
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Monotonicity Hazard
Occurs when an internal or output node: Becomes excited to change when it should stay
stable, or Makes a transition non-monotonically.
1
1
[4,6]
[1,3]
0
0
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Monotonicity Hazard
1
1
[4,6]
[1,3]
0
Occurs when an internal or output node: Becomes excited to change when it should stay
stable, or Makes a transition non-monotonically.
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Asynchronous Design Flow
Decomposition
Partitioning
Matching/Covering
Physical Design
Cost Factors
Layout
Library
Specifications
Logic SynthesisMapping
Technology
HazardVerification
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Hazard Verification
Must check all reachable states for hazards.Size of state space is O(2|I| x 2|O| x 2|N|).Beerel/Burch/Meng proposed using a cube to approximate internal signal behavior for speed-independent circuits.Reduces size of state space to O(2|I| x 2|O|).We extend this application to timed circuits.
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Hazard Verification Algorithm
Input: Time Petri Net and Gate Netlist. Check complex gate equivalence. Determine stability of internal signals. Check for acknowledgement hazards. Check for monotonicity hazards.
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Time Petri Net
Specification method for timed systems.Used to specify: Environmental behavior. Expected output behavior.
a+ [2,5]
b+ [2,5] c- [2,5]
b- [2,5]c+ [2,5]
a- [2,5] d-
c+ [2,5]
d+
b+ [2,5]
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Time Petri Net
State is a marking of places and ages of transitions.Transition enabled when all input places are marked.Transition fires after it has been enabled between [min,max] time units.
a+ [2,5]
b+ [2,5] c- [2,5]
b- [2,5]c+ [2,5]
a- [2,5] d-
c+ [2,5]
d+
b+ [2,5]
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Time Petri Net
After transition fires, marking removed from input places and added to output places.
a+ [2,5]
b+ [2,5] c- [2,5]
b- [2,5]c+ [2,5]
a- [2,5] d-
c+ [2,5]
d+
b+ [2,5]
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Gate Netlist
d
a
c
e
b
[2,3][2,3]
Gate-Level Netlist
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Gate Netlist
d
a
c
e
b
[2,3][2,3]
Gate-Level Netlist
abc
d
[2,6]
Complex Gate Equivalent (CGE)
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Checking Equivalence
abc
d
[2,6]
00000000
abcd
a+ [2,5]
b+ [2,5] c- [2,5]
b- [2,5]c+ [2,5]
a- [2,5] d-
c+ [2,5]
d+
b+ [2,5]
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abc
d
[2,6]
0000
1000
abcd
0000
1000
abcd
a+a+ [2,5]
b+ [2,5] c- [2,5]
b- [2,5]c+ [2,5]
a- [2,5] d-
c+ [2,5]
d+
b+ [2,5]
Checking Equivalence
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abc
d
[2,6]
0000
1000
1100
abcd
b+
0000
1000
1100
abcd
a+a+ [2,5]
b+ [2,5] c- [2,5]
b- [2,5]c+ [2,5]
a- [2,5] d-
c+ [2,5]
d+
b+ [2,5]
Checking Equivalence
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abc
d
[2,6]
0000
1000
1100
1101
abcd
b+
0000
1000
1100
1101
abcd
a+
d+
a+ [2,5]
b+ [2,5] c- [2,5]
b- [2,5]c+ [2,5]
a- [2,5] d-
c+ [2,5]
d+
b+ [2,5]
Checking Equivalence
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abc
d
[2,6]
0000
1111
1000
1100
1101
abcd
b+
c+
0000
1111
1000
1100
1101
abcd
a+
d+
c+
a+ [2,5]
b+ [2,5] c- [2,5]
b- [2,5]c+ [2,5]
a- [2,5] d-
c+ [2,5]
d+
b+ [2,5]
Checking Equivalence
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abc
d
[2,6]
0000
1111
1000
1100
11011110
abcd
b+
c+d
0000
1111
1000
1100
11011110
abcd
a+
d+
c+
a+ [2,5]
b+ [2,5] c- [2,5]
b- [2,5]c+ [2,5]
a- [2,5] d-
c+ [2,5]
d+
b+ [2,5]
Checking Equivalence
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abc
d
[2,6]
0000
1111
1000
1100
11011110
0110
abcd
b+
c+d
0000
1111
1000
1100
11011110
0110
abcd
a+
d+
c+
a
a+ [2,5]
b+ [2,5] c- [2,5]
b- [2,5]c+ [2,5]
a- [2,5] d-
c+ [2,5]
d+
b+ [2,5]
Checking Equivalence
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abc
d
[2,6]
0000
0010
1111
1000
1100
11011110
0110
abcd
b+
c+d
b
0000
0010
1111
1000
1100
11011110
0110
abcd
a+
d+
c+
a
a+ [2,5]
b+ [2,5] c- [2,5]
b- [2,5]c+ [2,5]
a- [2,5] d-
c+ [2,5]
d+
b+ [2,5]
Checking Equivalence
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abc
d
[2,6]
0000
0010
1111
1000
1100
11011110
0110
abcd
b+
c+d
b
0000
0010
1111
1000
1100
11011110
0110
abcd
a+
d+
c+
a
c
a+ [2,5]
b+ [2,5] c- [2,5]
b- [2,5]c+ [2,5]
a- [2,5] d-
c+ [2,5]
d+
b+ [2,5]
Checking Equivalence
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abc
d
[2,6]
0000
0100
0010
1111
1000
1100
11011110
0110
abcd
b+
b+
c+d
b
0000
0100
0010
1111
1000
1100
11011110
0110
abcd
a+
d+
c+
a
c+
c
a+ [2,5]
b+ [2,5] c- [2,5]
b- [2,5]c+ [2,5]
a- [2,5] d-
c+ [2,5]
d+
b+ [2,5]
Checking Equivalence
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0000
0100
0010
1111
1000
1100
11011110
0110
abcd
b+ a+
b+
d+
c+d
a
c+
b
c
Finding Stable States
eacb
d
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0000
0100
0010
1111
1000
1100
11011110
0110
abcd
b+ a+
b+
d+
c+d
a
c+
b
c
RisingHighFallingLow
eacb
d
Step 1: Boolean evaluation of node e.
Finding Stable States
0000
0100
0010
b+
c+
c
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0000
0100
0010
1111
1000
1100
11011110
0110
abcd
b+ a+
b+
d+
c+d
a
c+
b
c
RisingHighFallingLow
eacb
d
Finding Stable States
Step 2: Untimed stabilization of node e for d+
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0000
0100
0010
1111
1000
1100
11011110
0110
abcd
b+ a+
b+
d+
c+d
a
c+
b
c
RisingHighFallingLow
eacb
d
Finding Stable States
Step 2: Untimed stabilization of node e for d+
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0000
0100
0010
1111
1000
1100
11011110
0110
abcd
b+ a+
b+
d+
c+d
a
c+
b
c
RisingHighFallingLow
eacb
d
Finding Stable States
Step 2: State 1101 stable high.
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0000
0100
0010
1111
1000
1100
11011110
0110
abcd
b+ a+
b+
d+
c+d
a
c+
b
c
RisingHighFallingLow
eacb
d
Finding Stable States
Step 3: Untimed stabilization of node e for d-
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0000
0100
0010
1111
1000
1100
11011110
0110
abcd
b+ a+
b+
d+
c+d
a
c+
b
c
RisingHighFallingLow
eacb
d
Finding Stable States
Step 3: Untimed stabilization of node e for d-
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0000
0100
0010
1111
1000
1100
11011110
0110
abcd
b+ a+
b+
d+
c+d
a
c+
b
c
RisingHighFallingLow
eacb
d
Finding Stable States
Step 4: Propagate stable states.
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0000
0100
0010
1111
1000
1100
11011110
0110
abcd
b+ a+
b+
d+
c+d
a
c+
b
c
RisingHighFallingLow
eacb
d
Finding Stable States
Step 4: Propagate stable states.
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0000
0100
0010
1111
1000
1100
11011110
0110
abcd
b+ a+
b+
d+
c+d
a
c+
b
c
RisingHighFallingLow
eacb
d
Node e is hazard-free!
Checking for Hazards
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eabc
d
Alternative Gate-Level Netlist
eacb
d
With:
Try a different decomposition –
Replace:
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0000
0100
0010
1111
1000
1100
11011110
0110
abcd
b+ a+
b+
d+
c+d
a
c+
b
cabc
d
RisingHighFallingLow
Step 1: Boolean evaluation of node e.
Finding Stable States
e
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0000
0100
0010
1111
1000
1100
11011110
0110
abcd
b+ a+
b+
d+
c+d
a
c+
b
c eabc
d
RisingHighFallingLow
Step 2: Untimed stabilization of node e for d+
Finding Stable States
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0000
0100
0010
1111
1000
1100
11011110
0110
abcd
b+ a+
b+
d+
c+d
a
c+
b
c eabc
d
RisingHighFallingLow
Step 2: Untimed stabilization of node e for d+
Finding Stable States
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0000
0100
0010
1111
1000
1100
11011110
0110
abcd
b+ a+
b+
d+
c+d
a
c+
b
c eabc
d
RisingHighFallingLow
Finding Stable States
Step 3: Propagate stable states.
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0000
0100
0010
1111
1000
1100
11011110
0110
abcd
b+ a+
b+
d+
c+d
a
c+
b
c eabc
d
RisingHighFallingLow
Step 3: Propagate stable states.
Finding Stable States
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0000
0100
0010
1111
1000
1100
11011110
0110
abcd
b+ a+
b+
d+
c+d
a
c+
b
c eabc
d
RisingHighFallingLow
Step 4: Untimed stabilization of node e for d-
Finding Stable States
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0000
0100
0010
1111
1000
1100
11011110
0110
abcd
b+ a+
b+
d+
c+d
a
c+
b
c
RisingHighFallingLow
ACKNOWLEDGEMENTHAZARD!
Node e may glitch.
Checking Acknowledgement
eabc
d
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0000
0100
0010
1111
1000
1100
11011110
0110
abcd
b+ a+
b+
d+
c+d
a
c+
c
RisingHighFallingLow
Checking Monotonicity
eabc
d
Output d may glitch.
MONOTONICTY HAZARD!
b
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0000
0100
0010
1111
1000
1100
11011110
0110
abcd
b+ a+
b+
d+
c+d
a
c+
b
c
RisingHighFallingLow
eabc
d
[2,3] [2,3]
Consider Netlist timing.
Timed Stabilization
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0000
0100
0010
1111
1000
1100
11011110
0110
abcd
b+ a+
b+
d+
c+d
a
c+
c
RisingHighFallingLow
eabc
d
[2,3] [2,3]
Minimum elapsed time: 2
Timed Stabilization
b [2,5]
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0000
0100
0010
1111
1000
1100
11011110
0110
abcd
b+ a+
b+
d+
c+d
a
c+
b [2,5]
c [2,5]
RisingHighFallingLow
eabc
d
[2,3] [2,3]
Minimum elapsed time: 4 Node e has stabilized low
Timed Stabilization
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0000
0100
0010
1111
1000
1100
11011110
0110
abcd
b+ a+
b+
d+
c+d
a
c+
b
c
RisingHighFallingLow
eabc
d
Node e is now hazard-free!
[2,3] [2,3]
Propagate stable states.
Timed Stabilization
![Page 53: Technology Mapping of Timed Asynchronous Circuits](https://reader030.vdocument.in/reader030/viewer/2022032805/56813347550346895d9a4174/html5/thumbnails/53.jpg)
Asynchronous Design Flow
Decomposition
Partitioning
Matching/Covering
Physical Design
Cost Factors
Layout
Library
Specifications
Logic SynthesisMapping
Technology
HazardVerification
![Page 54: Technology Mapping of Timed Asynchronous Circuits](https://reader030.vdocument.in/reader030/viewer/2022032805/56813347550346895d9a4174/html5/thumbnails/54.jpg)
Partitioning
Each output is a tree-based structure which is decomposed, matched, and covered individually.Makes matching and covering tractable.May reduce quality of final netlist because gate-sharing is eliminated between outputs.For our work, synthesis provides a set of equations already partitioned by primary output.
![Page 55: Technology Mapping of Timed Asynchronous Circuits](https://reader030.vdocument.in/reader030/viewer/2022032805/56813347550346895d9a4174/html5/thumbnails/55.jpg)
Decomposition: Background
Decomposition performed to guarantee a solution.Changing the circuit structure may create hazards.Synchronous approach: Decompose synthesized circuit to base functions,
typically inverters, 2-input NANDs, and memory elements.
Asynchronous approaches are to: Decompose directly to library gates without
creating hazards (Burns, Beerel, Siegel, Kondratyev, Myers, etc).
Decompose without regard to hazard creation and remove hazards by inserting delay elements (Lavagno).
![Page 56: Technology Mapping of Timed Asynchronous Circuits](https://reader030.vdocument.in/reader030/viewer/2022032805/56813347550346895d9a4174/html5/thumbnails/56.jpg)
Decomposition: Our Approach
Follow synchronous approach, decompose into base functions (inverters, 2-input NANDs, and C-element’s).
Decompose without regard to hazard creation. Perform gate-level hazard verification. Do hazard-guided matching/covering later.
Insert inverter pairs to increase matching options.Use unbalanced structure to allow for:
Consistent architecture. Input pin re-ordering.
![Page 57: Technology Mapping of Timed Asynchronous Circuits](https://reader030.vdocument.in/reader030/viewer/2022032805/56813347550346895d9a4174/html5/thumbnails/57.jpg)
State-Holding Devices
CEL
set
~resetf resetu
f setufunctionset
u
functionreset
weak
~reset
set
u
C-elements (CEL’s).
1 0 sc hld
set ~reset gC CEL 0 0 0 0
1 1 1 1
0 1 hld hld
![Page 58: Technology Mapping of Timed Asynchronous Circuits](https://reader030.vdocument.in/reader030/viewer/2022032805/56813347550346895d9a4174/html5/thumbnails/58.jpg)
State-Holding Devices
C-elements (CEL’s).Generalized C-elements (gC’s).
set
~reset
+
f resetu
f setufunctionset
u
functionreset
gC
-
weak
~reset
setu
CEL
set
~resetf resetu
f setufunctionset
u
functionreset
weak
~reset
set
u
1 0 sc hld
set ~reset gC CEL 0 0 0 0
1 1 1 1
0 1 hld hld
![Page 59: Technology Mapping of Timed Asynchronous Circuits](https://reader030.vdocument.in/reader030/viewer/2022032805/56813347550346895d9a4174/html5/thumbnails/59.jpg)
Decomposition Architectures
CGE Netlist
Balanced
![Page 60: Technology Mapping of Timed Asynchronous Circuits](https://reader030.vdocument.in/reader030/viewer/2022032805/56813347550346895d9a4174/html5/thumbnails/60.jpg)
Decomposition Architectures
CGE Netlist
Balanced
Unbalanced
![Page 61: Technology Mapping of Timed Asynchronous Circuits](https://reader030.vdocument.in/reader030/viewer/2022032805/56813347550346895d9a4174/html5/thumbnails/61.jpg)
Decomposition Architectures
CGE Netlist
Balanced
Unbalanced with inverter pairs
Unbalanced
![Page 62: Technology Mapping of Timed Asynchronous Circuits](https://reader030.vdocument.in/reader030/viewer/2022032805/56813347550346895d9a4174/html5/thumbnails/62.jpg)
Asynchronous Design Flow
Decomposition
Partitioning
Matching/Covering
Physical Design
Cost Factors
Layout
Library
Specifications
Logic SynthesisMapping
Technology
HazardVerification
![Page 63: Technology Mapping of Timed Asynchronous Circuits](https://reader030.vdocument.in/reader030/viewer/2022032805/56813347550346895d9a4174/html5/thumbnails/63.jpg)
Matching and Covering
Structurally matches library elements to circuit decomposition.Typically guided by area, delay, or power.Ours must be guided by hazard-freedom.Proposed hazard-aware matching algorithm: Encapsulates acknowledgment hazards. Finds forcing side-inputs for monotonicity hazards.
![Page 64: Technology Mapping of Timed Asynchronous Circuits](https://reader030.vdocument.in/reader030/viewer/2022032805/56813347550346895d9a4174/html5/thumbnails/64.jpg)
Acknowledgement Hazard
Occurs when inputs to a gate change evaluation before the output stabilizes.Node must be encapsulated.
1
3 [2,4]
10 0
![Page 65: Technology Mapping of Timed Asynchronous Circuits](https://reader030.vdocument.in/reader030/viewer/2022032805/56813347550346895d9a4174/html5/thumbnails/65.jpg)
Acknowledgement Hazard
Occurs when inputs to a gate change evaluation before the output stabilizes.Node must be encapsulated.
1
01
0
0
3
1
3 [2,4]
10 0
![Page 66: Technology Mapping of Timed Asynchronous Circuits](https://reader030.vdocument.in/reader030/viewer/2022032805/56813347550346895d9a4174/html5/thumbnails/66.jpg)
Monotonicity Hazard
Occurs when an internal or output node becomes excited to change when it should stay stable.Prevented by forcing side inputs.Fanin node causing hazard must not be encapsulated.
1
1
[4,6]
[1,3]
![Page 67: Technology Mapping of Timed Asynchronous Circuits](https://reader030.vdocument.in/reader030/viewer/2022032805/56813347550346895d9a4174/html5/thumbnails/67.jpg)
Monotonicity Hazard
Occurs when an internal or output node becomes excited to change when it should stay stable.Prevented by forcing side inputs.Fanin node causing hazard must not be encapsulated.
1
1
0
[1,3]
1
1
[4,6]
[1,3]
![Page 68: Technology Mapping of Timed Asynchronous Circuits](https://reader030.vdocument.in/reader030/viewer/2022032805/56813347550346895d9a4174/html5/thumbnails/68.jpg)
Hazard-Aware Matching
Each match must undergo cost analysis.Objective is to minimize cost.Heuristic equation to determine hazard cost:
hazcost = (W1)monohaz + (W2)ackhaz
W1 ,W2 are coefficients.
monohaz is the number of exposed monotonicity hazards. ackhaz is the number of exposed acknowledgment hazards.
W1,W2 = 0: No hazard awareness.
W1,W2 = 1: Encourage encapsulation.
W1,W2 = -1: Discourage encapsulation.
W1,W2 = -1,1: Discourage monotonicity encapsulation. Encourage acknowledgment encapsulation.
![Page 69: Technology Mapping of Timed Asynchronous Circuits](https://reader030.vdocument.in/reader030/viewer/2022032805/56813347550346895d9a4174/html5/thumbnails/69.jpg)
Hazard-Aware Matching Example
ack AA
y0
y1
Mreq
![Page 70: Technology Mapping of Timed Asynchronous Circuits](https://reader030.vdocument.in/reader030/viewer/2022032805/56813347550346895d9a4174/html5/thumbnails/70.jpg)
Hazard-Aware Matching Example
W1, W2 = 0: No hazard awareness.ack AA
y0
y1
Mreq
W1, W2 = -1: Discourage encapsulation.ack AA
y0
y1
Mreq
W1, W2 = -1,1: Optimum.
ack AA
y0
y1
Mreq
1 Ack hazard.Mono hazards on req caused by
y0,y1.
W1, W2 = 1: Encourage encapsulation.ack AA
y0
y1
Mreq
No Hazards.
No Hazards.2 Ack hazards.
Mono hazard on req caused by node M.
![Page 71: Technology Mapping of Timed Asynchronous Circuits](https://reader030.vdocument.in/reader030/viewer/2022032805/56813347550346895d9a4174/html5/thumbnails/71.jpg)
Short-Circuit Issues
May occur when a gC is mapped to a portion of decomposition.
![Page 72: Technology Mapping of Timed Asynchronous Circuits](https://reader030.vdocument.in/reader030/viewer/2022032805/56813347550346895d9a4174/html5/thumbnails/72.jpg)
State = adbcx
a-
11101
0110110101
00101
a-d-
d-
x-
b+
[01]
[01]
[UU]
[U1]
Short-Circuit Issues
May occur when a gC is mapped to a portion of decomposition.
gC
-
+
6
21
-
+
11108 97
5
gC x
430a
d
a
d
Example: Map a plain gC element to a netlist.
![Page 73: Technology Mapping of Timed Asynchronous Circuits](https://reader030.vdocument.in/reader030/viewer/2022032805/56813347550346895d9a4174/html5/thumbnails/73.jpg)
Potential short-circuit in state 00101.
State = adbcx
a-
11101
0110110101
00101
a-d-
d-
x-
b+
[01]
[01]
[UU]
[U1]
gC
-
+
6
21
-
+
11108 97
5
gC x
430a
d
a
d
Short-Circuit Issues
![Page 74: Technology Mapping of Timed Asynchronous Circuits](https://reader030.vdocument.in/reader030/viewer/2022032805/56813347550346895d9a4174/html5/thumbnails/74.jpg)
Potential short-circuit in state 00101. reject gC and replace with CEL
gC
-
+
State = adbcx
a-
11101
0110110101
00101
a-d-
d-
x-
b+
[01]
[01]
[UU]
[U1]
CEL
-
+
6
21
-
+
11108 97
5
gC x
430a
d
a
d
Short-Circuit Issues
![Page 75: Technology Mapping of Timed Asynchronous Circuits](https://reader030.vdocument.in/reader030/viewer/2022032805/56813347550346895d9a4174/html5/thumbnails/75.jpg)
u
-
+
s
r
qp
gC
r
qp
weak
us
1
-
+6
11108 97
5
gC x
430a
d
a
d
2
State = adbcx
a-
11101
0110110101
00101
a-d-
d-
x-
b+
[01]
[0U]
[UU]
[U1]
Short-Circuit: Example 2
![Page 76: Technology Mapping of Timed Asynchronous Circuits](https://reader030.vdocument.in/reader030/viewer/2022032805/56813347550346895d9a4174/html5/thumbnails/76.jpg)
Short-Circuit: Example 2
u
-
+
s
r
qp
gC
1
-
+6
11108 97
5
x
430a
d
a
d
2
State = adbcx
a-
11101
0110110101
00101
a-d-
d-
x-
b+
[01]
[0U]
[UU]
[U1]
Reject gC.
r
qp
weak
us
gC
![Page 77: Technology Mapping of Timed Asynchronous Circuits](https://reader030.vdocument.in/reader030/viewer/2022032805/56813347550346895d9a4174/html5/thumbnails/77.jpg)
Common-Input Matching
Must be addressed when a library cell has a common-input on two or more leaves.Requires leaves to be driven by equivalent sub-networks.Prohibits short-circuit problems if the common-input is found in both set and reset networks of a gC.Can increase size of library dramatically.
![Page 78: Technology Mapping of Timed Asynchronous Circuits](https://reader030.vdocument.in/reader030/viewer/2022032805/56813347550346895d9a4174/html5/thumbnails/78.jpg)
Common-Inputs: Example
gC22 with 1 common-input (p)
r
p
pq
u
-
+
gC
1
-
+6
11108 97
5
gC x
430a
d
a
d
2
r
qp
weak
u
![Page 79: Technology Mapping of Timed Asynchronous Circuits](https://reader030.vdocument.in/reader030/viewer/2022032805/56813347550346895d9a4174/html5/thumbnails/79.jpg)
Common-Inputs: Example
gC22 with 1 common-input (p)
r
p
pq
u
-
+
gC
1
-
+6
11108 97
5
gC x
430a
d
a
d
2
r
qp
weak
u
![Page 80: Technology Mapping of Timed Asynchronous Circuits](https://reader030.vdocument.in/reader030/viewer/2022032805/56813347550346895d9a4174/html5/thumbnails/80.jpg)
Common-Inputs: Example
gC22 with 1 common-input (p)
r
p
pq
u
-
+
gC
1
-
+6
11108 97
5
gC x
430a
d
a
d
2
u
qp
p
r -
+
gC
![Page 81: Technology Mapping of Timed Asynchronous Circuits](https://reader030.vdocument.in/reader030/viewer/2022032805/56813347550346895d9a4174/html5/thumbnails/81.jpg)
Experimental Results
Algorithms implemented in 11,545 lines of C/C++ code within the ATACS software tool.Tests results presented for: Gate-level verification. Matching and covering.
Timed synthesis. Untimed synthesis. Hazard-aware matching.
![Page 82: Technology Mapping of Timed Asynchronous Circuits](https://reader030.vdocument.in/reader030/viewer/2022032805/56813347550346895d9a4174/html5/thumbnails/82.jpg)
Gate-level Verification
Compared our verifier with: KRONOS – timed automata tool, only checks
conformance, not hazards. Pena’s tools – conservative approximation
method, stops after finding first hazard. ATACS – explicit state timing verifier.
![Page 83: Technology Mapping of Timed Asynchronous Circuits](https://reader030.vdocument.in/reader030/viewer/2022032805/56813347550346895d9a4174/html5/thumbnails/83.jpg)
Gate-level Verification
0/00.180.34550>67817ram-read-sbuf
1/20.200.3241531.7717sbuf-ram-write
1/20.100.3022.938rpdft
1/10.080.1310.417half
3/30.130.1510.149ebergen
2/20.110.24120.1912converta
HazardsNew
CPU Time
ATACS
CPU Time
Pena
CPU Time
Kronos
CPU TimeGate
sExample
5/54.8710.7127>58024trimos-send
0/00.090.3330.0911
1/10.110.1610.639chu133
alloc-outbound
![Page 84: Technology Mapping of Timed Asynchronous Circuits](https://reader030.vdocument.in/reader030/viewer/2022032805/56813347550346895d9a4174/html5/thumbnails/84.jpg)
Gate-level Verification
0/00.180.34550>67817ram-read-sbuf
1/20.200.3241531.7717sbuf-ram-write
1/20.100.3022.938rpdft
1/10.080.1310.417half
3/30.130.1510.149ebergen
2/20.110.24120.1912converta
HazardsNew
CPU Time
ATACS
CPU Time
Pena
CPU Time
Kronos
CPU TimeGate
sExample
5/54.8710.7127>58024trimos-send
0/00.090.3330.0911
1/10.110.1610.639chu133
alloc-outbound
![Page 85: Technology Mapping of Timed Asynchronous Circuits](https://reader030.vdocument.in/reader030/viewer/2022032805/56813347550346895d9a4174/html5/thumbnails/85.jpg)
Gate-level Verification
--/524.81.20>256>2000213cnt11
--/463.30.90>256>2000164selopt
--/02.30.29>256>100085srgate
--/151.70.24>256>100080cnt3
0/01.80.2822918338elatch
0/01.30.1741.520.037lapbsv
0/01.80.1553.433.529slatch
0/01.30.137.91.3518scsiSV
HazardsNew
Mem (MB)New
Time(s)ATACS
Mem (MB)ATACSTime(s)GatesExample
![Page 86: Technology Mapping of Timed Asynchronous Circuits](https://reader030.vdocument.in/reader030/viewer/2022032805/56813347550346895d9a4174/html5/thumbnails/86.jpg)
Gate-level Verification
--/524.81.20>256>2000213cnt11
--/463.30.90>256>2000164selopt
--/02.30.29>256>100085srgate
--/151.70.24>256>100080cnt3
0/01.80.2822918338elatch
0/01.30.1741.520.037lapbsv
0/01.80.1553.433.529slatch
0/01.30.137.91.3518scsiSV
HazardsNew
Mem (MB)New
Time(s)ATACS
Mem (MB)ATACSTime(s)GatesExample
![Page 87: Technology Mapping of Timed Asynchronous Circuits](https://reader030.vdocument.in/reader030/viewer/2022032805/56813347550346895d9a4174/html5/thumbnails/87.jpg)
Gate-level Verification
--/524.81.20>256>2000213cnt11
--/463.30.90>256>2000164selopt
--/02.30.29>256>100085srgate
--/151.70.24>256>100080cnt3
0/01.80.2822918338elatch
0/01.30.1741.520.037lapbsv
0/01.80.1553.433.529slatch
0/01.30.137.91.3518scsiSV
HazardsNew
Mem (MB)New
Time(s)ATACS
Mem (MB)ATACSTime(s)GatesExample
![Page 88: Technology Mapping of Timed Asynchronous Circuits](https://reader030.vdocument.in/reader030/viewer/2022032805/56813347550346895d9a4174/html5/thumbnails/88.jpg)
Matching: Timed Synthesis
128selopt
21trimos-send
5sbuf-send-ctl
7ebergen
52cnt11
12cnt3
0chu133
0alloc-outbound
Com-InputsS-StackComboSimpleExample
![Page 89: Technology Mapping of Timed Asynchronous Circuits](https://reader030.vdocument.in/reader030/viewer/2022032805/56813347550346895d9a4174/html5/thumbnails/89.jpg)
Matching: Timed Synthesis
19128selopt
321trimos-send
05sbuf-send-ctl
27ebergen
052cnt11
012cnt3
00chu133
00alloc-outbound
Com-InputsS-StackComboSimpleExample
![Page 90: Technology Mapping of Timed Asynchronous Circuits](https://reader030.vdocument.in/reader030/viewer/2022032805/56813347550346895d9a4174/html5/thumbnails/90.jpg)
Matching: Timed Synthesis
1919128selopt
3321trimos-send
005sbuf-send-ctl
227ebergen
0052cnt11
0012cnt3
000chu133
000alloc-outbound
Com-InputsS-StackComboSimpleExample
![Page 91: Technology Mapping of Timed Asynchronous Circuits](https://reader030.vdocument.in/reader030/viewer/2022032805/56813347550346895d9a4174/html5/thumbnails/91.jpg)
Matching: Timed Synthesis
171919128selopt
3321trimos-send
0005sbuf-send-ctl
0227ebergen
00052cnt11
00012cnt3
0000chu133
0000alloc-outbound
Com-InputsS-StackComboSimpleExample
0
![Page 92: Technology Mapping of Timed Asynchronous Circuits](https://reader030.vdocument.in/reader030/viewer/2022032805/56813347550346895d9a4174/html5/thumbnails/92.jpg)
Matching: Untimed Synthesis
*selopt
121trimos-send
17sbuf-send-ctl
26ebergen
177cnt11
60cnt3
26chu133
14alloc-outbound
Com-InputsS-StackComboSimpleExample
![Page 93: Technology Mapping of Timed Asynchronous Circuits](https://reader030.vdocument.in/reader030/viewer/2022032805/56813347550346895d9a4174/html5/thumbnails/93.jpg)
Matching: Untimed Synthesis
**selopt
26121trimos-send
417sbuf-send-ctl
426ebergen
17177cnt11
1560cnt3
426chu133
014alloc-outbound
Com-InputsS-StackComboSimpleExample
![Page 94: Technology Mapping of Timed Asynchronous Circuits](https://reader030.vdocument.in/reader030/viewer/2022032805/56813347550346895d9a4174/html5/thumbnails/94.jpg)
Matching: Untimed Synthesis
***selopt
2626121trimos-send
4417sbuf-send-ctl
4426ebergen
1717177cnt11
5560cnt3
4426chu133
0014alloc-outbound
Com-InputsS-StackComboSimpleExample
![Page 95: Technology Mapping of Timed Asynchronous Circuits](https://reader030.vdocument.in/reader030/viewer/2022032805/56813347550346895d9a4174/html5/thumbnails/95.jpg)
Matching: Untimed Synthesis
****selopt
282626121trimos-send
44417sbuf-send-ctl
34426ebergen
151717177cnt11
45560cnt3
44426chu133
00014alloc-outbound
Com-InputsS-StackComboSimpleExample
![Page 96: Technology Mapping of Timed Asynchronous Circuits](https://reader030.vdocument.in/reader030/viewer/2022032805/56813347550346895d9a4174/html5/thumbnails/96.jpg)
Matching: Untimed Synthesis
****selopt
282626121trimos-send
44417sbuf-send-ctl
34426ebergen
151717177cnt11
45560cnt3
44426chu133
00014alloc-outbound
Com-InputsS-StackComboSimpleExample
![Page 97: Technology Mapping of Timed Asynchronous Circuits](https://reader030.vdocument.in/reader030/viewer/2022032805/56813347550346895d9a4174/html5/thumbnails/97.jpg)
Hazard-Aware Matching
8/48/58/48/410/97/4rpdft
13/413/413/513/422/1313/5sbuf-ram-write
26/1526/1528/1726/1551/4028/20cnt11
13/413/415/413/624/2014/11cnt3
33/2437/2833/2437/2856/4533/24trimos-send
10/410/410/210/220/1310/2sbuf-send-ctl
18/218/218/218/226/1217/7ram-read-sbuf
17/217/215/215/218/215/4nowick
5/25/25/25/210/86/4half
9/39/39/59/313/89/5ebergen
16/516/516/216/524/1615/11converta
6/46/46/46/413/106/4chu133
14/014/016/014/013/313/7alloc-outbound
(-1,2)(-1,1)(1,1)(0,1)(-1,0)(0,0)Example
![Page 98: Technology Mapping of Timed Asynchronous Circuits](https://reader030.vdocument.in/reader030/viewer/2022032805/56813347550346895d9a4174/html5/thumbnails/98.jpg)
Hazard-Aware Matching
Test conditions for 21 circuits: Untimed synthesis. Untimed verification. Common-input library implementation.
![Page 99: Technology Mapping of Timed Asynchronous Circuits](https://reader030.vdocument.in/reader030/viewer/2022032805/56813347550346895d9a4174/html5/thumbnails/99.jpg)
Hazard-Aware Matching
Test conditions for 21 circuits: Untimed synthesis. Untimed verification. Common-input library implementation.
Compared various coefficients of W1,W2 : W1,W2 = 0,0: No hazard awareness. W1,W2 = -1,0: Discourage mono encap, ignore ack. W1,W2 = 0,1: Ignore mono, encap ack. W1,W2 = 1,1: Encourage encapsulation. W1,W2 = -1,1: Discourage mono encap, encap ack. W1,W2 = -1,2: Discourage mono encap, double encap ack.
![Page 100: Technology Mapping of Timed Asynchronous Circuits](https://reader030.vdocument.in/reader030/viewer/2022032805/56813347550346895d9a4174/html5/thumbnails/100.jpg)
Hazard-Aware Matching
Results (win means fewer hazards in final netlist):
0,1 compared to –1,019 wins, 0 losses 0,1 compared to 0,0 13 wins, 2 losses 0,1 compared to 1,1 7 wins, 3 losses 0,1 compared to –1,14 wins, 1 loss 0,1 compared to –1,23 wins, 2 losses
![Page 101: Technology Mapping of Timed Asynchronous Circuits](https://reader030.vdocument.in/reader030/viewer/2022032805/56813347550346895d9a4174/html5/thumbnails/101.jpg)
Hazard-Aware Matching
Results (win means fewer hazards in final netlist):
0,1 compared to –1,019 wins, 0 losses 0,1 compared to 0,0 13 wins, 2 losses 0,1 compared to 1,1 7 wins, 3 losses 0,1 compared to –1,14 wins, 1 loss 0,1 compared to –1,23 wins, 2 losses
Lessons: Must encapsulate acknowledgement hazards.
![Page 102: Technology Mapping of Timed Asynchronous Circuits](https://reader030.vdocument.in/reader030/viewer/2022032805/56813347550346895d9a4174/html5/thumbnails/102.jpg)
Hazard-Aware Matching
Results (win means fewer hazards in final netlist):
0,1 compared to –1,019 wins, 0 losses 0,1 compared to 0,0 13 wins, 2 losses 0,1 compared to 1,1 7 wins, 3 losses 0,1 compared to –1,14 wins, 1 loss 0,1 compared to –1,23 wins, 2 losses
Lessons: Must encapsulate acknowledgement hazards. Give more emphasis to acknowledgment hazards.
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Hazard-Aware Matching
Results (win means fewer hazards in final netlist):
0,1 compared to –1,019 wins, 0 losses 0,1 compared to 0,0 13 wins, 2 losses 0,1 compared to 1,1 7 wins, 3 losses 0,1 compared to –1,14 wins, 1 loss 0,1 compared to –1,23 wins, 2 losses
Lessons: Must encapsulate acknowledgement hazards. Give more emphasis to acknowledgment hazards. Perhaps ignore monotonicity hazards all together.
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Hazard-Aware Matching
Results (win means fewer hazards in final netlist): 0,1 compared to –1,019 wins, 0 losses 0,1 compared to 0,0 13 wins, 2 losses 0,1 compared to 1,1 7 wins, 3 losses 0,1 compared to –1,14 wins, 1 loss 0,1 compared to –1,23 wins, 2 losses
Lessons: Must encapsulate acknowledgement hazards. Give more emphasis to acknowledgment hazards. Perhaps ignore monotonicity hazards all together. Try multiple solutions and pick the best.
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Conclusions
Synchronous technology mapping flow is adaptable to timed circuit technology mapping.Gate-level hazard verifier using timing is feasible.gC’s work well when short-circuit and common-input issues are resolved.Timed synthesis and verification, hazard-aware matching, in most cases, produce hazard-free circuits.
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Contributions
Adapting synchronous technology mapping flow to timed circuits.Efficient gate-level hazard verification using timing.Hazard-aware matching and covering algorithms utilizing gC’s in circuit solutions.
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Future Work
Investigate: Whether or not hazards are false. Hazard reduction via input re-ordering. Hazard reduction via inertial delay models. Hazard-free outputs with internal hazardous behavior. Circuits with internal cycles. Using other specification forms to increase example
suite. Monotonicity hazard creation during hazard-aware
matching.