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Time-Domain Segmentation based Massively Parallel Simulation
Bichen WuDept. Micro/nano electronicsTsinghua Univ., Beijing, ChinaEmail:[email protected]: +86 152 1056 0855
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Background• On the one hand, transient circuit simulation is time
consuming• Sigma-Delta ADC: 71h• SAR ADC: 41h• FLASH ADC: 38h• PLL: 148h
• On the other hand, we got strong parallel computing resource• Many core, distributed computing
• How can we increase the circuit simulation efficiency with parallel computing?
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Circuit simulation Transient circuit simulation is to solve the
initial condition problem of the following differential equation
Backward Euler was used to convert the above to sequence of discrete equations
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Previous parallel circuit simulation Domain decompositionA New Partitioning Method for Parallel Simulation of VLSI Circuits on Transistor Level ( 1996 )
Parallel numerical integral methodWavePipe: Parallel Transient Simulation of Analog and Digital Circuits on Multi-Core Shared-Memory Machines(DAC 2008)
Multi-algorithm parallelHierarchical Multi-algorithm Parallel Circuit Simulation (TCAD 2011)
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Time domain segmentation based parallel simulation
Method descriptiont0 tend
t0
t1
t2
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Time domain segmentation based parallel simulation
In general, solution of equation is dependent on initial condition
Uncertainty brought by time domain segmentation may leads to erroneous result
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Short memory assumption
Short memory : the state of the circuit at a certain time point is correlated only to the a limited history of the the input as well as the internal state of the circuit.
Circuits such as ADC , possess short memory property
A
D
Analog input
Digital output
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Calculating SNDR through transient simulation for ADC
A
DAnalog input
Digital output
Fourier Transfor
m Power spectrum density
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Two examples5bits FLASH ADC Fsam=3.75GHz, Ttotal=2us, Tov=6ns
Time for serial simulation : 38hNumber of segmentation : 1 , 2 , 4 , 8 , 100
6bits SAR ADC Fsam=2GHz, Ttotal=8us, Tov=13.3ns
Time for serial simulation : 41hNumber of segmentation : 1 , 2 , 4 , 8 , 100
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Transient simulation for ADCPower spectrum density of FLASH ADC(left) and SAR ADC ( right ) output, with serial and parallel simulation
FLASH SAR
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Transient simulation for ADC
Result
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Transient simulation for Sigma-Delta ADC
Sigma-Delta modulatorBecause of integrator, it’s not short memory
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Transient simulation for Sigma-Delta ADC
Direct segmentation with the modulator output of modulator brings erroneous result
Time domain deviation between serial and parallel result
Frequency domain deviation between serial and parallel result
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Transient simulation for Sigma-Delta ADC
Uncertainty brought by time domain segmentation
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Transient simulation for Sigma-Delta ADC
Digital filter realized in
matlab
Solution:
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Transient simulation for Sigma-Delta ADC
Result showed efficiency enhancement with high accuracy
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Transient simulation for PLL
Phase lock loop(PLL) is not short memory circuit Self-driven system Integral property
f[ ] h(t)+-
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Transient simulation for PLL
Phase lock loop(PLL)The expression of the phase growth in the equation above is as follow.
Let
So we get:
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Transient simulation for PLL
Phase lock loop(PLL)
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Transient noise analysis
PSD of 1/f noise generated in serial and parallel
Parallel:
Serial
The bandwidth gets wider
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Transient noise analysis
1/f noise in TDSM
serial parallel
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Summary We proposed TDSM for transient circuit simulation
Testified on FLASH , SAR , Sigma-Delta ADC
Maximum 78X acceleration with 100 cores parallelization
Efficient for phase noise simulation for PLL, testified by behavior model.
Proposed 1/f noise generator that support TDSM,
testified on a single transistor
Now submitted to DAC 2013