Time to Digital Conversion Performance Metrics and Tests
Jean-Francois GenatIN2P3/LPNHE Paris
IEEE Nuclear Science Symposium and Medical Imaging ConferenceOctober 23d 2011, Valencia, Spain
Key Performance Metrics of Time to Digital Coders and Techniques
for their Performance evaluation
Outline Time to Digital conversion TDC Performance Tests Conclusion
Time to Digital Conversion Performance Metrics and Tests, October 23d 2011, Valencia, Spain
Time to Digital Coding
Two edges as input, a number as output
Least significant bit = Input time quantum for one output unit difference
t = 1, LSB = 10ns
Time to Digital Conversion Performance Metrics and Tests, October 23d 2011, Valencia, Spain
Time to Digital Coding
“Coarse” < 1ns (1 GHz) time coding with counters
“Fine” 1-1000ps time coding with either
Time to Amplitude Coder and ADCor Digital delay lines phased locked on clock (DLL)
Both techniques can be differential or notIf a short time range only is required, single TAC or DLL OK.
Time to Digital Conversion Performance Metrics and Tests, October 23d 2011, Valencia, Spain
Architecture
Clock
Counter Fine time Synchro
Start Stop
Storage
MSB LSB
Time to Digital Conversion Performance Metrics and Tests, October 23d 2011, Valencia, Spain
Sub-multiples Multiples
Coarse, Fine scales
Electronics devices
- The unit is defined by the period of a « clock » synchronized on a reference frequency (e.g quartz, GPS)
- Multiples or sub-multiples can be measured:
Slower:
« Counters » divide frequencies, sub-multiples, « coarse » measurements
Faster:
« Verniers » multiples of clock frequency, « fine » measurements
Time to Digital Conversion Performance Metrics and Tests, October 23d 2011, Valencia, Spain
Features
Physical Interest
Timing resolution Dynamic range Linearity Response time Timing jitter Double pulse resolution
Response time Long-term stability
Power Integration, package Number of channels …
Environment , data acquisition standard,
Time to Digital Conversion Performance Metrics and Tests, October 23d 2011, Valencia, Spain
Key Performance Metrics of Time to Digital Coders and Techniques
for their Performance evaluation
Outline
Time to Digital conversion TDC Performance Tests Conclusion
Time to Digital Conversion Performance Metrics and Tests, October 23d 2011, Valencia, Spain
Numbers
- Resolution (binning, time jitter)- Full scale (number of bits) - Linearities (differential, integral)- Number of channels- Stop mode, input triggering capability- Double pulse resolution- Maximum input rate- Buffering capability- Response time- Reference clock range- Stability (temperature, voltage supply)
- Encoding, output format, trigger matching - Technology, input levels- Power, low power mode- Package, IP availability, voltage supply
Time to Digital Conversion Performance Metrics and Tests, October 23d 2011, Valencia, Spain
Units
Time to Digital Conversion Performance Metrics and Tests, October 23d 2011, Valencia, Spain
Resolution/StabilityLimitations
Coarse measurements: Clock jitter Ultimately in the ps range with current integrated CMOS technologies, but the reference dictates the jitter: GPS is 10ns only *
Fine measurements:Propagation spreads of delay elements and sensitivity to:- Voltage supply- Temperature- Process variations
ADC components used in Time to Amplitude Converters
Time to Digital Conversion Performance Metrics and Tests, October 23d 2011, Valencia, Spain
*The experiment OPERA at CERN measured very recently 60ns vith an accuracy of 10ns in order to estimate the neutrinos velocity
http://cerncourier.com/cws/article/cern/28439
Time References: Atomic Clock Chip
Courtesy: NIST
A few mm3
Time to Digital Conversion Performance Metrics and Tests, October 23d 2011, Valencia, Spain
StabilityShort time stability: < 1sLong term > 1s
Hydrogen clock: 1 femtosecond / second
Time to Digital Conversion Performance Metrics and Tests, October 23d 2011, Valencia, Spain
Phase noise, jitter
Δf
Power Spectrum:
Phase noise as Pnoise / Psignal in dB/Hz at a given frequency offset at one side from the carrier
http://smirc.stanford.edu/papers/iwdmic98s-raf.pdf
∣L( f )∣
Due to any analog noise source in the oscillator (thermal, 1/f…)Carrier: Psignal
Sideband Pnoise
Time to Digital Conversion Performance Metrics and Tests, October 23d 2011, Valencia, Spain
Frequency multiplication: coarse -> fine
- The reference is a device whose (time noise) jitter is smallcompared to the fine time bin
- The Voltage Controlled Oscillator (VCO) runs at a multiple ofthe reference frequency
Time to Digital Conversion Performance Metrics and Tests, October 23d 2011, Valencia, Spain
Frequency division
Counter : N
Clock
Counter
Memory
Start / Stop
Time to Digital Conversion Performance Metrics and Tests, October 23d 2011, Valencia, Spain
Scaling
Sub-multiples: Frequency division using (synchronous) Counters
Multiples: Frequency multiplication: Phase Locked Loops
5 MHz clock scaled to 20 MHz and 625 kHz
Time to Digital Conversion Performance Metrics and Tests, October 23d 2011, Valencia, Spain
Fine timing: Time to Amplitude Converter A voltage ramp is triggered on ‘Start’, stopped on “Stop”
Stop can be a clock edge
Amplitude is coded with a conventional ADC
ADCStart
Stop
To ADC
Time to Digital Conversion Performance Metrics and Tests, October 23d 2011, Valencia, Spain
A calibration of the current source is required to match a possible concurrent« coarse » measurement
Differential TAC
Same as above, ramp goes up at rate , down at rate
Time is stretched by , measured using a regular counter
δ ( v 1
v 2 )
ν1ν 2
To counter
ν 1
Resolution: a few ps
Time to Digital Conversion Performance Metrics and Tests, October 23d 2011, Valencia, Spain
ν2<< ν1
Fine timing: Digital Delay Lines- Locked delay line (DLL) or ring oscillator (PLL) if looped Loop of voltage controlled delay elements locked on a clock.
- Generation of subsequent logic transitions distant by can be as small as 10-100 ps
N delay elements
Delay + time offset controls
Time arbiter
Total delay is half a clock period when locked, the two edges can be locked
Clock
Time to Digital Conversion Performance Metrics and Tests, October 23d 2011, Valencia, Spain
[J-F. G High Resolution Time to Digital Converters Nucl. Instr. and Meth., Vol 315, N1-3, May 1992, pp 411-415]
Delay elementsActive RC element: R resistance of a switched on transistor
C total capacitance at the connecting node
Typically RC = 10ps-1ns using current IC technologies
σ
N delay elements
σ N = σ √ N is technology dependent: the fastest, the best !
Within a chip ~ 1 % a wafer ~ 5-10% a lot ~ 10-20%
[Mantyniemi et al. IEEE JSSC 28-8 pp 887-894]
Time to Digital Conversion Performance Metrics and Tests, October 23d 2011, Valencia, Spain
Time controlled delay element: Starved CMOS inverter
CMOS Technology 90 nm: >~ 20 ps45nm < L < 250nm : 65 nm in production today
Propagation delay ~ 10ps-1ns
Delay controlsthrough gatesvoltages PMOS
NMOS
B=A
100ps TDC 0.6 mm CMOS (1992)
Time to Digital Conversion Performance Metrics and Tests, October 23d 2011, Valencia, Spain
Starved CMOS inverter cell (CMOS 130nm)
Time to Digital Conversion Performance Metrics and Tests, October 23d 2011, Valencia, Spain
Phase lock
Lag Lag Lead OK
Clock
DLL output
Phase arbiter
Delay control
Time to Digital Conversion Performance Metrics and Tests, October 23d 2011, Valencia, Spain
Convergence when the device lags and leads alternately
Time arbitration
In1 In2
Y1 Y2
Six transistors implementation in CMOS
[V. Gutnik et al. MIT IEEE 2000 Symp. on VLSI Circuits]
Time to Digital Conversion Performance Metrics and Tests, October 23d 2011, Valencia, Spain
Issue: metastable states ifS and R “almost” synchronous(Spice simlation)
Final state depends upon first input activated:
in1 prior Iin2: Q=1 , Q=0in1 after in2: Q=0, Q=1
Time arbitration (FPGA)SR flip-flop in the “forbidden” state
R
S
Q
Q
Time to Digital Conversion Performance Metrics and Tests, October 23d 2011, Valencia, Spain
Can be implemented in an FPGA or IC standard cells (simulate after routing !)
Observed Metastability (from Eric Delagnes)
Phase comparator
Time to Digital Conversion Performance Metrics and Tests, October 23d 2011, Valencia, Spain
Latched Phase Comparator
Fast Stop catches slow StartTime quantum t1-t2 as small as technology spreads allow
Nbit = number of bits for ½ LSB precisionT = full-scale (maximum time interval to be measured) = delay elements spread
Nbit=12 Log2 (T / σ )
SR q0 q1 q2 qn
Start
StopN cellst2
t1
t2 < t1
Differential Delay Lines Time Vernier
[J-F. G High Resolution Time to Digital Converters Nucl. Instr. and Meth., Vol 315, N1-3, May 1992, pp 411-415]
Time to Digital Conversion Performance Metrics and Tests, October 23d 2011, Valencia, Spain
Time Vernier
Work for DELPHI (LEP) Outer Detector (1984 ! )
500 ps binning, 150ps resolution TDC using digital delay lines
2 mm CMOS Gate Array technology, all digital, but simulated as analog (Spice)
This work scaled today : 150 ps x 65nm / 2000nm = 4.8 ps
Time to Digital Conversion Performance Metrics and Tests, October 23d 2011, Valencia, Spain
Multipulse Time Vernier
Multipulse : - Generate vernier references at any time - Arbiter with incoming start and stopsClock propagated
J. Christiansen (CERN), see HPTDC slide
t1t2
Time to Digital Conversion Performance Metrics and Tests, October 23d 2011, Valencia, Spain
Full-scale
Maximum time to be encoded
T = LSB 2N
where N is the Number of bits of the device
Example: LSB= 10ns, N=16 bits
T = 653.6 ms
Full-scale, Number of bits
Time to Digital Conversion Performance Metrics and Tests, October 23d 2011, Valencia, Spain
Linearities
Integral linearity Difference between what should be measured and what is actually measured
Differential linearity Histogram of the bins widths
Both expressed in LSB units rms on the full time range
Time to Digital Conversion Performance Metrics and Tests, October 23d 2011, Valencia, Spain
LinearitiesIntegral linearity
Difference between what is measured and what should be measured
Differential linearity
Histogram of the bin’s width
- Can be specified as maximum or rms in LSB units - Integral linearity is the integral of the differential one
Time to Digital Conversion Performance Metrics and Tests, October 23d 2011, Valencia, Spain
Linearities: Example
Linearities for a 6 bit, 500ps LSB, 32ns full-scale CMOS TDC
Time to Digital Conversion Performance Metrics and Tests, October 23d 2011, Valencia, Spain
Number of channels, Stop modes, Triggering
Number of channels Number of independent channels inputs on an (IC) device, usually a power of 2 (e.g 32, 64).
May share some controls: Clock, Common start, Common stop, Gate
Triggering A channel may be triggered by an input level above a programmable threshold, the time and address are recorded in an event buffer
Time to Digital Conversion Performance Metrics and Tests, October 23d 2011, Valencia, Spain
Picosecond chipsDigital
Vernier delay lines offer 5–100 ps resolution for multi-channel chips
Full custom: 25ps J. Christiansen, CERN
8ps J. Jansson, A. Mantyniemi, J Kostamovaara, Olou Univ (Finland)
Analog
10ps TAC chip available from ACAM (2 channels) if channel rate < 500 kHz, 40ps @40 MHz
GHz Analog Memories
PSI (Stefan Ritt) 8GHz Timing resolution 10ps Hawaii (G. Varner 6 GHz Timing resolution 4ps Chicago (H. Frisch) 15 GHz Planned 2ps (under evaluation)
Time to Digital Conversion Performance Metrics and Tests, October 23d 2011, Valencia, Spain
The CERN High Precision TDC (HPTDC)
37Time to Digital Conversion Performance Metrics and Tests, October 23d 2011, Valencia, Spain
http://tdc.web.cern.ch/tdc/hptdc/hptdc.htm
The HPTDC is a high performance IC TDC with a highly flexible data driven architecture that allows it to be used in many different applications. The
architecture was originally developed for the use within the ATLAS and CMS muon detectors and for the ALICE Time Of Flight (TOF) detector. The HPTDC chip has now
been used by a multitude of different applications in particle physics and other research areas. The HPTDC can work in two major modes:
Low resolution: 32 channels with 100ps resolutionHigh resolution: 8 channels with 25ps resolution
Commercial general purpose TDC modules have also been made based on the HPTDC:
CAEN: V1190A, V1190B, V1290ABluesky electronics,
Cronologic.
Picosecond electronics
Becker & HicklGermany
5ps rms @ 200 MHz
Time to Digital Conversion Performance Metrics and Tests, October 23d 2011, Valencia, Spain
ACAM 10ps TDC
39Time to Digital Conversion Performance Metrics and Tests, October 23d 2011, Valencia, Spain
http://www.acam.de/products/time-to-digital-converters//
ACAM 10ps TDC
40
M-Mode
* 2 channels with 10 ps BIN * 70 ps peak-peak * Differential LVPECL inputs * Measurement range 0 ns to > 10 µs * Single hit per Start * Minimum pulsewidth 1.5 ns * Trigger to rising or falling edge * Quiet Mode (no ALU operation and Data-output during measurements) * 500 kHz continuous rate per channel
Time to Digital Conversion Performance Metrics and Tests, October 23d 2011, Valencia, Spain
Key Performance Metrics of Time to Digital Coders and Techniques for their Performance evaluation
Outline Time to Digital conversion TDC Performance Tests Conclusion
Time to Digital Conversion Performance Metrics and Tests, October 23d 2011, Valencia, Spain
TDC test benches
42
Can also use test benches with standard instrumentation such as: - CAMAC- Fastbus- VME- IEEE 488 (GPIB)- ATCA (very new)
Time to Digital Conversion Performance Metrics and Tests, October 23d 2011, Valencia, Spain
Test software:
Send random starts/stops with sufficient statistics and build histograms
Evaluate linearities, stability
TDC tests
43
http://www.quantumcomposers.com/item/9530-series.html
Time to Digital Conversion Performance Metrics and Tests, October 23d 2011, Valencia, Spain
Pulse generators
TDC tests
44http://www.greenfieldtechnology.com/IMG/pdf/GFT1004.pdf
Time to Digital Conversion Performance Metrics and Tests, October 23d 2011, Valencia, Spain
Pulse generators
45
http://www.highlandtechnology.com/DSS/V880DS.shtml
Time to Digital Conversion Performance Metrics and Tests, October 23d 2011, Valencia, Spain
Pulse generators TDC tests
Key Performance Metrics of Time to Digital Coders and Techniques for their Performance evaluation
Outline
Time to Digital conversion TDC Performance Tests Conclusion
Time to Digital Conversion Performance Metrics and Tests, October 23d 2011, Valencia, Spain46
Time to Digital Coders reach the picosecond range resolution
Many flavours, from various Deep Submicron CMOS technologies IC implementations
Today, 10 ps is integrated with regular CMOS IC processes
In all case, layout is more than critical as far as the ps range is targeted
Promising results from even thinner VLSI CMOS technologies in terms of
- Resolution- Dynamic range- Power- Number of Channels
Conclusion
Time to Digital Conversion Performance Metrics and Tests, October 23d 2011, Valencia, Spain47
Reference
Time to Digital Conversion Performance Metrics and Tests, October 23d 2011, Valencia, Spain
Y. Arai and M. Ikeno, “A Time Digitizer CMOS Gate-Array with a 250 ps Time Resolution”, IEEE Journal of Solid-State Circuits, Vol. 31, No.2,Feb. 1996, p.212-220.
- Y. Arai and M. Ikeno, “A Time Digitizer CMOS Gate-Array with a 250 ps Time Resolution”,
- IEEE Journal of Solid-State Circuits, Vol. 31, No.2, Feb. 1996, p.212-220.- A. Mantinyemi ”An Integrated CMOS High Prcision Time-To-Digital Converter Based On Stabilised Three Stage Delay Line Interpolation “ PhD dissertation, University of Oulu, Finland (2004)- M. Mota et al., “A Four Channel, Self-calibrating, High Resolution TDC,” Proceedings of the 5th IEEE International Conference onElectronics Circuits and Systems (ICECS’98), Lisbon, Sept 1998.- M. Mota, J. Christiansen, “A High-Resolution Time Interpolator Based on a DLL and a RC Delay Line”, IEEE JSSC, Vol 34, n°10, Oct 1999.Audoin & Guinot,1998, Les fondements de la mesure du temps , Masson , ISBN 2-225-83261-7;