Feb. 28, 2007 D&T Seminar Spring 2007 1
Transition Delay Fault Testing of Microprocessors
by Spectral MethodNitin Yogi and Vishwani D. AgrawalAuburn UniversityDepartment of ECEAuburn, AL 36849, USA
To be presented at the 39th Southeastern Symposium on System Theory (SSST), to be held in Macon, Georgia from March 4th to March 6th, 2007.
Feb. 28, 2007 D&T Seminar Spring 2007 2
OutlineIntroduction
Defects and Transition Delay Fault ModelMicroprocessor testing Issues
Problem and ApproachRTL transition delay faultsSpectral analysis & test generationTest set compaction
RTL DFTExperimental ResultsConclusion
Feb. 28, 2007 D&T Seminar Spring 2007 3
Physical DefectsDistributed defects
Systematic in natureCaused by errors in manufacturing process
Spot defectsRandom in natureCaused by local process variationsClassified based on temporal nature of defect
Active defectsLatent defects
Classified based on nature of defectOpen circuit defectsBridging defects
Feb. 28, 2007 D&T Seminar Spring 2007 4
Open Circuit Defects
Reference: W. Maly, “Realistic Fault Modeling for VLSI Testing”, Proceedings of the 24th ACM/IEEE Design Automation Conference, 1987, Miami Beach, Florida, Pages: 173-180
Feb. 28, 2007 D&T Seminar Spring 2007 5
Bridging Defects
Reference: W. Maly, “Realistic Fault Modeling for VLSI Testing”, Proceedings of the 24th ACM/IEEE Design Automation Conference, 1987, Miami Beach, Florida, Pages: 173-180
Feb. 28, 2007 D&T Seminar Spring 2007 6
Latent Defect
Reference: W. Maly, “Realistic Fault Modeling for VLSI Testing”, Proceedings of the 24th ACM/IEEE Design Automation Conference, 1987, Miami Beach, Florida, Pages: 173-180
Feb. 28, 2007 D&T Seminar Spring 2007 7
Fault ModelingModels to capture characteristics of physical defectsSome Fault Models:
Stuck-atBridgingIDDQ
Delay Fault Models
Feb. 28, 2007 D&T Seminar Spring 2007 8
Stuck-at Fault ModelVDD
A
B
Y
Short defect
Stuck-at 1
1
1
ON
OFF
NAND cell
GND
Feb. 28, 2007 D&T Seminar Spring 2007 10
Iddq Fault Model
VDD
A
B
Y
Short defect
1
1
ON
OFF
ON
Iddq
NAND cell
GND
Feb. 28, 2007 D&T Seminar Spring 2007 11
Timing DefectsGive rise to timing violationsCauses of timing defects:
Resistive bridges and opensIR drop in power gridsCapacitive couplingGeometrical abnormalitiesGate threshold variationsEtc …
Delay Fault Models Transition Delay Fault Model
Slow-to-riseSlow-to-fall
Path Delay Fault ModelDelay in path(s) exceeds specification
Feb. 28, 2007 D&T Seminar Spring 2007 12
Transition Delay Fault Model
VDD
A
B
Y
Slow to turn OFF
Input B
Output Y(good)
Output Y(faulty)
Slow-to-rise fault
NAND cell
Tpgood
Tpfaulty
time
Feb. 28, 2007 D&T Seminar Spring 2007 13
Transition Fault Detection
Slow-to-rise faultA
B
CY
Fault activated
Fault detected
Feb. 28, 2007 D&T Seminar Spring 2007 14
Microprocessor Testing Issues Issues arising from Increased Design Complexity
Increased Test Generation ComplexityViable Test Method: RTL test generationAdvantages:
Low testing complexityEarly detection of testability issues
Increased Demands on TestingViable Test Method: Functional at-speed testsAdvantages:
Better defect coverageDetection of delay faults
Feb. 28, 2007 D&T Seminar Spring 2007 15
Problem and ApproachThe problem is …
Develop an RTL-based ATPG method to generate functional at-speed tests.
And our approach is …Circuit characterization using RTL:
RTL test generationAnalysis of information content and noise in RTL vectors.
Test generation for gate-level implementation:Generation of spectral vectorsFault simulation and vector compaction
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Faults Modeled for an RTL Module
CombinationalLogic
FF
FF
Inputs Outputs
RTL transition
delay fault sites
A circuit is an interconnect of several RTL modules.
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Walsh Functions and Hadamard Spectrum
1 1 1 1 1 1 1 11 -1 1 -1 1 -1 1 -11 1 -1 -1 1 1 -1 -11 -1 -1 1 1 -1 -1 11 1 1 1 -1 -1 -1 -11 -1 1 -1 -1 1 -1 11 1 -1 -1 -1 -1 1 11 -1 -1 1 -1 1 1 -1
H8 =
w0
w1
w2
w3
w4
w5
w6
w7
Wal
sh fu
nctio
ns (o
rder
8)
• Walsh functions form an orthogonal and complete set of basis functions that can represent any arbitrary bit-stream.
• Walsh functions are the rows of the Hadamard matrix.
• Example of Hadamard matrix of order 8:
Feb. 28, 2007 D&T Seminar Spring 2007 18
Analyzing Bit-Streams
0 to -1
Bit-stream
Vector 1Vector 2
.
.
.
Inpu
t 1
Inpu
t 2 . . .
Bit-stream ofInput 2
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Spectral Characterization of a Bit-Stream
Bit stream to analyze
Correlating with Walsh functions by multiplying with Hadamard matrix.
Essential component (others regarded noise)
Hadamard Matrix
Bit stream
Spectral coeffs.
Feb. 28, 2007 D&T Seminar Spring 2007 20
Generation of New Bit-StreamsPerturbation
Generation of new bit-stream by multiplying with Hadamard matrix
Spectral components
Essential component
retained; noise components
randomly perturbed
New bit stream
Bits changed
Sign function
-1 to 0
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PARWAN Processor
Reference: Z. Navabi, Analysis and Modeling of Digital Systems. New York: McGraw-Hill, 1993.
Feb. 28, 2007 D&T Seminar Spring 2007 22
Power Spectrum for “Interrupt” Bit-Stream
Spectral Coefficients
Nor
mal
ized
Pow
er
Essential components
Some noise components
Randomlevel
(1/128)
Analysis of 128 test vectors.
Feb. 28, 2007 D&T Seminar Spring 2007 23
Power Spectrum for “DataIn[5]” Signal
Theoretical random noise
level(1/128)
Nor
mal
ized
Pow
er
Spectral Coefficients
Some essential
componentsSome noise components
Analysis of 128 test vectors.
Feb. 28, 2007 D&T Seminar Spring 2007 24
Power Spectrum for Random SignalN
orm
aliz
ed P
ower
Theoretical random noise
level(1/128)
Spectral Coefficients
Analysis of 128 random vectors.
Feb. 28, 2007 D&T Seminar Spring 2007 25
Selecting Minimal Vector Sequences Using ILPFault simulation of new sequences
A set of perturbation vector sequences {V1, V2, .. , VM} is generated.Vector sequences are simulated and all gate-level faults detected by each are obtained.
Compaction problemFind minimum set of vector sequences that cover all detected faults.Minimize Count{V1, … ,VM} to obtain compressed seq. {V1,… ,VC}, where {V1, … ,VC} {V1, … , VM}, andFault Coverage{V1, … ,VC} = Fault Coverage{V1, … ,VM}Compaction problem is formulated as an Integer Linear Program (ILP) [1].
⊆
[1] P. Drineas and Y. Makris, “Independent Test Sequence Compaction through Integer Programming," Proc. ICCD’03, pp. 380-386.
Feb. 28, 2007 D&T Seminar Spring 2007 26
RTL DFTGoals of DFT:
Improve controllability and observabilityMost hard-to-detect transition faults were experimentally found to have poor observabilityXOR tree as DFT
Low area overheadLow performance penaltyHard-to-detect RTL faults used for observation test points24 observation test points selected
Hard-to-detect RTL transition faults
To test output
XOR tree
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Experimental Results
47.84%77.07%3652160737
RTL coverage (%)
Gate-level fault
coverage(%)CPU (s)No. of
vectors
No of RTL Transition
Faults
RTL transition fault characterization
PARWAN processor
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Experimental Results
73.7992.44131843574OriginalGate-level FlexTestfor transition faults 81.9096.29144440119DFT for t-f
65.8286.2051200DFT for s-a-f
58.6782.2851200OriginalRandom vectors
81.8597.6067006428OriginalRTL-spectral for transition faults 85.9498.2551206428DFT for t-f
81.8598.479027OriginalRTL-spectral combined stuck-at &
transition tests85.8798.917086DFT for s-a-f
86.2798.777086DFT for t-f
ATPG usedTransition fault cov.
(%)
Stuck-at fault cov.
(%)
No. of vectors
CPU secs.*
Version of PARWAN
circuit
* Sun Ultra 5, 256MB RAM
** N. Yogi and V. D. Agrawal, “Spectral RTL Test Generation for Microprocessors,” in Proc. 20th International Conf. VLSI Design, Jan. 2007, pp. 473-478.
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Experimental ResultsPARWAN without DFT
0
20
40
60
80
100
1 10 100 1000 10000No. of vectors
Test
Cov
erag
e (%
)
Stuck-atFaultCoverageTransitionFaultCoverage
Transition VectorsStuck-at Vectors
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Experimental ResultsPARWAN with DFT
0
20
40
60
80
100
1 10 100 1000 10000No. of vectors
Test
Cov
erag
e (%
)
Stuck-atFaultCoverageTransitionFaultCoverage
Stuck-at VectorsTransition
Vectors
Feb. 28, 2007 D&T Seminar Spring 2007 31
ConclusionSpectral RTL ATPG technique applied to PARWAN processor for transition delay faults.Proposed ATPG method provides:
Good quality “almost” functional at-speed transition delay testsLower test generation complexityEnables testability appraisal at RTL
RTL based XOR tree as DFT was found to improve results.Multiple fault model optimization:
Yogi and Agrawal, “Optimizing Tests for Multiple Fault Models,”submitted to the North Atlantic Test Workshop 2007.